a CDMA Power Management System ADP3510 FUNCTIONAL BLOCK DIAGRAM FEATURES Handles All CDMA Baseband Power Management Six LDOs Optimized for Specific CDMA Subsystems Li-Ion and NiMH Battery Charge Function Ambient Temperature: 20C to +85C TSSOP 28-Lead Package Optimized for LSI Logic Baseband Chipset APPLICATIONS CDMA Handsets VBAT VBAT2 PWRONKEY ALARM TCXOEN The ADP3510 is a multifunction power system chip optimized for CDMA handset power management. It contains six specialized LDOs, one to power each of the critical CDMA subblocks. Sophisticated controls are available for power-up during battery charging, keypad interface, and RTC alarm. If a Li-Ion battery is being charged, the charge circuit maintains low current charging during the initial charge phase and provides an end of charge (EOC) signal when the cell has been fully charged. The ADP3510 is specified over the temperature range of –20∞C to +85∞C and is available in a narrow body TSSOP 28-Lead package. VIO LDO VIO ANALOG LDO POWER-UP SEQUENCING AND PROTECTION LOGIC PDCAP GENERAL DESCRIPTION VTRC DIGITAL CORE LDO ROWX PWRONIN RTC RESCAP VCORE VAN TCXO LDO VTCXO MEMORY LDO VMEM REF BUFFER REFOUT RESET CHRDET BATTERY VOLTAGE DIVIDER EOC MVBAT CHGEN GATEIN BATSNS ISENSE BATTERY CHARGE CONTROLLER DGND ADP3510 AGND GATEDR CHRIN REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADP3510–SPECIFICATIONS (–20C ⱕ T ⱕ +85C, VBAT = VBAT2 = 3.2 V–7.5 V, CVIO = CVCORE = CVAN = CVMEM = 2.2 F, ELECTRICAL CHARACTERISTICS1 VTCXO = 0.47 F, CVBAT = 10 F, min. loads applied on all outputs, unless otherwise noted.) A Parameter Symbol SHUTDOWN SUPPLY CURRENT VBAT £ 2.5 V (Deep Discharged Lockout Active) 2.5 V < VBAT £ 3.2 V (UVLO Active) VBAT >3.2 V ICC OPERATING GROUND CURRENT All LDOs On Except TCXO All LDOs On All LDOs On IGND Conditions Min Typ Max Unit VBAT = VBAT2 = 2.3 V 5 15 mA VBAT = VBAT2 = 3.15 V VBAT = VBAT2 = 4.0 V 30 45 55 60 mA mA Minimum Loads Minimum Loads Maximum Loads 300 340 2.0 390 430 3.5 mA mA % of Max Load Current UVLO ON THRESHOLD VBAT UVLO HYSTERESIS VBAT 3.1 DEEP DISCHARGED LOCKOUT ON THRESHOLD VBAT DEEP DISCHARGED LOCKOUT HYSTERESIS VBAT INPUT HIGH VOLTAGE (PWRONIN, TCXOEN, CHGEN, GATEIN) VIH INPUT LOW VOLTAGE (PWRONIN, TCXOEN, CHGEN, GATEIN) VIL 0.4 V INPUT HIGH BIAS CURRENT (PWRONIN, TCXOEN, CHGEN, GATEIN) IIH 1.0 mA INPUT LOW BIAS CURRENT (PWRONIN, TCXOEN, CHGEN, GATEIN) IIL –1.0 mA PWRONKEY INPUT HIGH VOLTAGE VIH 0.7 VBAT V PWRONKEY INPUT LOW VOLTAGE VIL 2.0 ROWX Output High Leakage Current 70 I/O LDO (VIO) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage DIGITAL CORE LDO (VCORE) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability IL VIO DVIO DVIO CO VDO VCORE DVCORE DVCORE CO 2.4 2.75 V mV V 0.3 VBAT V 2 VOL V mV 2.0 THERMAL SHUTDOWN HYSTERESIS ROWX CHARACTERISTICS ROWX Output Low Voltage 3.3 100 PWRONKEY INPUT PULLUP RESISTANCE TO VBAT THERMAL SHUTDOWN THRESHOLD 3.2 200 105 145 kW 150 ºC 25 ºC PWRONKEY = Low IOL = 200 mA PWRONKEY = High V(ROWX) = 5 V Line, Load, Temp Minimum Load 50 mA £ ILOAD £ 25 mA 2.85 –2– V 1 mA 2.935 1 3 3.02 V mV mV mF 50 150 mV 1.85 1 8 1.92 V mV mV mF 2.2 VO = VINITIAL – 100 mV ILOAD = 25 mA Line, Load, Temp Minimum Load 50 mA £ ILOAD £ 120 mA 0.4 1.78 2.2 REV. 0 ADP3510 Parameter Symbol Conditions Min Typ ANALOG LDO (VAN) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage VAN DVAN DVAN CO VDO Line, Load, Temp Minimum Load 50 mA £ ILOAD £ 75 mA 2.85 2.935 3.02 1 6 V mV mV mF 100 75 mV dB Ripple Rejection Output Noise Voltage TCXO LDO (VTCXO) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage DVBAT/ DVAN VNOISE VTCXO DVTCXO DVTCXO CO VDO DVBAT/ DVTCXO VNOISE 2.2 VO = VINITIAL 100 mV ILOAD = 75 mA f = 217 Hz (T = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 75 mA VBAT = 3.6 V Line, Load, Temp Minimum Load 50 mA £ ILOAD £ 10 mA Max 2.71 175 80 mV rms 2.765 2.82 1 3 V mV mV mF mV 0.47 VO = VINITIAL – 100 mV ILOAD = 10 mA f = 217 Hz (T = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 10 mA VBAT = 3.6 V Unit 175 75 dB 80 mV rms REAL-TIME CLOCK LDO/ BATTERY CHARGER (VRTC) Maximum Output Voltage Off Reverse Input Current Dropout Voltage VRTC IL VDO 1 mA £ ILOAD £ 6 mA 2.0 V < VBAT < UVLO VO = VINITIAL – 100 mV ILOAD = 10 mA 2.77 2.85 2.93 1 175 V mA mV MEMORY LDO (VMEM) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage VMEM DVMEM DVMEM CO VDO Line, Load, Temp Minimum Load 50 mA £ ILOAD £ 60 mA 2.85 2.935 3.02 1 5 2.2 100 175 V mV mV mF mV 1.19 1.210 1.23 0.3 0.6 V mV mV 75 dB 100 40 pF mV rms REFOUT Output Voltage Line Regulation Load Regulation Ripple Rejection Maximum Capacitive Load Output Noise Voltage RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Output Current Delay Time per Unit Capacitance Applied to RESCAP Pin SEQUENCING Delay Time per Unit Capacitance Applied to PDCAP Pin PDCAP Charging Current VAN Discharge Resistance VIO Discharge Resistance REV. 0 VO = VINITIAL – 100 mV ILOAD = 60 mA VREFOUT Line, Load, Temp DVREFOUT Minimum Load DVREFOUT 0 mA £ ILOAD £ 50 mA VBAT = 3.6 V DVBAT/ f = 217 Hz (T = 4.6 ms) DVREFOUT VBAT = 3.6 V CO VNOISE f = 10 Hz to 100 kHz VOH VOL IOL/IOH TD IOH = +500 mA IOL = –500 mA TD IOH VPDCAP = 0 –3– 2.4 V V mA ms/nF 0.8 1.5 0.25 1 4.0 0.3 0.8 3.0 ms/nF 2.5 5 200 200 8 mA W W ADP3510 Parameter Symbol Conditions BATTERY VOLTAGE DIVIDER Divider Ratio Divider Impedance at MVBAT Divider Leakage Current Divider Resistance BATSNS/MVBAT TCXOEN = High ZO TCXOEN = Low TCXOEN = High BATTERY CHARGER Charger Output Voltage BATSNS Charger Output Voltage BATSNS Load Regulation ⌬BATSNS CHRDET on Threshold CHRDET Hysteresis CHRDET Off Delay3 CHRIN Supply Current CHRIN–VBAT Current Limit Threshold High Current Limit (100%: UVLO Not Active) CHRIN–ISENSE Low Current Limit (10%: UVLO Active) ISENSE Bias Current End of Charge Signal Threshold CHRIN–ISENSE End of Charge Reset Threshold VBAT GATEDR Transition Time Min Typ Max Unit 2.94 50 3.00 80 230 350 3.06 110 1 430 kW mA kW 4.5 V < CHRIN < 10 V, 4.158 4.200 4.242 CHGEN = Low, TA = 0∞C to 50∞C CHRIN = 10 V, VSENSE = 10 mV, 4.162 4.200 4.238 TA = 0∞C to 50∞C CHRIN = 5 V, 2 8 0 < CHRIN – ISENSE < Current Limit Threshold, CHGEN = Low VBAT = 3.6 V 260 70 CHRIN < VBAT 6 CHRIN = 5 V 0.6 1 V CHRIN = 5 V dc VBAT = 3.6 V CHGEN = Low CHRIN = 5 V VBAT = 2 V CHGEN = Low CHRIN = 5 V V mV mV mV ms/nF mA 150 172 195 mV 2 15 30 mV 180 250 mA CHRIN = 5 V dc VBAT > 4.0 V CHGEN = Low CHGEN = Low 2 12 26 mV 3.82 3.96 4.10 V t R , tF CHRIN = 5 V VBAT > 3.6 V CHGEN = High, CL = 2 nF 1 10 ms GATEDR High Voltage VOH CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = High IOH = –1 mA 4.5 GATEDR Low Voltage VOL Output High Voltage (EOC, CHRDET) Output Low Voltage (EOC, CHRDET) Battery Overvoltage Protection Threshold (GATEDRÆHigh) Battery Overvoltage Protection Hysteresis VOH CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = Low IOL = +1 mA IOH = –250 mA VOL IOL = +250 mA BATSNS CHRIN = 7.5 V CHGEN = High GATEIN = Low CHRIN = 7.5 V CHGEN = High GATEIN = Low BATSNS V 0.5 2.4 5.30 V V 5.50 400 0.25 V 5.70 V mV NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125C. Operation beyond 125C could cause permanent damage to the device. 3 Delay set by external capacitor on the RESCAP pin. Specifications subject to change without notice. –4– REV. 0 ADP3510 ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE Voltage on any pin with respect to any GND Pin . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V Voltage on any pin may not exceed VBAT, with the following exceptions: CHRIN, GATEDR, ISENSE Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C Operating Ambient Temperature Range . . . . –20∞C to +85∞C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C qJA, Thermal Impedance (TSSOP-28) 2-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98∞C/W 4-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68∞C/W Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C Model Temperature Range Package Option ADP3510ARU –20∞C to 85∞C RU-28 *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION ∑ PWRONIN 1 28 TCXOEN PWRONKEY 2 27 AGND ROWX 3 26 REFOUT ALARM 4 25 VTCXO PDCAP 5 24 VAN VRTC 6 23 VBAT BATSNS 7 22 VCORE MVBAT 8 21 VMEM CHRDET 9 20 VBAT2 CHRIN 10 19 VIO GATEIN 11 18 RESET GATEDR 12 17 RESCAP DGND 13 16 CHGEN ISENSE 14 15 EOC ADP3510 TOP VIEW (Not to Scale) Pin Mnemonic 1 PWRONIN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function Power-On/-Off Signal from Microprocessor PWRONKEY Power-On/-Off Key ROWX Power Key Interface Output ALARM Alternative Power-On PDCAP Power-On Delay Timer Capacitor VRTC VRTC LDO Output BATSNS Battery Voltage Sense Input MVBAT Divided Battery Voltage Output CHRDET Charge Detect Output CHRIN Charger Input Voltage GATEIN Microprocessor Gate Input Signal GATEDR Gate Drive Output DGND Digital Ground ISENSE Charge Current Sense Input EOC End of Charge Signal CHGEN Charger Enable for GATEIN, NiMH Pulse Charging RESCAP Reset Delay Time RESET Main Reset VIO I/O LDO Output VBAT2 Battery Input Voltage 2 VMEM Memory LDO Output VCORE Digital Core LDO Output VBAT Battery Input Voltage VAN Analog LDO Output VTCXO TCXO LDO Output REFOUT Output Reference AGND Analog Ground TCXOEN TCXO LDO Enable and MVBAT Enable CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3510 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE ADP3510 UT M VB RE FO VM AT VT VR TC VA N X X X X X OFF OFF OFF OFF OFF OFF OFF OFF State #2 phone off H L X X X X OFF OFF OFF OFF OFF ON OFF OFF State #3 phone off, turn on allowed H H L H L X OFF OFF OFF OFF OFF ON OFF OFF State #4 charger applied H H H X X L ON ON ON ON ON ON OFF** ON State #5 phone turned on by user key H H X L X L ON ON ON ON ON ON OFF** ON State #6 phone turned on by BB H H L H H L ON ON ON OFF ON ON OFF ON State #7 phone and TCXO LDO kept on by BB H H L H H H ON ON ON ON ON ON ON ON O L VI O VC CX O RE EN TC XO RO PW EM N NI NK PW RO ET CH RD UV State #1 battery deep discharged D D LO LO * EY or AL AR M Table I. LDO Control Logic Phone Status *UVLO is only active when phone is turned off. UVLO is ignored once the phone is turned on. **Controlled by TCXOEN. –6– REV. 0 ADP3510 VBAT VBAT2 23 20 IO LDO ADP3510 VBAT OUT VREF 110k PWRONKEY 2 ROWX 3 PWRONIN 1 ALARM 4 UVLO DEEP DISCHARGED UVLO UVLO S EN 19 VIO PG DGND Q R DIGITAL CORE LDO OVER TEMP SHUTDOWN VBAT VREF EN OUT 22 VCORE OUT 24 VAN DGND ANALOG LDO VBAT VREF CHARGER DETECT EN AGND TCXOEN 28 CHRDET TCXO LDO RESET GENERATOR RESCAP 17 VREF EOC 15 CHGEN 16 GATEIN 11 BATSNS 7 ISENSE 14 EN LI-ION BATTERY CHARGE CONTROLLER AND PROCESSOR CHARGE INTERFACE OUT 25 VTCXO AGND MEMORY LDO VBAT VREF EN OUT DGND 21 VMEM PG RTC LDO DGND VBAT GATEDR 12 VREF CHRIN 10 EN POWERON DELAY MVBAT 18 RESET VBAT 9 8 OUT VRTC DGND EN REF BUFFER 1.21V 6 26 REFOUT 27 AGND 13 DGND AGND 5 PDCAP Figure 1. Functional Block Diagram EOC CHGEN GATEIN CHRIN (10V MAX) ISENSE ADP3510 BATTERY CHARGE CONTROLLER GATEDR BATSNS CHRDET Figure 2. Battery Charger Typical Application REV. 0 –7– ADP3510 —Typical Performance Characteristics (VBAT = 3.6 V, T = 25C, unless otherwise specified.) A 160 400 400 +85C 140 ALL LDO, MVBAT, REFOUT, ON MIN LOAD (TCXOEN = H) 300 VIO, VCORE, VMEM, VRTC, VAN, REFOUT ON, MIN LOAD (TCXOEN = L) 120 I VRTC – A 350 IGND – A IGND – A 350 ALL LDO, MVBAT, REFOUT ON, MIN LOAD (TCXOEN = H) 300 VIO, VCORE, VMEM, VRTC, VAN, REFOUT, ON MIN LOAD (TCXOEN = L) 80 –20C 60 40 250 250 +25C 100 20 200 3.0 3.5 4.0 4.5 VBAT – V 5.0 200 40 20 5.5 1.6 160 1.0 0.8 RTC REVERSE LEAKAGE (VBAT = 2.3V) 0.6 0.4 DROPOUT VOLTAGE – mV REVERSE LEAKAGE CURRENT – A 180 1.2 60 80 100 120 10 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 VRTC – V TPC 3. RTC I/V Characteristic VTCXO 3.5V 140 VBAT 120 3.3V 100 80 60 VSIM VTCXO 10mV/DIV VMEM 10mV/DIV VMEM 40 20 0.2 TIME 100s/DIV 0 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TEMPERATURE – C 0 20 40 60 LOAD CURRENT – mA 80 TPC 5. Dropout Voltage vs. Load Current TPC 4. VTRC Reverse Leakage Current vs. Temperature 3.5V 3.5V 3.3V 40 TPC 2. Ground Current vs. Temperature 1.8 RTC REVERSE LEAKAGE (VBAT = FLOAT) 20 TEMPERATURE – C TPC 1. Ground Current vs. Battery Voltage 1.4 0 VBAT 3.3V VTCXO 10mV/DIV VMEM 10mV/DIV TIME 100s/DIV TPC 7. Line Transient Response, Maximum Loads TPC 6. Line Transient Response, Minimum Loads 3.5V VBAT 3.3V VBAT VAN 10mV/DIV VAN 10mV/DIV VCORE 10mV/DIV VCORE 10mV/DIV VIO 2mV/DIV 2mV/DIV VIO TIME 100s/DIV TPC 8. Line Transient Response, Minimum Loads –8– TIME 100s/DIV TPC 9. Line Transient Response, Maximum Loads REV. 0 ADP3510 LOAD 60mA 25mA 10mA 1mA LOAD 2mA LOAD VTCXO 5mA VMEM 10mV/DIV VIO 10mV/DIV 5mV/DIV TIME 200s/DIV TIME 200s/DIV TIME 200s/DIV TPC 10. VTCXO Load Step TPC 11. VIO Load Step TPC 12. VMEM Load Step 120mA 75mA PWRONIN (2V/DIV) LOAD 10mA LOAD VAN (200mV/DIV) 8mA VCORE PDCAP = 1nF 10mV/DIV VAN VIO (200mV/DIV) 10mV/DIV VCORE (200mV/DIV) TIME 200s/DIV TIME – 200s/DIV TIME 200s/DIV TPC 13. VCORE Load Step TPC 14. VAN Load Step TPC 15. Turn On Transient by PWRONIN, Minimum Load PWRONIN (2V/DIV) REFOUT (200mV/DIV) PWRONIN (2V/DIV) PWRONIN (2V/DIV) REFOUT (200mV/DIV) PDCAP = 1nF PDCAP = 1nF VMEM (200mV/DIV) PDCAP = 1nF VAN (200mV/DIV) VMEM (200mV/DIV) VIO (200mV/DIV) VTCXO (200mV/DIV) VTCXO (200mV/DIV) VCORE (200mV/DIV) TIME 200s/DIV TPC 16. Turn On Transient by PWRONIN, Minimum Load REV. 0 TIME 200s/DIV TIME 200s/DIV TPC 17. Turn On Transient by PWRONIN, Maximum Load TPC 18. Turn On Transient by PWRONIN, Maximum Load –9– ADP3510 4.25 4.22 VIN = 5V RSENSE = 250m OUTPUT VOLTAGE – V 4.23 CHARGER VOUT – V 4.210 VIN = 5.0V ILOAD = 10mA 4.22 4.21 4.20 4.19 4.18 RSENSE = 250m ILOAD = 500mA 4.21 OUTPUT VOLTAGE – V 4.24 4.20 4.19 4.205 4.200 ILOAD = 10mA 4.195 4.17 4.16 4.15 –40 –20 4.18 0 20 40 60 80 TEMPERATURE – C 4.190 0 100 120 TPC 19. Charger VOUT vs. Temperature, VIN = 5.0 V, ILOAD = 10mA 200 400 600 ILOAD – mA 800 5 1000 The ADP3510 is a total solution power management chip for use with CDMA baseband chipsets and is optimized for the CBP3.0/ 4.0 type chipsets. Figure 1 shows a block diagram of the ADP3510. The ADP3510 contains several blocks: 7 8 INPUT VOLTAGE – V 9 10 TPC 21. Charger VOUT vs. VIN TPC 20. Charger VOUT vs. ILOAD (VIN = 5.0 V) THEORY OF OPERATION 6 These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. The ADP3510 combines the benefits of both worlds by providing an integrated standard product where every block is optimized to operate in a CDMA environment while maintaining a cost-competitive solution. ∑ Six Low Dropout Regulators (Input-Output, Core, Analog, Crystal Oscillator, Memory, Realtime Clock) Figure 3 shows the external circuitry associated with the ADP3510. Only a minimal number of support components are required. ∑ Reset Generator Input Voltage The input voltage range of the ADP3510 is 3.2 V to 7.5 V and is optimized for a single Li-Ion cell or three NiMH cells. The thermal impedance of the ADP3510 is 68∞C/W for four layer boards. The end of charge voltage for high capacity NiMH cells can be as high as 5.5 V. Power dissipation should be calculated at maximum ambient temperatures and battery voltage in order not to exceed the 125∞C maximum allowable junction temperature. Figure 4 shows the maximum power dissipation as a function of ambient temperature. ∑ Buffered Precision Reference ∑ Lithium Ion Charge Controller and Processor Interface ∑ Power-On/-Off Logic ∑ Undervoltage Lockout ∑ Deep Discharge Lockout ADP3510 PWRON 1 PWRONIN PWRONKEY 2 PWRONKEY KEYPADROW 3 ROWX ALARM 4 ALARM VTCXO 25 5 PDCAP VAN 24 6 VRTC 7 BATSNS VCORE 22 ADC 8 MVBAT VMEM 21 GPIO 9 CHRDET VBAT2 20 CHARGER IN 10 CHRIN GPIO 11 GATEIN 12 GATEDR 13 DGND 14 ISENSE VRTC C1 0.1F R1 0.25 C2 10nF C3 1.0nF TCXOEN 28 AGND 27 REFOUT 26 VBAT 23 TCXOEN R2 10 REF VTCXO C4 C9 2.2F 10F C10 0.22F VMEM C7 2.2F VIO 19 VIO C6 2.2F CHGEN 16 EOC 15 Q1 SI3441DY VAN VCORE RESET 18 RESCAP 17 C11 0.1F C8 2.2F RESET GPIO C5 0.1F GPIO D1 10BQ015 Li BATTERY Figure 3. Typical Application Circuit –10– REV. 0 ADP3510 (ML614, ML621, or ML1220) from Sanyo. The ML621 has a small physical size (6.8 mm diameter) and will give many hours of backup time. 1.2 POWER DISSIPATION – W 1.0 The ADP3510 supplies current both for charging the coin cell and for the RTC module. The nominal charging voltage is 2.85 V, which ensures long cell life while obtaining in excess of 90% of the nominal capacity. In addition, it features a very low quiescent current since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage, which is needed when the main battery is removed and the coin cell supplies the RTC module. 0.8 0.6 0.4 0.2 IO LDO (VIO) 0.0 –20 0 20 40 60 AMBIENT TEMPERATURE – C 80 100 Figure 4. Power Dissipation vs. Temperature However, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. In this mode, there is a relatively light load on the LDOs. A fully charged Li-Ion battery is 4.245 V, where the ADP3510 can deliver the maximum power (0.52 W) up to 85∞C ambient temperature. Low Dropout Regulators (LDOs) The ADP3510 high performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, regulation, ripple rejection, and output noise. 2.2 mF tantalum or MLCC ceramic capacitors are recommended for use with the core, memory, IO, and analog LDOs. A 0.22 mF capacitor is recommended for the TCXO LDO. The IO LDO generates the voltage needed for the peripheral subsystems of the baseband processor, including GPIO, display, and serial interfaces. It is rated for 25 mA of supply current and is controlled by the power-on delay block of the ADP3510. Reference Output (REFOUT) The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.65% over temperature. The reference can be used with the baseband converter, if the converter’s own reference is not accurate. This may significantly reduce the calibration time needed for the baseband converter during production. Power ON/OFF The ADP3510 handles all issues regarding the powering ON and OFF of the handset. It is possible to turn on the ADP3510 in four different ways: ∑ Pulling the PWRONKEY Low ∑ Pulling PWRONIN High Digital Core LDO (VCORE) The digital core LDO supplies the baseband circuitry in the handset (baseband processor and baseband converter). The LDO has been optimized for very low quiescent current at light loads as this LDO is on at all times. Memory LDO (VMEM) The memory LDO supplies the memory of the baseband processor. The memory LDO is capable of supplying 60 mA of current and has also been optimized for low quiescent current and will power up at the same time as the core LDO. Analog LDO (VAN) This LDO has the same features as the core LDO. It has furthermore been optimized for good low frequency ripple rejection for use with the baseband converter sections in order to reject the ripple coming from the RF power amplifier. VAN is rated to 75 mA load, which is sufficient to supply the complete analog section of the baseband converter. The analog LDO is controlled by the power-on delay block of the ADP3510. ∑ Pulling ALARM High ∑ CHRIN Exceeds CHRDET Threshold Pulling the PWRONKEY low is the normal way of turning on the handset. This will turn on all the LDOs, as long as the PWRONKEY is held low. When the VIO LDO comes into regulation, the RESET timer is started. After timing out, the RESET pin goes high, allowing the baseband processor to start up. With the baseband processor running, it can poll the ROWX pin of the ADP3510 to determine if the PWRONKEY has been depressed and pull PWRONIN high. Once the PWRONIN is taken high, the PWRONKEY can be released. Note that by monitoring the ROWX pin, the baseband processor can detect a second PWRONKEY press and turn the LDOs off in an orderly manner. In this way, the PWRONKEY can be used for ON/OFF control. TCXO LDO (VTCXO) Pulling the ALARM pin high is how the alarm in the realtime clock module will turn the handset on. Asserting ALARM will turn the core, IO, memory, and analog LDOs on, starting up the baseband processor. The TCXO LDO is intended as a supply for a temperature compensated crystal oscillator, which needs its own ultralow noise supply. VTCXO is rated for 10 mA of output current and is turned on when TCXOEN is asserted. Applying an external charger can also turn the handset on. This will turn on all the LDOs, again starting up the baseband processor. Note that if the battery voltage is below the undervoltage lockout threshold, applying the adapter will not start up the LDOs. RTC LDO (VRTC) The RTC LDO charges up a rechargeable lithium type coin cell to run the realtime clock module. It has been designed to charge manganese lithium batteries such as the ML series REV. 0 –11– ADP3510 Power On Delay The power-on delay block in the ADP3510 controls the turn-on sequence of VCORE, VIO, and VAN. Asserting a power-on in one of the four above methods will start the LDOs in the following sequence: 1. The VMEM LDO will start up. If the handset is off and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and puts the ADP3510 into UVLO shutdown mode. In this mode, the ADP3510 draws very low quiescent current, typically 30 mA. The RTC LDO is still running until the DDLO disables it. In this mode, the ADP3510 draws 5 mA of quiescent current. NiMH batteries can reverse polarity if the 3-cell battery voltage drops below 3.0 V, which will degrade the battery’s performance. Lithium Ion batteries will lose their capacity if over discharged repeatedly so minimizing the quiescent currents helps prevent battery damage. 2. The VIO and VAN outputs will be discharged by the poweron delay block. The discharge delay time is set by the value of the PDCAP. 3. After the discharge time has expired, the VCORE LDO is allowed to start up. 4. When the output of VCORE exceeds 1.2 V, the VIO and VAN LDOs are allowed to start up. The power-on delay is set by an external capacitor on PDCAP: ms ¥ CPDCAP nF See Figure 5 for the power-up timing sequence. t PD = 0.8 Once the system is started and the core, memory, analog, and IO LDOs are up and running, the UVLO function is entirely disabled. The ADP3510 is then allowed to run until the battery voltage reaches the DDLO threshold, typically 2.4 V. Normally, the battery voltage is monitored by the baseband processor and usually shuts the phone off at around 3.0 V. (1) RESET The ADP3510 contains a reset circuit that is active both at power-up and power-down. The RESET pin is held low at initial powerup. An internal power good signal is generated by the IO LDO when its output is in regulation which starts the reset delay timer. The delay is set by an external capacitor on RESCAP: INTERNAL POWER ON* 1.8V ms ¥ CRESCAP (2) nF Should the IO or MEM LDO drop out of regulation, the RESET signal will go low and remain low until the IO and MEM LDO outputs are back in regulation and the RESET timer has timed out. At power-off, RESET will be kept low to prevent any baseband processor starts. t RESET = 1.5 VCORE 1.2V 3.0V VMEM Over-Temperature Protection In case of a failure that causes excess power dissipation to the IC, the thermal shutdown function will be activated. The maximum die temperature for the ADP3510 is 125C. If the die temperature exceeds 160C, the ADP3510 will disable all the LDOs except the RTC LDO. The LDOs will not be re-enabled before the die temperature is below 125C, regardless of the state of PWRONKEY, PWRONIN, ALARM, and CHRDET. This ensures that the handset will always power-off before the ADP3510 exceeds its absolute maximum thermal ratings. 3.0V V10, VAN *PWRONIN or CHRDET or ALARM or PWRONKEY POWER-ON DELAY V10, VAN < VCORE UNTIL VCORE > 1.2V Figure 5. Power-Up Timing Diagram Battery Charging Deep Discharge Lockout (DDLO) The DDLO block in the ADP3510 will shut down the handset in the event the software fails to turn off the phone when the battery drops below 2.9 V to 3.0 V. The DDLO will shut down the handset when the battery falls below 2.4 V to prevent further discharge and damage to the cell. The ADP3510 battery charger can be used with lithium ion (Li+) and nickel metal hydride (NiMH) batteries. The charger initialization, trickle charging, and Li+ charging are implemented in hardware. Battery type determination and NiMH charging must be implemented in software. The charger block works in three different modes: ∑ Low Current (Trickle) Charging Undervoltage Lockout (UVLO) The UVLO function in the ADP3510 prevents startup when the initial voltage of the battery is below the 3.2 V threshold. If the battery voltage is this low with no load, there is insufficient capacity left to run the handset. When the battery is greater than 3.2 V, such as inserting a fresh battery, the UVLO comparator trips and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery decays to below 3.0 V. Note that the DDLO has enabled the RTC LDO under this condition. ∑ Lithium Ion Charging ∑ Nickel Metal Hydride Charging See Figure 6 for the battery charger flowchart. –12– REV. 0 ADP3510 poll the battery to determine which chemistry is present and set the charger to the proper mode. NONCHARGING MODE Lithium Ion Charging For lithium ion charging, the CHGEN input must be low. This allows the ADP3510 to continue charging the battery at the full current. The full charge current can be calculated by using: NO CHARGER DETECTED CHRIN > BATSNS YES ICHR ( FULL ) = YES VBAT > UVLO BATTERY TYPE VSENSE = 15mV NiMH CHGEN = HIGH Li CHGEN = LOW NiMH CHARGING MODE GATEIN = PULSED HIGH CURRENT CHARGE MODE The baseband processor can either let the charger continue to charge the battery for an additional amount of time or terminate the charging. To terminate the charging, the processor must pull the GATEIN and CHGEN pins high. VSENSE = 172mV NO VBAT > 5.5V NO VBAT > 4.2V YES (4) If the voltage at BATSNS is below the charger’s output voltage of 4.2 V, the battery will continue to charge in the constant current mode. If the battery has reached the final charge voltage, a constant voltage is applied to the battery until the charge current has reduced to the charge termination threshold. The charge termination threshold is determined by the voltage across the sense resistor. If the battery voltage is above 4.0 V and the voltage across the sense resistor has dropped to 12 mV, then an end of charge signal is generated and the EOC output goes high (see Figure 7). NO LOW CURRENT CHARGE MODE 172 mV RSENSE YES 4.2V NiMH CHARGER OFF VBAT GATEIN = HIGH 3.2V CONSTANT VOLTAGE MODE VBAT < 5.5V NO HIGH CURRENT NO END OF CHARGE VSENSE < 12mV YES ICHARGE 0 YES LOW CURRENT EOC CURRENT EOC = HIGH TERMINATE CHARGE CHREN = HIGH GATEIN = HIGH EOC INDICATOR Figure 6. Battery Charger Flowchart Figure 7. Lithium Ion Charging Diagram Trickle Charging NiMH Charging When the battery voltage is below the UVLO threshold, the charge current is set to the low current limit, or about 10% of the full charge current. The low current limit is determined by the voltage developed across the current sense resistor. Therefore, the trickle charge current can be calculated by: For NiMH charging, the processor must pull the CHGEN pin high. This disables the internal Li+ mode control of the gate drive pin. The gate drive must now be controlled by the baseband processor. By pulling GATEIN high, the GATEDR pin is driven high, turning the PMOS off. By pulling the GATEIN pin low, the GATEDR pin is driven low, and the PMOS is turned on. So, by pulsing the GATEIN input, the processor can charge a NiMH battery. Note that when charging NiMH cells, a current limited adapter is required. ICHR (TRICKLE ) = 15 mV RSENSE (3) Trickle charging is performed for deeply discharged batteries to prevent undue stress on either the battery or the charger. Trickle charging will continue until the battery voltage exceeds the UVLO threshold. Once the UVLO threshold has been exceeded, the charger will switch to the high current limit, the LDOs will start up, and the baseband processor will start to run. The processor must then REV. 0 During the PMOS off periods, the battery voltage needs to be monitored through the MVBAT pin. The battery voltage is continually polled until the final battery voltage is reached. Then the charge can either be terminated or the frequency of the pulsing reduced. An alternative method of determining the end of charge is to monitor the temperature of the cells and terminate the charging when a rapid rise in temperature is detected. –13– ADP3510 Battery Voltage Monitoring Power-On Delay Capacitor Selection The battery voltage can be monitored at MVBAT during charging and discharging to determine the condition of the battery. An internal resistor divider is connected to BATSNS when both the baseband processor and the crystal oscillator are powered up. To enable MVBAT, both PWRONIN and TCXOEN must be high. The PDCAP sets the interval that the VAN and VIO LDOs are discharged. To ensure that the baseband processor is properly reset, the VIO and VAN LDOs should be fully discharged before power is reapplied. The discharge time can be estimated using: The ratio BATSNS/MVBAT of the voltage divider is set to 3.0. The divider will be disconnected from the battery when the baseband processor is powered down. t PD = 900 ¥ COUT SEC where tPD is the discharge time, and COUT is the VIO or VAN LDO output capacitor value. Charge Detection The ADP3510 charger block has a detection circuit that determines if an adapter has been applied to the CHRIN pin. If the adapter voltage exceeds the battery voltage by 260 mV, the CHRDET output will go high. If the adapter is then removed or the voltage at the CHRIN pin drops to around 190 mV above the BATSNS pin, then CHRDET goes low. The power-on delay is set by an external capacitor on PDCAP. For worst-case delay: ms ¥ CPDCAP or nF nF = t PD ¥ 3.33 ms t PD = 0.3 CPDCAP (7) So, for a 2.2 mF output capacitor, the required delay is about 2 ms. This results in a 6.8 nF PDCAP value. APPLICATION INFORMATION Input Capacitor Selection For the input (VBAT and VBAT2) of the ADP3510, a local bypass capacitor is recommended. Use a 10 mF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 mF tantalum capacitor with a small (1 mF to 2 mF) ceramic in parallel. Setting the Charge Current The ADP3510 is capable of charging both lithium ion and NiMH batteries. For NiMH batteries, the charge current is limited by the adapter. For lithium ion batteries, the charge current is programmed by selecting the sense resistor, R1. The lithium ion charge current is calculated using: A separate input for the IO LDO is supplied for additional bypassing or filtering. The IO LDO has VBAT2 as its input. ICHR = LDO Capacitor Selection The performance of any LDO is a function of the output capacitor. The core, memory, IO, and analog LDOs require a 2.2 mF capacitor, and the TCXO LDO requires a 0.22 mF capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR (any CAP technology). The ADP3510 is stable with extremely low ESR capacitors (ESR ~ 0), such as multilayer ceramic capacitors, but care should be taken in their selection. Note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. A good quality dielectric capacitor, X7R or better, is recommended. RESET Capacitor Selection RESET is held low at power-up. An internal power-good signal starts the reset delay when the IO LDO is up. The delay is set by an external capacitor on RESCAP: (5) A 100 nF capacitor will produce a 150 ms reset delay. The current capability of RESET is minimal (a few hundred nA) when VIO is off to minimize power consumption. When VIO is on, RESET is capable of driving 500 mA. VSENSE 172 mV = R1 R1 (8) Where VSENSE is the high current limit threshold voltage. Or, if the charge current is known, R1 can be found: R1 = VSENSE 172 mV = ICHR ICHR (9) Similarly the trickle charge current and the end of charge current can be calculated: ITRICKLE = The RTC LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 mF ceramic capacitor is recommended for stability and best performance. tRESET = 1.5 ms / nF ¥ CRESCAP (6) I EOC = VSENSE 15 mV = R1 R1 VSENSE 12 mV = R1 R1 (10) Example: Assume a 850 mA-H capacity lithium ion battery and a 1 C charge rate. R1 = 200 m⍀. Then ITRICKLE = 75 mA and IEOC = 60 mA. Appropriate sense resistors are available from the following vendors: Vishay Dale IRC Panasonic Charger FET Selection The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and the charge current. The selected PMOS must satisfy the physical, electrical, and thermal design requirements. –14– REV. 0 ADP3510 VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT To ensure proper operation, the minimum VGS the ADP3510 can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following: VGS = VADAPTER( MIN ) - VSENSE - VGATEDR (15) = 5 V – 0.5 V – 0.170 V – 4.2 V = 130 mV (11) where: RDS (ON ) = VADAPTER(MIN) is the minimum adapter voltage. VDIODE is the maximum forward drop of the charger diode, D1. VDS 130 mV = I CHR( MAX ) 850 mV (16) = 153 mW VGATEDR is the gate drive “low” voltage, 0.5 V. ( ) VSENSE is the maximum high current limit threshold voltage. PDISS = VADAPTER( MAX ) - VDIODE - VSENSE - UVLO ¥ I CHR The difference between the adapter voltage (VADAPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the ON resistance of the FET at maximum charge current. PDISS = (6.5 V - 0.5 V - 0.170 V - 3.2) ¥ 0 / 85 A = 2.24 W VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT Appropriate PMOS FETs are available from the following vendors: Siliconix IR Fairchild (12) Then the RDS(ON) of the FET can be calculated. RDS (ON ) = Charger Diode Selection VDS (13) I CHR( MAX ) The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using: ( ) PDISS = VADAPTER( MAX ) - VDIODE - VSENSE - UVLO ¥ I CHR It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case, the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an over-specified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design. For example: VADAPTER(MAX) = 6.5 V VDIODE = 0.5 V at 850 mA VSENSE = 170 mV VGS = 5 V – 0.5 V – 0.170 V = 4.3 V. So choose a low-threshold voltage FET. Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: 1. Connect the battery to the VBAT and VBAT2 pins of the ADP3510. Locate the input capacitor as close to the pins as possible. 2. VAN and VTCXO capacitors should be returned to AGND. 3. VCORE, VMEM, and VIO capacitors should be returned to DGND. VADAPTER(MIN) = 5.0 V VGATEDR = 0.5 V The diode, D1, shown in Figure 3, is used to prevent the battery from discharging through the PMOS’ body diode into the charger’s internal bias circuits. A Schottky diode is recommended to minimize the voltage difference from the charger to the battery and the power dissipation. Choose a diode with a current rating high enough to handle the battery charging current, a voltage rating greater than VBAT, and a low leakage current. The blocking diode is required for both lithium and nickel battery types. (14) 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. 5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement. 6. Kelvin connect the charger’s sense resistor by running separate traces to the CHRIN pin and ISENSE pin. Make sure that the traces are terminated as close to the resistor’s body as possible. 7. Use the best industry practice for thermal considerations during the layout of the ADP3510 and charger components. Careful use of copper area, weight, and multilayer construction all contribute to improved thermal performance. REV. 0 –15– ADP3510 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Thin Shrink Small Outline (TSSOP) (RU-28) 28 C02714–0–5/02(0) 0.386 (9.80) 0.378 (9.60) 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8 0 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. SEATING PLANE 0.0433 (1.10) MAX –16– REV. 0