IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER FEATURES: • • • • • DESCRIPTION: Bidirectional interface between GTLP and TTL logic levels Edge Rate Control Circuit reduces output noise VREF pin provides reference voltage for receiver threshold CMOS technology for low power dissipation Special PVT Compensation circuitry to provide consistent performance over variations of process, supply voltage, and temperature 5V tolerant inputs and outputs on A-Port Bus-Hold to eliminate the need for external pull-up resistors for unused inputs to A-Port Power up/down high-impedance TTL-compatible Driver and Control inputs High Output source/sink ±32mA on A-Port pins Flow-through architecture optimizes system layout D-type latch and flip-flop architecture for data flow in clocked, transparent, or latched mode Open drain on GTLP to support wired OR connection Available in SSOP and TSSOP packages • • • • • • • • • IDT74GTLP16612 The GTLP16612 is an 18-bit universal bus transceiver. It provides signal level translation, from TTL to GTLP, for applications requiring a highspeed interface between cards operating at TTL logic levels and backplanes operating at GTLP logic levels. GTLP provides reduced output swing (<1V), reduced input threshold levels, and output edge-rate control to minimize signal setting times. The GTLP16612 is a derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates internal edge-rate control, which is process, voltage, and temperature (PVT) compensated. GTLP output low voltage is less than 0.5V. The output high is 1.5V, and the receiver threshold is 1V. FUNCTIONAL BLOCK DIAGRAM OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA 1 56 55 2 28 30 29 27 ONE OF 18 CHANNELS A1 CE 1D C1 3 GTLP 54 B1 CLK CE 1D C1 CLK TO 17 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE OCTOBER 1999 1 c 1999 Integrated Device Technology, Inc. DSC-5477/2 IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1,2) PIN CONFIGURATION Symbol Rating VCC OEAB 1 56 CEAB LEAB 2 55 CLKAB Max. Unit Supply Voltage –0.5 to +7 V VCCQ VI DC Input Voltage –0.5 to +7 V VO DC Output Voltage, 3-State –0.5 to +7 V VO DC Output Voltage, Active –0.5 to VCC + 0.5 V IOL DC Output Sink Current into A-port 64 mA A1 3 54 B1 GND 4 53 GND A2 5 52 B2 IOH DC Output Source Current from A-port –64 mA A3 6 51 B3 IOL DC Output Sink Current into B-port 80 mA VCC (3.3V) 7 50 VCCQ (5V) –50 mA (in the LOW state) IIK DC Input Diode Current VI < 0V A4 8 49 B4 9 48 IOK DC Output Diode Current VO < 0V –50 mA A5 B5 DC Output Diode Current VO > VCC +50 mA A6 10 IOK 47 B6 TSTG Storage Temperature –65 to +150 °C GNDQ 11 46 GND A7 12 45 B7 A8 13 44 B8 A9 14 43 B9 A10 15 42 B10 16 41 B11 A12 17 40 B12 GND 18 39 GND A13 19 38 B13 C IN A14 20 37 B14 CI/O A15 21 36 B15 CI/O A11 22 35 VREF A16 23 34 B16 A17 24 33 B17 GND 25 32 GND A18 26 31 B18 27 30 CLKBA 29 CEBA VCC (3.3V) OEBA LEBA 28 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Unused inputs without Bus-Hold must be held HIGH or LOW. CAPACITANCE (TA = +25°C, f = 1.0MHZ) Parameter(1) Conditions Typ.(2) Max. Unit Control Pins VI = VCCQ or 0 8 — pF A-Port VI = VCCQ or 0 9 — pF B-Port VI = VCCQ or 0 6 — pF Symbol NOTES: 1. As applicable to the device type. 2. All typical values are at VCC = 3.3V and VCCQ = 5V. PIN DESCRIPTION Pin Names SSOP/ TSSOP TOP VIEW Description(1) OEAB A-to-B Output Enable (Active LOW) OEBA B-to-A Output Enable (Active LOW) CEAB A-to-B Clock Enable (Active LOW) CEBA B-to-A Clock Enable (Active LOW) LEAB A-to-B Latch Enable (Transparent HIGH) LEBA B-to-A Latch Enable (Transparent HIGH) CLKAB A-to-B Clock Pulse CLKBA B-to-A Clock Pulse VREF GTLP Input Reference Voltage A1 - A18 A-to-B TTL Data Inputs or B-to-A 3-State Outputs B1 - B18 B-to-A GTLP Data Inputs or A-to-B Open Drain Outputs NOTE: 1. A-Port pins have Bus-Hold. All other pins are standard input, output, or I/O. 2 IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE RECOMMENDED OPERATING CONDITIONS(1) Symbol Rating VCC Supply Voltage VCCQ FUNCTIONAL DESCRIPTION: Recommended Unit 3.15 to 3.45 V The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clock mode. 4.75 to 5.25 VTT Bus Termination Voltage VI Input Voltage on A-Port and Control Pins 1.35 to 1.65 V 0 to 5.5 V IOH IOL HIGH Level Output Current (A-Port) -32 mA LOW Level Output Current (A-Port) +32 mA IOL LOW Level Output Current (B-Port) TA Operating Temperature +34 mA –40 to +85 °C NOTE: 1. Unused inputs without Bus-Hold must be held HIGH or LOW. FUNCTION TABLE(1,2) Inputs Outputs CLKAB Ax Mode CEAB OEAB LEAB Bx X H X X X Z Latched L L L H X B0(3) storage (4) L L L L X B0 X L H X L L X L H X H H L L L ↑ L L Clocked storage L L L ↑ H H of A data H L L X X B0 (4) NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW-to-HIGH Transition 2. A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. Output level before the indicated steady-state input conditions were established. 3 of A data Transparent Clock Inhibit IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VREF = 1V, VCC = 3.3V ± 5%, VCCQ = 5V ± 5% Symbol VIH VIL Test Conditions Min. Typ.(1) Max. Unit B-Port — VREF+ 0.1 — V TT V All Other ports — 2 — — B-Port — 0 — VREF– 0.1 — — — 0.8 — — 1 — V — — –1.2 V VCC–0.2 — — 2.4 — — Parameter All Other ports VREF — VIK — VCC = 3.15V II = –18mA V VCCQ = 4.75V VOH VOH A-Port A-Port VCC, VCCQ = Min to Max(2) IOH = –100µA VCC = 3.15V IOH = –8mA VCCQ = 4.75V IOH = –32mA 2 — — VCC, VCCQ = Min to Max(2) IOL = 100µA — — 0.2 VCC = 3.15V IOL = 32mA — — 0.5 VCCQ = 4.75V B-Port V V VCC = 3.15V IOL = 34mA — — 0.65 VCCQ = 4.75V II Control Pins VCC, VCCQ = 0 or Max VI = 5.5V or 0V — — ±10 A-Port VCC = 3.45V VI = 5.5V — — 20 VCCQ = 5.25V VI = VCC — — 1 VI = 0 — — –30 B-Port VCC = 3.45V VI = VCCQ — — 5 VCCQ = 5.25V VI = 0 — — –5 µA IOFF A-Port VCC = VCCQ = 0 VI or VO = 0 to 4.5V — — 100 µA II (HOLD) A-Port VCC = 3.15V VI = 0.8V 75 — — µA VCCQ = 4.75V VI = 2V –20 — — IOZH A-Port VCC = 3.45V VO = 3.45 V — — 1 B-Port VCCQ = 5.25V VO = 1.5V — — 5 A-Port VCC = 3.45V VO = 0 — — –20 B-Port VCCQ = 5.25V VO = 0.65V — — –10 A or B Ports VCC = 3.45V Outputs HIGH — 30 40 VCCQ = 5.25V Outputs LOW — 30 40 IOZL ICCQ (VCCQ) µA µA mA IO = 0 ICC (VCC) A or B Ports VI = VCCQ or GND Outputs Disabled — 30 40 VCC = 3.45V Outputs HIGH — 0 1 VCCQ = 5.25V Outputs LOW — 0 1 mA IO = 0 ∆ICC (3) A-Port and Control Pins VI = VCCQ or GND Outputs Disabled — 0 1 VCC = 3.45V One Input at 2.7V — 0 1 VCCQ = 5.25V A or Control Inputs at VCC or GND NOTES: 1. All typical values are at VCC = 3.3V, VCCQ = 5V, and TA = 25°C. 2. For conditions shown as Max. or Min., use appropriate value specified under Recommended Operating Conditions. 3. ∆ICC is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 mA IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE (1,2) IDT74GTLP16612 Symbol fCLOCK Parameter Max Clock Frequency Min. Typ.(3) Max. Unit 175 — — MHz 3 — — ns tW Pulse Duration, LEAB or LEBA HIGH tW Pulse Duration, CLKAB or CLKBA HIGH or LOW 3.2 — — tS Setup Time, Ax before CLKAB ↑ 0.5 — — tS Setup Time, Bx before CLKBA ↑ 3.1 — — tS Setup Time, Ax before LEAB ↓ 1.3 — — tS Setup Time, Bx before LEBA ↓ 3.7 — — tS Setup Time, CEAB before CLKAB ↑ 0.4 — — tS Setup Time, CEBA beforeCLKBA ↑ tH Hold Time, Ax after CLKAB ↑ tH Hold Time, Bx after CLKBA ↑ tH Hold Time, Ax after LEAB ↓ tH Hold Time, Bx after LEBA ↓ 0 — — tH Hold Time, CEAB after CLKAB ↑ 1.5 — — tH Hold Time, CEBA afterCLKBA ↑ 1.7 — — 1 4.3 6.5 tPLH Ax to Bx tPHL tPLH LEAB to Bx tPHL tPLH — — 0 — — 0.5 — — 1 5 8.2 1.8 4.5 6.7 1.5 5.3 8.6 1.8 4.6 6.7 1.5 5.4 8.7 OEAB to Bx 1.6 4.4 6.2 tPHL tRISE — — CLKAB to Bx tPHL tPLH 1 1.5 ns ns ns ns ns ns 1.3 6.1 9.8 Transition Time, B outputs (20% to 80%) — 2.6 — ns Bx to Ax 2 5.6 8.2 ns tFALL tPLH tPHL tPLH LEBA to Ax tPHL tPLH 5 7.2 4.2 6.3 1.9 3.3 5 CLKBA to Ax 2.3 4.4 6.8 2.2 3.5 5.2 OEBA to Ax 1.5 5 6.2 1.9 3.9 7.9 tPHL tPZH 1.4 2.1 ns ns tPZL tPHZ tPLZ NOTES: 1. See Test Circuits and Waveforms. TA = –40°C to +85°C. 2. Unless otherwise noted, VREF = 1V, CL = 30pF for B-Port, and CL = 50pF for A-Port. 3. Typical values are at VCC = 3.3V, VCCQ = 5V, and TA = 25°C. 5 ns IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS S 500 Ω FROM OUTPUT UNDER TEST 1.5V (GTLP) 6V Open GND 25 Ω FROM OUTPUT UNDER TEST 500 Ω C L = 50pF 30pF NOTE: 1. CL includes probes and jig capacitance. For B-Port outputs, CL = 30pF is used for worst case edge rate. NOTE: 1. CL includes probes and jig capacitance. Test Circuit for A Outputs(1) Test Circuit for B Outputs(1) SWITCH POSITION Test Switch Open Drain Disable Low Enable Low 6V Disable High Enable High GND All Other Tests Open INPUT 3V 1.5V 0V 1.5V tPH L tPL H OUTPUT 1V V OH 1V V OL Voltage Waveforms Propagation Delay Times (A-Port to B-Port) tW 3V INPUT Vm V Vm V 0V Voltage Waveforms Pulse Duration (Vm = 1.5V for A-Port and 1V for B-Port) NOTE: All input pulses have the following characteristics: frequency = 10 MHz, tR = tF = 2 ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. 6 IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS 1.5V 1V 0V 3V TIM ING INPUT 1V INPUT Vm V 0V t SU t PHL t PLH tH 1.5V OUTPUT Vm V 1.5V V OL 3V DATA INPUT V OH Vm V 0V Voltage Waveforms Setup and Hold Times (Vm = 1.5V for A-Port and 1V for B-Port) Voltage Waveforms Propagation Delay Times (B-Port to A-Port) NOTE: All input pulses have the following characteristics: frequency = 10 MHz, tR = tF = 2 ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. OUTPUT CONTROL 3V 1.5V 1.5V tPZL 0V tPLZ 3V OUTPUT W AVEFORM 1 (S AT 6V) 1.5V V OL V OL t PZH + 0.3V – 0.3V tPHZ V OH OUTPUT W AVEFORM 2 (S AT GND) 1.5V V OH 0V Voltage Waveforms Enable and Disable Times (A-Port) NOTE: Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. All input pulses have the following characteristics: frequency = 10 MHz, tR = tF = 2 ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. 7 IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION GTLP XX IDT XX Family Temp. Range XX XXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA Shrink Small Outline Package Thin Shrink Small Outline Package 612 18-bit TTL/GTLP Universal Bus Transceiver 16 Double-Density, High Drive, ±32mA A Port +34mA B Port 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8 for Tech Support: [email protected] (408) 654-6459