SEMICONDUCTOR TECHNICAL DATA The MPC953 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 87.5MHz and output skews of 150ps the MPC953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and phase jitter. • • • • • LOW VOLTAGE PLL CLOCK DRIVER Fully Integrated PLL Output Frequency up to 87.5MHz Outputs Disable in High Impedance TQFP Packaging 100ps Cycle–to–Cycle Jitter The MPC953 has a differential LVPECL reference input along with an external feedback input. These features make the MPC953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and tristate the output buffers when driven “high”. If the reference clock (PECL_CLK) is lost or shut down when the MPC953 is in phase–lock, the output frquency will slew slowly downward. The final VCO frequency will be around TBDMHz. The MPC953 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50Ω transmission lines. For series terminated 50Ω lines, each of the MPC953 outputs can drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead TQFP package to provide the optimum combination of board density and performance. FA SUFFIX 32–LEAD TQFP PACKAGE CASE 873A–02 QFB PECL_CLK PECL_CLK 7 Phase Detector FB_CLK LPF VCO 200–350MHz Q0:6 ÷4 ÷2 Q7 VCO_SEL BYPASS MR/OE Figure 1. Logic Diagram This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 9/97 Motorola, Inc. 1997 1 REV 0.1 Q1 VCCO Q2 GNDO Q3 VCCO Q4 GNDO MPC953 24 23 22 21 20 19 18 17 GNDO 25 16 Q5 Q0 26 15 VCCO VCCO 27 14 Q6 QFB 28 13 GNDO GNDO 29 12 Q7 NC 30 11 VCCO 1 0 BYPASS 31 10 MR/OE VCO_SEL VCO_SEL 32 FUNCTION TABLES BYPASS 1 0 MPC953 5 FB_CLK NC NC NC 6 7 8 PECL_CLK 4 GNDI 3 NC 2 VCCA 9 1 MR/OE 1 0 PECL_CLK Function PLL Enabled PLL Bypass Function Outputs Disabled Outputs Enabled Function ÷2 ÷1 Figure 2. 32–Lead Pinout (Top View) ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VCC Supply Voltage –0.3 4.6 V VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current ±20 mA TStor Storage Temperature Range 125 °C –40 * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. MOTOROLA 2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MPC953 DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%) Symbol Characteristic Min VIH Input HIGH Voltage LVCMOS Inputs VIL Input LOW Voltage LVCMOS Inputs VPP Peak–to–Peak Input Voltage PECL_CLK VCMR Common Mode Range VOH Output HIGH Voltage VOL Output LOW Voltage IIN Input Current CIN Input Capacitance Cpd Power Dissipation Capacitance ICC Maximum Quiescent Supply Current PECL_CLK Typ Max Unit 3.6 V 0.8 V 300 1000 mV VCC–1.5 VCC–0.6 mV 2.0 2.4 Condition Note 1. V IOH = –40mA, Note 2. 0.5 V IOL = 40mA, Note 2. ±120 µA 4 pF 25 75 pF Per Output mA All VCC Pins ICCPLL Maximum PLL Supply Current 15 20 mA VCCA Pin Only 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the VCMR range and the input swing lies within the VPP specification. 2. The MPC953 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications Info section). PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C) Symbol fref Characteristic Reference Input Frequency Min Max Unit Note 3. Note 3. MHz frefDC Reference Input Duty Cycle 25 75 3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider. Condition % AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%) Symbol Characteristic tr, tf Output Rise/Fall Time tpw Output Duty Cycle tsk(O) Output–to–Output Skews (Relative to QFB) fVCO PLL VCO Lock Range fmax Maximum Output Frequency tpd(lock) Input to Ext_FB Delay (with PLL Locked) tpd(bypass) Input to Q Delay (with PLL Bypassed) tPLZ,HZ Min Typ 0.10 45 Unit 1.0 ns 55 % ±75 ps 200 350 MHz 50 87.5 MHz X+100 ps 10 ns Output Disable Time 7 ns tPZL Output Enable Time 6 ns tjitter Cycle–to–Cycle Jitter (Peak–to–Peak) X–100 50 Max X (Note 4.) 5 tlock Maximum PLL Lock Time 4. X will be targeted for 0ns, but may vary from target by ±150ps based on characterization of silicon. ECLinPS and ECLinPS Lite DL140 — Rev 3 3 100 ps 10 ms Condition 0.8 to 2.0V VCO_SEL = ‘0’ fref = 75MHz MOTOROLA MPC953 be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Power Supply Filtering The MPC953 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC953 provides separate power supplies for the output buffers (VCCO) and the phase–locked loop (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase–locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC953. Driving Transmission Lines The MPC953 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). In most high performance clock networks point–to–point distribution of signals is the method of choice. In a point–to–point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC953 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC953 clock driver is effectively doubled due to its capability to drive multiple lines. Figure 3 illustrates a typical power supply filter scheme. The MPC953 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC953. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 3 must have a resistance of 10–15Ω to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it’s overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. It is recommended that the user start with an 8–10Ω resistor to avoid potential VCC drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed. MPC953 OUTPUT BUFFER IN 7Ω MPC953 OUTPUT BUFFER RS = 43Ω ZO = 50Ω OutA RS = 43Ω ZO = 50Ω OutB0 3.3V IN 7Ω RS = 43Ω RS=5–15Ω ZO = 50Ω OutB1 PLL_VCC 22µF MPC953 0.01µF Figure 4. Single versus Dual Transmission Lines The waveform plots of Figure 5 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC953 output buffers is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the MPC953. The output waveform in Figure 5 shows a step in the waveform, this step is caused VCC 0.01µF Figure 3. Power Supply Filter Although the MPC953 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may MOTOROLA 4 ECLinPS and ECLinPS Lite DL140 — Rev 3 MPC953 by the impedance mismatch seen looking into the driver. The parallel combination of the 43Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. VL = VS ( Zo / (Rs + Ro +Zo)) Zo = 50Ω || 50Ω Rs = 43Ω || 43Ω Ro = 7Ω VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5) = 1.40V MPC953 OUTPUT BUFFER At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). RS = 36Ω ZO = 50Ω RS = 36Ω ZO = 50Ω 7Ω 3.0 VOLTAGE (V) 2.5 OutA tD = 3.8956 7Ω + 36Ω k 36Ω = 50Ω k 50Ω 25Ω = 25Ω OutB tD = 3.9386 Figure 6. Optimized Dual Line Termination 2.0 In SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use. 1.5 1.0 0.5 0 2 4 6 8 TIME (nS) 10 12 14 Figure 5. Single versus Dual Waveforms ECLinPS and ECLinPS Lite DL140 — Rev 3 5 MOTOROLA MPC953 OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX TQFP PACKAGE CASE 873A–02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M_ R J D SECTION AE–AE W K X DETAIL AD Q_ GAUGE PLANE H 0.250 (0.010) C E MOTOROLA M N 0.20 (0.008) SEATING PLANE 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF ECLinPS and ECLinPS Lite DL140 — Rev 3 MPC953 Motorola reserves the right to make changes without further notice to any products herein. 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