SEMICONDUCTOR TECHNICAL DATA The MPC972/973 are 3.3V compatible, PLL based clock driver devices targeted for high performance CISC or RISC processor based systems. With output frequencies of up to 125MHz and skews of 550ps the MPC972/973 are ideally suited for most synchronous systems. The devices offer twelve low skew outputs plus a feedback and sync output for added flexibility and ease of system implementation. • • • • • • LOW VOLTAGE PLL CLOCK DRIVER Fully Integrated PLL Output Frequency up to 125MHz Compatible with PowerPC and Pentium Microprocessors TQFP Packaging 3.3V VCC ± 100ps Typical Cycle–to–Cycle Jitter The MPC972/973 features an extensive level of frequency programmability between the 12 outputs as well as the input vs output relationships. Using the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock edge prior to the coincident edges of the Qa and Qc outputs. The Sync output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies, this allows for very flexible programming of the input reference vs output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non–binary factor. The Power–On Reset ensures proper programming if the frequency select pins are set at power up. If the fselFB2 pin is held high, it may be necessary to apply a reset after power–up to ensure synchronization between the QFB output and the other outputs. The internal power–on reset is designed to provide this function, but with power–up conditions being system dependent, it is difficult to guarantee. All other conditions of the fsel pins will automatically synchronize during PLL lock acquisition. FA SUFFIX 52–LEAD TQFP PACKAGE CASE 848D-03 The MPC972/973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines. The MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen” the outputs will be locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen” the outputs will activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A power-on reset will ensure that upon power up all of the outputs will be active. Note that all of the control inputs on the MPC972/973 have internal pull–up resistors. The MPC972/973 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive 50Ω transmission lines. For series terminated lines each MPC972/973 output can drive two 50Ω lines in parallel thus effectively doubling the fanout of the device. The MPC972/973 can consume significant power in some configurations. Users are encouraged to review Application Note AN1545/D in the Timing Solutions book (BR1333/D) for a discussion on the thermal issues with the MPC family of clock drivers. PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation. 8/97 Motorola, Inc. 1997 1 REV 1 GNDO Qb0 VCCO Qb1 GNDO Qb2 VCCO Qb3 Ext_FB GNDO QFB VCCI fselFB0 MPC972 MPC973 39 38 37 36 35 34 33 32 31 30 29 28 27 fselb1 40 26 fselFB1 fselb0 41 25 QSync fsela1 42 24 GNDO fsela0 43 23 Qc0 Qa3 44 22 VCCO VCCO 45 21 Qc1 Qa2 46 20 fselc0 GNDO 47 19 fselc1 Qa1 48 18 Qc2 VCCO 49 17 VCCO Qa0 50 16 Qc3 GNDO 51 15 GNDO VCO_Sel 52 14 Inv_Clk 9 10 11 12 13 VCCA 8 xtal1 (972) PECL_CLK (973) xtal2 (972) PECL_CLK (973) Frz_Data 7 TClk1 Frz_Clk 6 TClk0 MR/OE 5 TClk_Sel 4 Ref_Sel 3 PLL_EN 2 fselFB2 1 GNDI MPC972/ MPC973 Figure 1. 52–Lead Pinout (Top View) FUNCTION TABLE 1 fsela1 fsela0 Qa fselb1 fselb0 Qb fselc1 fselc0 Qc 0 0 1 1 0 1 0 1 ÷4 ÷6 ÷8 ÷12 0 0 1 1 0 1 0 1 ÷4 ÷6 ÷8 ÷10 0 0 1 1 0 1 0 1 ÷2 ÷4 ÷6 ÷8 FUNCTION TABLE 2 FUNCTION TABLE 3 fselFB2 fselFB1 fselFB0 QFB Control Pin Logic ‘0’ Logic ‘1’ 0 0 0 0 0 0 1 1 0 1 0 1 ÷4 ÷6 ÷8 ÷10 1 1 1 1 0 0 1 1 0 1 0 1 ÷8 ÷12 ÷16 ÷20 VCO_Sel Ref_Sel TCLK_Sel PLL_En MR/OE Inv_Clk VCO/2 TCLK TCLK0 Bypass PLL Master Reset/Output Hi–Z Non–Inverted Qc2, Qc3 VCO Xtal (PECL) TCLK1 Enable PLL Enable Outputs Inverted Qc2, Qc3 MOTOROLA 2 TIMING SOLUTIONS BR1333 — Rev 6 MPC972 MPC973 972 OPTION xtal1 xtal2 VCO_Sel PLL_En REF_SEL D Q TCLK0 0 1 TCLK1 PHASE DETECTOR 0 1 VCO Sync Frz Qa1 Qa2 LPF TCLK_Sel Qa0 Qa3 Ext_FB D Q Sync Frz 973 OPTION Qb0 Qb1 PCLK PCLK Qb2 Qb3 fselFB2 MR/OE D Q POWER-ON RESET D Q ÷2, ÷4, ÷6, ÷8 fselb0:1 fselc0:1 fselFB0:1 2 2 Sync Frz Qc2 Qc3 ÷4, ÷6, ÷8, ÷10 ÷2 2 2 Qc0 Qc1 ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 fsela0:1 Sync Frz 0 1 D Q Sync Frz QFB D Q Sync Frz QSync Sync Pulse Data Generator Frz_Clk Frz_Data Output Disable Circuitry 12 Inv_Clk Figure 2. Logic Diagram TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA MPC972 MPC973 fVCO 1:1 Mode Qa Qc Sync 2:1 Mode Qa Qc Sync 3:1 Mode Qc(÷2) Qa(÷6) Sync 3:2 Mode Qa(÷4) Qc(÷6) Sync 4:1 Mode Qc(÷2) Qa(÷8) Sync 4:3 Mode Qa(÷6) Qc(÷8) Sync 6:1 Mode Qa(÷12) Qc(÷2) Sync Figure 3. Timing Diagrams MOTOROLA 4 TIMING SOLUTIONS BR1333 — Rev 6 MPC972 MPC973 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VCC Supply Voltage –0.3 4.6 V VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current ±20 mA TStor Storage Temperature Range –40 125 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. DC CHARACTERISTICS (Note 4.; TA = 10° to 70°C; VCC = 3.3V ±5%) Symbol Characteristic Min Typ Max Unit 3.6 V 0.8 V mV VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage VPP Peak–to–Peak Input Voltage PECL_CLK 300 1000 VCMR Common Mode Range PECL_CLK VCC–2.0 VCC–0.6 VOH Output HIGH Voltage VOL Output LOW Voltage IIN Input Current ICC Maximum Quiescent Supply Current ICCA Analog VCC Current CIN Input Capacitance Cpd Power Dissipation Capacitance 2.4 Condition Note 1. V IOH = –20mA (Note 2.) 0.5 V IOL = 20mA (Note 2.) ±120 µA Note 3. 190 215 mA All VCC PIns 15 20 mA 4 pF 25 pF Per Output 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 2. The MPC972/973 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications Info section). 3. Inputs have pull–up/pull–down resistors which affect input current. 4. Special thermal handling may be required in some configurations. PLL INPUT REFERENCE CHARACTERISTICS (TA = 10° to 70°C) Symbol Characteristic tr, tf TCLK Input Rise/Falls fref Reference Input Frequency frefDC Reference Input Duty Cycle Min Max Unit 3.0 ns Note 5. 100, Note 5. MHz 25 75 % Condition Note 5. txtal Crystal Oscillator Frequency 10 25 MHz Note 6. 5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100MHz, minimum input reference frequency is limited by the VCO lock range and the feedback divider. 6. See Applications Info section for more crystal information. TIMING SOLUTIONS BR1333 — Rev 6 5 MOTOROLA MPC972 MPC973 AC CHARACTERISTICS (TA = 10° to 70°C; VCC = 3.3V ±5%) Symbol Characteristic tr, tf Output Rise/Fall Time (Note 7.) tpw Output Duty Cycle (Note 7.) tpd SYNC to Feedback Propagation Delay Min Typ 0.15 Max Unit 1.2 ns Condition 0.8 to 2.0V tCYCLE/2 –750 tCYCLE/2 ±500 tCYCLE/2 +750 ps MPC973 TCLK0 TCLK1 PECL_CLK –70 –130 –225 130 70 –25 330 270 175 ps Notes 7., 8.; QFB = ÷8 MPC972 TCLK0 TCLK1 –270 –330 130 70 530 470 550 ps Note 7. 480 MHz 125 120 80 60 MHz tos Output-to-Output Skew fVCO VCO Lock Range fmax Maximum Output Frequency tjitter Cycle–to–Cycle Jitter (Peak–to–Peak) tPLZ, tPHZ Output Disable Time 2 8 ns tPZL, tPZH Output ENable TIme 2 10 ns tlock Maximum PLL Lock Time 10 ms 200 Q (÷2) Q (÷4) Q (÷6) Q (÷8) ±100 ps fMAX Maximum Frz_Clk Frequency 20 MHz 7. 50Ω transmission line terminated into VCC/2. 8. tpd is specified for a 50MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. The tpd does not include jitter. APPLICATIONS INFORMATION reference frequency was equal to the lowest output frequency the feedback output would be set in the ÷10 mode. If the input needed to be half the lowest frequency output the fselFB2 input could be asserted to half the feedback frequency. This action multiplies the output frequencies by two relative to the input reference frequency. With 7 unique feedback divide capabilities there is a tremendous amount of flexibility. Again assume the above 5:3:2 relationship is needed with the highest frequency output equal to 100MHz. If one was also constrained because the only reference frequency available was 50MHz the setup in Figure 8 could be used. The MPC972/973 provides the 100, 66 and 40MHz outputs all synthesized from the 50MHz source. With its multitude of divide ratio capabilities the MPC972/973 can generate almost any frequency from a standard, common frequency already present in a design. Figure 9 and Figure 10 illustrate a few more examples of possible MPC972/973 configurations. The MPC972/973 has one more programming feature added to its arsenal. The Inv_Clk input pin when asserted will invert the Qc2 and Qc3 outputs. This inversion will not affect the output–output skew of the device. This inversion allows for the development of 180° phase shifted clocks. This output could also be used as a feedback output to the MPC972/973 or a second PLL device to generate early or late clocks for a specific design. Figure 11 illustrates the use of two Programming the MPC972/973 The MPC972/973 is the most flexible frequency programming device in the Motorola timing solution portfolio. With three independent banks of four outputs as well as an independent PLL feedback output the total number of possible configurations is too numerous to tabulate. Table 1 tabulates the various selection possibilities for the three banks of outputs. The divide numbers presented in the table represent the divider applied to the output of the VCO for that bank of outputs. To determine the relationship between the three backs the three divide ratios would be compared. For instance if a frequency relationship of 5:3:2 was desired the following selection could be made. The Qb outputs could be set to ÷10, the Qa outputs to ÷6 and the Qc outputs to ÷4. With this output divide selection the desired 5:3:2 relationship would be generated. For situations where the VCO will run at relatively low frequencies the PLL may not be stable for the desired divide ratios. For these circumstances the VCO_Sel pin allows for an extra ÷2 to be added into the clock path. When asserted this pin will maintain the desired output relationships, but will provide an enhanced lock range for the PLL. Once the output frequency relationship is set and the VCO is in its stable range the feedback output would be programmed to match the input reference frequency. The MPC972/973 offers only an external feedback to the PLL. A separate feedback output is provided to optimize the flexibility of the device. If in the example above the input MOTOROLA 6 TIMING SOLUTIONS BR1333 — Rev 6 MPC972 MPC973 following information for static phase offset (SPO) and I/O jitter: the SPO variation will be 300ps (–100ps to +200ps assuming a TCLK is used) and the I/O jitter will be ±105ps (assuming a VCO/6 configuration and a ±3 sigma for min and max). The nominal delay from Figure 5 is 50ps so that the propagation delay between the reference clock and the feedback clock is 50ps ±255ps. MPC972/973’s to generate two banks of clocks with one bank divided by 2 and delayed by 180° relative to the first. Using the MPC973 as a Zero Delay Buffer The external feedback of the MPC973 clock driver allows for its use as a zero delay buffer. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the MPC973 is a function of the configuration used. Figure 4 can now be used to establish the uncertainty between the reference clock and all of the outputs for the MPC973. Figure 4 provides the skew of the MC973 outputs with respect to the feedback output. From Figure 4, if all of the outputs are used the propagation delay of the device will range from –555ps (50ps – 255ps – 350ps) to +705ps (50ps + 255ps + 400ps) for a total uncertainty of 1.26ns. This 1.26ns uncertainty would hold true if multiple 973’s are used in parallel in the application given that the skew between the reference clock for the devices were zero. Notice from the data in Figure 4 that if a subset of the outputs were used significant reductions in uncertainty could be obtained. When used as a zero delay buffer the MPC973 will likely be in a nested clock tree application. For these applications the MPC973 offers a LVPECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The MPC973 then can lock onto the LVPECL reference and translate with near zero delay to low skew LVCMOS outputs. Clock trees implemented in this fashion will show significantly tighter skews than trees developed from CMOS fanout buffers. SYNC Output Description In situations where output frequency relationships are not integer multiples of each other there is a need for a signal for system synchronization purposes. The SYNC output of the MPC972/973 is designed to specifically address this need. The MPC972/973 monitors the relationship between the Qa and the Qc banks of outputs. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the Qa and Qc outputs. The duration and the placement of the pulse is dependent on the higher of the Qa and Qc output frequencies. The timing diagrams in the data sheet show the various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the Qa and Qc outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. To calculate the overall uncertainty between the input reference clock and the output clocks the following approach should be used. Figure 4 through Figure 7 contain the performance information required to calculate the overall uncertainty. Since the overall skew performance is a function of the input reference frequency all of the graphs provide relavent data with respect to the input reference frequency. The overall uncertainty can be broken down into three parts; the static phase offset variation (Tpd), the I/O phase jitter and the output skew. If we assume that we have a 75MHz reference clock, from the graphs we can pull the Table 1. Programmable Output Frequency Relationships (VCO_Sel=‘1’) fsela1 fsela0 Qa fselb1 fselb0 Qb fselc1 fselc0 Qc 0 0 1 1 0 1 0 1 VCO/4 VCO/6 VCO/8 VCO/12 0 0 1 1 0 1 0 1 VCO/4 VCO/6 VCO/8 VCO/10 0 0 1 1 0 1 0 1 VCO/2 VCO/4 VCO/6 VCO/8 Table 2. Programmable Output Frequency Relationships (VCO_Sel=‘1’) TIMING SOLUTIONS BR1333 — Rev 6 fselFB2 fselFB1 fselFB0 QFB 0 0 0 0 0 0 1 1 0 1 0 1 VCO/4 VCO/6 VCO/8 VCO/10 1 1 1 1 0 0 1 1 0 1 0 1 VCO/8 VCO/12 VCO/16 VCO/20 7 MOTOROLA MPC972 MPC973 400 300 200 ps 100 0 –100 –200 –300 –400 Qc3 Qc2 Qc1 Qc0 Qb3 Qb2 Qb1 Qb0 Qa3 Qa2 Qa1 Qa0 Figure 4. Skews Relative to QFB 500 400 400 300 Max Max 200 Tpd (ps) Tpd (ps) 300 200 100 Nom 0 100 0 Nom –100 –100 –200 Min Min –200 –300 10 20 30 40 50 60 70 80 90 100 110 10 20 30 Reference Clock Frequency (MHz) 1σ I/O Jitter (ps) 50 60 70 80 90 100 110 Reference Clock Frequency (MHz) Figure 5. Static Phase Offset versus Reference Frequency Tpd versus TCLK 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 40 Figure 6. Static Phase Offset versus Reference Frequency Tpd versus PECL_CLK VCO/8 VCO/4 VCO/6 30 40 50 60 70 80 90 100 110 Reference Clock Frequency (MHz) Figure 7. Phase Jitter versus Reference Frequency I/O Jitter MOTOROLA 8 TIMING SOLUTIONS BR1333 — Rev 6 MPC972 MPC973 MPC972 ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ ‘1’ ‘0’ MPC972 fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 50MHz Qa Qb Qc 4 ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ 100MHz 4 40MHz 4 66.66MHz QFB 50MHz Input Ref fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 24MHz Qa Qb Qc QFB 4 4 4 60MHz (Processor) 60MHz (Processor) 30MHz (PCI) 24MHz (Floppy Disk Clk) Input Ref Ext_FB Ext_FB VCO = 400MHz Figure 8. Programming Configuration Example Figure 9. Generating Pentium Clocks from Floppy Clock MPC972 ‘1’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ 20MHz fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 Qa Qb Qc 4 33MHz (PCI) 4 50MHz (Processor) 4 50MHz (Processor) QFB 20MHz (Ethernet) Input Ref Ext_FB Figure 10. Generating MPC604 Clocks from Ethernet Clocks MPC972/973 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘1’ ‘0’ ‘1’ fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 Inv_Clk MPC972/973 Qa Qb Qc Qc QFB 4 4 2 2 66MHz 66MHz 66MHz 66MHz ‘0’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 Inv_Clk Qa Qb Qc QFB 4 4 4 33MHz Shifted 90° 33MHz Shifted 90° 33MHz Shifted 90° 66MHz 66MHz 66MHz Input Ref Input Ref Ext_FB 66MHz Ext_FB 33MHz Shifted 90° Figure 11. Phase Delay Using Multiple MPC972/973’s TIMING SOLUTIONS BR1333 — Rev 6 9 MOTOROLA MPC972 MPC973 Using the On–Board Crystal Oscillator Power Supply Filtering The MPC972 features an on–board crystal oscillator to allow for seed clock generation as well as final distribution. The on–board oscillator is completely self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC972 as possible to avoid any board level parasitics. To facilitate co–location surface mount crystals are recommended, but not required. The MPC972/973 is a mixed analog/digital product and exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC972/973 provides separate power supplies for the output buffers (VCCO) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase–locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC972/973. The oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large on–board capacitors. Because the design is a series resonant design for the optimum frequency accuracy a series resonant crystal should be used (see specification table below). Unfortunately most of the shelf crystals are characterized in a parallel resonant mode. However a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel resonant mode. Therefore in the majority of cases a parallel specified crystal can be used with the MPC972 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. Typically a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. For most processor implementations a few hundred ppm translates into kHz inaccuracies, a level which does not represent a major issue. 3.3V RS=5–10Ω VCCA 22µF MPC972/973 0.01µF VCC 0.01µF Figure 12. Power Supply Filter Figure 12 illustrates a typical power supply filter scheme. The MPC972/973 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC972/973. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 12 must have a resistance of 5–10Ω to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it’s overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Table 3. Crystal Specifications Parameter Value Crystal Cut Fundamental AT Cut Resonance Series Resonance* Frequency Tolerance ±75ppm at 25°C Frequency/Temperature Stability ±150pm 0 to 70°C Operating Range 0 to 70°C Shunt Capacitance 5–7pF Equivalent Series Resistance (ESR) 50 to 80Ω Max Correlation Drive Level 100µW Aging 5ppm/Yr (First 3 Years) * See accompanying text for series versus parallel resonant discussion. The MPC972/973 is a clock driver which was designed to generate outputs with programmable frequency relationships and not a synthesizer with a fixed input frequency. As a result the crystal input frequency is a function of the desired output frequency. For a design which utilizes the external feedback to the PLL the selection of the crystal frequency is straight forward; simply chose a crystal which is equal in frequency to the fed back signal. MOTOROLA Although the MPC972/973 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be 10 TIMING SOLUTIONS BR1333 — Rev 6 MPC972 MPC973 combination of the line impedances. The voltage wave launched down the two lines will equal: adequate to eliminate power supply noise related problems in most designs. VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V Driving Transmission Lines The MPC972/973 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 15 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. In most high performance clock networks point–to–point distribution of signals is the method of choice. In a point–to–point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC972/973 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 13 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC972/973 clock driver is effectively doubled due to its capability to drive multiple lines. 3.0 VOLTAGE (V) 2.5 7Ω OutB tD = 3.9386 2.0 In 1.5 1.0 0.5 MPC972/973 OUTPUT BUFFER IN OutA tD = 3.8956 0 RS = 43Ω ZO = 50Ω 2 4 OutA 6 8 TIME (nS) 10 12 14 Figure 14. Single versus Dual Waveforms MPC972/973 OUTPUT BUFFER IN RS = 43Ω MPC972/973 OUTPUT BUFFER ZO = 50Ω OutB0 7Ω ZO = 50Ω RS = 36Ω ZO = 50Ω 7Ω RS = 43Ω ZO = 50Ω OutB1 Figure 13. Single versus Dual Transmission Lines 7Ω + 36Ω k 36Ω = 50Ω k 50Ω 25Ω = 25Ω The waveform plots of Figure 14 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC972/973 output buffers is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the MPC972/973. The output waveform in Figure 14 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43Ω series resistor plus the output impedance does not match the parallel TIMING SOLUTIONS BR1333 — Rev 6 RS = 36Ω Figure 15. Optimized Dual Line Termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use. Using the Output Freeze Circuitry With the recent advent of a “green” classification for computers the desire for unique power management among system designers is keen. The individual output enable 11 MOTOROLA MPC972 MPC973 force a newly–unfrozen clock to a logic ‘1’ state before the time at which it would normally transition there. The logic re–enables the unfrozen clock during the time when the respective clock would normally be in a logic ‘0’ state, eliminating the possibility of ‘runt’ clock pulses. control of the MPC972/973 allows designers, under software control, to implement unique power management schemes into their designs. Although useful, individual output control at the expense of one pin per output is too high, therefore a simple serial interface was derived to economize on the control pins. The freeze control logic provides a mechanism through which the MPC972 clock outputs may be frozen (stopped in the logic ‘0’ state): The freeze mechanism allows serial loading of the 12–bit Serial Input Register, this register contains one program– mable freeze enable bit for 12 of the 14 output clocks. The Qc0 and QFB outputs cannot be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the Serial Input Register. The user may programmably freeze an output clock by writing logic ‘0’ to the respective freeze enable bit. Likewise, the user may programmably unfreeze an output clock by writing logic ‘1’ to the respective enable bit. The freeze logic will never force a newly–frozen clock to a logic ‘0’ state before the time at which it would normally transition there. The logic simply keeps the frozen clock at logic ‘0’ once it is there. Likewise, the freeze logic will never MOTOROLA The user may write to the Serial Input register through the Frz_Data input by supplying a logic ‘0’ start bit followed serially by 12 NRZ freeze enable bits. The period of each Frz_Data bit equals the period of the free–running Frz_Clk signal. The Frz_Data serial transmission should be timed so the MPC972 can sample each Frz_Data bit with the rising edge of the free–running Frz_Clk signal. Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0–D3 are the control bits for Qa0–Qa3, respectively D4–D7 are the control bits for Qb0–Qb3, respectively D8–D10 are the control bits for Qc1–Qc3, respectively D11 is the control bit for QSync Figure 16. Freeze Data Input Protocol 12 TIMING SOLUTIONS BR1333 — Rev 6 MPC972 MPC973 OUTLINE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 848D–03 ISSUE C 4X –X– X=L, M, N 4X TIPS 0.20 (0.008) H L–M N 0.20 (0.008) T L–M N CL 52 AB 40 1 G 39 AB 3X VIEW Y –L– VIEW Y –M– B V B1 13 ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ V1 J 27 14 26 0.13 (0.005) –N– A1 BASE METAL F PLATING M D T L–M U S N S SECTION AB–AB ROTATED 90_ CLOCKWISE S1 A S 4X C θ2 0.10 (0.004) T –H– –T– SEATING PLANE 4X θ3 VIEW AA 0.05 (0.002) S W θ1 2XR R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA TIMING SOLUTIONS BR1333 — Rev 6 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC ––– 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC ––– 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ MOTOROLA MPC972 MPC973 Motorola reserves the right to make changes without further notice to any products herein. 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