PCS5I961C November 2006 rev 0.3 Low Voltage Zero Delay Buffer Features The PCS5I961 configurations. is The offered with PCS5I961C two offers different an input LVCMOS Fully Integrated PLL Up to 200MHz I/O Frequency reference clock. LVCMOS Outputs When pulled high the OE pin will force all of the outputs Outputs Disable in High Impedance (except QFB) into a high impedance state. Because the OE LVCMOS Reference Clock Options pin does not affect the QFB output, down stream clocks LQFP and TQFP Packaging ±50pS Cycle-Cycle Jitter 150pS Output Skews reference clock while the PCS5I961P offers an LVPECL can be disabled without the internal PLL losing lock. The PCS5I961C is fully 2.5V or 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of Functional Description The PCS5I961C is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150pS the device meets the needs of the most demanding clock tree applications. driving terminated 50Ω transmission lines. For series terminated lines the PCS5I961C can drive two lines per output giving the device an effective fanout of 1:36. The device is packaged in a 32 lead LQFP and TQFP Packages. Block Diagram Q0 CCLK 50K 0 50-100 MHz 1 FB FB_IN Q1 PLL Ref 100-200 MHz Q2 Q3 50K Q14 F_RANGE 50K Q15 Q16 OE 50K QFB Figure 1. PCS5I961C Logic Diagram PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS5I961C November 2006 rev 0.3 Q11 Q10 Q9 GND Q8 Q7 Q6 VCC Pin Configuration 24 23 22 21 20 19 18 17 Q5 25 16 VCC Q4 26 15 Q12 Q3 27 14 Q13 GND 28 13 Q14 PCS5I961C Q16 9 QFB 1 2 3 4 5 6 7 8 VCC 10 32 FB_IN 31 OE Q0 VCC VCCA Q15 F_RANGE GND 11 NC 12 30 CCLK 29 Q1 GND Q2 c Figure 2. PCS5I961C 32-Lead Package Pinout (Top View) Table 1: Pin Configuration Pin # Pin Name I/O Type 2 CCLK Input LVCMOS 7 FB_IN Input LVCMOS 4 F_RANGE Input LVCMOS PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Input LVCMOS Output enable/disable Clock outputs 6 OE 31,30,29,27,26,25,23,22,21, 19,18,17,15,14,13,11,10 Q0 - Q16 Output LVCMOS 9 QFB Output LVCMOS 1,12,20,28 GND Supply Ground 5 VCCA Supply VCC 8,16,24,32 VCC Supply VCC 3 NC Function PLL feedback signal output, connect to a FB_IN Negative power supply PLL positive power supply (analog power supply). The PCS5I961C requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Positive power supply for I/O and core Not connected Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 14 PCS5I961C November 2006 rev 0.3 Table 2: FUNCTION TABLE Control Default F_RANGE 0 OE 0 0 PLL high frequency range. PCS5I961C input reference and output clock frequency range is 100 – 200MHz 1 PLL low frequency range. PCS5I961C input reference and output clock frequency range is 50 – 100MHz Outputs enabled Outputs disabled (high–impedance state) Table 3: ABSOLUTE MAXIMUM RATINGS1 Symbol Parameter Min Max Unit VCC Supply Voltage -0.3 3.6 V VIN DC Input Voltage -0.3 VCC + 0.3 V DC Output Voltage -0.3 VCC + 0.3 V ±20 mA ±50 125 mA °C VOUT IIN IOUT TS DC Input Current DC Output Current Storage Temperature Range -40 Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Table 4: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = -40°C to +85°C) Symbol Max Unit Condition VIH Input HIGH Voltage Characteristic Min 2.0 VCC + 0.3 V LVCMOS 0.8 VIL Input LOW Voltage -0.3 VOH Output HIGH Voltage 2.4 VOL Output LOW Voltage ZOUT Output Impedance Typ 14 IIN Input Current CIN Input Capacitance 4.0 V LVCMOS V IOH = –20mA1 0.55 V IOL = 20mA1 20 Ω ±120 µA pF CPD Power Dissipation Capacitance 8.0 10 pF Per Output ICCA Maximum PLL Supply Current 2.0 5.0 mA VCCA Pin ICC VTT Maximum Quiescent Supply Current Output Termination Voltage TBD mA V All VCC Pins VCC÷2 Note: 1. The PCS5I961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines. Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 14 PCS5I961C November 2006 rev 0.3 Table 5: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 40°C to +85°C)1 Symbol Characteristic Min Typ Max Unit fref Input Frequency F_RANGE = 0 F_RANGE = 1 100 50 200 100 MHz fmax Maximum Output Frequency F_RANGE = 0 F_RANGE = 1 100 50 200 100 MHz frefDC Reference Input Duty Cycle tr, tf TCLK Input Rise/Fall Time t(∅) Propagation Delay (static phase offset) tsk(O) 25 CCLK to FB_IN -80 F_RANGE = 0 F_RANGE = 1 42 45 Output–to–Output Skew2 75 % 3.0 nS 0.8 to 2.0V 120 pS PLL locked 90 150 pS 50 50 55 55 % 1.0 nS DCO Output Duty Cycle tr, tf Output Rise/Fall Time tPLZ,HZ Output Disable Time 10 nS tPZL,LZ Output Enable Time 10 nS 0.1 tJIT(CC) Cycle–to–Cycle Jitter RMS (1σ) tJIT(PER) Period Jitter RMS (1σ) tJIT(∅) tlock Condition 3 7.0 I/O Phase Jitter RMS (1σ) Maximum PLL Lock Time 15 pS 10 pS 15 10 nS mS 0.55 to 2.4V Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. See applications section for part–to–part skew calculation 3. See applications section for calculation for other confidence factors than 1σ Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 14 PCS5I961C November 2006 rev 0.3 Table 6: DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C) Symbol Characteristic Min Typ Max Unit Condition V LVCMOS VIH Input HIGH Voltage 1.7 VCC + 0.3 0.7 VIL Input LOW Voltage -0.3 VOH Output HIGH Voltage 1.8 VOL Output LOW Voltage ZOUT Output Impedance IIN 0.6 18 Input Current CIN Input Capacitance 4.0 CPD Power Dissipation Capacitance 8.0 ICCA Maximum PLL Supply Current 2.0 ICC VTT Maximum Quiescent Supply Current Output Termination Voltage V LVCMOS V IOH = –15mA1 V IOL = 15mA1 26 Ω ±120 mA pF 10 pF 5.0 mA VCCA Pin TBD mA V All VCC Pins VCC ÷2 Per Output Note: 1.The PCS5I961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines. Table 7: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = 40°C to +85°C)1 Symbol Characteristic Min fref Input Frequency F_RANGE = 0 F_RANGE = 1 fmax Maximum Output Frequency F_RANGE = 0 F_RANGE = 1 frefDC Reference Input Duty Cycle tr, tf TCLK Input Rise/Fall Time t(∅) Propagation Delay (static phase offset) tsk(O) Max Unit 100 50 Typ 200 100 MHz 100 50 200 100 MHz 25 CCLK to FB_IN -80 F_RANGE = 0 F_RANGE = 1 40 45 2 Output–to–Output Skew 75 % 3.0 nS 0.7 to 1.7V 120 pS PLL locked 90 150 pS 50 50 60 55 % 1.0 nS DCO Output Duty Cycle tr, tf Output Rise/Fall Time tPLZ,HZ Output Disable Time 10 nS tPZL,LZ Output Enable Time 10 nS 0.1 tJIT(CC) Cycle–to–Cycle Jitter RMS (1σ) tJIT(PER) Period Jitter RMS (1σ) tJIT(∅) tlock Condition 3 7.0 I/O Phase Jitter RMS (1σ) Maximum PLL Lock Time 15 pS 10 pS 15 10 nS mS 0.6 to 1.8V Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. 2 See applications section for part–to–part skew calculation 3 See applications section for calculation for other confidence factors than 1σ Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 14 PCS5I961C November 2006 rev 0.3 APPLICATIONS INFORMATION Power Supply Filtering The PCS5I961C is a mixed analog/digital product and as such it exhibits some sensitivity that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The PCS5I961C provides separate power supplies for the output buffers (VCC) and the phase–locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase–locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the PCS5I961C. Figure 3. illustrates a typical power supply filter scheme. The PCS5I961C is most susceptible to noise with spectral content in the 10KHz to 10MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the PCS5I961C. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 2mA (5mA maximum), assuming that a minimum of 2.375V (VCC = 3.3V or VCC = 2.5V) must be maintained on the VCCA pin. The resistor RF shown in Figure 3. must have a resistance of 270Ω (VCC = 3.3V) or 5 to 15Ω (VCC = 2.5V) to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it’s overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. RF = 270Ω for VCC = 3.3V RF = 5-15Ω for VCC = 2.5V RF VCC Driving Transmission Lines The PCS5I961C clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 15Ω the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point–to–point distribution of signals is the method of choice. In a point–to–point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCS5I961C clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4. illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the PCS5I961C clock driver is effectively doubled due to its capability to drive multiple lines. PCS5I961C OUTPUT BUFFER IN 14Ω RS=36Ω PCS5I961C OUTPUT BUFFER IN RS=36Ω 14Ω RS=36Ω Z0=50Ω OUTA Z0=50Ω OUTB0 Z0=50Ω OUTB1 Figure 4. Single versus Dual Transmission Lines VCCA 22 µF may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. 10 nF VCC 33…100 nF Figure 3. Power Supply Filter Although the PCS5I961C has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still The waveform plots of Figure 5. show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the PCS5I961C output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43pS exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the PCS5I961C. The output waveform in Figure 5. shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 14 PCS5I961C November 2006 rev 0.3 output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / (Rs + Ro +Zo)) Zo = 50Ω || 50Ω Rs = 36Ω || 36Ω Ro = 14Ω VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.62V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). 3.0 VOLTAGE (V) 2.5 OutA tD = 3.8956 OutB tD = 3.9386 Nested clock trees are typical applications for the PCS5I961C. Designs using the PCS5I961C as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the PCS5I961C clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of part-to-part skew 2.0 The PCS5I961C zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more PCS5I961C are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: In 1.5 1.0 0.5 tSK(PP) = t(ϕ) + tSK(O) + tPD, LINE(FB) + tJIT(ϕ) CF 0 2 4 6 8 10 12 14 TIME (nS) Figure 5. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6. should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. PCS5I961C OUTPUT BUFFER IN Using the PCS5I961C in zero-delay applications RS=22Ω 14Ω RS=22Ω This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: PCLKCommon tPD,LINE (FB) -t(Ø) QFBDevice 1 tJIT(Ø) Any QDevice 1 +tSK(O) Z0=50Ω +t(Ø QFBDevice 2 Z0=50Ω tJIT(Ø) 14Ω + 22Ω ║ 22Ω = 50Ω ║ 50Ω 25Ω = 25Ω Figure 6. Optimized Dual Line Termination Any QDevice 2 +tSK(O) Max. skew tSK(PP) Figure 7. PCS5I961C max. device-to-device skew Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 14 PCS5I961C November 2006 rev 0.3 Due to the statistical nature of I/O jitter a rms value (1σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8: Confidence Factor CF ± 1σ Probability of clock edge within the distribution 0.68268948 ± 2σ 0.95449988 ± 3σ 0.99730007 ± 4σ 0.99993663 ± 5σ 0.99999943 ± 6σ 0.99999999 CF The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (± 3 σ) is assumed, resulting in a worst case timing uncertainty from input to any output of -275 pS to 315 pS relative to CCLK: tSK(PP) = [–80pS...120pS] + [–150pS...150pS] + [(15pS* –3)...(15pS* 3)] + tPD, LINE(FB) tSK(PP) = [–275pS...315pS] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 8. “Max. I/O Jitter versus frequency” can be used for a more precise timing performance analysis. tjit(Ø)[ps] RMS F_RANGE=0 F_RANGE=1 18 TA = 85°C 16 14 VCC=2.5V 12 VCC=3.3V 10 VCC=3.3V 8 VCC=2.5V 6 4 frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCS5I961C die junction temperature and the associated device reliability. Table 9: Die junction temperature and MTBF Junction temperature (°C) MTBF (Years) 100 20.4 110 9.1 120 130 4.2 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the PCS5I961C needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the PCS5I961C is represented in equation 1. Where ICCQ is the static current consumption of the PCS5I961C, CPD is the power dissipation capacitance per output, (M)ΣCL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the PCS5I961C). The PCS5I961C supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. 2 0 50 70 90 110 130 170 190 150 Clock frequency [MHz] Figure 8. Max. I/O Jitter versus frequency Power Consumption of the PCS5I961C and Thermal Management The PCS5I961C AC specification is guaranteed for the entire operating frequency range up to 200MHz. The PCS5I961C power consumption and the associated longterm reliability may decrease the maximum frequency limit, depending on operating conditions such as clock Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 14 PCS5I961C November 2006 rev 0.3 PTOT = I CCQ + VCC ⋅ f CLOCK ⋅ N ⋅ C PD + ∑ C L ⋅ VCC Equation 1 M PTOT = VCC ⋅ I CCQ + VCC ⋅ f CLOCK ⋅ N ⋅ C PD + ∑ C L + ∑ DC Q ⋅ I OH (VCC − VOH ) + (1 − DC Q ) ⋅ I OL ⋅ VOL Equation 2 M P TJ = T A + PTOT ⋅ Rthja Equation 3 [ f CLOCKMAX = C PD 1 2 ⋅ N ⋅ VCC T − TA ⋅ JMAX − (I CCQ ⋅ VCC ) Rthja Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the PCS5I961C in a series terminated transmission line system. Table 10: Thermal package impedance of the 32LQFP Convection, LFPM Rthja (1P2S board), °C/W Still air 80 100 lfpm 70 200 lfpm 61 300 lfpm 57 400 lfpm 56 500 lfpm 55 TJ,MAX should be selected according to the MTBF system requirements and Table 9. Rthja can be derived from Equation 4 Table 10. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. If the calculated maximum frequency is below 200MHz, it becomes the upper clock speed limit for the given application conditions. The following two derating charts describe the safe frequency operation range for the PCS5I961C. The charts were calculated for a maximum tolerable die junction temperature of 110°C, corresponding to an estimated MTBF of 9.1 years, a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. There are no operating frequency limitations if a 2.5V power supply or the system specifications allow for a MTBF of 4 years (corresponding to a max. junction temperature of 120°C. Operating frequency (MHz) 190 ° TA = 85 C 160 140 120 100 80 Safe operation 60 fMAX (AC) 200 fMAX (AC) 200 Operating frequency (MHz) ] 190 TA = 75°C 160 TA = 85°C 140 120 100 80 Safe operation 60 40 40 20 20 0 0 500 400 200 300 Convection Ifpm 100 0 Figure 9. Maximum PCS5I961C frequency, VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines 500 400 200 300 Convection Ifpm 100 0 Figure 10. Maximum PCS5I961C frequency, VCC = 3.3V, MTBF 9.1 years,4pF load per line Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 14 PCS5I961C November 2006 rev 0.3 Z0=50Ω Pulse Generator Z=50Ω Z0=50Ω RT=50Ω RT=50Ω VTT VTT Figure 11. TCLK PCS5I961C AC test reference for VCC = 3.3V and VCC = 2.5V VCC VCC ÷2 VCC CCLK VCC ÷2 GND GND VCC VCC ÷2 VCC FB_IN GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device VCC ÷2 GND t(Ø) Figure 13. Propagation delay (tPD, static phase offset) test reference Figure 12. Output–to–Output Skew tSK(O) VCC CCLK VCC ÷2 GND FB_IN tP TJIT(Ø) =│T0-T1 mean│ T0 The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles DC= (tP ÷T0 Χ 100%) The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Figure 15.I/O Jitter Figure 14. Output Duty Cycle (DC) TN TN+1 T0 TJIT(PER) =│TN-1/f0│ The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles TJIT(CC) =│TN-TN+1│ Figure 17. Period Jitter The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 16. Cycle-to-cycle Jitter VCC = 3.3V tF VCC = 2.5V 2.4 1.8V 0.55 0.6V tR Figure 18. Output Transition Time Test Reference Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 14 PCS5I961C November 2006 rev 0.3 Package Diagram 32-lead TQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.031 BASE 0.8 BASE Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 14 PCS5I961C November 2006 rev 0.3 32-lead LQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0630 … 1.6 A1 0.0020 0.0059 0.05 0.15 A2 0.0531 0.0571 1.35 1.45 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.20 e a 0.031 BASE 0° 7° 0.8 BASE 0° 7° Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 14 PCS5I961C November 2006 rev 0.3 Ordering Information Marking Part Number Package Type Temperature PCS5I961CG-32-ET PCS5I961CG 32 pin TQFP, Green Industrial PCS5I961CG-32-LT PCS5I961CG 32 pin LQFP – Tape and Reel, Green Industrial Device Ordering Information P C S 5 I 9 6 1 C G - 3 2 - L T R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 14 PCS5I961C November 2006 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5I961C Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Low Voltage Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 14