MOTOROLA MPC9774

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
3.3V/2.5V 1:14 LVCMOS PLL
Order Number: MPC9774/D
Rev 1, 04/2002
MPC9774
Clock Generator
The MPC9774 is a 3.3V or 2.5V compatible, 1:14 PLL based clock
generator targeted for high performance low-skew clock distribution in
mid-range to high-performance networking, computing and telecom
applications. With output frequencies up to 125 MHz and output skews
less than 300 ps1 the device meets the needs of the most demanding
clock applications.
Features
• 1:14 PLL based low-voltage clock generator
•
•
•
•
•
•
•
•
•
•
•
3.3V/2.5V 1:14 LVCMOS
PLL CLOCK GENERATOR
2.5V or 3.3V power supply
Internal power–on reset
Generates clock signals up to 125 MHz
Maximum output skew of 300 ps1
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range 0°C to +85°C
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
Pin and function compatible to the MPC974
Functional Description
The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range.
The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input
relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate
configurable feedback output which allows for a wide variety of of input/output frequency multiplication alternatives. The
VCO_SEL pin provides an extended PLL input reference frequency range.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
The MPC9774 has an internal power–on reset.
The MPC9774 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL)
accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω
transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the
devices an effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP
package.
1. Final specification of this parameter is pending characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
 Motorola, Inc. 2002
1
MPC9774
All input resistors have a value of 25kΩ
Bank A
VCC
CCLK0
0
Ref
CCLK1
VCO
1
CCLK_SEL
QA0
QA1
0
÷2
0
1
÷4
1
CLK
STOP
÷2, ÷4
÷2, ÷4
PLL
QA3
÷4, ÷6
QA4
÷4, ÷6, ÷8, ÷12
200-500 MHz
QA2
Bank B
VCC
QB0
QB1
FB_IN
CLK
STOP
FB
PLL_EN
VCO_SEL
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QB2
QB3
QB4
2
Bank C
CLK
STOP
VCC
CLK_STOP
QC0
QC1
QC2
QC3
VCC
POWER–ON RESET
QFB
MR/OE
NC
VCC
QFB
GND
FB_IN
QB4
VCC
QB3
GND
QB2
VCC
QB1
GND
Figure 1. MPC9774 Logic Diagram
39 38 37 36 35 34 33 32 31 30 29 28 27
QB0
40
26
VCC
VCC
41
25
QA0
NC
42
24
GND
GND
43
23
QA1
QC3
44
22
VCC
VCC
45
21
QA2
20
FSEL_FB1
MPC9774
VCC
QC0
50
16
QA4
GND
51
15
GND
VCO_SEL
52
14
FSEL_FB0
4
5
6
7
8
9
10 11 12 13
VCC_PLL
3
VCC
2
NC
1
CCLK1
VCC
CCLK0
QA3
17
CCLK_SEL
18
49
PLL_EN
48
FSEL_A
QC1
FSEL_C
GND
FSEL_B
19
CLK_STOP
47
GND
GND
MR/OE
QC2
46
Figure 2. MPC9774 52–Lead Package Pinout (Top View)
MOTOROLA
2
TIMING SOLUTIONS
MPC9774
Table 1. PIN CONFIGURATION
Pin
I/O
Type
Function
CCLK0
Input
LVCMOS
PLL reference clock
CCLK1
Input
LVCMOS
Alternative PLL reference clock
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to QFB
CCLK_SEL
Input
LVCMOS
LVCMOS clock reference select
VCO_SEL
Input
LVCMOS
VCO operating frequency select
PLL_EN
Input
LVCMOS
PLL enable/PLL bypass mode select
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
CLK_STOP
Input
LVCMOS
Output enable/clock stop (logic low state)
FSEL_A
Input
LVCMOS
Frequency divider select for bank A outputs
FSEL_B
Input
LVCMOS
Frequency divider select for bank B outputs
FSEL_C
Input
LVCMOS
Frequency divider select for bank C outputs
FSEL_FB[1:0]
Input
LVCMOS
Frequency divider select for the QFB output
QA[4:0]
Output
LVCMOS
Clock outputs (Bank A)
QB[4:0]
Output
LVCMOS
Clock outputs (Bank B)
QC[3:0]
Output
LVCMOS
Clock outputs (Bank C)
QFB
Output
LVCMOS
PLL feedback output. Connect to FB_IN.
GND
Supply
Ground
Negative power supply
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter
for the analog power supply pin VCC_PLL. Please see applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
Table 2. Function Table (MPC9774 configuration controls)
Control
Default
CCLK_SEL
0
Selects CCLK0 as PLL refererence signal input
0
Selects CCKL1 as PLL reference signal input
1
VCO_SEL
0
Selects VCO ÷ 2. The VCO frequency is scaled by a
factor of 2 (high input frequency range)
Selects VCO ÷ 4. The VCO frequency is scaled by a
factor of 4 (low input frequency range).
PLL_EN
1
Test mode with the PLL bypassed. The reference clock is
substituted for the internal VCO output. MPC9774 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Normal operation mode with PLL enabled.
CLK_STOP
1
QA, QB an QC outputs disabled in logic low state. QFB
is not affected by CLK_STOP. CLK_STOP deassertion
may cause the initial output clock pulse to be distorted.
Outputs enabled (active)
MR/OE
1
Outputs disabled (high-impedance state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the internal VCO is tied to its lowest
frequency. The MPC9774 requires reset after any loss of
PLL lock. Loss of PLL lock may occur when the external
feedback path is interrupted. The length of the reset
pulse should be greater than one reference clock cycle
(CCLKx). The device is reset by the internal power–on
reset (POR) circuitry during power–up.
Outputs enabled (active)
VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.
See Table 3 and Table 4 for the device frequency configuration.
TIMING SOLUTIONS
3
MOTOROLA
MPC9774
Table 3. Function Table (Output Dividers Bank A, B, and C)
VCO_SEL
FSEL_A
QA[4:0]
VCO_SEL
FSEL_B
QB[4:0]
VCO_SEL
FSEL_C
QC[3:0]
0
0
VCO ÷ 4
0
0
VCO ÷ 4
0
0
VCO ÷ 8
0
1
VCO ÷ 8
0
1
VCO ÷ 8
0
1
VCO ÷ 12
1
0
VCO ÷ 8
1
0
VCO ÷ 8
1
0
VCO ÷ 16
1
1
VCO ÷ 16
1
1
VCO ÷ 16
1
1
VCO ÷ 24
Table 4. Function Table (QFB)
VCO_SEL
FSEL_B1
FSEL_B0
QFB
0
0
0
VCO ÷ 8
0
0
1
VCO ÷ 16
0
1
0
VCO ÷ 12
0
1
1
VCO ÷ 24
1
0
0
VCO ÷ 16
1
0
1
VCO ÷ 32
1
1
0
VCO ÷ 24
1
1
1
VCO ÷ 48
MOTOROLA
4
TIMING SOLUTIONS
MPC9774
Table 5. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
VCC ÷ 2
VTT
MM
Output termination voltage
ESD protection (Machine model)
200
HBM
ESD protection (Human body model)
2000
V
Latch-up immunity
200
mA
LU
Condition
V
V
CPD
Power dissipation capacitance
12
pF
Per output
CIN
Input capacitance
4.0
pF
Inputs
Table 6. Absolute Maximum Ratingsa
Symbol
Min
Max
Unit
VCC
Supply Voltage
-0.3
3.6
V
VIN
DC Input Voltage
-0.3
VCC + 0.3
V
DC Output Voltage
-0.3
VOUT
IIN
IOUT
a.
Characteristics
VCC + 0.3
V
DC Input Current
±20
mA
DC Output Current
±50
mA
Condition5
TS
Storage temperature
-65
125
°C
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 7. DC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to +85°C)
Symbol
VCC_PLL
VIH
b.
Min
2.325
Input high voltage
2.0
VIL
VOH
Input low voltage
VOL
Output Low Voltage
ZOUT
IIN
Output impedance
Input Currentb
ICC_PLL
ICCQ
a.
Characteristics
PLL supply voltage
Output High Voltage
Typ
Max
Unit
VCC
VCC + 0.3
V
LVCMOS
V
LVCMOS
0.8
V
LVCMOS
V
IOH = -24 mAa
IOL = 24 mA
IOL = 12 mA
2.4
0.55
0.30
Ω
14 - 17
Maximum PLL Supply Current
3.0
V
V
Condition
±200
µA
5.0
mA
VIN = VCC or GND
VCC_PLL Pin
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
The MPC9774 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
Inputs have pull-down or pull-up resistors affecting the input current.
TIMING SOLUTIONS
5
MOTOROLA
MPC9774
Table 8. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to + 85°C)a b
Symbol
fref
Characteristics
Input reference frequency
Min
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
Typ
25.0
16.6
12.5
8.33
6.25
4.16
Input reference frequency in PLL bypass modec
fVCO
fMAX
VCO frequency ranged
frefDC
tr, tf
Reference Input Duty Cycle
t(∅)
tsk(O)
DC
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(∅)
BW
a
b
c
d
e
f
g
Output Frequency
÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
Max
Unit
62.5
41.6
31.25
20.83
15.625
10.41
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
PLL bypass
TBD
MHz
200
500
MHz
50.0
25.0
16.6
12.5
8.33
125.0
62.5
41.6
31.25
20.83
MHz
MHz
MHz
MHz
MHz
40
CCLKx Input Rise/Fall Time
Output duty cycle
45
Output Rise/Fall Time
0.1
50
Output Disable Time
Output Enable Time
60
%
ns
0.8 to 2.0V
ps
PLL locked
300
ps
55
%
1.0
ns
8
ns
8
ns
Cycle-to-cycle jitter
RMS (1 σ)f
TBD
ps
Period Jitter
RMS (1 σ)
TBD
ps
I/O Phase Jitter
RMS (1 σ)
TBD
PLL closed loop bandwidthg
PLL locked
1.0
±150
Propagation Delay (static phase offset)
CCLKx or FB_IN
Output-to-output Skewe
Condition
0.55 to 2.4V
ps
kHz
tLOCK
Maximum PLL Lock Time
10
ms
All AC characteristics are design targets and subject to change upon device characterization.
AC characteristics apply for parallel output termination of 50Ω to VTT.
In bypass mode, the MPC9774 divides the input reference clock.
The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M ⋅ VCO_SEL).
See application section for part-to-part skew calculation.
See application section for a jitter calculation for other confidence factors than 1 σ.
-3 dB point of PLL transfer characteristics.
MOTOROLA
6
TIMING SOLUTIONS
MPC9774
Table 9. DC Characteristics (VCC = 2.5V ± 5%, TA = 0°C to + 85°C)
Symbol
VCC_PLL
VIH
Typ
2.325
Max
Unit
V
LVCMOS
V
LVCMOS
V
LVCMOS
V
IOH =-15 mAa
IOL = 15 mA
Input high voltage
1.7
VIL
VOH
Input low voltage
-0.3
0.7
Output High Voltage
1.8
VOL
ZOUT
Output Low Voltage
ICC_PLL
ICC
b.
Min
VCC
VCC + 0.3
IIN
a.
Characteristics
PLL supply voltage
0.6
Output impedance
Input Currentb
V
W
17 - 20
Maximum PLL Supply Current
2.0
Maximum Quiescent Supply Current
Condition
±200
µA
5.0
mA
VIN = VCC or GND
VCCA Pin
1.0
mA
All VCC Pins
The MPC9774 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per
output.
Inputs have pull-down or pull-up resistors affecting the input current.
Table 10. AC Characteristics (VCC = 2.5V ± 5%, TA = 0°C to + 85°C)a b
Symbol
fref
Characteristics
Input reference frequency
Min
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
Typ
25.0
16.6
12.5
8.33
6.25
4.16
Input reference frequency in PLL bypass modec
fVCO
fMAX
VCO frequency ranged
frefDC
tr, tf
Reference Input Duty Cycle
t(∅)
tsk(O)
DC
Output Frequency
÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
Max
Unit
50.0
33.3
25.0
16.6
12.5
8.3
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
PLL bypass
TBD
MHz
200
400
MHz
50.0
25.0
16.6
12.5
8.33
100.0
50.0
33.3
25.0
16.6
MHz
MHz
MHz
MHz
MHz
40
60
%
1
ns
0.7 to 1.7V
ps
PLL locked
CCLKx Input Rise/Fall Time
±150
Propagation Delay (static phase offset)
CCLKx or PCLK to FB_IN
Output-to-output Skewe
ps
55
%
1.0
ns
10
ns
10
ns
45
tr, tf
tPLZ, HZ
tPZL, LZ
Output Rise/Fall Time
0.1
tJIT(CC)
tJIT(PER)
Cycle-to-cycle jitter
RMS (1 σ)f
TBD
ps
Period Jitter
RMS (1 σ)
TBD
ps
I/O Phase Jitter
RMS (1 σ)
TBD
a.
b.
c.
d.
e.
f.
g.
50
300
Output duty cycle
tJIT(∅)
BW
Output Disable Time
Output Enable Time
PLL closed loop bandwidthg
Condition
PLL locked
0.6 to 1.8V
ps
TBD
kHz
tLOCK
Maximum PLL Lock Time
10
ms
All AC characteristics are design targets and subject to change upon device characterization.
AC characteristics apply for parallel output termination of 50Ω to VTT.
In bypass mode, the MPC9774 divides the input reference clock.
The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M ⋅ VCO_SEL).
See application section for part-to-part skew calculation.
See application section for a jitter calculation for other confidence factors than 1 σ.
-3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
7
MOTOROLA
MPC9774
APPLICATIONS INFORMATION
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio. The output frequency for each
bank can be derived from the VCO frequency and the output
divider:
MPC9774 Configurations
Configuring the MPC9774 amounts to properly configuring
the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
fQA[4:0] = fVCO ÷ (VCO_SEL ⋅ NA)
fQB[4:0] = fVCO ÷ (VCO_SEL ⋅ NB)
fQC[3:0] = fVCO ÷ (VCO_SEL ⋅ NC)
fOUT = fREF ⋅ M ÷ N
fREF
÷VCO_SEL
PLL
fOUT
÷N
Table 11. MPC9774 Divider
÷M
where fREF is the reference frequency of the selected input
clock source (CCLKO or CCLK1), M is the PLL feedback
divider and N is a output divider. M is configured by the
FSEL_FB[0:1] and N is individually configured for each
output bank by the FSEL_A, FSEL_B and FSEL_C inputs.
The PLL post-divider VCO_SEL is either a divide-by-two
or a divide-by-four and can be used to situate the VCO into
the specified frequency range. This divider is controlled by
Figure 3. Example Configuration
0
0
0
1
0
10
VCO_SEL
Values
M
PLL feedback
FSEL_FB[0:2]
÷2
8, 12, 16, 24
÷4
16, 24, 32, 48
Bank A Output
Divider FSEL_A
÷2
4, 8
÷4
8, 16
NB
Bank B Output
Divider FSEL_B
÷2
4, 8
÷4
8, 16
NC
Bank C Output
Divider FSEL_C
÷2
8, 12
÷4
16, 24
1. The VCO frequency range for 2.5V operation is specified
from 200 to 400 MHz.
Table 11 shows the various PLL feedback and output
dividers. The output dividers for the three output banks allow
the user to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1
frequency ratios. Figure 3 and Figure 4 display example
configurations for the MPC9774:
(fREF ⋅ VCO_SEL ⋅ M) fVCO,MAX
fref = 20.83 MHz
Function
NA
The reference frequency fREF and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. fREF and M must be configured to match the VCO
frequency range of 200 to 5001 MHz (VCC = 3.3V) in order to
achieve stable PLL operation:
fVCO,MIN
Divider
Figure 4. Example Configuration
CCLK0
CCLK1
CCLK_SEL
QA[4:0]
VCO_SEL
FB_IN
QB[4:0]
62.5 MHz
0
FSEL_A
QC[3:0]
FSEL_B
FSEL_C
QFB
FSEL_FB[1:0]
62.5 MHz
0
1
1
01
fref = 25 MHz
125 MHz
0
CCLK0
CCLK1
CCLK_SEL
QA[4:0]
100 MHz
VCO_SEL
FB_IN
QB[4:0]
50 MHz
FSEL_A
QC[3:0]
FSEL_B
FSEL_C
QFB
FSEL_FB[1:0]
MPC9774
33.3 MHz
MPC9774
20.83 MHz (Feedback)
25 MHz (Feedback)
MPC9774 example configuration (feedback of
QFB = 20.83 MHz, VCO_SEL = ÷2, M = 12, NA =
2, NB = 4, NC = 4, fVCO = 500 MHz).
MPC9774 example configuration (feedback of
QFB = 25 MHz, VCO_SEL = ÷2, M = 8, NA = 2,
NB = 4, NC = 6, fVCO = 400 MHz).
Frequency range
Min
Max
Frequency range
Min
Max
Input
8.33 MHz
20.83 MHz
Input
20 MHz
48 MHz
QA outputs
50 MHz
125 MHz
QA outputs
50 MHz
120 MHz
QB outputs
25 MHz
62.5 MHz
QB outputs
50 MHz
120 MHz
QC outputs
25 MHz
62.5 MHz
QC outputs
100 MHz
200 MHz
MOTOROLA
8
TIMING SOLUTIONS
MPC9774
Using the MPC9774 in zero-delay applications
Table 12. MPC9774 Divider
Nested clock trees are typical applications for the
MPC9774. Designs using the MPC9774 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback of the
MPC9774 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
The MPC9774 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9774 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -495 ps to 495 ps2 relative to CCLK:
Calculation of part-to-part skew
tSK(PP) = t( ∅) + tSK(O) + tPD, LINE(FB) + tJIT( ∅)
CF
tSK(PP) =
[–300ps...300ps] + [–150ps...150ps] +
[(15ps @ –3)...(15ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–495ps...495ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 6
can be used for a more precise timing performance analysis.
TBD.
See MPC961C application section for an example I/O jitter characteristic
CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 6.
2. Final skew data pending specification
CCLKCommon
QFBDevice 1
Driving Transmission Lines
tPD,LINE(FB)
–t(∅)
The MPC9774 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC ÷ 2.
tJIT(∅)
Any QDevice 1
±tSK(O)
+t(∅)
QFBDevice2
Any QDevice 2
Max. skew
tJIT(∅)
±tSK(O)
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9774 clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 7 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9774 clock driver is effectively doubled
due to its capability to drive multiple lines.
tSK(PP)
Figure 5. MPC9774 max. device-to-device skew
Due to the statistical nature of I/O jitter a rms value (1 σ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 12.
TIMING SOLUTIONS
9
MOTOROLA
MPC9774
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
MPC9774
OUTPUT
BUFFER
RS = 36Ω
14Ω
2.5
OutA
tD = 3.8956
OutB
tD = 3.9386
OutA
MPC9774
OUTPUT
BUFFER
IN
ZO = 50Ω
RS = 36Ω
VOLTAGE (V)
IN
3.0
ZO = 50Ω
OutB0
2.0
In
1.5
1.0
14Ω
RS = 36Ω
ZO = 50Ω
OutB1
0.5
0
Figure 7. Single versus Dual Transmission Lines
2
The waveform plots in Figure 8 “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9774 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9774. The output waveform in Figure 8 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
6
8
TIME (nS)
10
12
14
Figure 8. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 9 “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is
perfectly matched.
MPC9774
OUTPUT
BUFFER
RS = 22Ω
ZO = 50Ω
RS = 22Ω
ZO = 50Ω
14Ω
= VS ( Z0 ÷ (RS + R0 + Z0))
= 50Ω || 50Ω
= 36Ω || 36Ω
= 14Ω
= 3.0 ( 25 ÷ (18 + 17 + 25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
VL
Z0
RS
R0
VL
MOTOROLA
4
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 9. Optimized Dual Line Termination
10
TIMING SOLUTIONS
MPC9774
whose spectral content is above 100 kHz. In the example RC
filter shown in MPC9774, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
Power Supply Filtering
The MPC9774 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL power supply impacts the device
characteristics, for instance I/O jitter. The MPC9774 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCC_PLL) of the device.The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
VCC_PLL pin for the MPC9774. Figure 10 illustrates a typical
power supply filter scheme. The MPC9774 frequency and
phase stability is most susceptible to noise with spectral
content in the 100 kHz to 20 MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor RF. From the data sheet
the ICC_PLL current (the current sourced through the
VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming
that a minimum of 2.325V (VCC = 3.3V or VCC = 2.5V) must
be maintained on the VCC_PLL pin. The resistor RF shown in
MPC9774 must have a resistance of 9-10Ω (VCC = 2.5V) to
meet the voltage drop criteria.
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
CF = 22 µF
RF = 9–10Ω
RF
VCC_PLL
VCC
CF
10 nF
MPC9774
VCC
33...100 nF
Figure 10. VCC Power Supply Filter
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9774 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
MPC9774 DUT
Pulse
Generator
Z = 50
Z = 50Ω
Z = 50Ω
W
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 11. CCLK MPC9774 AC test reference for Vcc = 3.3V and Vcc = 2.5V
TIMING SOLUTIONS
11
MOTOROLA
MPC9774
VCC
VCC 2
B
GND
VCC
VCC 2
B
CCLKx
VCC
VCC 2
B
GND
GND
VCC
VCC 2
B
FB_IN
tSK(O)
GND
The pin–to–pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a
single device
t(∅)
Figure 12. Output–to–output Skew tSK(O)
Figure 13. Propagation delay (t(∅), static phase
offset) test reference
VCC
VCC 2
B
CCLKx
GND
tP
FB_IN
T0
DC = tP /T0 x 100%
TJIT(∅) = |T0 –T1 mean|
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
Figure 15. I/O Jitter
Figure 14. Output Duty Cycle (DC)
TN
TN+1
tJIT(CC) = |TN – TN + 1 |
T0
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 16. Cycle–to–cycle Jitter
tF
tJIT(PER) = |TN – (1 ÷ f0 )|
Figure 17. Period Jitter
VCC = 3.3V
2.4
VCC = 2.5V
1.8V
0.55
0.6V
tR
Figure 18. Output Transition Time Test Reference
MOTOROLA
12
TIMING SOLUTIONS
MPC9774
OUTLINE DIMENSIONS
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D-03
ISSUE D
4X
4X 13 TIPS
0.20 (0.008) H L–M N
0.20 (0.008) T L–M N
52
40
1
–X–
X=L, M, N
39
3X
CL
VIEW Y
–L–
AB
–M–
B
G
V
AB
B1
13
VIEW Y
V1
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4 DATUMS –L–, –M– AND –N– TO BE DETERMINED
AT DATUM PLANE –H–.
5 DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –T–.
6 DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7 DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
27
14
26
–N–
A1
S1
A
S
4X
C
q2
0.10 (0.004) T
–H–
–T–
SEATING
PLANE
4X
q3
VIEW AA
0.05 (0.002)
S
W
2X R
q1
R1
0.25 (0.010)
C2
q
GAGE PLANE
K
C1
E
VIEW AA
BASE METAL
F
PLATING
Z
J
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
0.13 (0.005)
U
M
D
T L–M
S
N
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
θ
θ1
θ2
θ3
MILLIMETERS
MIN
MAX
10.00 BSC
5.00 BSC
10.00 BSC
5.00 BSC
–––
1.70
0.05
0.20
1.30
1.50
0.20
0.40
0.45
0.75
0.22
0.35
0.65 BSC
0.07
0.20
0.50 REF
0.08
0.20
12.00 BSC
6.00 BSC
0.09
0.16
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
0_
7_
–––
0_
12 _ REF
12 _ REF
INCHES
MIN
MAX
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
–––
0.067
0.002
0.008
0.051
0.059
0.008
0.016
0.018
0.030
0.009
0.014
0.026 BSC
0.003
0.008
0.020 REF
0.003
0.008
0.472 BSC
0.236 BSC
0.004
0.006
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
0_
7_
–––
0_
12 _ REF
12 _ REF
S
SECTION AB–AB
ROTATED 90_ CLOCKWISE
TIMING SOLUTIONS
13
MOTOROLA
MPC9774
NOTES
MOTOROLA
14
TIMING SOLUTIONS
MPC9774
NOTES
TIMING SOLUTIONS
15
MOTOROLA
MPC9774
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA and the
logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2002.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334
Technical Information Center: 1–800–521–6274
HOME PAGE: http://www.motorola.com/semiconductors/
MOTOROLA
◊
16
MPC9774/D
TIMING
SOLUTIONS