MOTOROLA MPC93R52

MOTOROLA
Order Number: MPC93R52/D
Rev 2, 04/2003
SEMICONDUCTOR TECHNICAL DATA
3.3V 1:11 LVCMOS Zero Delay
Clock Generator
The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output
frequencies up to 240 MHz and output skews lower than 200 ps the
device meets the needs of most demanding clock applications.
Features
Configurable 11 outputs LVCMOS PLL clock generator
•
•
•
•
Fully integrated PLL
Wide range of output clock frequency of 16.67 MHz to 240 MHz
Multiplication of the input reference clock frequency by 3, 2, 1, 3
2 3, 1 3 and 1 2
• 3.3V LVCMOS compatible
B B
B
MPC93R52
LOW VOLTAGE
3.3V LVCMOS 1:11
CLOCK GENERATOR
B2,
• Maximum output skew of 200 ps
• Supports zero–delay applications
• Designed for high–performance telecom, networking and computing
applications
• 32 lead LQFP package
• Ambient Temperature Range – 0°C to +70°C
• Pin and function compatible to the MPC952
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
Functional Description
The MPC93R52 is a fully 3.3V compatible PLL clock generator and
clock driver. The device has the capability to generate output clock
signals of 16.67 to 240 MHz from external clock sources. The internal PLL
optimized for its frequency range and does not require external look filter
components. One output of the MPC93R52 has to be connected to the
PLL feedback input FB_IN to close the external PLL feedback path. The
output divider of this output setting determines the PLL frequency
multiplication factor. This multiplication factor, F_RANGE and the
reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be
configured individually for all three output banks by the FSELx pins
supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50Ω transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93R52 is package in a 32 ld LQFP.
 Motorola, Inc. 2003
1
MPC93R52
CCLK
CCLK
÷2
1
÷6
1
0
÷4
0
QA0
QA1
Ref
PLL
FB_IN
Bank A
1
VCO 0
QA2
FB
QA3
÷2
200 – 480 MHz
QA4
PLL_EN
Bank B
QB0
1
F_RANGE
QB1
0
FSELA
QB2
QB3
FSELB
Bank C
1
QC0
FSELC
QC1
0
POWER–ON RESET
MR/OE
W
(all input resistors have a value of 25k )
GND
QB1
QB0
VCC
VCC
QA4
QA3
GND
Figure 1. MPC93R52 Logic Diagram
24
23
22
21
20
19
18
17
VCC
25
16
VCC
QB2
26
15
QA2
QB3
27
14
QA1
GND
28
13
GND
MPC93R52
GND
29
12
QA0
QC0
30
11
VCC
QC1
31
10
VCCA
VCC
32
FSELB
FSELA
6
7
8
FB_IN
FSELC
5
GND
4
CCLK
3
MR/OE
2
F_RANGE
9
1
PLL_EN
It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see application section for details.
Figure 2. MPC93R52 32–Lead Package Pinout (Top View)
MOTOROLA
2
TIMING SOLUTIONS
MPC93R52
Table 1: PIN CONFIGURATION
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
F_RANGE
Input
LVCMOS
PLL frequency range select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high–impedance tristate) and device reset
QA0–4, QB0–3, QC0–1
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply
VCCA
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an
external RC filter for the analog power supply pin VCCA. Please see
applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2: FUNCTION TABLE
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 1 and Table 2 for supported frequency ranges and output to input frequency ratios.
F_RANGE
0
VCO ÷ 1 (High input frequency range)
VCO ÷ 2 (Low input frequency range)
FSELA
0
Output divider ÷ 4
Output divider ÷ 6
FSELB
0
Output divider ÷ 4
Output divider ÷ 2
FSELC
0
Output divider ÷ 2
Output divider ÷ 4
MR/OE
0
Outputs enabled (active)
Outputs disabled (high–impedance state) and
reset of the device. During reset, the PLL
feedback loop is open and the VCO is operating
at its lowest frequency. The MPC93R52 requires
reset after any loss of PLL lock. Loss of PLL
lock may occur when the external feedback path
is interrupted. The length of the reset pulse
should be greater than two reference clock
cycles (CCLK). The device is reset by the
internal power–on reset (POR) circuitry during
power–up.
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is
substituted for the internal VCO output.
MPC93R52 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
TIMING SOLUTIONS
3
MOTOROLA
MPC93R52
Table 3: GENERAL SPECIFICATIONS
Symbol
Characteristics
Min
Typ
Max
Unit
Output Termination Voltage
ESD Protection (Machine Model)
200
HBM
ESD Protection (Human Body Model)
2000
V
Latch–Up Immunity
200
mA
LU
VCC
B2
VTT
MM
Condition
V
V
CPD
Power Dissipation Capacitance
10
pF
Per output
CIN
Input Capacitance
4.0
pF
Inputs
Table 4: ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
-0.3
3.9
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
DC Output Voltage
-0.3
VOUT
IIN
IOUT
VCC+0.3
V
DC Input Current
±20
mA
DC Output Current
±50
mA
Condition
TS
Storage Temperature
-65
125
°C
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 5: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0° to 70°C)
Symbol
a
b
c
Characteristics
VIH
VIL
Input high voltage
VOH
VOL
Output High Voltage
ZOUT
IIN
Output impedance
Input Currentb
ICCA
ICCQc
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Min
Typ
2.0
Input low voltage
Max
Unit
VCC + 0.3
0.8
V
LVCMOS
V
LVCMOS
V
IOH=-24 mAa
IOL= 24 mA
IOL= 12 mA
2.4
Output Low Voltage
0.55
0.30
14 - 17
V
V
W
Condition
±200
µA
3.0
5.0
mA
VIN=VCC or VIN=GND
VCCA Pin
7.0
10
mA
All VCC Pins
The MPC93R52 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
Inputs have pull-down resistors affecting the input current.
ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
MOTOROLA
4
TIMING SOLUTIONS
MPC93R52
Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0° to 70°C)a
Symbol
Characteristics
Min
Max
Unit
fref
Input reference frequency in PLL modebc ÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
50.0
33.3
25.0
16.67
120.0
80.0
60.0
40.0
MHz
MHz
MHz
MHz
Input reference frequency in PLL bypass moded
VCO lock frequency rangee
50.0
250.0
MHz
200
480
MHz
100
50
33.3
25
16.67
240
120
80
60
40
MHz
MHz
MHz
MHz
MHz
fVCO
fMAX
tPWMIN
tr, tf
t(∅)
tsk(O)
DC
2.0
Propagation Delay CCLK to FB_IN
(fref = 50MHz)
(static phase offset)
Output-to-output Skewh
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
ns
-100
0.8 to 2.0V
+200
ps
ps
PLL locked
150
100
100
50
ps
ps
ps
ps
53
%
1.0
ns
8
ns
Output Rise/Fall Time
0.1
10
ns
tJIT(CC)
Cycle-to-cycle jitter
output frequencies mixed
all outputs same frequency
450
100
ps
ps
Period Jitter
output frequencies mixed
all outputs same frequency
450
100
ps
ps
BW
50
ns
tr, tf
tPLZ, HZ
tPZL, LZ
Output Disable Time
Output Enable Time
÷4 feedback divider RMS (1 σ)
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
PLL closed loop bandwidthj
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
I/O Phase Jitteri
Condition
1.0
47
tJIT(∅)
h
i
j
Minimum Reference Input Pulse Width
CCLK Input Rise/Fall Timeg
Output duty cycle
tJIT(PER)
a
b
c
d
e
f
g
÷2 outputf
÷4 output
÷6 output
÷8 output
÷12 output
Output Frequency
Typ
40
50
60
80
ps
ps
ps
ps
2.0–8.0
1.0–4.0
0.8–2.5
0.6–1.5
MHz
MHz
MHz
MHz
0.55 to 2.4V
tLOCK
Maximum PLL Lock Time
10
ms
AC characteristics apply for parallel output termination of 50Ω to VTT.
PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation.
The PLL may be unstable with a divide by 2 feedback ratio.
In PLL bypass mode, the MPC93R52 divides the input reference clock.
The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
See Table 9 and Table 10 for output divider configurations.
The MPC93R52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t(∅), can only be guaranteed if
tr/tf are within the specified range.
See application section for part-to-part skew calculation.
See application section for a jitter calculation for other confidence factors than 1 s.
-3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
5
MOTOROLA
MPC93R52
APPLICATIONS INFORMATION
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2
as well as 2:3, 3:1 and 2:1. Table 1 illustrates the various
output configurations and frequency ratios supported by the
MPC93R52. See also Table 9, Table 10 and Figure 3 to
Figure 6 for further reference. A ÷2 output divider cannot be
used for feedback.
Programming the MPC93R52
The MPC93R52 supports output clock frequencies from
16.67 to 240 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 480 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
Table 9: MPC93R52 Example Configuration (F_RANGE = 0)
PLL Feedback
VCO ÷ 4b
VCO ÷ 6c
a.
b.
c.
frefa [MHz]
FSELA
FSELB
FSELC
50-120
0
0
0
fref
(50-120 MHz)
fref
0
0
1
fref
(50-120 MHz)
1
0
0
fref ⋅ 2÷3 (33-80 MHz)
1
0
1
1
0
1
0
1
1
33.3-80
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
(50-120 MHz)
fref ⋅ 2 (100-240 MHz)
fref
(50-120 MHz)
fref
fref
(50-120 MHz)
fref ⋅ 2 (100-240 MHz)
fref ⋅ 2÷3 (33-80 MHz)
fref
(50-120 MHz)
fref
0
fref
(33-80 MHz)
fref ⋅3÷2 (50-120 MHz)
fref ⋅ 3 (100-240 MHz)
1
fref
(33-80 MHz)
fref ⋅3÷2 (50-120 MHz)
fref ⋅3÷2 (50-120 MHz)
1
0
fref
(33-80 MHz)
fref ⋅ 3 (100-240 MHz)
fref ⋅ 3 (100-240 MHz)
1
1
fref
(33-80 MHz)
fref ⋅ 3 (100-240 MHz)
fref ⋅3÷2 (50-120 MHz)
(50-120 MHz)
(50-120 MHz)
fref is the input clock reference frequency (CCLK)
QAx connected to FB_IN and FSELA=0
QAx connected to FB_IN and FSELA=1
Table 10: MPC93R52 Example Configurations (F_RANGE = 1)
PLL Feedback
VCO ÷ 8b
VCO ÷ 12c
a.
b.
c.
frefa [MHz]
FSELA
FSELB
FSELC
25-60
0
0
0
fref
(25-60 MHz)
fref
0
0
1
fref
(25-60 MHz)
1
0
0
fref ⋅2÷3 (16-40 MHz)
1
0
1
1
0
1
0
1
1
16.67-40
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
(25-60 MHz)
fref ⋅ 2 (50-120 MHz)
fref
(25-60 MHz)
fref
fref
(25-60 MHz)
fref ⋅ 2 (50-120 MHz)
fref ⋅2÷3 (16-40 MHz)
fref
(25-60 MHz)
fref
0
fref
(16-40 MHz)
fref ⋅3÷2 (25-60 MHz)
fref ⋅ 3 (50-120 MHz)
1
fref
(16-40 MHz)
fref ⋅3÷2 (25-60 MHz)
fref ⋅3÷2 (25-60 MHz)
1
0
fref
(16-40 MHz)
fref ⋅ 3 (50-120 MHz)
fref ⋅ 3 (50-120 MHz)
1
1
fref
(16-40 MHz)
fref ⋅ 3 (50-120 MHz)
fref ⋅3÷2 (25-60 MHz)
(25-60 MHz)
(25-60 MHz)
fref is the input clock reference frequency (CCLK)
QAx connected to FB_IN and FSELA=0
QAx connected to FB_IN and FSELA=1
MOTOROLA
6
TIMING SOLUTIONS
MPC93R52
Example Configurations for the MPC93R52
Figure 3. MPC93R52 Default Configuration
fref = 100 MHz
FB_IN
QA0
QA1
QA2
QA3
QA4
FSELA
FSELB
FSELD
QB0
QB1
QB2
QB3
100 MHz
QC0
QC1
200 MHz
CCLK
F_RANGE
MPC93R52
Figure 4. MPC93R52 Zero Delay Buffer Configuration
fref = 62.5 MHz
62.5 MHz
FB_IN
QA0
QA1
QA2
QA3
QA4
FSELA
FSELB
FSELC
QB0
QB1
QB2
QB3
62.5 MHz
F_RANGE
QC0
QC1
62.5 MHz
CCLK
100 MHz
VCC
MPC93R52
100 MHz (Feedback)
62.5 MHz (Feedback)
MPC93R52 default configuration (feedback of QB0 = 100
MHz). All control pins are left open.
MPC93R52 zero–delay (feedback of QB0 = 62.5 MHz).
All control pins are left open except FSELC = 1. All outputs are locked in frequency and phase to the input clock.
Frequency range
Min
Max
Frequency range
Min
Max
Input
50 MHz
120 MHz
Input
50 MHz
120 MHz
QA outputs
50 MHz
120 MHz
QA outputs
50 MHz
120 MHz
QB outputs
50 MHz
120 MHz
QB outputs
50 MHz
120 MHz
QC outputs
100 MHz
240 MHz
QC outputs
50 MHz
120 MHz
Figure 5. MPC93R52 Default Configuration
fref = 33.3 MHz
VCC
VCC
FB_IN
QA0
QA1
QA2
QA3
QA4
FSELA
FSELB
FSELC
QB0
QB1
QB2
QB3
50 MHz
QC0
QC1
100 MHz
CCLK
F_RANGE
VCC
MPC93R52
Figure 6. MPC93R52 Zero Delay Buffer Config. 2
33.3 MHz
FB_IN
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
33.3 MHz
VCC
FSELA
FSELB
FSELC
VCC
F_RANGE
QC0
QC1
33.3 MHz
fref = 33.3 MHz
33.3 MHz
MPC93R52
33.3 MHz (Feedback)
33.3 MHz (Feedback)
MPC93R52 configuration to multiply the reference frequency by 3, 3÷2 and 1. PLL feedback of QA4 = 33.3 MHz.
Frequency range
Min
CCLK
MPC93R52 zero–delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
Max
Frequency range
Min
Max
Input
25 MHz
60 MHz
Input
25 MHz
60 MHz
QA outputs
50 MHz
120 MHz
QA outputs
25 MHz
60 MHz
QB outputs
50 MHz
120 MHz
QB outputs
25 MHz
60 MHz
QC outputs
100 MHz
240 MHz
QC outputs
25 MHz
60 MHz
TIMING SOLUTIONS
7
MOTOROLA
MPC93R52
Power Supply Filtering
Using the MPC93R52 in zero–delay applications
The MPC93R52 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCCA (PLL) power supply impacts the
device characteristics, for instance I/O jitter. The MPC93R52
provides separate power supplies for the output buffers (VCC)
and the phase-locked loop (VCCA) of the device. The purpose
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC93R52. Figure 7. illustrates a typical power
supply filter scheme. The MPC93R52 frequency and phase
stability is most susceptible to noise with spectral content in
the 100kHz to 20MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor RF. From the data sheet the
ICCA current (the current sourced through the VCCA pin) is
typically 3 mA (5 mA maximum), assuming that a minimum of
2.98V must be maintained on the VCCA pin. The resistor RF
shown in Figure 7. “VCCA Power Supply Filter” should have a
resistance of 5–25 to meet the voltage drop criteria.
Nested clock trees are typical applications for the
MPC93R52. Designs using the MPC93R52 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC93R52 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a ÷4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of part-to-part skew
The MPC93R52 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC93R52 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
W
CF = 22 µF
RF = 5–25Ω
RF
tSK(PP) = t( ∅) + tSK(O) + tPD, LINE(FB) + tJIT( ∅)
VCCA
VCC
CF
10 nF
CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
MPC93R52
VCC
33...100 nF
CCLKCommon
tPD,LINE(FB)
–t(∅)
Figure 7. VCCA Power Supply Filter
QFBDevice 1
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7. “VCCA Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
Any QDevice 1
+tSK(O)
+t(∅)
QFBDevice2
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R52 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
MOTOROLA
tJIT(∅)
Any QDevice 2
Max. skew
tJIT(∅)
+tSK(O)
tSK(PP)
Figure 8. MPC93R52 max. device-to-device skew
s
Due to the statistical nature of I/O jitter a RMS value (1 ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 11.
8
TIMING SOLUTIONS
MPC93R52
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93R52 clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 10. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC93R52 clock driver is
effectively doubled due to its capability to drive multiple lines.
Table 11: Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3s) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -445 ps to 395 ps relative to CCLK:
tSK(PP) =
[–200ps...150ps] + [–200ps...200ps] +
[(15ps @ –3)...(15ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–445ps...395ps] + tPD, LINE(FB)
MPC93R52
OUTPUT
BUFFER
IN
RS = 36Ω
14Ω
OutA
MPC93R52
OUTPUT
BUFFER
Due to the frequency dependence of the I/O jitter,
Figure 9. “Max. I/O Jitter versus frequency” can be used for a
more precise timing performance analysis.
IN
ZO = 50Ω
RS = 36Ω
ZO = 50Ω
OutB0
14Ω
RS = 36Ω
ZO = 50Ω
OutB1
Figure 10. Single versus Dual Transmission Lines
The waveform plots in Figure 11. “Single versus Dual
Line Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both cases
the drive capability of the MPC93R52 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC93R52. The output waveform in Figure 11.
“Single versus Dual Line Termination Waveforms” shows a
step in the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
Figure 9. Max. I/O Jitter versus frequency
Driving Transmission Lines
The MPC93R52 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC÷2.
TIMING SOLUTIONS
= VS ( Z0 ÷ (RS+R0 +Z0))
= 50Ω || 50Ω
= 36Ω || 36Ω
= 14Ω
= 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
VL
Z0
RS
R0
VL
9
MOTOROLA
MPC93R52
3.0
VOLTAGE (V)
2.5
OutA
tD = 3.8956
match the impedances when driving multiple lines the
situation in Figure 12. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
OutB
tD = 3.9386
2.0
In
MPC93R52
OUTPUT
BUFFER
1.5
1.0
RS = 22Ω
ZO = 50Ω
RS = 22Ω
ZO = 50Ω
14Ω
0.5
0
2
4
6
8
TIME (nS)
10
12
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
14
Figure 12. Optimized Dual Line Termination
Figure 11. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
Pulse
Generator
Z = 50
MPC93R52
DUT
ZO = 50Ω
ZO = 50Ω
W
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 13. CCLK MPC93R52 AC test reference for Vcc = 3.3V and Vcc = 2.5V
MOTOROLA
10
TIMING SOLUTIONS
MPC93R52
VCC
VCC 2
B
GND
VCC
VCC 2
B
CCLK
VCC
VCC 2
B
GND
GND
VCC
VCC 2
B
FB_IN
tSK(O)
GND
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
t(∅)
Figure 14. Output–to–output Skew tSK(O)
Figure 15. Propagation delay (t(∅), static phase
offset) test reference
VCC
VCC 2
B
CCLK
GND
tP
FB_IN
T0
DC = tP /T0 x 100%
TJIT(∅) = |T0 –T1 mean|
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
Figure 17. I/O Jitter
Figure 16. Output Duty Cycle (DC)
TN
TN+1
TJIT(CC) = |TN –TN+1 |
T0
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
TJIT(PER) = |TN –1/f0 |
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 18. Cycle–to–cycle Jitter
Figure 19. Period Jitter
VCC=3.3V
2.4
0.55
tF
tR
Figure 20. Output Transition Time Test Reference
TIMING SOLUTIONS
11
MOTOROLA
MPC93R52
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-03
ISSUE B
4X
0.20 H A–B D
6
D1
e/2
D1/2
PIN 1 INDEX
32
3
A, B, D
25
1
E1/2 A
F
B
6 E1
E
4
F
DETAIL G
17
8
9
7
E/2
DETAIL G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08–mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07–mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25–mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1–mm AND
0.25–mm FROM THE LEAD TIP.
D
D/2
4
D
4X
0.20 C A–B D
H
28X
e
32X
0.1 C
SEATING
PLANE
C
DETAIL AD
BASE
METAL
PLATING
ÉÉÉ
ÉÉÉ
b1
c
8X
b
( q1_)
0.20
R R2
A2
0.25
GAUGE PLANE
A1
(S)
L
q_
(L1)
DETAIL AD
MOTOROLA
12
5
C A–B D
SECTION F–F
R R1
A
M
c1
8
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
θ
θ1
R1
R2
S
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.30
0.40
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.50
0.70
1.00 REF
0_
7_
12 _REF
0.08
0.20
0.08
–––
0.20 REF
TIMING SOLUTIONS
MPC93R52
NOTES
TIMING SOLUTIONS
13
MOTOROLA
MPC93R52
NOTES
MOTOROLA
14
TIMING SOLUTIONS
MPC93R52
NOTES
TIMING SOLUTIONS
15
MOTOROLA
MPC93R52
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E Motorola Inc. 2003
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MOTOROLA
◊
16
MPC93R52/D
TIMING
SOLUTIONS