IRF9140 Data Sheet February 1999 -19A, -100V, 0.200 Ohm, P-Channel Power MOSFET These are P-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17521. Ordering Information PART NUMBER IRF9140 PACKAGE TO-204AA File Number 2278.3 Features • -19A, -100V • rDS(ON) = 0.200Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D IRF9140 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-204AA DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) 5-14 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF9140 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF9140 -100 -100 -19 -12 -76 ±20 125 1 960 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = -250µA (Figure 10) -100 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = -250µA -2.0 - -4.0 V - - -25 µA Zero Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC On-State Drain Current (Note 2) Gate to Source Leakage ID(ON) IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time rDS(ON) gfs td(ON) Rise Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) VDS > ID(ON) x rDS(ON) Max, ID = -10A VDD = -50V, ID ≈ −19A, RG = 9.1Ω, RL = 2.3Ω (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature -250 µA - - A - - ±100 nA - 0.15 0.20 Ω 5.0 7.0 - S 16 20 ns 65 100 ns td(OFF) - 47 70 ns tf - 28 90 ns - 70 90 nC - 14 - nC - 56 - nC Qg(TOT) Gate to Source Charge Qgs Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS LD Internal Source Inductance VGS = -10V, ID = -10A (Figures 8, 9) - - Gate to Drain “Miller” Charge Internal Drain Inductance VGS = ±20V -19 - tr Turn-Off Delay Time VDS > ID(ON) x rDS(ON) Max, VGS = -10V (Figure 7) LS VGS = -10V, ID = -19A, VDS = 0.8 x Rated BVDSS, Ig (REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = -25V, f = 1.0MHz (Figure 10) Measured Between the Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die Measured From The Source Lead, 6mm (0.25in) From the Flange and the Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances - 1100 - pF - 550 - pF - 250 - pF - 5.0 - nH - 12.5 - nH - - 1 oC/W - - 30 oC/W D LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 5-15 Free Air Operation IRF9140 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) TEST CONDITIONS MIN TYP MAX UNITS - - -19 A - - -76 A TJ = 25oC, ISD = -19A, VGS = 0V - - -1.5 V trr TJ = 150oC, ISD = 19A, dISD/dt = 100A/µs - 170 - ns QRR TJ = 150oC, ISD = -19A, dISD/dt = 100A/µs - 0.8 - µC ISD Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode ISDM D G S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge VSD NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 4µH, RG = 25Ω, peak IAS = 19A. See Figures 15, 16. Typical Performance Curves Unless Otherwise Specified -20 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 -15 -10 -5 0.2 0 0.0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 0 50 100 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 ZθJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 0.1 0.1 PDM 0.05 0.02 0.01 t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 5-16 1 10 IRF9140 Typical Performance Curves Unless Otherwise Specified (Continued) -100 102 ID, DRAIN CURRENT (A) 10µs 100µs 1ms 10 10ms OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 100ms DC 1 TJ = MAX RATED TC = 25oC RJC = 1oC/W SINGLE PULSE 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) VGS = -16V VGS = -16V 80µs PULSE TEST VGS = -12V -60 VGS = -10V -40 VGS = -9V VGS = -8V VGS = -7V -20 VGS = -6V VGS = -5V 0 102 VGS = -4V -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 -30 VGS = -8V VGS = -7V VGS = -6V -2 -10 -5 -2 TJ = 25oC TJ = -55oC -5 -2 VGS = -4V -2 -4 -6 -8 -10 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 TJ = 125oC -1.0 VGS = -5V 0 80µs PULSE TEST -5 VGS = -10V VGS = -9V -10 -102 VGS = -12V -40 -20 -0.1 0 -2 FIGURE 6. SATURATION CHARACTERISTICS 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE 80µs PULSE TEST VGS = -10V 0.18 0.14 VGS = -20V 0.10 0 0 -20 -40 -60 ID, DRAIN CURRENT (A) -80 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 5-17 -12 -4 -6 -8 -10 VGS, GATE TO SOURCE VOLTAGE (V) -14 FIGURE 7. TRANSFER CHARACTERISTICS 0.26 0.22 -50 FIGURE 5. OUTPUT CHARACTERISTICS ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = -14V 80µs PULSE TEST -80 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA -50 VGS = -14V -100 ID = -10A VGS = -10V 2.0 1.5 1.0 0.5 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF9140 Typical Performance Curves Unless Otherwise Specified (Continued) 2000 1.15 1.05 0.95 CISS 1200 0.85 0.75 -60 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 1600 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 800 COSS 400 -40 -20 0 20 40 60 80 0 100 120 140 160 CRSS 0 IDR, SOURCE TO DRAIN CURRENT (A) TJ = -55oC 12 TJ = 25oC 9 TJ = 125oC 6 3 -40 -60 ID, DRAIN CURRENT (A) -80 -100 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 5 TJ = 150oC 2 TJ = 25oC 10 5 2 1.0 5 2 0.1 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 0 VGS, GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) -50 102 80µs PULSE TEST -20 -40 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 15 0 -30 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 0 -20 -10 TJ, JUNCTION TEMPERATURE (oC) ID = -24A -5 VDS = -20V VDS = -50V VDS = -80V -10 -15 -20 0 20 40 60 Qg(TOT), TOTAL GATE CHARGE (nC) 80 FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5-18 1.8 IRF9140 Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN - RG REQUIRED PEAK IAS + VDD DUT 0V tP VGS VDD IAS IAS 0.01Ω VDS tP BVDSS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tf tr RL 0 - DUT VDD RG VGS 10% 10% VDS VGS 0 90% 90% + 10% 50% 50% PULSE WIDTH 90% FIGURE 17. SWITCHING TIME TEST CIRCUIT -VDS (ISOLATED SUPPLY) CURRENT REGULATOR FIGURE 18. RESISTIVE SWITCHING WAVEFORMS 0 VDS DUT 12V BATTERY 0.2µF 50kΩ 0.3µF Qgs VGS Qgd D Qg(TOT) DUT G 0 0 S Ig(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 5-19 VDD IG(REF) FIGURE 20. GATE CHARGE WAVEFORMS IRF9140 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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