19-1899; Rev 1; 5/04 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference Ordering Information PART TEMP RANGE MAX1422CCM 0°C to +70°C 48 TQFP MAX1422ECM -40°C to +85°C 48 TQFP 37 38 39 40 41 42 43 44 45 46 AGND AVDD CML REFN REFP REFIN AVDD AGND PD OE D11 D10 47 48 AGND AVDD AVDD AGND AGND 1 36 2 35 3 34 4 33 5 32 D9 D8 D7 D6 DVDD INP INN 6 31 DVDD 30 AGND AGND AVDD 8 29 9 28 DGND DGND D5 10 27 D4 AVDD 11 26 AGND 12 25 D3 D2 24 23 22 21 20 MAX1422 7 AGND AVDD AVDD AGND CLK CLK AGND AVDD DVDD DGND D0 D1 Functional Diagram appears at end of data sheet. PIN-PACKAGE Pin Configuration 13 IF and Baseband Digitization ♦ Space-Saving 48-Pin TQFP Package 19 Radar ♦ Power-Down Modes 130mW (Reference Shutdown Mode) 10µW (Shutdown Mode) 18 Data Acquisition ♦ Differential Wideband Input T/H Amplifier 17 CCD Pixel Processing ♦ Internal 2.048V Precision Bandgap Reference 16 Medical Ultrasound Imaging ♦ 67dB SNR at fIN = 5MHz 15 ________________________Applications ♦ Single 3.3V Power Supply 14 The MAX1422 3.3V, 12-bit analog-to-digital converter (ADC) features a fully differential input, pipelined, 12stage ADC architecture with wideband track-and-hold (T/H) and digital error correction incorporating a fully-differential signal path. The MAX1422 is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The converter operates from a single 3.3V supply, consuming only 137mW while delivering a 67dB (typ) signal-to-noise ratio (SNR) at a 5MHz input frequency and a 20Msps sampling frequency. The fully-differential input stage has a small signal -3dB bandwidth of 400MHz and may be operated with single-ended inputs. An internal 2.048V precision bandgap reference sets the ADCs full-scale range. A flexible reference structure accommodates an internally or externally applied buffered or unbuffered reference for applications requiring increased accuracy or a different input voltage range. In addition to low operating power, the MAX1422 features two power-down modes, a reference power-down, and a shutdown mode. In reference power-down, the internal bandgap reference is deactivated, resulting in a 2mA (typ) supply current reduction. For idle periods, a full shutdown mode is available to maximize power savings. The MAX1422 provides parallel, offset binary, CMOScompatible three-state outputs. The MAX1422 is available in a 7mm ✕ 7mm ✕ 1.4mm, 48-pin TQFP package and is specified over the commercial (0°C to +70°C) and extended industrial (-40°C to +85°C) temperature ranges. Pin-compatible higher-speed versions of the MAX1422 are also available. Please refer to the MAX1421 data sheet for 40Msps and the MAX1420 data sheet for 60Msps. Features TQFP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1422 General Description MAX1422 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference ABSOLUTE MAXIMUM RATINGS AVDD, DVDD to AGND ..............................................-0.3V to +4V DVDD, AVDD to DGND..............................................-0.3V to +4V DGND to AGND.....................................................-0.3V to +0.3V INP, INN, REFP, REFN, REFIN, CML,CLK, CLK, ....................(AGND - 0.3V) to (AVDD + 0.3V) D0–D11, OE, PD .......................(DGND - 0.3V) to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 21.7mW/°C above +70°C)........1739mW Operating Temperature Ranges MAX1422CCM ....................................................0°C to +70°C MAX1422ECM .................................................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dBFS, internal reference, fCLK = 20MHz (50% duty cycle); digital output load CL = 10pF, ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity Mid-scale Offset Mid-scale Offset Temperature Coefficient Gain Error RES DNL INL 12 TA = +25°C, no missing codes TA = TMIN to TMAX ±2 -3 GETC ±.75 -5 ±0.1 5 External reference applied to REFIN, (Note 2) -5 ±0.2 5 External reference applied to REFP, CML, and REFN (Note 3) %FSR %/°C Internal reference (Note 1) -1.5 LSB LSB 3 3 ✕ 10-4 MSOTC GE Bits 1 ±0.5 TA = TMIN to TMAX MSO External reference applied to REFP, CML, and REFN (Note 3) Gain Error Temperature Coefficient -1 %FSR 1.5 15 ✕ 10-6 %/°C 67 dB DYNAMIC PERFORMANCE (fCLK = 20MHz, 4096-point FFT) Signal-to-Noise Ratio SNR fIN = 5MHz, TA = +25°C 63 Spurious-Free Dynamic Range SFDR fIN = 5MHz, TA = +25°C 64 Total Harmonic Distortion THD fIN = 5MHz, TA = +25°C SINAD ENOB fIN = 5MHz, TA = +25°C fIN = 5MHz Signal-to-Noise and Distortion Effective Number of Bits 74 -72 60 dBc -63 dBc 65 dB 10.5 Bits -77 dBc Two-Tone Intermodulation Distortion IMD Differential Gain DG ±1 % Differential Phase DP ±0.25 Degrees fIN1 = 7.028MHz, fIN2 = 8.093MHz (Note 4) ANALOG INPUTS (INP, INN, CML) Input Resistance RIN Either input to ground 61 kΩ Input Capacitance CIN Either input to ground 4 pF VAVDD ✕ 0.5 V Common-Mode Input Level (Note 5) 2 VCML _______________________________________________________________________________________ 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference (VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dBFS, internal reference, fCLK = 20MHz (50% duty cycle); digital output load CL = 10pF, ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Common-Mode Input Voltage Range (Note 5) SYMBOL CONDITIONS MIN TYP VCMVR Differential Input Range VIN VINP - VINN (Note 6) MAX UNITS VCML ±5% V ±VDIFF V MHz Small-Signal Bandwidth BW-3dB (Note 7) 400 Large-Signal Bandwidth FPBW -3dB (Note 7) 150 MHz 1 Clock cycles Overvoltage Recovery OVR 1.5 ✕ FS input INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF) Common-Mode Reference Voltage VCML At CML VAVDD ✕ 0.5 V Positive Reference Voltage VREFP At REFP VCML + 0.512 V Negative Reference Voltage VREFN At REFN Differential Reference Voltage VDIFF (Note 6) VCML - 0.512 1.024 ±5% Differential Reference REFTC Temperature Coefficient EXTERNAL REFERENCE (VREFIN = 2.048V) V V ±100 REFIN Input Resistance RIN REFIN Input Capacitance CIN 10 pF VREFIN 2.048 ±10% V 0.92 ✕ 1.08 ✕ VREFIN/2 VREFIN/2 VREFIN/2 V REFIN Reference Input Voltage Range Differential Reference Voltage Range VDIFF (Note 8) ppm/°C (Note 6) 5 kΩ EXTERNAL REFERENCE (VREFIN = 0, reference voltage applied to REFP, REFN, and CML) REFP, REFN, CML Input Current REFP, REFN, CML Input Capacitance Differential Reference Voltage Range IIN -200 15 CIN VDIFF 200 pF 1.024 ±10% 1.65 ±10% (Note 6) µA V CML Input Voltage Range VCML V REFP Input Voltage Range VREFP VCML + VDIFF/2 V REFN Input Voltage Range VREFN VCML VDIFF/2 V DIGITAL INPUTS (CLK, CLK, PD, OE) Input Logic High VIH Input Logic Low VIL 0.7 ✕ VDVDD V 0.3 ✕ VDVD V _______________________________________________________________________________________ 3 MAX1422 ELECTRICAL CHARACTERISTICS (continued) MAX1422 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dBFS, internal reference, fCLK = 20MHz (50% duty cycle); digital output load CL = 10pF, ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS µA ±330 CLK, CLK Input Current TYP PD -20 20 OE -20 20 Input Capacitance 10 pF DIGITAL OUTPUTS (D0–D11) Output Logic High VOH IOH = 200µA VDVDD - 0.5 VDVDD V Output Logic Low VOL IOL = -200µA 0 0.5 V 10 µA Three-State Leakage -10 Three-State Capacitance 2 pF POWER REQUIREMENTS Analog Supply Voltage VAVDD 3.138 3.3 3.465 Digital Supply Voltage VDVDD 2.7 3.3 3.63 V Analog Supply Current IAVDD 39 46 mA 37 44 mA 20 µA Analog Supply Current with Internal Reference in Shutdown VREFIN = 0 Analog Shutdown Current PD = DVDD Digital Supply Current IDVDD Digital Shutdown Current 3 PD = DVDD V mA 20 µA 152 mW Power Dissipation PDISS Analog power dissipation 137 Power-Supply Rejection Ratio PSRR (Note 9) ±1 Maximum Clock Frequency fCLK Figure 6 Clock High tCH Figure 6, clock period 50ns 25 ns Clock Low tCL Figure 6, clock period 50ns 25 ns Figure 6 7 Clock cycles mV/V TIMING CHARACTERISTICS Pipeline Delay (Latency) 20 MHz Aperture Delay tAD Figure 10 2 ns Aperture Jitter tAJ Figure 10 2 ps Data Output Delay tOD Figure 6 Bus Enable Time tBE Figure 5 5 ns Bus Disable Time tBD Figure 5 5 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: 4 5 10 14 ns Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor. External 2.048V reference applied to REFIN. Internal reference disabled. VREFIN = 0, VREFP = 2.162V, VCML = 1.65V, and VREFN = 1.138V. IMD is measured with respect to either of the fundamental tones. Specifies the common-mode range of the differential input signal supplied to the MAX1422. VDIFF = VREFP - VREFN. Input bandwidth is measured at a 3dB level. VREFIN is internally biased to 2.048V through a 10kΩ resistor. Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in VAVDD, using the internal reference. _______________________________________________________________________________________ 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference FFT PLOT (4096-POINT DATA RECORD) HD2 -80 -100 -60 -80 2 3 4 5 6 7 8 10 1 2 3 4 5 6 7 8 9 -60 MAX1422 toc03 HD3 -80 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY 2 3 4 5 6 7 8 9 10 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY 70 MAX1422 toc05 77 1 ANALOG INPUT FREQUENCY (MHz) TWO-TONE IMD PLOT (4096-POINT DATA RECORD) 85 0 10 ANALOG INPUT FREQUENCY (MHz) fIN2 HD2 -120 0 ANALOG INPUT FREQUENCY (MHz) fIN1 = 7.0283MHz fIN2 = 8.0931MHz fCLK = 20.0056MHz AIN1 = AIN2 = -6.5dB FS -20 9 MAX1422 toc04 0 1 -40 -100 -120 0 66 fIN1 -60 IMD2 IMD3 69 SNR (dB) SFDR (dBc) -40 61 62 58 -80 53 -100 -120 54 45 1 2 3 4 5 6 7 8 9 10 50 1 10 100 1 10 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 5MHz) 66 -62 -68 70 60 SFDR (dBc) SINAD (dB) -56 80 MAX1422 toc09 70 MAX1422 toc07 -50 MAX1422 toc08 0 THD (dBc) HD3 HD2 -20 -100 -120 AMPLITUDE (dB) -40 fIN = 19.8051MHz MAX1422 toc06 HD3 FFT PLOT (4096-POINT DATA RECORD) 0 AMPLITUDE (dB) -40 fIN = 8.1637MHz -20 AMPLITUDE (dB) AMPLITUDE (dB) -20 -60 0 MAX1422 toc01 fIN = 5.2235MHz MAX1422 toc02 FFT PLOT (4096-POINT DATA RECORD) 0 62 58 50 40 30 20 -74 54 10 -80 0 50 1 10 ANALOG INPUT FREQUENCY (MHz) 100 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT POWER (dB FS) _______________________________________________________________________________________ 5 MAX1422 Typical Operating Characteristics (VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input drive, AIN = -0.5dBFS, fCLK = 20MHz (50% duty cycle) digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 °C.) Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input drive, AIN = -0.5dBFS, fCLK = 20MHz (50% duty cycle) digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 °C.) 80 SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER (fIN = 5MHz) 80 MAX1422 toc11 -10 MAX1422 toc10 100 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER (fIN = 5MHz) -20 70 60 40 SINAD (dB) THD (dBc) -40 -50 20 20 -70 0 10 -80 -40 -30 -20 -10 0 0 -60 -50 -40 -30 -20 -10 0 -60 -30 -20 -10 ANALOG INPUT POWER (dB FS) SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE SIGNAL-TO-NOISE RATIO vs. TEMPERATURE TOTAL HARMONIC DISTORTION vs. TEMPERATURE 68 SNR (dB) 76 fIN = 5.5224MHz 66 72 64 68 62 -67 fIN = 5.5224MHz -69 -15 10 35 60 -73 -77 -40 85 -71 -75 60 64 -15 10 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE fIN = 5.5224MHz 68 0.50 MAX1422 toc17 2 MAX1422 toc16 70 INL (LSB) 0 64 -1 62 60 10 35 TEMPERATURE (°C) 60 85 0 -0.25 -2 -15 85 0.25 DNL (LSB) 1 66 0 MAX1422 toc15 70 THD (dBc) 80 -40 -40 ANALOG INPUT POWER (dB FS) fIN = 5.5224MHz -40 -50 ANALOG INPUT POWER (dB FS) MAX1422 toc14 84 -50 MAX1422 toc13 -60 SFDR (dBc) 40 30 -60 6 50 MAX1422 toc18 SNR (dB) -30 60 MAX1422 toc12 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 5MHz) SINAD (dB) MAX1422 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference -0.50 0 1024 2048 3072 DIGITAL OUTPUT CODE 4096 0 1024 2048 3072 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 4096 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference 6 MAX1422 toc20 46 CL = 10pF 5 4 -0.4 42 IDVDD (mA) IAVDD (mA) -0.1 38 3 2 -0.7 34 -1.0 1 30 -40 -15 10 35 60 85 0 -40 TEMPERATURE (°C) -15 10 35 60 85 SNR SFDR 35 60 85 2.05 2.04 THD VREFIN (V) 65 SINAD 60 10 TEMPERATURE (°C) MAX1422 toc23 75 SNR/SINAD, THD/SFDR (dB, dBc) -15 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1422 toc22 80 70 -40 TEMPERATURE (°C) SNR/SINAD, THD/SFDR vs. CLOCK FREQUENCY 55 50 2.03 2.02 2.01 45 fIN = 5MHz 5.0 7.5 2.00 10.0 12.5 15.0 17.5 3.1 20.0 3.2 3.3 3.4 3.5 VDD (V) CLOCK FREQUENCY (MHz) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE OUTPUT NOISE HISTOGRAM (DC-INPUT) 30,000 MAX1422 toc24 2.10 2.08 MAX1422 toc25 40 27360 25,000 20,000 2.06 COUNTS VREFIN (V) GAIN ERROR (%FSR) 0.2 DIGITAL SUPPLY CURRENT vs. TEMPERATURE 50 MAX1422 toc19 0.5 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1422 toc21 GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) 16623 15029 15,000 2.04 10,000 2.02 3431 5000 0 2.00 -40 -15 10 35 TEMPERATURE (°C) 60 85 2596 22 310 162 2 1 N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 DIGITAL OUTPUT NOISE _______________________________________________________________________________________ 7 MAX1422 Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input drive, AIN = -0.5dBFS, fCLK = 20MHz (50% duty cycle) digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 °C.) 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422 Pin Description PIN NAME FUNCTION 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 AGND Analog Ground. Connect all return paths for analog signals to AGND. 2, 3, 10, 11, 14, 15, 20, 42, 47 AVDD Analog Supply Voltage. For optimum performance, bypass to the closest AGND with a parallel combination of a 0.1µF, and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between AVDD and AGND. 6 INP Positive Analog Signal Input 7 INN Negative Analog Signal Input 17 CLK Clock Frequency Input. Clock frequency input ranges from 100kHz to 20MHz. 18 CLK Complementary Clock Frequency Input. This input is used for differential clock input. If the ADC is driven with a single-ended clock, bypass CLK with 0.1µF capacitor to AGND. 21, 31, 32 DVDD Digital Supply Voltage. For optimum performance, bypass to the closest DGND with a parallel combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between DVDD and DGND. 22, 29, 30 DGND Digital Ground 23–28 D0–D5 Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB. 33–38 D6–D11 Digital Data Outputs. D6 through D11, where D11 represents the MSB. 39 OE Output Enable Input. A logic "1" on OE places the outputs D0–D11 into a high-impedance state. A logic "0" allows for the data bits to be read from the outputs. 40 PD Shutdown Input. A logic "1" on PD places the ADC into shutdown mode. 43 REFIN External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND. 44 REFP Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFP should be biased toVCML + VDIFF/2. 45 REFN Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFN should be biased to VCML - VDIFF/2. 46 CML Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF. With the internal reference disabled (REFIN = AGND). Detailed Description The MAX1422 uses a 12-stage, fully differential, pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Including the delay through the output latch, the latency is seven clock cycles. A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digital- 8 to-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. The resulting error signal is then multiplied by two and the product is passed along to the next pipeline stage. This process is repeated until the signal has been processed by all 12 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. _______________________________________________________________________________________ 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track-and-hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b) through-switches (S4a and S4b). Switches S2a and S2b set the common mode for the transconductance amplifier (OTA) input and open simultaneously with S1, sampling the input waveform. The resulting differential voltage is held on capacitors C2a and C2b. Switches S4a and S4b, are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The OTA is used to charge capacitors, C1a and C1b, to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide input bandwidth, T/H amplifier allows the MAX1422 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs INP and INN can be driven either differentially or single-ended. Match the impedance of INP and INN and set the common-mode voltage to midsupply (AV DD /2) for optimum performance. Analog Input and Reference Configuration The full-scale range of the MAX1422 is determined by the internally generated voltage difference between REFP (AVDD/2 + VREFIN/4) and REFN (AVDD/2 - VREFIN/4). The MAX1422’s full-scale range is adjustable through REFIN, which provides a high input impedance for this purpose. REFP, CML (AVDD/2), and REFN are internally buffered, low impedance outputs. The MAX1422 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the on-chip 2.048V bandgap reference is active and REFIN, REFP, CML, and REFN, left floating. For stability purposes bypass REFIN, REFP, REFN, and CML with a capacitor network of 0.22µF, in parallel with a 1nF capacitor to AGND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In unbuffered external reference mode, REFIN is connected to AGND, which deactivates the on-chip buffers of REFP, CML, and REFN. With their buffers shut down, MDAC VIN Σ T/H x2 INTERNAL BIAS VOUT CML S5a S2a TO NEXT STAGE FLASH ADC C1a S3a DAC S4a 2 BITS IN+ OUT C2a S4c VIN STAGE 1 STAGE 2 STAGE 12 S1 OTA OUT INS4b C2b C1b DIGITAL CORRECTION LOGIC Figure 1. Pipelined Architecture S3b 12 S2b D11–D0 INTERNAL BIAS S5b CML Figure 2. Internal T/H Circuit _______________________________________________________________________________________ 9 MAX1422 Input Track-and-Hold Transconductance Circuit MAX1422 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference AVDD 50Ω CML R 0.22µF 0.1nF AVDD 2 50Ω R REFP MAX4284 R R AVDD 2 0.22µF 0.1nF MAX1422 AVDD 4 R 50Ω R REFN MAX4284 0.22µF 0.1nF R AVDD 4 REFIN R AGND 1V Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled these nodes become high impedance and can be driven by external reference sources, as shown in Figure 3. Clock Inputs (CLK, CLK) The MAX1422’s CLK and CLK inputs accept both single-ended and differential input operation, and accept CMOS-compatible clock signals. If CLK is driven with a single-ended clock signal, bypass CLK with a 0.1µF capacitor to AGND. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC according to the following relationship: 1 SNRdB = 20 × log10 2π × ƒIN × t AJ where fIN represents the analog input frequency, and tAJ is the aperture jitter. Clock jitter is especially critical for high input frequency applications. The clock input should always be consid- 10 ered as an analog input and routed away from any analog or digital signal lines. The MAX1422 clock input operates with a voltage threshold set to AVDD/2. Clock inputs must meet the specifications for high and low periods, as stated in the Electrical Characteristics. Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10kΩ resistors to bias the common-mode level of each input. This circuit may be used to AC-couple the system clock signal to the MAX1422 clock input. Output Enable (OE), Power-Down (PD) and Output Data (D0–D11) With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power-down. All data outputs, D0 (LSB) through D11 (MSB), are TTL/CMOS logic compatible. There is a seven clockcycle latency between any particular sample and its valid output data. The output coding is in offset binary format (Table 1). The capacitive load on the digital outputs D0 through D11 should be kept as low as possible (≤10pF) to avoid large digital currents that could feed back into the ana- ______________________________________________________________________________________ 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422 INP OE D11–D0 ADC INN tBD tBE AVDD OUTPUT DATA D11–D0 10kΩ HIGH-Z VALID DATA HIGH-Z 10kΩ CLK Figure 5. Output Enable Timing 10kΩ 10kΩ CLK MAX1422 AGND Figure 4. Simplified Clock Input Circuit log portion of the MAX1421, thereby degrading its dynamic performance. The use of digital buffers (e.g. 74LVCH16244) on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the MAX1422 dynamic performance, add small 100Ω series resistors to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output. System Timing Requirements Figure 6 depicts the relationship between the clock input, analog input, and data output. The MAX1422 samples the analog input signal on the rising edge of CLK (falling edge of CLK). and output data is valid seven clock cycles (latency) later. Figure 6 also displays the relationship between the input clock parameters and the valid output data. Applications Information Figure 7 depicts a typical application circuit containing a single-ended to differential converter. The internal reference provides an AVDD/2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter at the input suppresses some of the wideband noise associated with high-speed op amps. Select the R ISO and CIN values to optimize the filter performance and to suit a particular application. For the application in Figure 7, a RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor.Connecting CIN from INN to INP may further improve dynamic performance. Table 1. MAX1422 Output Code For Differential Inputs DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT OFFSET BINARY VREF ✕ 2047/2048 +FULL SCALE 1LSB 1111 1111 1111 VREF ✕ 2046/2048 +FULL SCALE 2LSB 1111 1111 1110 VREF ✕ 1/2048 +1 LSB 1000 0000 0001 0 Bipolar Zero 1000 0000 0000 -VREF ✕ 1/2048 -1 LSB 0111 1111 1111 -VREF ✕ 2046/2048 -FULL SCALE +1 LSB 0000 0000 0001 -VREF ✕ -FULL SCALE 2047/2048 *VREF = VREFP - VREFN 0000 0000 0000 Using Transformer Coupling An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1422 for optimum performance. Connecting the center tap of the transformer to CML provides an AVDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements. In general, the MAX1422 provides better SFDR and THD with fully differential input signals over singleended input signals, especially for very high input frequencies. In differential input mode, even-order harmonics are suppressed and each of the inputs requires only half the signal swing compared to singleended mode. ______________________________________________________________________________________ 11 MAX1422 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference 7 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 N+7 ANALOG INPUT CLK CLK tDO DATA OUTPUT N-8 tCH N-7 N-6 N-5 tCL N-4 N-3 N-2 N-1 N Figure 6. System and Output Timing Diagram Single-Ended, AC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal. Grounding, Bypassing and Board Layout The MAX1422 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass REFP, REFN, REFIN, and CML with a parallel network of 0.22µF capacitors and 1nF to AGND. AVDD should be bypassed with a similar network of a 10µF bipolar capacitor in parallel with two ceramic capacitors of 1nF and 0.1µF. Follow the same rules to bypass the digital supply DV DD to DGND. Multilayer boards with separate ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arrangement to match the physical location of the analog ground (AGND) and the digital output driver ground (DGND) on the ADCs package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. Alternatively, all ground pins could share the 12 same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces, and remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and free of 90 degree turns. Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight-line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1422 are measured using the best straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes. Dynamic Parameter Definitions Aperture Jitter Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. ______________________________________________________________________________________ 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference MAX1422 5V 0.1µF LOWPASS FILTER INP MAX4108 RISO 50Ω 0.1µF 300Ω CIN* 22pF 0.1µF -5V 600Ω 300Ω 600Ω 44pF* MAX1422 CML 5V 0.1µF 0.22µF 5V 0.1µF 1nF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INN MAX4108 RISO 50Ω 300Ω -5V CIN* 22pF 0.1µF 300Ω 300Ω 300Ω *TWO CIN (22pF) CAPS MAY BE REPLACED BY ONE 44pF CAP, TO IMPROVE PERFORMANCE. Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical, minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-Bits): SNR(MAX) = (6.02 ✕ N + 1.76)dB In reality, there are other noise sources besides quantization noise e.g., thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADCs error consists of quantization noise only. ENOB is computed from: ENOB = SINAD - 1.76 6.02 ______________________________________________________________________________________ 13 MAX1422 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: V2 2 + V3 2 + V4 2 + V5 2 V1 THD = 20 × log 10 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale. 25Ω INP 22pF * 0.1µF VIN 1 T1 44pF * 6 N.C. 2 5 3 4 VIN RISO 50Ω 0.1µF INP MAX4108 100Ω 1kΩ MAX1422 CIN 22pF MAX1422 CML 0.22µF CML 1nF 0.22µF MINICIRCUITS T1–1T–KK81 INN 100Ω 25Ω CIN 22pF INN 22pF * *REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROVE DYNAMIC PERFORMANCE. 1nF RISO 50Ω Figure 9. Single-Ended AC-Coupled Input Figure 8. Using a Transformer for AC-Coupling Functional Diagram CLK CLK CLK CLK AVDD MAX1422 AGND INTERFACE ANALOG INPUT INP INN tAJ SAMPLED DATA (T/H) PD T/H PIPELINE ADC T/H tAD TRACK HOLD BANDGAP REFERENCE DGND TRACK Figure 10. T/H Aperature Timing ______________________________________________________________________________________ D11–D0 DVDD REF SYSTEM + BIAS REFIN REFP CML REFN 14 OUTPUT DRIVERS OE 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference 32L/48L,TQFP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1422 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)