19-3259; Rev 0; 5/04 KIT ATION EVALU E L B AVAILA 40Msps, 12-Bit ADC Features The MAX1206 is a 3.3V, 12-bit analog-to-digital converter (ADC) featuring a fully differential wideband track-andhold (T/H) input, driving the internal quantizer. The MAX1206 is optimized for low power, small size, and high dynamic performance. This ADC operates from a single 3.0V to 3.6V supply, consuming only 159mW, while delivering a typical signal-to-noise ratio (SNR) performance of 68.6dB at a 20MHz input frequency. The T/H-driven input stage accepts single-ended or differential inputs. In addition to low operating power, the MAX1206 features a 0.15mW power-down mode to conserve power during idle periods. ♦ Excellent Dynamic Performance 68.6dB SNR at fIN = 20MHz 90dBc SFDR at fIN = 20MHz A flexible reference structure allows the MAX1206 to use its internal precision bandgap reference or accept an externally applied reference. A common-mode reference is provided to simplify design and reduce external component count in differential analog input circuits. The MAX1206 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer. ♦ Adjustable Full-Scale Analog Input Range The MAX1206 features parallel, CMOS-compatible outputs. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate power input for the digital outputs accepts a voltage from 1.7V to 3.6V for flexible interfacing with various logic levels. The MAX1206 is available in a 6mm x 6mm x 0.8mm, 40pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C) temperature range. Refer to the MAX1209 and MAX1211 (see Pin-Compatible Higher/Speed Versions table) for applications that require high dynamic performance for IF input frequencies. ♦ Low-Power Operation 159mW at 3.0V (Single-Ended Clock) 181mW at 3.3V (Single-Ended Clock) 198mW at 3.3V (Differential Clock) ♦ Differential or Single-Ended Clock ♦ Accepts 20% to 80% Clock Duty Cycle ♦ Fully Differential or Single-Ended Analog Input ♦ Common-Mode Reference ♦ Power-Down Mode ♦ CMOS-Compatible Outputs in Two’s Complement or Gray Code ♦ Data-Valid Indicator Simplifies Digital Design ♦ Out-of-Range and Data-Valid Indicators ♦ Miniature, 40-Pin Thin QFN Package with Exposed Paddle ♦ Pin-Compatible, IF Sampling ADC Available (MAX1211ETL) ♦ Evaluation Kit Available (Order MAX1211EVKIT) Ordering Information PART TEMP RANGE PIN-PACKAGE MAX1206ETL -40°C to +85°C 40 Thin QFN (6mm x 6mm) Pin-Compatible Higher Speed Versions Applications Communication Receivers Cellular, LMDS, Point-to-Point Microwave, MMDS, HFC, WLAN PART SPEED GRADE (Msps) TARGET APPLICATION MAX1206 40 Baseband Ultrasound and Medical Imaging MAX1207 65 Baseband Portable Instrumentation MAX1208 80 Baseband Low-Power Data Acquisition MAX1211 65 IF MAX1209 80 IF Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1206 General Description MAX1206 40Msps, 12-Bit ADC ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +3.6V OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND.....-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V D11–D0, I.C., DAV, DOR to GND ............-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated 26.3mW/°C above +70°C)........................2105.3mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 12 Bits Integral Nonlinearity INL fIN = 20MHz (Note 2) ±0.3 ±0.7 LSB Differential Nonlinearity DNL fIN = 20MHz, no missing codes over temperature (Note 2) ±0.3 ±0.7 LSB Offset Error VREFIN = 2.048V ±0.2 ±1.1 %FS Gain Error VREFIN = 2.048V ±0.3 ±4.8 %FS ANALOG INPUT (INP, INN) Differential Input Voltage Range VDIFF Differential or single-ended inputs Common-Mode Input Voltage Input Resistance RIN Input Capacitance CIN Switched capacitor load ±1.024 V VDD / 2 V 24 kΩ 4 pF CONVERSION RATE Maximum Clock Frequency fCLK 40 MHz Minimum Clock Frequency 5 Data Latency Figure 5 MHz Clock cycles 8.5 DYNAMIC CHARACTERISTICS (Differential inputs, 4096-point FFT) Signal-to-Noise Ratio SNR Signal-to-Noise and Distortion SINAD Single-Tone Spurious-Free Dynamic Range SFDR Total Harmonic Distortion THD 2 fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 2) 68.4 67.0 fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 2) 68.3 66.9 fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 2) dB 68.6 dB 68.5 89.5 83.2 dBc 90 fIN = 3MHz at -0.5dBFS -88.4 fIN = 20MHz at -0.5dBFS (Note 2) -88.4 _______________________________________________________________________________________ -81 dBc 40Msps, 12-Bit ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP fIN = 3MHz at -0.5dBFS -92.5 fIN = 20MHz at -0.5dBFS (Note 3) -96.3 fIN = 3MHz at -0.5dBFS -93.8 fIN = 20MHz at -0.5dBFS (Note 3) -92.1 MAX UNITS Second Harmonic HD2 Third Harmonic HD3 Third-Order Intermodulation IM3 fIN1 = 69MHz at -7dBFS, fIN2 = 71MHz at -7dBFS -89 dBc SFDRTT fIN1 = 69MHz at -7dBFS, fIN2 = 71MHz at -7dBFS 88 dBc tAD Figure 14 0.9 ns Aperture Jitter tAJ Figure 14 <0.2 psRMS Output Noise nOUT 0.5 LSBRMS 1 Clock cycles Two-Tone Spurious-Free Dynamic Range Aperture Delay Overdrive Recovery Time INP = INN = COM ±10% beyond full scale -84.9 -83.3 dBc dBc INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally) REFOUT Output Voltage VREFOUT 1.988 2.048 2.080 V COM Output Voltage VCOM VDD / 2 1.65 V Differential Reference Output Voltage VREF VREF = VREFP - VREFN 1.024 V REFOUT Load Regulation REFOUT Temperature Coefficient TCREF REFOUT Short-Circuit Current 35 mV/mA +100 ppm/°C Short to VDD 0.24 Short to GND 2.1 mA BUFFERED EXTERNAL REFERENCE (REFIN driven externally, VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage VREFIN 2.048 V REFP Output Voltage VREFP (VDD / 2) + (VREFIN / 4) 2.162 V REFN Output Voltage VREFN (VDD / 2) - (VREFIN / 4) 1.138 V COM Output Voltage VCOM VDD / 2 1.60 1.65 1.70 V Differential Reference Output Voltage VREF VREF = VREFP - VREFN 0.970 1.024 1.070 V Differential Reference Temperature Coefficient +12.5 Maximum REFP Current IREFP Maximum REFN Current IREFN Maximum COM Current ICOM REFIN Input Resistance Source 0.4 Sink 1.4 Source 1.0 Sink 1.0 Source 1.0 Sink 0.4 >50 ppm/°C mA mA mA MΩ _______________________________________________________________________________________ 3 MAX1206 ELECTRICAL CHARACTERISTICS (continued) MAX1206 40Msps, 12-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are applied externally) COM Input Voltage VDD / 2 1.65 V REFP Input Voltage VCOM VREFP - VCOM 0.512 V REFN Input Voltage VREFN - VCOM -0.512 V 1.024 V 1.1 mA Differential Reference Input Voltage VREF VREF = VREFP - VREFN REFP Sink Current IREFP VREFP = 2.162V REFN Source Current IREFN VREFN = 1.138V COM Sink Current ICOM 1.1 mA 0.3 mA REFP, REFN, Capacitance 13 pF COM Capacitance 6 pF CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold VIH CLKTYP = GND, CLKN = GND Single-Ended Input Low Threshold VIL CLKTYP = GND, CLKN = GND 0.8 x VDD V 0.2 x VDD V Differential Input Voltage Swing CLKTYP = high 1.4 VP-P Differential Input Common-Mode Voltage CLKTYP = high VDD / 2 V Minimum Clock Duty Cycle Maximum Clock Duty Cycle Input Resistance RCLK Input Capacitance CCLK DCE = OVDD 20 DCE = GND 45 % DCE = OVDD 80 DCE = GND 60 Figure 4 5 kΩ 2 pF % DIGITAL INPUTS (CLKTYP, G/T, PD) Input High Threshold VIH Input Low Threshold VIL Input Leakage Current Input Capacitance 4 CDIN 0.8 x OVDD V 0.2 x OVDD VIH = OVDD ±5 VIL = 0 ±5 5 _______________________________________________________________________________________ V µA pF 40Msps, 12-Bit ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUTS (D0–D11, DAV, DOR) Output-Voltage Low VOL Output-Voltage High D0–D11, DOR, ISINK = 200µA 0.2 DAV, ISINK = 600µA 0.2 D0–D11, DOR, ISOURCE = 200µA OVDD - 0.2 DAV, ISOURCE = 600µA OVDD - 0.2 VOH V V Tri-State Leakage Current ILEAK (Note 4) ±5 µA D11–D0, DOR Tri-State Output Capacitance COUT (Note 4) 3 pF DAV Tri-State Output Capacitance CDAV (Note 4) 6 pF POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage Analog Supply Current Analog Power Dissipation VDD 3.0 3.3 3.6 V OVDD 1.7 2.0 VDD + 0.3V V IVDD PDISS Normal operating mode, fIN = 20MHz at -0.5dBFS, CLKTYP = GND, single-ended clock 54.7 Normal operating mode, fIN = 20MHz at -0.5dBFS, CLKTYP = OVDD, differential clock 60.1 Power-down mode; clock idle, PD = OVDD 0.045 Normal operating mode, fIN = 20MHz at -0.5dBFS, CLKTYP = GND, single-ended clock 181 Normal operating mode, fIN = 20MHz at -0.5dBFS, CLKTYP = OVDD, differential clock 198 Power-down mode, clock idle, PD = OVDD 0.15 66 218 mA mW _______________________________________________________________________________________ 5 MAX1206 ELECTRICAL CHARACTERISTICS (continued) MAX1206 40Msps, 12-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Digital Output Supply Current SYMBOL IOVDD CONDITIONS MIN Normal operating mode, fIN = 20MHz at -0.5dBFS, OVDD = 2.0V, CL ≈ 5pF Power-down mode; clock idle, PD = OVDD TYP MAX UNITS 6.1 mA 6 µA 12.5 ns 12.5 ns 6.4 ns TIMING CHARACTERISTICS (Figure 5) Clock Pulse-Width High Clock Pulse-Width Low Data Valid Delay tCH tCL tDAV CL = 5pF (Note 5) Data Setup Time Before Rising Edge of DAV tSETUP CL = 5pF (Notes 3, 5) 13.9 ns Data Hold Time After Rising Edge of DAV tHOLD CL = 5pF (Notes 3, 5) 10.7 ns Wake-Up Time from Power-Down tWAKE VREFIN = 2.048V Note 1: Note 2: Note 3: Note 4: Note 5: 6 10 Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Specifications guaranteed by design and characterization. Devices tested for performance during production test. Guaranteed by design and characterization. During power-down, D11–D0, DOR, and DAV are high impedance. Digital outputs settle to VIH or VIL. _______________________________________________________________________________________ ms 40Msps, 12-Bit ADC -50 -60 -70 HD3 HD5 -80 -20 -30 -40 -50 0 -20 -70 HD2 HD3 HD2 -80 -30 -40 -50 -60 -70 -90 -90 -90 -100 -100 -110 0 4 8 12 20 16 -110 0 FREQUENCY (MHz) 4 8 12 20 16 -30 fIN1 -40 -50 -60 fIN2 -70 fCLK = 40.0004Msps fIN1 = 44.0019MHz AIN1 = -7.0dBFS fIN2 = 46.0039MHz AIN2 = -7.0dBFS SNR = 64.64dBc SINAD = 64.63dBc SFDRTT = 88.3dBc IMD = -85.21dB IM3 = -93.89dBc 0 -20 -30 -40 -50 -70 -80 -90 -100 -100 -110 -110 8 12 16 fIN2 -60 -90 4 0 20 12 16 20 0.3 0.1 DNL (LSB) 0.2 0 -0.2 0 -0.1 -0.4 -0.2 -0.6 -0.3 -0.8 -0.4 -1.0 -0.5 512 1024 1536 2048 2560 3072 3584 4096 MAX1206 toc07 0.4 0.2 DIGITAL OUTPUT CODE 8 DIFFERENTIAL NONLINEARITY 0.4 0 4 0.5 MAX1206 toc06 0.6 20 FREQUENCY (MHz) INTEGRAL NONLINEARITY 0.8 16 fIN1 FREQUENCY (MHz) 1.0 12 fCLK = 40.0004Msps fIN1 = 69.0022MHz AIN1 = -7.0dBFS fIN2 = 71.0041MHz AIN2 = -7.0dBFS SNR = 64.01dBc SINAD = 64.00dBc SFDRTT = 88.44dBc IMD = -85.56dB IM3 = -88.65dBc -10 -80 0 8 TWO-TONE FFT PLOT (16,384-POINT DATA RECORD) AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 4 FREQUENCY (MHz) MAX1206 toc04 0 0 FREQUENCY (MHz) TWO-TONE FFT PLOT (16,384-POINT DATA RECORD) -10 HD2 HD5 HD4 -80 -100 -110 fCLK = 40.0004Msps fIN = 70.0837MHz AIN = -0.48dBFS SNR = 68.22dBc SINAD = 68.16dBc THD = -86.9dBc SFDR = 90.1dBc -10 -60 MAX1206 toc03 fCLK = 40.0004Msps fIN = 19.9074MHz AIN = -0.5304dBFS SNR = 68.71dBc SINAD = 68.67dBc THD = -89.7dBc SFDR = 92.4dBc MAX1206 toc05 -40 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) AMPLITUDE (dBFS) -30 INL (LSB) AMPLITUDE (dBFS) -20 0 -10 AMPLITUDE (dBFS) fCLK = 40.0004Msps fIN = 9.8975MHz AIN = -0.5dBFS SNR = 68.72dBc SINAD = 68.67dBc THD = -88.4dBc SFDR = 92.18dBc -10 MAX1206 toc01 0 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) MAX1206 toc02 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 7 MAX1206 Typical Operating Characteristics (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) fIN = 19.9MHz 69 70 MAX1206 toc08 70 68 69 fIN = 19.9MHz 68 67 SINAD (dB) 67 SNR (dB) MAX1206 toc09 SIGNAL-TO-NOISE + DISTORTION vs. SAMPLING RATE SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE 66 65 64 66 65 64 63 63 62 62 61 61 60 60 10 15 20 25 30 35 10 40 15 20 TOTAL HARMONIC DISTORTION vs. SAMPLING RATE 35 40 100 -75 85 SFDR (dBc) 90 -85 fIN = 19.9MHz 95 -70 -80 MAX1206 toc11 fIN = 19.9MHz -65 80 75 -90 70 -95 65 -100 10 15 20 25 fCLK (MHz) 8 30 SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE MAX1206 toc10 -60 25 fCLK (MHz) fCLK (MHz) THD (dBc) MAX1206 40Msps, 12-Bit ADC 30 35 40 60 10 15 20 25 30 35 fCLK (MHz) _______________________________________________________________________________________ 40 40Msps, 12-Bit ADC fIN = 70.1MHz 69 70 MAX1206 toc12 70 68 69 fIN = 70.1MHz 68 67 SINAD (dB) 67 SNR (dB) MAX1206 toc13 SIGNAL-TO-NOISE + DISTORTION vs. SAMPLING RATE SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE 66 65 64 66 65 64 63 63 62 62 61 61 60 60 10 15 20 25 30 35 10 40 15 20 TOTAL HARMONIC DISTORTION vs. SAMPLING RATE 35 40 100 85 SFDR (dBc) 90 -75 -85 fIN = 70.1MHz 95 -70 -80 MAX1206 toc15 fIN = 70.1MHz -65 THD (dBc) 30 SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE MAX1206 toc14 -60 25 fCLK (MHz) fCLK (MHz) 80 75 -90 70 -95 65 -100 10 15 20 25 fCLK (MHz) 30 35 40 60 10 15 20 25 30 35 40 fCLK (MHz) _______________________________________________________________________________________ 9 MAX1206 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY 69 68 69 68 67 67 SINAD (dB) SNR (dB) MAX1206 toc17 70 MAX1206 toc16 70 66 65 64 66 65 64 63 63 62 62 61 61 60 60 0 25 50 75 100 125 0 ANALOG INPUT FREQUENCY (MHz) 100 100 95 90 -75 85 SFDR (dBc) -70 -80 -85 125 80 75 -90 70 -95 65 -100 0 25 50 75 100 ANALOG INPUT FREQUENCY (MHz) 10 75 MAX1206 toc19 -65 50 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY MAX1206 toc18 -60 25 ANALOG INPUT FREQUENCY (MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY THD (dBc) MAX1206 40Msps, 12-Bit ADC 125 60 0 25 50 75 100 ANALOG INPUT FREQUENCY (MHz) ______________________________________________________________________________________ 125 40Msps, 12-Bit ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER 60 60 SINAD (dB) 65 55 50 50 45 45 40 40 35 35 -25 -20 -15 -10 -5 0 -30 -25 -20 -15 -10 -5 ANALOG INPUT POWER (dBFS) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER -55 fIN = 19.900286MHz -60 95 80 SFDR (dBc) 85 -70 -80 fIN = 19.900286MHz 90 -65 -75 0 MAX1206 toc23 ANALOG INPUT POWER (dBFS) MAX1206 toc22 -30 THD (dBc) fIN = 19.900286MHz 70 65 55 MAX1206 toc21 fIN = 19.900286MHz 70 SNR (dB) 75 MAX1206 toc20 75 SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT POWER 75 70 -85 65 -90 60 -95 -30 -25 -20 -15 -10 ANALOG INPUT POWER (dBFS) -5 0 55 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS) ______________________________________________________________________________________ 11 MAX1206 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE SINGLE-ENDED CLOCK fIN = 19.9002858MHz 70 71 69 70 SINGLE-ENDED CLOCK fIN = 19.9002858MHz 69 68 68 67 SINAD (dB) DCE = HIGH 66 65 64 67 DCE = HIGH 66 65 64 DCE = LOW 63 63 62 62 61 DCE = LOW 61 20 30 40 50 60 70 80 20 30 CLOCK DUTY CYCLE (%) 50 60 70 80 SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE 100 MAX1206 toc26 -65 -70 95 DCE = LOW SINGLE-ENDED CLOCK fIN = 19.9002858MHz 90 SFDR (dBc) -75 40 CLOCK DUTY CYCLE (%) MAX1206 toc27 SNR (dB) MAX1206 toc25 SIGNAL-TO-NOISE + DISTORTION vs. CLOCK DUTY CYCLE MAX1206 toc24 71 THD (dBc) MAX1206 40Msps, 12-Bit ADC -80 -85 85 DCE = HIGH 80 DCE = LOW 75 -90 DCE = HIGH -95 70 SINGLE-ENDED CLOCK fIN = 19.9002858MHz 65 -100 20 30 40 50 60 CLOCK DUTY CYCLE (%) 12 70 80 20 30 40 50 60 70 CLOCK DUTY CYCLE (%) ______________________________________________________________________________________ 80 40Msps, 12-Bit ADC SIGNAL-TO-NOISE RATIO vs. ANALOG POWER-INPUT VOLTAGE 70 68 68 SINAD (dB) SNR (dB) 67 66 65 64 66 65 64 63 63 62 62 61 61 60 60 2.7 3.0 3.6 3.3 2.7 3.0 3.3 3.6 VDD (V) VDD (V) TOTAL HARMONIC DISTORTION vs. ANALOG POWER-INPUT VOLTAGE SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG POWER-INPUT VOLTAGE 100 MAX1206 toc30 fIN = 19.9MHz -65 fIN = 19.9MHz 95 90 -75 85 SFDR (dBc) -70 -80 80 -85 75 -90 70 -95 65 60 -100 2.7 3.0 2.7 3.6 3.3 3.0 3.3 3.6 VDD (V) VDD (V) 240 MAX1206 toc31b ANALOG POWER DISSIPATION vs. ANALOG POWER-INPUT VOLTAGE fIN = 19.9MHz 220 DIFFERENTIAL CLOCK 200 PDISS (mW) THD (dBc) fIN = 19.9MHz 69 67 -60 MAX1206 toc29 fIN = 19.9MHz MAX1206 toc31a 69 MAX1206 toc28 70 SIGNAL-TO-NOISE + DISTORTION vs. ANALOG POWER-INPUT VOLTAGE 180 160 SINGLE-ENDED CLOCK 140 120 2.7 3.0 3.3 3.6 VDD (V) ______________________________________________________________________________________ 13 MAX1206 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. TEMPERATURE 70 68 68 67 SINAD (dB) 66 65 64 66 65 64 63 63 62 62 61 61 60 60 -70 -15 10 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) TOTAL HARMONIC DISTORTION vs. TEMPERATURE SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE 100 MAX1206 toc34 -40 fIN = 19.9MHz -75 fIN = 19.9MHz 95 -80 85 MAX1206 toc35 SNR (dB) fIN = 19.9MHz 69 67 SFDR (dBc) 90 -85 85 -90 80 -95 75 -100 70 -40 -15 10 35 TEMPERATURE (°C) 14 MAX1206 toc33 fIN = 19.9MHz 69 SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE MAX1206 toc32 70 THD (dBc) MAX1206 40Msps, 12-Bit ADC 60 85 -40 -15 10 35 60 TEMPERATURE (°C) ______________________________________________________________________________________ 85 40Msps, 12-Bit ADC GAIN ERROR vs. TEMPERATURE OFFSET ERROR vs. TEMPERATURE 0.8 GAIN ERROR (%FR) -0.20 -0.22 VREFIN = 2.048V 0.9 -0.16 -0.18 MAX1206 toc37 VREFIN = 2.048V -0.14 OFFSET ERROR (%FS) 1.0 MAX1206 toc36 -0.12 -0.24 0.7 0.6 0.5 0.4 0.3 0.2 -0.26 0.1 -0.28 0 -40 -15 10 35 60 -40 85 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) Pin Description PIN NAME FUNCTION 1 REFP Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFP to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. 2 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. 3 COM Common-Mode Voltage I/O. Bypass COM to GND with a ≥2.2µF capacitor in parallel with a 0.1µF capacitor. 4, 7, 16, 35 GND Ground. Connect all ground pins and the EP together. 5 INP Positive Analog Input. For single-ended input operation, connect signal source to INP and connect INN to COM. For differential operation, connect the input signal between INP and INN. 6 INN Negative Analog Input. For single-ended input operation, connect INN to COM. For differential operation, connect the input signal between INP and INN. 8 DCE Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OVDD or DVDD) to enable the internal duty-cycle equalizer. 9 CLKN Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the clock signal to CLKP and tie CLKN to GND. 10 CLKP Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. ______________________________________________________________________________________ 15 MAX1206 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1µF, CL ≈ 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1µF to GND, 1µF in parallel with 10µF between REFP and REFN, CCOM = 0.1µF in parallel with 2.2µF to GND, TA = +25°C, unless otherwise noted.) MAX1206 40Msps, 12-Bit ADC Pin Description (continued) PIN NAME 11 CLKTYP Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OVDD or VDD to define the differential clock input. 12–15, 36 VDD Analog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential. 17, 34 OVDD Output Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of ≥2.2µF and 0.1µF. 18 DOR Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range. 19 D11 CMOS Digital Output, Bit 11 (MSB) 20 D10 CMOS Digital Output, Bit 10 21 D9 CMOS Digital Output, Bit 9 22 D8 CMOS Digital Output, Bit 8 23 D7 CMOS Digital Output, Bit 7 24 D6 CMOS Digital Output, Bit 6 25 D5 CMOS Digital Output, Bit 5 26 D4 CMOS Digital Output, Bit 4 27 D3 CMOS Digital Output, Bit 3 28 D2 CMOS Digital Output, Bit 2 29 D1 CMOS Digital Output, Bit 1 16 FUNCTION 30 D0 CMOS Digital Output, Bit 0 (LSB) 31, 32 I.C. Internally Connected. Leave I.C. unconnected. 33 DAV Data Valid Output. The DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. The MAX1211 evaluation kit (MAX1211EVKIT) utilizes DAV to latch data (D0–D11) into external back-end digital circuitry. 37 PD 38 REFOUT 39 REFIN 40 G/T Output Format Select Input. Connect G/T to GND for the two’s complement digital output format. Connect G/T to OVDD or VDD for the Gray code digital output format. — EP Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified performance. Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation. Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive-divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥0.1µF capacitor. Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass REFIN to GND with a ≥0.1µF capacitor. ______________________________________________________________________________________ 40Msps, 12-Bit ADC The MAX1206 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output, the total clock-cycle latency is 8.5 clock cycles. Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX1206 functional diagram. C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input-bandwidth T/H amplifier allows the MAX1206 to track and sample/hold analog inputs of high frequencies well beyond Nyquist. Analog input INP to INN can be driven either differentially or single ended. For differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (VDD / 2) for optimum performance. CLKP CLKN DCE CLKTYP CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER MAX1206 OVDD Input Track-and-Hold (T/H) Circuit Figure 3 displays a simplified functional diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the operational transconductance amplifier (OTA), and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on INP T/H INN VDD GND 12-BIT PIPELINE ADC D0–D11 DAV DOR OUTPUT DRIVERS DEC G/T REFOUT REFIN REFP COM REFN REFERENCE SYSTEM POWER CONTROL AND BIAS CIRCUITS PD Figure 2. Functional Diagram SWITCHES SHOWN IN TRACK MODE INTERNAL BIAS CML MAX1206 + T/H S2a ∑ x2 C1a S5a VDD - S3a C2a S4a INP FLASH ADC DAC OUT S4c S1 OTA OUT 1.5 BITS INN INP T/H INN STAGE 1 GAIN OF 8 4 BITS STAGE 2 GAIN OF 2 STAGE 9 GAIN OF 2 1.5 BITS 1.5 BITS STAGE 10 END OF PIPE S4b C2b C1b GND S3b 1 BIT S2b S5b DIGITAL ERROR CORRECTION D0–D11 Figure 1. Pipeline Architecture—Stage Blocks INTERNAL BIAS CML Figure 3. Internal T/H Circuit ______________________________________________________________________________________ 17 MAX1206 Detailed Description MAX1206 40Msps, 12-Bit ADC Table 1. Reference Modes VREFIN REFERENCE MODE 35% VREFOUT to 100% VREFOUT Internal reference mode. REFIN is driven by REFOUT either through a direct short or a resistive divider. VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. 0.7V to 2.3V Buffered external reference mode. An external 0.7V to 2.3V reference voltage is applied to REFIN. VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. <0.5V Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference sources. VREF is the difference between the externally applied VREFP and VREFN. Reference Output (REFOUT) An internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX1206. The power-down logic input (PD) enables and disables the reference circuit. REFOUT has approximately 17kΩ to GND when the MAX1206 is in power-down. The reference circuit requires 10ms to power up and settle when power is applied to the MAX1206 or when PD transitions from high to low. The internal bandgap reference and buffer generate REFOUT to be 2.048V with a +100ppm/°C temperature coefficient. Connect an external ≥0.1µF bypass capacitor from REFOUT to GND for stability. REFOUT sources up to 1.4mA and sinks up to 100µA for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits IREFOUT to a 2.1mA source current when shorted to GND and a 240µA sink current when shorted to VDD. Analog Inputs and Reference Configurations The MAX1206 full-scale analog input range is ±VREF with a common-mode input range of V DD / 2 ±0.8V. VREF is the difference between VREFP and VREFN. The MAX1206 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). To operate the MAX1206 with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive-divider. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 VREFIN / 4. The REFIN input impedance is very large (>50MΩ). When driving REFIN through a resistive-divider, use resistances ≥10kΩ to avoid loading REFOUT. Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX1206 REFOUT. In buffered external reference mode, apply a stable 0.7V to 2.3V source at REFIN. COM, REFP, and REFN are low-impedance outputs 18 with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. To operate the MAX1206 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With their buffers deactivated, COM, REFP, and REFN inputs must be driven through separate, external reference sources. Drive V COM to V DD / 2 ±5%, and drive REFP and REFN such that VCOM = (VREFP + VREFN) / 2. The analog input range is ±(VREFP - VREFN). All three modes of reference operation require the same bypass capacitor combination. Bypass COM with a 0.1µF capacitor in parallel with a ≥2.2µF capacitor to GND. Bypass REFP and REFN each with a 0.1µF capacitor to GND. Bypass REFP to REFN with a 1µF capacitor in parallel with a 10µF capacitor. Place the 1µF capacitor as close to the device as possible. Bypass REFIN and REFOUT to GND with a 0.1µF capacitor. For detailed circuit suggestions, see Figures 12 and 13. Clock Input and Clock Control Lines (CLKP, CLKN, CLKTYP, DCE) The MAX1206 accepts both differential and singleended clock inputs. For single-ended clock input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock input operation, connect CLKTYP to OVDD or VDD and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN are high impedance when the MAX1206 is powered down (Figure 4). Low clock jitter is required for the specified SNR performance of the MAX1206. Analog input sampling occurs on the falling edge of the clock signal, requiring this ______________________________________________________________________________________ 40Msps, 12-Bit ADC VDD S1H 1 SNR = 20 × log 2 × π × fIN × t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 68.5dB of SNR with an input frequency of 20MHz, the system must have less than 3ps of clock jitter. MAX1206 10kΩ CLKP 10kΩ Disabling the clock duty-cycle equalizer reduces the analog supply current by 1.5mA. System Timing Requirements Figure 5 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the falling edge of the clock. Data Valid Output (DAV) DAV is a single-ended version of the input clock (CLKP). The output data changes on the falling edge of DAV, and DAV rises once the output data is valid. The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE low), the DAV signal is the inverse of the signal at CLKP delayed by 6.4ns. With the duty-cycle equalizer enabled (DCE high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D0–D11 and DOR are valid from 13.9ns before the DUTYCYCLE EQUALIZER S2H 10kΩ S1L CLKN Clock Duty-Cycle Equalizer (DCE) The MAX1206 clock duty-cycle equalizer allows for a wide 20% to 80% clock duty cycle when enabled (DCE = OV DD or V DD ). When disabled (DCE = GND), the MAX1206 accepts a narrow 45% to 60% clock duty cycle. The clock duty-cycle equalizer uses a delay-locked loop to create internal timing signals that are duty-cycle independent. Due to this delay-locked loop, the MAX1206 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. MAX1206 edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 10kΩ S2L GND SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE. Figure 4. Simplified Clock Input Circuit rising edge of DAV to 10.7ns after the rising edge of DAV, and the rising edge of DAV is synchronized to have a 6.4ns delay from the falling edge of CLKP. DAV is high impedance when the MAX1206 is in powerdown (PD = high). DAV is capable of sinking and sourcing 600µA and has three times the drive strength of D0–D11 and DOR. DAV is typically used to latch the MAX1206 output data into an external back-end digital circuit. Keep the capacitive load on DAV as low as possible (<25pF) to avoid large digital currents feeding back into the analog portion of the MAX1206 and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX1211 evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer. Data Out-of-Range Indicator (DOR) The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (VREFP - VREFN) to (VREFN - VREFP). Signals outside this valid differential range cause DOR to assert high as shown in Table 2. ______________________________________________________________________________________ 19 MAX1206 40Msps, 12-Bit ADC Table 2. Output Codes vs. Input Voltage GRAY CODE OUTPUT CODE T = 1) (G/T TWO’S COMPLEMENT OUTPUT CODE T = 0) (G/T DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT DOR OF OF D11 D0 D11 D0 (CODE10) BINARY D11 D0 DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT DOR OF OF D11 D0 D11 D0 (CODE10) BINARY D11 D0 +2047 >+1.0235V (DATA OUT OF RANGE) 0 0x7FF +2047 +1.0235V 0 0x7FE +2046 +1.0230V 0000 0000 0010 0 0x002 +2 +0.0010V 0000 0000 0001 0 0x001 +1 +0.0005V +2048 0000 0000 0000 0 0x000 0 +0.0000V +2047 1111 1111 1111 0 0xFFF -1 -0.0005V +2046 1111 1111 1110 0 0xFFE -2 -0.0010V 0x001 +1 1000 0000 0001 0 0x801 -2047 -1.0235V 0x000 0 1000 0000 0000 0 0x800 -2048 -1.0240V 0x000 0 1000 0000 0000 1 0x800 -2048 <-1.0240V (DATA OUT OF RANGE) 1 0x800 +4095 0111 1111 1111 1 1000 0000 0000 0 0x800 +4095 0111 1111 1111 1000 0000 0001 0 0x801 +4094 0111 1111 1110 1100 0000 0011 0 0xC03 +2050 1100 0000 0001 0 0xC01 +2049 1100 0000 0000 0 0xC00 0100 0000 0000 0 0x400 0100 0000 0001 0 0x401 0000 0000 0001 0 0000 0000 0000 0 0000 0000 0000 1 N+4 DIFFERENTIAL ANALOG INPUT (INP - INN) N+5 N+3 N-3 N-2 N-1 ) ( 0x7FF 1000 0000 0000 (VREFP - VREFN) VINP - VINN VREFP = 2.162V VREFN = 1.138V N N+1 N+6 N+2 N+7 N+9 N+8 (VREFN - VREFP) tAD CLKN CLKP tDAV tCL tCH DAV tSETUP D0–D11 tHOLD N-3 8.5 CLOCK CYCLE DATA LATENCY N-2 N-1 N N+1 N+ 2 N+3 N+4 N+5 N+6 tSETUP DOR Figure 5. System Timing Diagram 20 ______________________________________________________________________________________ N+7 N+8 N+9 tHOLD 40Msps, 12-Bit ADC The MAX1206 output data format is either Gray code or two’s complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two’s complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code-conversion example. The following equations, Table 2, Figure 6, and Figure 8 define the relationship between the digital output and the analog input: CODE10 − 2048 VINP − VINN = (VREFP − VREFN ) × 2 × 4096 TWO'S COMPLEMENT OUTPUT CODE (LSB) Digital Output Data (D0–D11), Output Format (G/T) The MAX1206 provides a 12-bit, parallel, tri-state output bus. D0–D11 and DOR update on the falling edge of DAV and are valid on the rising edge of DAV. 1 LSB = 2 x VREF 4096 VREF MAX1206 DOR is synchronized with DAV and transitions along with output data D0–D11. There is an 8.5 clock-cycle latency in the DOR function just as with the output data (Figure 5). DOR is high impedance when the MAX1206 is in power-down (PD = high). DOR enters a high-impedance state within 10ns of the rising edge of PD and becomes active within 10ns of PD’s falling edge. VREF = VREFP - VREFN VREF 0x7FF 0x7FE 0x7FD 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 6. Two’s Complement Transfer Function (G/T = 0) for Gray code (G/T = 1). 1 LSB = CODE10 VINP − VINN = (VREFP − VREFN ) × 2 × 4096 Keep the capacitive load on the MAX1206 digital outputs D0–D11 as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX1206 and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolate the MAX1206 from heavy capacitive loads. To improve the dynamic performance of the MAX1206, add 220Ω resistors in series with the digital outputs close to the MAX1206. Refer to the MAX1211 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 220Ω series resistors. Power-Down Input (PD) VREF = VREFP - VREFN VREF 0x800 0x801 0x803 GRAY OUTPUT CODE (LSB) for two’s complement (G/T = 0). where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. The digital outputs D0–D11 are high impedance when the MAX1206 is in power-down (PD = high). D0–D11 go high impedance within 10ns of the rising edge of PD and become active within 10ns of PD’s falling edge. 2 x VREF 4096 VREF 0xC01 0xC00 0x400 0x002 0x003 0x001 0x000 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 7. Gray Code Transfer Function (G/T = 1) MAX1206 is in its normal operating mode. With PD high, the MAX1206 is in power-down mode. The MAX1206 has two power modes that are controlled with the power-down digital input (PD). With PD low, the ______________________________________________________________________________________ 21 MAX1206 40Msps, 12-Bit ADC BINARY-TO-GRAY CODE CONVERSION GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D11 0 D7 1 1 1 0 D3 1 0 0 1 D0 1 0 0 0 BIT POSITION D11 BINARY 0 GRAY CODE 0 2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: 0 0 1 D3 1 1 BINARY10 = BINARY11 + GRAY10 BINARY10 = 0 + 1 GRAY10 = 1 BINARY10 = 1 D7 1 1 0 D3 1 1 0 BIT POSITION GRAY CODE WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION. GRAY10 = 1 + 0 1 D0 0 BINARY GRAY10 = BINARY10 + BINARY11 + 1 BINARYX = BINARYX+1 + GRAYX WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION. D11 0 2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAYX = BINARYX + BINARYX + 1 0 D7 1 0 0 1 D0 1 0 0 D11 BIT POSITION BINARY 0 D7 1 0 0 1 D3 1 1 0 1 D0 0 1 0 BIT POSITION GRAY CODE + 0 GRAY CODE 1 0 3) REPEAT STEP 2 UNTIL COMPLETE BINARY 1 3) REPEAT STEP 2 UNTIL COMPLETE GRAY9 = BINARY9 + BINARY10 BINARY9 = BINARY10 + GRAY9 GRAY9 = 1 + 1 BINARY9 = 1 + 0 GRAY9 = 0 BINARY9 = 1 D11 0 1 D7 + 1 1 0 D3 1 0 0 1 D0 1 0 0 BIT POSITION D11 BINARY 0 D7 1 0 0 1 D3 1 1 0 1 D0 0 1 0 BIT POSITION GRAY CODE + 0 1 0 GRAY CODE 0 4) THE FINAL GRAY CODE CONVERSTION IS: D11 D7 1 1 BINARY 4) THE FINAL BINARY CONVERSTION IS: BIT POSITION D11 0 1 1 1 0 1 0 0 D3 1 1 0 D0 0 BINARY 0 1 0 0 D7 1 1 1 0 D3 1 0 1 D0 0 GRAY CODE 0 1 0 0 1 1 1 0 1 0 1 0 GRAY CODE 0 1 1 1 0 1 0 0 1 1 0 0 BINARY EXCULSIVE OR TRUTH TABLE A B 0 0 1 1 0 1 0 1 Y = A + B 0 1 1 0 Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion 22 ______________________________________________________________________________________ BIT POSITION 40Msps, 12-Bit ADC • REFOUT has approximately 17kΩ to GND. • REFP, COM, REFN go high impedance with respect to VDD and GND, but there is an internal 4kΩ resistor between REFP and COM, as well as an internal 4kΩ resistor between REFN and COM. • D0–D11, DOR, and DAV go high impedance. • CLKP, CLKN clock inputs go high impedance (Figure 4). The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 10ms. When operating in the unbuffered external reference mode, the wake-up time is dependent on the external reference drivers. Applications Information Using Transformer Coupling In general, the MAX1206 provides better SFDR and THD with fully differential input signals than singleended input drive. In differential input mode, evenorder harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX1206 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 9 is good for input frequencies up to Nyquist (fCLK / 2). The circuit of Figure 10 converts a single-ended input signal to fully differential just as in Figure 9. However, MAX1206 The power-down mode allows the MAX1206 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX1206 parallel output bus goes high impedance in power-down mode, allowing other devices on the bus to be accessed. In power-down mode, all internal circuits are off, the analog supply current reduces to 0.045mA, and the digital supply current reduces to 6µA. The following list shows the state of the analog inputs and digital outputs in power-down mode: • INP, INN analog inputs are disconnected from the internal input amplifier (Figure 3). 24.9Ω INP 12pF 0.1µF 1 VIN N.C. 2 3 T1 MAX1206 6 5 4 MINICIRCUITS TT1-6 OR T1-1T COM 2.2µF 0.1µF 24.9Ω INN 12pF Figure 9. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist Figure 10 utilizes an additional transformer to improve the common-mode rejection, allowing high-frequency signals beyond the Nyquist frequency. The two sets of 49.9Ω termination resistors provide an equivalent 50Ω termination to the signal source. The second set of termination resistors connects to COM, providing the correct input common-mode voltage. Two 0Ω resistors in series with the analog inputs allow high IF input frequencies. These 0Ω resistors can be replaced with lowvalue resistors to limit the input bandwidth. Single-Ended AC-Coupled Input Signal Figure 11 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. Buffered External Reference Drives Multiple ADCs The buffered external reference mode allows for more control over the MAX1206 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50MΩ. Figure 12 shows the MAX6062 precision bandgap reference used as a common reference for multiple converters. The 2.048V output of the MAX6062 passes through a one-pole 10Hz lowpass filter to the MAX4250. The MAX4250 buffers the 2.048V reference before its ______________________________________________________________________________________ 23 MAX1206 40Msps, 12-Bit ADC 0Ω* INP 0.1µF 1 VIN N.C. T1 6 2 5 3 4 MINICIRCUITS ADT1-1WT 1 49.9Ω 0.5% N.C. 49.9Ω 0.5% T1 6 2 5 3 4 12pF 49.9Ω 0.5% N.C. 0.1µF MAX1206 COM 4.7µF 49.9Ω 0.5% MINICIRCUITS ADT1-1WT 0Ω* INN *0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH. 12pF Figure 10. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist output is applied to the REFIN input of the MAX1206. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. Unbuffered External Reference Drives Multiple ADCs The unbuffered external reference mode allows for precise control over the MAX1206 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources. Figure 13 shows the MAX6066 precision bandgap reference used as a common reference for multiple converters. The 2.500V output of the MAX6066 is followed by a 10Hz lowpass filter and precision voltage-divider. The MAX4254 buffers the taps of this divider to provide the +2.000V, +1.500V, and +1.000V sources to drive REFP, REFN, and COM. The MAX4254 provides a low offset voltage and low noise level. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nV/√Hz. The 2.000V and 1.000V reference voltages set the differential full-scale range of the associated ADCs at ±1.000V. The common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4254 matching better than 0.1%, the buffers and subsequent lowpass support as many as 8 ADCs. Grounding, Bypassing, and Board Layout The MAX1206 requires high-speed board layout design techniques. Refer to the MAX1211 evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, prefer24 VIN MAX1206 0.1µF INP MAX4108 12pF 100Ω 24.9Ω 100Ω 24.9Ω 2.2µF 0.1µF COM INN 12pF Figure 11. Single-Ended, AC-Coupled Input Drive ably on the same side as the ADC, using surfacemount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Bypass OVDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All MAX1206 GNDs and the exposed backside paddle must be connected to the same ground plane. The MAX1206 relies on the exposed backside paddle connection for a low-inductance ground connection. Use mulitple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. ______________________________________________________________________________________ 40Msps, 12-Bit ADC MAX1206 +3.3V 2.2µF 0.1µF VDD 39 1 3 5 MAX6062 *1µF MAX1206 MAX4250 2 16.2kΩ 1 0.1µF 0.1µF 0.1µF REFP REFIN REFN 2 0.1µF 1µF 4 3 2 10µF 6V 10µF 2.048V 47Ω 1 0.1µF 47µF 6V 38 REFOUT 0.1µF COM 3 0.1µF GND 2.2µF 1.47kΩ NOTE: ONE FRONT-END REFERENCE CIRCUIT PROVIDES ±15mA OF OUTPUT DRIVE. +3.3V 2.2µF 0.1µF VDD 39 REFIN REFP 1 0.1µF *1µF MAX1206 REFN 0.1µF 10µF 2 0.1µF 38 0.1µF REFOUT COM GND 3 0.1µF 2.2µF *PLACE AS CLOSE TO THE DEVICE AS POSSIBLE. Figure 12. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1211 evaluation kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1206 are guaranteed by design using the best-straight-line fit method. ______________________________________________________________________________________ 25 26 Figure 13. External Unbuffered Reference Driving 8 ADCs with MAX4254 and MAX6066 ______________________________________________________________________________________ 13 12 11 4 14 1µF 3 MAX4254 1/4 0.1µF UNCOMMITTED *PLACE AS CLOSE TO THE DEVICE AS POSSIBLE. 1MΩ 1MΩ +3.3V 1 MAX6066 NOTE: ONE FRONT-END REFERENCE CIRCUIT SUPPORTS UP TO 8 MAX1206s. 0.1µF +3.3V 2 2.500V 21.5kΩ 1% 21.5kΩ 1% 21.5kΩ 1% 21.5kΩ 1% 21.5kΩ 1% 9 10 6 5 2 3 10µF 6V 8 1/4 MAX4254 10µF 6V 7 1/4 MAX4254 10µF 6V 1 1/4 MAX4254 1.47kΩ 47Ω 1.47kΩ 47Ω 1.47kΩ 47Ω 330µF 6V 1.000V 330µF 6V 1.500V 330µF 6V 2.000V 2.2µF 10µF 2.2µF 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF *1µF *1µF 3 2 1 3 2 1 COM REFN REFP +3.3V COM REFN REFP GND MAX1206 VDD GND 0.1µF REFIN REFOUT REFIN REFOUT MAX1206 VDD 39 38 39 38 0.1µF 0.1µF 0.1µF 2.2µF 2.2µF MAX1206 40Msps, 12-Bit ADC 40Msps, 12-Bit ADC CLKN CLKP tAD ANALOG INPUT tAJ SAMPLED DATA T/H HOLD TRACK HOLD Figure 14. T/H Aperture Timing SNRdB[max] = 6.02dB × N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset. Signal-to-Noise Plus Distortion (SINAD) Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Offset Error Ideally, the midscale MAX1206 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. Gain Error Ideally, the positive full-scale MAX1206 transition occurs at 1.5 LSB below positive full scale, and the negative full-scale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points. Aperture Jitter Figure 14 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD − 1.76 ENOB = 6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 × log V1 Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14). where V1 is the fundamental amplitude, and V2 through V7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2–HD7). Overdrive Recovery Time Single-Tone Spurious-Free Dynamic Range (SFDR) Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX1206 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ±10%. SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset. ______________________________________________________________________________________ 27 MAX1206 Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): Two-Tone Spurious-Free Dynamic Range (SFDRTT) The fundamental input tone amplitudes (V1 and V2) are at -7dBFS. Fourteen intermodulation products (VIMP_) are used in the MAX1206 calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies: • 2nd-order intermodulation products: f1 + f2, f2 - f1 • 3rd-order intermodulation products: 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 • 4th-order intermodulation products: 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 • 5th-order intermodulation products: 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1 29 D1 3 28 D2 4 27 D3 GND 7 24 D6 DCE CLKN 8 23 D7 26 D4 5 MAX1206 6 9 25 D5 22 D8 EXPOSED PADDLE (GND) 21 D9 CLKP 10 THIN QFN 6mm × 6mm × 0.8mm intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1. Chip Information TRANSISTOR COUNT: 18,700 PROCESS: CMOS 3rd-Order Intermodulation (IM3) IM3 is the total power of the 3rd-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -7dBFS. The 3rd-order 28 31 I.C. 32 I.C. 33 DAV 34 OVDD 35 GND 36 VDD 37 PD 38 REFOUT 39 REFIN 40 G/T 30 D0 2 D11 19 D10 20 2 2 V 2 + V IMP1 IMP2 + • • • • + VIMPn IMD = 20 x log V12 + V22 1 DOR 18 IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: REFP REFN COM GND INP INN VDD 15 GND 16 OVDD 17 Intermodulation Distortion (IMD) TOP VIEW VDD 12 VDD 13 VDD 14 SFDRTT represents the ratio, expressed in decibels, of the RMS amplitude of either input tone to the RMS amplitude of the next-largest spurious component in the spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist and is usually an intermodulation product or a harmonic. Pin Configuration CLKTYP 11 MAX1206 40Msps, 12-Bit ADC ______________________________________________________________________________________ 40Msps, 12-Bit ADC QFN THIN 6x6x0.8.EPS Note: For the MAX1206 exposed pad variations, the package code is T4066-3. D2 D CL D/2 b D2/2 k E/2 E2/2 (NE-1) X e E CL E2 k e L (ND-1) X e e L CL CL L1 L L e A1 A2 e A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1206 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)