19-3343; Rev 0; 8/04 KIT ATION EVALU LE B A IL A AV 14-Bit, 65Msps, 3.3V ADC Features ♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Performance 74.0dB/71dB SNR at fIN = 3MHz/175MHz 90.6dBc/80.7dBc SFDR at fIN = 3MHz/175MHz ♦ Low Noise Floor: -76dBFS ♦ 3.3V Low-Power Operation 337mW (Single-Ended Clock Mode) 363mW (Differential Clock Mode) 150µW (Power-Down Mode) ♦ Fully Differential or Single-Ended Analog Input ♦ Adjustable Full-Scale Analog Input Range: ±0.35V to ±1.10V Applications IF and Baseband Communication Receivers Cellular, Point-to-Point Microwave, HFC, WLAN Ultrasound and Medical Imaging Portable Instrumentation ♦ Common-Mode Reference ♦ CMOS-Compatible Outputs in Two’s Complement or Gray Code ♦ Data-Valid Indicator Simplifies Digital Interface ♦ Data Out-of-Range Indicator ♦ Miniature, 40-Pin Thin QFN Package with Exposed Paddle ♦ Evaluation Kit Available (Order MAX12555EVKIT) Ordering Information PART TEMP RANGE PIN-PACKAGE PKG CODE MAX12553ETL -40°C to +85°C 40 Thin QFN (6mm x 6mm x 0.8mm) T4066-3 Pin-Compatible Versions PART SAMPLING RATE (Msps) RESOLUTION (BITS) TARGET APPLICATION MAX12553 65 14 IF/Baseband MAX1209 80 12 IF MAX1211 65 12 IF MAX1208 80 12 Baseband MAX1207 65 12 Baseband MAX1206 40 12 Baseband Low-Power Data Acquisition Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX12553 General Description The MAX12553 is a 3.3V, 14-bit, 65Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts singleended or differential signals. The MAX12553 is optimized for low-power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12553 ideal for intermediatefrequency (IF) sampling applications. Powered from a single 3.15V to 3.60V supply, the MAX12553 consumes only 363mW while delivering a typical signal-to-noise (SNR) performance of 71dB at an input frequency of 175MHz. In addition to low operating power, the MAX12553 features a 150µW powerdown mode to conserve power during idle periods. A flexible reference structure allows the MAX12553 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12553 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12553 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 14-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply, allowing the MAX12553 to interface with various logic levels. The MAX12553 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C) temperature range. See the Pin-Compatible Versions table for a complete family of 14-bit and 12-bit high-speed ADCs. MAX12553 14-Bit, 65Msps, 3.3V ADC ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated 26.3mW/°C above +70°C)........................2105.3mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C VDD to GND ...........................................................-0.3V to +3.6V OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND................-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V D13–D0, DAV, DOR to GND....................-0.3V to (OVDD + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity 14 Bits INL fIN = 3MHz (Note 5) ±1.4 ±4.2 LSB DNL fIN = 3MHz, no missing codes over temperature (Note 3) ±0.5 ±1.0 LSB Offset Error VREFIN = 2.048V ±0.1 ±0.55 %FS Gain Error VREFIN = 2.048V ±0.5 ±4.9 %FS ANALOG INPUT (INP, INN) Differential Input Voltage Range VDIFF Differential or single-ended inputs Common-Mode Input Voltage Input Capacitance (Figure 3) CPAR CSAMPLE Fixed capacitance to ground ±1.024 V VDD/2 V 2 Switched capacitance pF 4.5 CONVERSION RATE Maximum Clock Frequency fCLK 65 MHz Minimum Clock Frequency 5 Data Latency Figure 6 MHz 8.5 Clock cycles -76.0 dBFS DYNAMIC CHARACTERISTICS (differential inputs, Note 2) Small-Signal Noise Floor SSNF Input at less than -35dBFS fIN = 3MHz at -0.5dBFS (Note 8) Signal-to-Noise Ratio Signal-to-Noise and Distortion SNR SINAD 74.0 fIN = 32.5MHz at -0.5dBFS 73.9 fIN = 70MHz at -0.5dBFS 73.4 fIN = 175MHz at -0.5dBFS (Notes 7, 8) 68.0 71.0 fIN = 3MHz at -0.5dBFS (Note 8) 69.2 73.9 fIN = 32.5MHz at -0.5dBFS 73.1 fIN = 70MHz at -0.5dBFS 73.1 fIN = 175MHz at -0.5dBFS (Notes 7, 8) 2 69.3 67.6 70.0 _______________________________________________________________________________________ dB dB 14-Bit, 65Msps, 3.3V ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS fIN = 3MHz at -0.5dBFS Spurious-Free Dynamic Range SFDR THD HD2 Third Harmonic HD3 Intermodulation Distortion Third-Order Intermodulation Two-Tone Spurious-Free Dynamic Range IMD IM3 SFDRTT 79.8 90.6 84.0 fIN = 70MHz at -0.5dBFS 87.8 75.9 MAX UNITS dBc 80.7 fIN = 3MHz at -0.5dBFS -90.6 fIN = 32.5MHz at -0.5dBFS -81.0 fIN = 70MHz at -0.5dBFS -85.4 fIN = 175MHz at -0.5dBFS -78.9 fIN = 3MHz at -0.5dBFS Second Harmonic TYP fIN = 32.5MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS (Note 7) Total Harmonic Distortion MIN -80.2 dBc -71.3 -99 fIN = 32.5MHz at -0.5dBFS -91 fIN = 70MHz at -0.5dBFS -92 fIN = 175MHz at -0.5dBFS -81 fIN = 3MHz at -0.5dBFS -94 fIN = 32.5MHz at -0.5dBFS -84 fIN = 70MHz at -0.5dBFS -88 fIN = 175MHz at -0.5dBFS -86 fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS -87 fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS -80 fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS -91 fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS -83 fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS 90 fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS 81 dBc dBc dBc dBc dBc Aperture Delay tAD Figure 4 1.2 ns Aperture Jitter tAJ Figure 4 <0.2 psRMS Output Noise nOUT INP = INN = COM 0.95 LSBRMS 1 Clock cycles Overdrive Recovery Time ±10% beyond full scale _______________________________________________________________________________________ 3 MAX12553 ELECTRICAL CHARACTERISTICS (continued) MAX12553 14-Bit, 65Msps, 3.3V ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.048 2.066 V INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally) REFOUT Output Voltage VREFOUT 2.002 COM Output Voltage VCOM VDD/2 1.65 V Differential Reference Output Voltage VREF VREF = VREFP - VREFN = VREFIN x 3/4 1.536 V REFOUT Load Regulation REFOUT Temperature Coefficient TCREF REFOUT Short-Circuit Current 35 mV/mA +50 ppm/°C Short to VDD—sinking 0.24 Short to GND—sourcing 2.1 mA BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage VREFIN 2.048 V REFP Output Voltage VREFP (VDD/2) + (VREFIN x 3/8) 2.418 V REFN Output Voltage VREFN (VDD/2) - (VREFIN x 3/8) 0.882 V COM Output Voltage VCOM VDD/2 1.60 1.65 1.70 V Differential Reference Output Voltage VREF VREF = VREFP - VREFN = VREFIN x 3/4 1.463 1.536 1.601 V Differential Reference Temperature Coefficient ±25 ppm/°C REFIN Input Resistance >50 MΩ UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally) COM Input Voltage VDD/2 1.65 V REFP Input Voltage VCOM VREFP - VCOM 0.768 V REFN Input Voltage VREFN - VCOM -0.768 V 1.536 V 1 mA Differential Reference Input Voltage VREF VREF = VREFP - VREFN = VREFIN x 3/4 REFP Sink Current IREFP VREFP = 2.418V REFN Source Current IREFN VREFN = 0.882V COM Sink Current ICOM 0.7 mA 0.7 mA REFP, REFN Capacitance 13 pF COM Capacitance 6 pF CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold VIH CLKTYP = GND, CLKN = GND Single-Ended Input Low Threshold VIL CLKTYP = GND, CLKN = GND 0.8 x VDD V 0.2 x VDD V Differential Input Voltage Swing CLKTYP = high 1.4 VP-P Differential Input Common-Mode Voltage CLKTYP = high VDD / 2 V 4 _______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Input Resistance RCLK Input Capacitance CCLK CONDITIONS MIN Figure 5 TYP MAX UNITS 5 kΩ 2 pF DIGITAL INPUTS (CLKTYP, G/T, PD) Input High Threshold VIH Input Low Threshold VIL Input Leakage Current Input Capacitance 0.8 x OVDD V 0.2 x OVDD VIH = OVDD ±5 VIL = 0 ±5 CDIN 5 V µA pF DIGITAL OUTPUTS (D13–D0, DAV, DOR) Output Voltage Low Output Voltage High VOL D13–D0, DOR, ISINK = 200µA 0.2 DAV, ISINK = 600µA 0.2 D13–D0, DOR, ISOURCE = 200µA OVDD 0.2 DAV, ISOURCE = 600µA OVDD 0.2 V V VOH Tri-State Leakage Current ILEAK (Note 4) ±5 µA D13–D0, DOR Tri-State Output Capacitance COUT (Note 4) 3 pF DAV Tri-State Output Capacitance CDAV (Note 4) 6 pF POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage Analog Supply Current VDD 3.15 3.3 3.60 V OVDD 1.7 2.0 VDD + 0.3V V IVDD Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = GND, single-ended clock 102 Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = OVDD, differential clock 110 Power-down mode clock idle, PD = OVDD mA 123 0.045 _______________________________________________________________________________________ 5 MAX12553 ELECTRICAL CHARACTERISTICS (continued) MAX12553 14-Bit, 65Msps, 3.3V ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Analog Power Dissipation Digital Output Supply Current SYMBOL PDISS IOVDD CONDITIONS MIN TYP MAX UNITS Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = GND, single-ended clock 337 Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = OVDD, differential clock 363 Power-down mode clock idle, PD = OVDD 0.15 Normal operating mode, fIN = 175MHz at -0.5dBFS, OVDD = 2.0V, CL ≈ 5pF 8.2 mA Power-down mode clock idle, PD = OVDD 20 µA mW 406 TIMING CHARACTERISTICS (Figure 6) Clock Pulse-Width High tCH 7.7 ns Clock Pulse-Width Low tCL 7.7 ns 6.9 ns Data-Valid Delay tDAV CL = 5pF (Note 6) Data Setup Time Before Rising Edge of DAV tSETUP CL = 5pF (Notes 5, 6) 8.5 ns Data Hold Time After Rising Edge of DAV tHOLD CL = 5pF (Notes 5, 6) 6.3 ns Wake-Up Time from Power-Down tWAKE VREFIN = 2.048V 10 ms Specifications ≥+25°C guaranteed by production test; <+25°C guaranteed by design and characterization. See definitions in the Parameter Definitions section at the end of this data sheet. Specifications guaranteed by design and characterization. Devices tested for performance during production test. During power-down, D13–D0, DOR, and DAV are high impedance. Guaranteed by design and characterization. Digital outputs settle to VIH or VIL. Due to test-equipment-jitter limitations at 175MHz, 0.15% of the spectrum on each side of the fundamental is excluded from the spectral analysis. Note 8: Limit specifications include performance degradations due to a production test socket. Performance is improved when the MAX12553 is soldered directly to the PC board. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 6 _______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC HD2 HD3 -110 -120 -50 -60 -70 -80 -90 -100 HD2 4 8 HD3 12 16 20 24 28 32 -110 -120 0 4 8 12 16 20 24 28 32 0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 HD3 HD2 0 -10 -20 -30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) HD5 fCLK = 64.96256MHz fIN = 250.00911MHz AIN = -0.494dBFS SNR = 69.39dB SINAD = 68.67dB THD = -76.8dBc SFDR = 78.6dBc 16 20 24 28 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32 0 INTEGRAL NONLINEARITY 12 16 1.5 24 28 20 24 32 28 0.6 0.4 0.5 0 -0.5 32 16 0.8 DNL (LSB) INL (LSB) fIN1 + fIN2 20 12 DIFFERENTIAL NONLINEARITY 1.0 FREQUENCY (MHz) 8 1.0 MAX12553 toc08 2.0 MAX12553 toc07 fIN2 fIN1 -100 -110 -120 8 4 FREQUENCY (MHz) 0.2 0 -0.2 -0.4 -1.0 4 2 x fIN2 - fIN1 FREQUENCY (MHz) fCLK = 65.00352MHz fIN1 = 172.4870625MHz AIN1 = -7.047dBFS fIN2 = 177.4861125MHz AIN2 = -6.984dBFS SFDRTT = 81.484dBc IMD = -80.035dBc IM3 = -83.511dBc fIN2 - fIN1 2 x fIN2 - fIN1 fIN2 MAX12553 toc09 4 fCLK = 65MHz fIN1 = 68.50311279MHz AIN1 = -7.018dBFS fIN2 = 71.50238037MHz AIN2 = -7.087dBFS SFDRTT = 90.085dBc IMD = -87.812dBc IM3 = -91.844dBc fIN1 -40 -50 -60 -70 -80 -90 32 -100 -110 -120 TWO-TONE FFT PLOT (16,384-POINT DATA RECORD) 0 12 TWO-TONE FFT PLOT (16,384-POINT DATA RECORD) FREQUENCY (MHz) -70 -80 -90 8 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) -100 -110 -120 -40 -50 -60 4 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) -100 -110 -120 0 -10 -20 -30 HD3 HD2 FREQUENCY (MHz) HD2 0 -50 -60 -70 -80 -90 -100 FREQUENCY (MHz) fCLK = 65MHz fIN = 174.9017334MHz AIN = -0.499dBFS SNR = 70.971dB SINAD = 70.260dB THD = -78.475dBc SFDR = 80.267dBc -40 -50 -60 -70 -80 -90 -40 FREQUENCY (MHz) MAX12553 toc04 0 -10 -20 -30 AMPLITUDE (dBFS) -20 -30 -110 -120 0 AMPLITUDE (dBFS) -40 fCLK = 65MHz fIN = 69.89562988MHz AIN = -0.460dBFS SNR = 73.772dB SINAD = 73.615dB THD = -88.110dBc SFDR = 88.325dBc MAX12553 toc03 -20 -30 0 -10 MAX12553 toc06 -50 -60 -70 -80 -90 -100 fCLK = 65MHz fIN = 32.39685059MHz AIN = -0.469dBFS SNR = 74.206dB SINAD = 73.534dB THD = -81.965dBc SFDR = 86.015dBc AMPLITUDE (dBFS) -40 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) MAX12553 toc05 AMPLITUDE (dBFS) -20 -30 0 -10 AMPLITUDE (dBFS) fCLK = 65MHz fIN = 3.00720215MHz AIN = -0.542dBFS SNR = 74.223dB SINAD = 74.147dB THD = -91.794dBc SFDR = 91.499dBc MAX12553 toc01 0 -10 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) MAX12553 toc02 SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD) -0.6 -1.5 -0.8 -2.0 -1.0 0 4096 8192 12288 DIGITAL OUTPUT CODE 16384 0 4096 8192 12288 16384 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 7 MAX12553 Typical Operating Characteristics (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK ≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK ≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) SFDR, -THD vs. SAMPLING RATE 90 72 71 70 69 68 85 80 75 70 67 65 SNR SINAD 66 65 20 40 60 80 ANALOG + DIGITAL POWER ANALOG POWER 200 0 20 40 60 80 20 0 40 60 SFDR, -THD vs. SAMPLING RATE POWER DISSIPATION vs. SAMPLING RATE 95 70 69 85 80 75 68 70 67 SNR SINAD 66 65 65 500 80 0 20 40 fCLK (MHz) SNR, SINAD vs. ANALOG INPUT FREQUENCY SFDR, -THD vs. ANALOG INPUT FREQUENCY fCLK ≈ 65MHz 73 71 fCLK ≈ 65MHz 90 SFDR, -THD (dBc) 67 65 63 80 75 70 61 65 59 SNR SINAD 60 55 200 300 ANALOG INPUT FREQUENCY (MHz) 400 20 40 60 500 DIFFERENTIAL CLOCK fCLK ≈ 65MHz CL ≈ 5pF 450 80 400 350 300 250 SFDR -THD 55 100 0 POWER DISSIPATION vs. ANALOG INPUT FREQUENCY 85 69 ANALOG + DIGITAL POWER ANALOG POWER fCLK (MHz) 95 MAX12553 toc16 75 300 80 60 fCLK (MHz) POWER DISSIPATION (mW) 60 350 200 MAX12553 toc17 40 400 250 SFDR -THD 60 20 DIFFERENTIAL CLOCK fIN ≈ 175MHz CL ≈ 5pF 450 MAX12553 toc18 SFDR, -THD (dB) 71 80 MAX12553 toc15 fIN ≈ 175MHz POWER DISSIPATION (mW) MAX12553 toc14 MAX12553 toc13 100 90 0 300 SNR, SINAD vs. SAMPLING RATE 72 57 350 fCLK (MHz) 73 0 400 250 SFDR -THD MAX12553 toc12 450 fCLK (MHz) fIN ≈ 175MHz 74 DIFFERENTIAL CLOCK fIN ≈ 70MHz CL ≈ 5pF fCLK (MHz) 75 8 500 60 0 SNR, SINAD (dB) fIN ≈ 70MHz 95 SFDR, -THD (dB) SNR, SINAD (dB) 73 MAX12553 toc11 fIN ≈ 70MHz 74 100 MAX12553 toc10 75 POWER DISSIPATION vs. SAMPLING RATE POWER DISSIPATION (mW) SNR, SINAD vs. SAMPLING RATE SNR, SINAD (dB) MAX12553 14-Bit, 65Msps, 3.3V ADC ANALOG + DIGITAL POWER ANALOG POWER 200 0 100 200 300 ANALOG INPUT FREQUENCY (MHz) 400 0 100 200 300 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 400 14-Bit, 65Msps, 3.3V ADC SFDR, -THD vs. ANALOG INPUT AMPLITUDE 55 50 45 40 80 70 60 50 450 35 40 SNR SINAD 30 25 30 -35 -30 -25 -20 -15 -10 0 -5 -30 -25 -20 -15 -10 0 -5 -40 -35 -30 -25 -20 -15 -10 POWER DISSIPATION vs. ANALOG SUPPLY VOLTAGE 90 72 71 70 69 85 80 75 70 67 SNR SINAD 66 3.2 3.4 3.6 2.8 3.0 VDD (V) 3.2 3.4 3.6 2.6 73 100 71 70 69 68 fCLK = 65MHz fIN = 174.9007416MHz 95 85 80 75 70 SNR SINAD SFDR -THD 65 2.6 OVDD (V) 3.0 3.4 3.8 3.2 3.4 500 DIFFERENTIAL CLOCK fCLK = 65MHz fIN = 174.9007416MHz CL ≈ 5pF 450 3.6 400 350 300 ANALOG + DIGITAL POWER ANALOG POWER 250 60 65 2.2 3.0 POWER DISSIPATION vs. DIGITAL SUPPLY VOLTAGE 90 SFDR, -THD (dBc) 72 1.8 2.8 VDD (V) POWER DISSIPATION (mW) fCLK = 65MHz fIN = 174.9007416MHz 66 ANALOG + DIGITAL POWER ANALOG POWER SFDR, -THD vs. DIGITAL SUPPLY VOLTAGE MAX12553 toc25 75 67 300 VDD (V) SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE 74 350 200 2.6 MAX12553 toc26 3.0 400 250 60 2.8 DIFFERENTIAL CLOCK fCLK = 64.96256MHz fIN = 175.00717MHz CL ≈ 5pF 450 SFDR -THD 65 65 500 MAX12553 toc24 95 fCLK = 64.96256MHz fIN = 175.00717MHz POWER DISSIPATION (mW) MAX12553 toc22 100 0 -5 SFDR, -THD vs. ANALOG SUPPLY VOLTAGE SFDR, -THD (dBc) SNR, SINAD (dB) -35 SNR, SINAD vs. ANALOG SUPPLY VOLTAGE 68 SNR, SINAD (dB) ANALOG + DIGITAL POWER ANALOG POWER ANALOG INPUT AMPLITUDE (dBFS) 73 1.4 300 ANALOG INPUT AMPLITUDE (dBFS) fCLK = 64.96256MHz fIN = 175.00717MHz 2.6 350 ANALOG INPUT AMPLITUDE (dBFS) 75 74 400 200 -40 MAX12553 toc23 -40 DIFFERENTIAL CLOCK fCLK = 64.96256MHz fIN = 175.0071MHz CL ≈ 5pF 250 SFDR -THD MAX12553 toc21 500 MAX12553 toc27 60 fCLK = 64.96256MHz fIN = 175.0071MHz 90 SFDR, -THD (dBc) SNR, SINAD (dB) 65 MAX12553 toc20 fCLK = 64.96256MHz fIN = 175.0071MHz 70 100 MAX12553 toc19 75 POWER DISSIPATION vs. ANALOG INPUT AMPLITUDE POWER DISSIPATION (mW) SNR, SINAD vs. ANALOG INPUT AMPLITUDE 200 1.4 1.8 2.2 2.6 OVDD (V) 3.0 3.4 3.8 1.4 1.8 2.2 2.6 3.0 3.4 3.8 OVDD (V) _______________________________________________________________________________________ 9 MAX12553 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK ≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK ≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) 73 71 70 69 fCLK = 65MHz fIN = 175MHz 86 SFDR, -THD (dBc) 72 88 68 84 82 80 78 76 67 74 SNR SINAD 66 SFDR -THD 72 65 500 70 -40 -15 10 35 60 85 10 35 60 85 450 400 350 300 250 -40 -15 TEMPERATURE (°C) 10 35 TEMPERATURE (°C) GAIN ERROR vs. TEMPERATURE OFFSET ERROR vs. TEMPERATURE VREFIN = 2.048V VREFIN = 2.048V 2 GAIN ERROR (%FS) 0.2 3 MAX12553 toc31 0.3 OFFSET ERROR (%FS) DIFFERENTIAL CLOCK fCLK = 65MHz fIN = 175MHz 200 -15 -40 TEMPERATURE (°C) 0.1 0 -0.1 1 0 -1 -2 -0.2 -3 -0.3 -40 -15 10 35 TEMPERATURE (°C) 10 MAX12553 toc30 90 MAX12553 toc32 fCLK = 65MHz fIN = 175MHz MAX12553 toc29 74 MAX12553 toc28 75 ANALOG POWER DISSIPATION vs. TEMPERATURE SFDR, -THD vs. TEMPERATURE ANALOG POWER DISSIPATION (mW) SNR, SINAD vs. TEMPERATURE SNR, SINAD (dB) MAX12553 14-Bit, 65Msps, 3.3V ADC 60 85 -40 -15 10 35 60 TEMPERATURE (°C) ______________________________________________________________________________________ 85 60 85 14-Bit, 65Msps, 3.3V ADC REFERENCE OUTPUT VOLTAGE LOAD REGULATION 2.03 3.0 2.5 1.99 1.97 2.0 1.5 +25°C 2.031 0.5 1.95 -1.5 -1.0 2.033 1.0 1.96 -0.5 0 -40°C 0 0.5 2.029 -2.0 -3.0 IREFOUT SINK CURRENT (mA) -1.0 0 1.0 -15 -40 IREFOUT SINK CURRENT (mA) 35 60 85 REFP, COM, REFN SHORT-CIRCUIT PERFORMACE VREFP 3.5 2.5 MAX12553 toc37 3.0 3.0 VCOM 2.5 VOLTAGE (V) 2.0 1.5 VREFN 10 TEMPERATURE (°C) REFP, COM, REFN LOAD REGULATION MAX12553 toc36 -2.0 2.035 +25°C -40°C 1.98 2.037 +85°C VREFOUT (V) VREFOUT (V) +85°C 2.00 VOLTAGE (V) VREFOUT (V) 2.02 2.039 MAX12553 toc35 2.04 MAX12553 toc34 3.5 MAX12553 toc33 2.05 2.01 REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE REFERENCE OUTPUT VOLTAGE SHORT-CIRCUIT PERFORMANCE VCOM 1.0 VREFP 2.0 1.5 VREFN 1.0 INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE 0.5 INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE 0.5 0 0 -2 -1 0 SINK CURRENT (mA) 1 2 -8 -4 0 4 8 12 SINK CURRENT (mA) ______________________________________________________________________________________ 11 MAX12553 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK ≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) 14-Bit, 65Msps, 3.3V ADC MAX12553 Pin Description PIN NAME FUNCTION REFP Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFP to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side of the PC board. 2 REFN Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFN to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side of the PC board. 3 COM Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the opposite side of the PC board and connected to the MAX12553 through a via. 4, 7, 16, 35 GND Ground. Connect all ground pins and EP together. 1 5 INP Positive Analog Input 6 INN Negative Analog Input 8 DCE Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer. 9 CLKN Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. 10 CLKP Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. 11 CLKTYP 12–15, 36 VDD Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential. 17, 34 OVDD Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of ≥2.2µF and 0.1µF. 18 DOR Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range (Figure 6). 19 D13 CMOS Digital Output, Bit 13 (MSB) 20 D12 CMOS Digital Output, Bit 12 21 D11 CMOS Digital Output, Bit 11 22 D10 CMOS Digital Output, Bit 10 23 D9 CMOS Digital Output, Bit 9 24 D8 CMOS Digital Output, Bit 8 25 D7 CMOS Digital Output, Bit 7 26 D6 CMOS Digital Output, Bit 6 27 D5 CMOS Digital Output, Bit 5 12 Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OVDD or VDD to define the differential clock input. ______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC PIN NAME 28 D4 CMOS Digital Output, Bit 4 FUNCTION 29 D3 CMOS Digital Output, Bit 3 30 D2 CMOS Digital Output, Bit 2 31 D1 CMOS Digital Output, Bit 1 32 D0 CMOS Digital Output, Bit 0 (LSB) 33 DAV 37 PD 38 REFOUT 39 REFIN 40 G/T Output Format Select Input. Connect G/T to GND for the two’s complement digital output format. Connect G/T to OVDD or VDD for the Gray code digital output format. — EP Exposed Paddle. The MAX12553 relies on the exposed paddle connection for a low-inductance ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the top-side PC board ground plane to the bottom-side PC board ground plane. Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. DAV is typically used to latch the MAX12553 output data into an external back-end digital circuit. Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation. Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥0.1µF capacitor. Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to GND with a ≥0.1µF capacitor. In these modes,VREFP - VREFN = VREFIN x 3/4. For unbuffered external reference mode operation, connect REFIN to GND. + MAX12553 T/H Σ − FLASH ADC DAC INP T/H STAGE 1 STAGE 2 STAGE 9 INN STAGE 10 END OF PIPE DIGITAL ERROR CORRECTION D13–D0 OUTPUT DRIVERS D13–D0 Figure 1. Pipeline Architecture—Stage Blocks ______________________________________________________________________________________ 13 MAX12553 Pin Description (continued) MAX12553 14-Bit, 65Msps, 3.3V ADC CLKP CLKN DCE CLKTYP CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER MAX12553 VDD GND BOND WIRE INDUCTANCE 1.5nH VDD INP OVDD INP INN T/H 14-BIT PIPELINE ADC DEC OUTPUT DRIVERS DOR *CSAMPLE 4.5pF BOND WIRE INDUCTANCE 1.5nH CPAR 2pF *CSAMPLE 4.5pF VDD INN REFIN COM CPAR 2pF D13–D0 DAV G/T REFOUT REFP MAX12553 REFERENCE SYSTEM POWER CONTROL AND BIAS CIRCUITS PD REFN Figure 2. Simplified Functional Diagram SAMPLING CLOCK Detailed Description The MAX12553 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. From input to output, the total clock-cycle latency is 8.5 clock cycles. Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX12553 functional diagram. Input Track-and-Hold (T/H) Circuit Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies of 175MHz and beyond and supports a common-mode input voltage of VDD/2 ±0.5V. The MAX12553 sampling clock controls the ADC’s switched-capacitor T/H architecture (Figure 3) allowing the analog input signal to be stored as charge on the sampling capacitors. These switches are closed (track) when the sampling clock is high and open (hold) when the sampling clock is low (Figure 4). The analog input signal source must be capable of providing the dynamic current necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these 14 *THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS: RSAMPLE = 1 fCLK x CSAMPLE Figure 3. Simplified Input T/H Circuit capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle. The analog input of the MAX12553 supports differential or single-ended input drive. For optimum performance with differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (VDD/2). The MAX12553 provides the optimum common-mode voltage of VDD/2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 10, 11, and 12. Reference Output (REFOUT) An internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX12553. The power-down logic input (PD) enables and disables the reference circuit. The reference circuit requires 10ms to power up and settle when power is applied to the MAX12553 or when PD transitions from high to low. REFOUT has approximately 17kΩ to GND when the MAX12553 is in power-down. The internal bandgap reference and its buffer generate VREFOUT to be 2.048V. The reference temperature coefficient is typically +50ppm/°C. Connect an external ≥0.1µF bypass capacitor from REFOUT to GND for stability. ______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC MAX12553 CLKP CLKN tAD ANALOG INPUT tAJ SAMPLED DATA T/H TRACK HOLD TRACK HOLD TRACK HOLD TRACK HOLD Figure 4. T/H Aperture Timing REFOUT sources up to 1.0mA and sinks up to 0.1mA for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits I REFOUT to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD. Analog Inputs and Reference Configurations The MAX12553 full-scale analog input range is adjustable from ±0.35V to ±1.10V with a commonmode input range of VDD/2 ±0.5V. The MAX12553 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). To operate the MAX12553 with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive divider. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD/2, VREFP = VDD/2 + VREFIN x 3/8, and VREFN = VDD/2 - VREFIN x 3/8. The REFIN input impedance is very large (>50MΩ). When driving REFIN through a resistive divider, use resistances ≥10kΩ to avoid loading REFOUT. Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX12553 REFOUT. In buffered external reference mode, apply a stable 0.7V to 2.2V source at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD/2, VREFP = VDD/2 + VREFIN x 3/8, and VREFN = VDD/2 - VREFIN x 3/8. To operate the MAX12553 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With the respective buffers deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive VCOM to VDD/2 ±5%, and drive REFP and REFN such that VCOM = (VREFP + VREFN)/2. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Table 1. Reference Modes VREFIN REFERENCE MODE 35% VREFOUT to 100% VREFOUT 0.7V to 2.2V <0.4V Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider. The full-scale analog input range is ±VREFIN/2: VCOM = VDD/2 VREFP = VDD/2 + VREFIN x 3/8 VREFN = VDD/2 - VREFIN x 3/8 Buffered External Reference Mode. Apply an external 0.7V to 2.2V reference voltage to REFIN. The full-scale analog input range is ±VREFIN/2: VCOM = VDD/2 VREFP = VDD/2 + VREFIN x 3/8 VREFN = VDD/2 - VREFIN x 3/8 Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. ______________________________________________________________________________________ 15 MAX12553 14-Bit, 65Msps, 3.3V ADC All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a 2.2µF capacitor to GND. Bypass REFP and REFN each with a 0.1µF capacitor to GND. Bypass REFP to REFN with a 1µF capacitor in parallel with a 10µF capacitor. Place the 1µF capacitor as close to the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a 0.1µF capacitor. For detailed circuit suggestions, see Figure 13 and Figure 14. VDD S1H MAX12553 10kΩ CLKP 10kΩ Clock Input and Clock Control Lines (CLKP, CLKN, CLKTYP) The MAX12553 accepts both differential and singleended clock inputs. For single-ended clock input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock input operation, connect CLKTYP to OVDD or VDD, and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN are high impedance when the MAX12553 is powered down (Figure 5). Low clock jitter is required for the specified SNR performance of the MAX12553. Analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 × log 2 × π fIN × t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 71dB of SNR with an input frequency of 175MHz, the system must have less than 0.25ps 16 DUTY-CYCLE EQUALIZER S2H S1L 10kΩ CLKN 10kΩ S2L GND SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE. Figure 5. Simplified Clock-Input Circuit of clock jitter. In actuality, there are other noise sources such as thermal noise and quantization noise that contribute to the system noise, requiring the clock jitter to be less than 0.2ps to obtain the specified 71dB of SNR at 175MHz. Clock Duty-Cycle Equalizer (DCE) The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the MAX12553 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. Disabling the clock duty-cycle equalizer reduces the analog supply current by 1.5mA. ______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC (VREFP - VREFN) x 2/3 N+5 N+3 N-3 N-2 N-1 N N+1 MAX12553 N+4 DIFFERENTIAL ANALOG INPUT (INP–INN) N+6 N+2 N+7 N+9 N+8 (VREFN - VREFP) x 2/3 tAD CLKN CLKP tDAV tCL tCH DAV tSETUP tHOLD D13–D0 N-3 8.5 CLOCK-CYCLE DATA LATENCY N-2 N-1 N N+1 N+2 N+3 N+4 N+5 tSETUP N+6 N+7 N+8 N+9 tHOLD DOR Figure 6. System-Timing Diagram System-Timing Requirements Figure 6 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the falling edge of the conversion clock (CLKP-CLKN). Data-Valid Output (DAV) DAV is a single-ended version of the input clock (CLKP). Output data changes on the falling edge of DAV, and DAV rises once output data is valid (Figure 6). The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE = low), the DAV signal is the inverse of the signal at CLKP delayed by 6.8ns (tDAV). With the duty-cycle equalizer enabled (DCE = high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D13–D0 and DOR are valid from 8.5ns before the rising edge of DAV to 6.3ns after the rising edge of DAV, and the rising edge of DAV is synchronized to have a 6.9ns (tDAV) delay from the falling edge of CLKP. DAV is high impedance when the MAX12553 is in power-down (PD = high). DAV is capable of sinking and sourcing 600µA and has three times the drive strength of D13–D0 and DOR. DAV is typically used to latch the MAX12553 output data into an external backend digital circuit. Keep the capacitive load on DAV as low as possible (<25pF) to avoid large digital currents feeding back into the analog portion of the MAX12553 and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX12555 evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer. ______________________________________________________________________________________ 17 MAX12553 14-Bit, 65Msps, 3.3V ADC Data Out-of-Range Indicator (DOR) The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (VREFP - VREFN) x 3/4 to (VREFN - VREFP) x 3/4. Signals outside this valid differential range cause DOR to assert high as shown in Table 2 and Figure 6. DOR is synchronized with DAV and transitions along with the output data D13–D0. There is an 8.5 clockcycle latency in the DOR function as is with the output data (Figure 6). DOR is high impedance when the MAX12553 is in power-down (PD = high). DOR enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD’s falling edge. Digital Output Data (D13–D0), Output Format (G/T) The MAX12553 provides a 14-bit, parallel, tri-state output bus. D13–D0 and DOR update on the falling edge of DAV and are valid on the rising edge of DAV. The MAX12553 output data format is either Gray code or two’s complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two’s complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code-conversion example. The following equations, Table 2, Figure 7, and Figure 8 define the relationship between the digital output and the analog input: 18 VINP − VINN = (VREFP − VREFN ) × 4 CODE10 − 8192 × 3 16384 for Gray code (G/T = 1) VINP − VINN = (VREFP − VREFN ) × 4 CODE10 × 3 16384 for two’s complement (G/T = 0) where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. Digital outputs D13–D0 are high impedance when the MAX12553 is in power-down (PD = high). D13–D0 transition high 10ns after the rising edge of PD and become active 10ns after PD’s falling edge. Keep the capacitive load on the MAX12553 digital outputs D13–D0 as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX12553 and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolates the MAX12553 from heavy capacitive loading. To improve the dynamic performance of the MAX12553, add 220Ω resistors in series with the digital outputs close to the MAX12553. Refer to the MAX12555 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 220Ω series resistors. Power-Down Input (PD) The MAX12553 has two power modes that are controlled with the power-down digital input (PD). With PD ______________________________________________________________________________________ ______________________________________________________________________________________ 0 0 0 0 1 01 0000 0000 0000 01 0000 0000 0001 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 0 11 0000 0000 0011 0 0 10 0000 0000 0001 0 0 10 0000 0000 0000 11 0000 0000 0000 1 10 0000 0000 0000 11 0000 0000 0001 DOR BINARY D13 ➝ D0 0x0000 0x0000 0x0001 0x1001 0x1000 0x3000 0x3001 0x3003 0x2001 0x2000 0x2000 0 0 +1 +8190 +8191 +8192 +8193 +8194 +16382 +16383 +16383 DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT OF OF D13 ➝ D0 D13 ➝ D0 (CODE10) GRAY CODE OUTPUT CODE (G/T = 1) 10 0000 0000 0000 10 0000 0000 0000 10 0000 0000 0001 11 1111 1111 1110 11 1111 1111 1111 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 01 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 BINARY D13 ➝ D0 1 0 0 0 0 0 0 0 0 0 1 DOR 0x2000 0x2000 0x2001 0x3FFE 0x3FFF 0x0000 0x0001 0x0002 0x1FFE 0x1FFF 0x1FFF -8192 -8192 -8191 -2 -1 0 +1 +2 +8190 +8191 +8191 DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT OF OF D13 ➝ D0 D13➝ D0 (CODE10) TWO’S-COMPLEMENT OUTPUT CODE (G/T = 0) ( <-1.024000V (DATA OUT OF RANGE) -1.024000V -1.023875V -0.000250V -0.000125V +0.000000V +0.000125V +0.000250V +1.023750V +1.023875V >+1.023875V (DATA OUT OF RANGE) ) VINP - VINN VREFP = 2.418V VREFN = 0.882V MAX12553 Table 2. Output Codes vs. Input Voltage 14-Bit, 65Msps, 3.3V ADC 19 1 LSB = VREFP - VREFN 4 x 3 16384 (VREFP - VREFN) x 2/3 1 LSB = (VREFP - VREFN) x 2/3 0x2000 0x1FFE 0x1FFD 0x2001 0x2003 0x0001 0x0000 0x3FFF 0x3000 0x1000 0x0002 0x0003 0x2001 0x2000 0x0001 0x0000 -1 0 +1 +8189 +8191 DIFFERENTIAL INPUT VOLTAGE (LSB) (VREFP - VREFN) x 2/3 0x3001 0x2003 0x2002 -8191 -8189 VREFP - VREFN 4 x 3 16384 (VREFP - VREFN) x 2/3 0x1FFF GRAY OUTPUT CODE (LSB) TWO'S COMPLEMENT OUTPUT CODE (LSB) MAX12553 14-Bit, 65Msps, 3.3V ADC -8191 -8189 -1 0 +1 +8189 +8191 DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 7. Two’s Complement Transfer Function (G/T = 0) Figure 8. Gray Code Transfer Function (G/T = 1) low, the MAX12553 is in normal operating mode. With PD high, the MAX12553 is in power-down mode. typically 10ms with the recommended capacitor array (Figure 13). When operating in unbuffered external reference mode, the wake-up time is dependent on the external reference drivers. The power-down mode allows the MAX12553 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX12553 parallel output bus is high impedance in power-down mode, allowing other devices on the bus to be accessed. In power-down mode, all internal circuits are off, the analog supply current reduces to 0.045mA, and the digital supply current reduces to 0.02mA. The following list shows the state of the analog inputs and digital outputs in power-down mode: • INP, INN analog inputs are disconnected from the internal input amplifier (Figure 3). • REFOUT has approximately 17kΩ to GND. • REFP, COM, REFN go high impedance with respect to VDD and GND, but there is an internal 4kΩ resistor between REFP and COM, as well as an internal 4kΩ resistor between REFN and COM. • D13–D0, DOR, and DAV go high impedance. • CLKP, CLKN go high impedance (Figure 5). The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is 20 Applications Information Using Transformer Coupling In general, the MAX12553 provides better SFDR and THD performance with fully differential input signals as opposed to single-ended input drive. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. An RF transformer (Figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12553 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 10 is good for frequencies up to Nyquist (fCLK/2). The circuit of Figure 11 converts a single-ended input signal to fully differential just as Figure 10. However, Figure 11 utilizes an additional transformer to improve ______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY CODE BIT. 1) THE MOST SIGNIFICANT GRAY CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. D13 D11 D7 D3 0 1 1 0 1 1 0 1 0 0 1 1 0 0 D0 0 BIT POSITION BINARY D13 D11 D7 D3 0 1 0 1 1 0 1 1 1 0 1 0 1 0 GRAY CODE 0 WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION. BINARY13 BINARY12 = BINARY13 BINARY12 = 0 1 D11 0 1 D7 1 0 1 1 D3 0 1 0 0 D0 1 1 0 0 BIT POSITION D13 BINARY 0 1 GRAY CODE 0 1 GRAY11 = BINARY11 GRAY11 = 1 1 D11 D7 D3 D0 0 1 1 0 1 1 1 0 1 0 1 0 BIT POSITION GRAY CODE BINARY 3) REPEAT STEP 2 UNTIL COMPLETE. 3) REPEAT STEP 2 UNTIL COMPLETE. BINARY12 BINARY11 = BINARY12 BINARY11 = 1 0 GRAY11 = 0 D13 GRAY12 BINARY12 = 1 D13 1 BINARY WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION. GRAY12 = 1 0 BIT POSITION GRAY CODE 2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: BINARYX = BINARYX+1 GRAYX 2) SUBSEQUENT GRAY CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAYX = BINARYX BINARYX+1 GRAY12 = BINARY12 GRAY12 = 1 0 D0 GRAY11 BINARY11 = 1 D11 D7 0 1 1 0 1 1 0 1 0 0 1 0 0 D3 D0 1 1 0 0 D13 D11 D7 D3 BINARY 0 1 0 1 1 0 1 1 1 0 1 0 1 0 GRAY CODE 0 1 1 BIT POSITION D0 BIT POSITION GRAY CODE BINARY 4) THE FINAL GRAY CODE CONVERSION IS: 4) THE FINAL GRAY CODE CONVERSION IS: BIT POSITION D13 D11 D7 D3 1 1 0 0 BINARY 0 1 0 1 1 0 1 1 1 0 1 0 1 0 GRAY CODE 1 0 1 0 GRAY CODE 0 1 1 0 1 1 0 1 0 0 1 1 0 0 BINARY D13 D11 D7 D3 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 1 1 0 D0 D0 BIT POSITION EXCULSIVE OR TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y=A B 0 1 1 0 Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion ______________________________________________________________________________________ 21 MAX12553 BINARY-TO-GRAY CODE CONVERSION MAX12553 14-Bit, 65Msps, 3.3V ADC MAX4108 24.9Ω 0.1µF INP T1 N.C. 2 0.1µF 12pF 6 1 VIN VIN INP 5.6pF MAX12553 100Ω 5 24.9Ω MAX12553 COM COM 2.2µF 3 4 MINICIRCUITS TT1-6 OR T1-1T 2.2µF 100Ω 24.9Ω 24.9Ω INN INN 12pF 5.6pF Figure 12. Single-Ended, AC-Coupled Input Drive Figure 10. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist 0Ω* INP 0.1µF 6 1 VIN 75Ω 0.5% T1 N.C. 2 5 75Ω 0.5% 2 5 3 4 MINICIRCUITS ADT1-1WT 5.6pF 110Ω 0.1% T2 N.C. 3 4 MINICIRCUITS ADT1-1WT 6 1 MAX12553 N.C. COM 110Ω 0.1% 2.2µF 0Ω* INN 5.6pF *0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE BANDWIDTH. Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist the common-mode rejection, allowing high-frequency signals beyond the Nyquist frequency. The two sets of termination resistors provide an equivalent 75Ω termination to the signal source. The second set of termination resistors connects to COM, providing the correct input common-mode voltage. Two 0Ω resistors in series with the analog inputs allow high IF input frequencies. These 0Ω resistors can be replaced with low-value resistors to limit the input bandwidth. 22 Single-Ended, AC-Coupled Input Signal Figure 12 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. ______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC MAX12553 +3.3V 0.1µF 2.2µF 0.1µF +3.3V 1 2 VDD MAX6029EUK21 38 0.1µF 5 REFP REFOUT 0.1µF 1µF* 2.048V 0.1µF REFN 2 0.1µF +3.3V 39 16.2kΩ 1 10µF MAX12553 NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING 15mA AND SINKING 30mA OF OUTPUT CURRENT. 1µF 1 5 MAX4230 4 3 3 REFIN GND COM 2.2µF 2.048V 47Ω +3.3V 2 10µF 6V 330µF 6V 0.1µF 2.2µF 0.1µF 1.47kΩ VDD 38 *PLACE THE 1µF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE. REFP 1 REFOUT 0.1µF 1µF* 10µF MAX12553 REFN 2 0.1µF 39 3 REFIN GND COM 2.2µF Figure 13. External Buffered Reference Driving Multiple ADCs Buffered External Reference Drives Multiple ADCs The buffered external reference mode allows for more control over the MAX12553 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50MΩ. Figure 13 uses the MAX6029EUK21 precision 2.048V reference as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a one-pole 10Hz lowpass filter to the MAX4230. The MAX4230 buffers the 2.048V reference and provides additional 10Hz lowpass filtering before its output is applied to the REFIN input of the MAX12553. ______________________________________________________________________________________ 23 MAX12553 14-Bit, 65Msps, 3.3V ADC +3.3V 1 0.1µF MAX6029EUK30 2 +3.3V 5 0.1µF +3.3V 2.2µF 3.000V 0.1µF 0.1µF 1 20kΩ 1% 5 MAX4230 1 10µF 6V 330µF 6V 10µF 0.1µF 1.47kΩ +3.3V 0.1µF MAX12553 REFN 0.1µF 52.3kΩ 1% 1 52.3kΩ 1% 5 2 10µF 6V 20kΩ 1% COM REFIN GND 39 2.2µF +3.3V 330µF 6V 2.2µF 0.1µF 20kΩ 1% 20kΩ 1% 1.647V 47Ω 4 3 3 MAX4230 38 1µF* 2 0.47µF VDD REFP REFOUT 2 20kΩ 1% 47Ω 4 3 2.413V 0.1µF 1.47kΩ 0.1µF +3.3V 1 1 5 REFOUT MAX4230 4 3 38 0.880V 10µF 47Ω 0.1µF 1µF* MAX12553 2 2 VDD REFP 10µF 6V 330µF 6V 3 1.47kΩ *PLACE THE 1µF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE. REFN 0.1µF COM GND REFIN 39 2.2µF Figure 14. External Unbuffered Reference Driving Multiple ADCs Unbuffered External Reference Drives Multiple ADCs The unbuffered external reference mode allows for precise control over the MAX12553 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources. 24 Figure 14 uses the MAX6029EUK30 precision 3.000V reference as a common reference for multiple converters. A seven-component resistive divider chain follows the MAX6029 voltage reference. The 0.47µF capacitor along this chain creates a 10Hz lowpass filter. Three MAX4230 operational amplifiers buffer taps along this resistor chain providing 2.413V, 1.647V, and 0.880V to the MAX12553’s REFP, COM, REFN reference inputs, ______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC Grounding, Bypassing, and Board Layout The MAX12553 requires high-speed board layout design techniques. Refer to the MAX12555 evaluation kit. data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Bypass OVDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All MAX12553 GNDs and the exposed backside paddle must be connected to the same ground plane. The MAX12553 relies on the exposed backside paddle connection for a low-inductance ground connection. Use multiple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX12555 evaluation kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX12553, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX12553, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale MAX12553 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale MAX12553 transition occurs at 1.5 LSBs below positive full scale, and the negative fullscale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points. Small-Signal Noise Floor (SSNF) Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. Go to www.maxim-ic.com for application notes on thermal + quantization noise floor. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR[max] = 6.02 × N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the ______________________________________________________________________________________ 25 MAX12553 respectively. The feedback around the MAX4230 op amps provides additional 10Hz lowpass filtering. The 2.413V and 0.880V reference voltages set the full-scale analog input range to ±1.022V = ±(VREFP - VREFN) x 2/3. A common power source for all active components removes any concern regarding power-supply sequencing when powering up or down. MAX12553 14-Bit, 65Msps, 3.3V ADC fundamental, the first six harmonics (HD2–HD7), and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD − 1.76 ENOB = 6.02 SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: where V1 is the fundamental amplitude, and V2 through V7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2–HD7). Intermodulation Distortion (IMD) IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: 26 The fundamental input tone amplitudes (V1 and V2) are at -7dBFS. Fourteen intermodulation products (VIM_) are used in the MAX12553 IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where fIN1 and fIN2 are the fundamental input tone frequencies: • Second-order intermodulation products: fIN1 + fIN2, fIN2 - fIN1 • Third-order intermodulation products: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 Single-Tone Spurious-Free Dynamic Range (SFDR) 2 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 + V7 THD = 20 × log V1 VIM12 + VIM22 + ....... + VIM132 + VIM14 2 IMD = 20 × log V12 + V22 • Fourth-order intermodulation products: 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1 • Fifth-order intermodulation products: 3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2, 3 x fIN2 + 2 x fIN1 Third-Order Intermodulation (IM3) IM3 is the total power of the third-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The thirdorder intermodulation products are 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1. Two-Tone Spurious-Free Dynamic Range (SFDRTT) SFDRTT represents the ratio, expressed in decibels, of the RMS amplitude of either input tone to the RMS amplitude of the next-largest spurious component in the spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist and is usually an intermodulation product or a harmonic. Aperture Delay The MAX12553 samples data on the falling edge of its sampling clock. In actuality, there is a small delay between the falling edge of the sampling clock and the ______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC D1 D0 DAV OVDD GND VDD PD REFOUT 1 30 D2 2 29 D3 COM 3 28 D4 GND 4 27 D5 INP 5 26 D6 INN 6 25 D7 GND 7 24 D8 DCE 8 23 D9 CLKN 9 22 D10 CLKP 10 21 D11 MAX12553 EXPOSED PADDLE (GND) D12 D13 DOR OVDD GND VDD 11 12 13 14 15 16 17 18 19 20 VDD Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX12553 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ±10%. REFP REFN VDD Overdrive Recovery Time 40 39 38 37 36 35 34 33 32 31 VDD Output Noise (nOUT) The output noise (nOUT) parameter is similar to the thermal + quantization noise parameter and is an indication of the ADC’s overall noise performance. No fundamental input tone is used to test for nOUT; INP, INN, and COM are connected together and 1024k data points collected. nOUT is computed by taking the RMS value of the collected data points. REFIN G/T TOP VIEW Figure 4 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. CLKTYP Aperture Jitter Pin Configuration THIN QFN 6mm x 6mm x 0.8mm ______________________________________________________________________________________ 27 MAX12553 actual sampling instant. Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 4). Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN 6x6x0.8.EPS MAX12553 14-Bit, 65Msps, 3.3V ADC D2 D CL D/2 b D2/2 k E/2 E2/2 (NE-1) X e E CL E2 k e L (ND-1) X e e L CL CL L1 L L e A1 A2 e A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.