19-5099; Rev 0; 1/10 Ultra-Low-Power, 10Msps, 8-Bit ADC Features The MAX19191 is an ultra-low-power, 8-bit, 10Msps analog-to-digital converter (ADC). The device features a fully differential wideband track-and-hold (T/H) input. This input has a 440MHz bandwidth and accepts fully differential or single-ended signals. The MAX19191 delivers a typical signal-to-noise and distortion (SINAD) of 48.6dB at an input frequency of 1.875MHz and a sampling rate of 10Msps while consuming only 15.3mW. This ADC operates from a 2.7V to 3.6V analog power supply. A separate 1.8V to 3.6V supply powers the digital output driver. In addition to ultra-low operating power, the MAX19191 features three power-down modes to conserve power during idle periods. Excellent dynamic performance, ultra-low power, and small size make the MAX19191 ideal for applications in imaging, instrumentation, and digital communications. An internal 1.024V precision bandgap reference sets the full-scale range of the ADC to ±0.512V. A flexible reference structure allows the MAX19191 to use its internal reference or accept an externally applied reference for applications requiring increased accuracy. The MAX19191 features parallel, CMOS-compatible three-state outputs. The digital output format is offset binary. A separate digital power input accepts a voltage from 1.8V to 3.6V for flexible interfacing to different logic levels. The MAX19191 is available in a 5mm × 5mm, 28pin thin QFN package, and is specified for the extended industrial (-40°C to +85°C) temperature range. For higher sampling frequency applications, refer to the MAX1195–MAX1198 dual 8-bit ADCs. For a dual-channel, pin-compatible version, refer to the MAX19192 data sheet. o Ultra-Low Power 15.3mW (Normal Operation: 10Msps) 2µW (Shutdown Mode) o Excellent Dynamic Performance 48.6dB SNR at fIN = 1.875MHz 70dBc SFDR at fIN = 1.875MHz o 2.7V to 3.6V Single Analog Supply o 1.8V to 3.6V TTL/CMOS-Compatible Digital Outputs o Fully Differential or Single-Ended Analog Inputs o Internal/External Reference Option o Multiplexed CMOS-Compatible Three-State Outputs o 28-Pin Thin QFN Package o Evaluation Kit Available (Order MAX19191EVKIT+) Ordering Information TEMP RANGE PIN-PACKAGE MAX19191ETI+ PART -40°C to +85°C 28 Thin QFN-EP* MAX19191ETI/V+** -40°C to +85°C 28 Thin QFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. /V denotes an automotive qualified part. **Future product—contact factory for availability. Pin Configuration Ultrasound and Medical Imaging Battery-Powered Portable Instruments VDD REFP REFN COM REFIN PD0 PD1 27 26 25 24 23 22 Applications 28 TOP VIEW 21 D0 2 20 D1 GND 3 19 D2 CLK 4 18 D3 GND 5 17 DVAL GND 6 16 D4 15 D5 IN- 1 IN+ + Low-Power Video 11 12 13 14 OGND OVDD D7 D6 VDD 10 7 GND EXPOSED PAD 8 GND MAX19191 9 Digital Audio Receiver Front-End VDD WLAN, Mobile DSL, WLL Receiver 5mm x 5mm THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX19191 General Description MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.9V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND ...........-0.3V to the lesser of (VDD + 0.3V or + 3.9V) CLK, REFIN, REFP, REFN, COM to GND...........-0.3V to the lesser of (VDD + 0.3V or + 3.9V) PD0, PD1 to OGND ...........-0.3V to the lesser of (OVDD + 0.3V or + 3.9V) Digital Outputs to OGND.............................-0.3V to the lesser of (OVDD + 0.3V or + 3.9V) Continuous Power Dissipation (TA = +70°C) 28-Pin Thin QFN (derated 20.8mW/°Cabove +70°C).............................1667mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error Gain Error No missing codes over temperature Bits ±0.14 ±1.00 LSB ±0.12 ±1.00 LSB +25°C ±4 < +25°C ±6 Excludes REFP - REFN error ±2 Gain Temperature Coefficient ±30 Power-Supply Rejection %FS %FS ppm/°C Offset (VDD ±5%) ±0.2 Gain (VDD ±5%) ±0.05 Differential or single-ended inputs ±0.512 V VDD/2 V 540 k 5 pF 5.0 Clock cycles LSB ANALOG INPUT Differential Input Voltage Range VDIFF Common-Mode Input Voltage Range VCOM Input Resistance RIN Input Capacitance CIN Switched capacitor load CONVERSION RATE Maximum Clock Frequency fCLK 10 Data Latency MHz DYNAMIC CHARACTERISTICS (Differential Inputs, 4096-Point FFT) Signal-to-Noise Ratio (Note 2) SNR Signal-to-Noise and Distortion (Note 2) SINAD Spurious-Free Dynamic Range (Note 2) SFDR Third-Harmonic Distortion (Note 2) HD3 2 f IN = 1.875MHz 47 f IN = 3.0MHz f IN = 1.875MHz 48.6 47 f IN = 3.0MHz f IN = 1.875MHz 48.6 48.6 48.5 59 70.0 f IN = 3.0MHz 70.0 f IN = 1.875MHz -71.0 f IN = 3.0MHz -71.0 _______________________________________________________________________________________ dB dB dBc dBc Ultra-Low-Power, 10Msps, 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP Intermodulation Distortion IMD f IN1 = 1.8MHz at -7dBFS, f IN2 = 3.0MHz at -7dBFS Third-Order Intermodulation IM3 f IN1 = 1.8MHz at -7dBFS, f IN2 = 3.0MHz at -7dBFS -64 Total Harmonic Distortion (Note 2) THD f IN = 1.875MHz -69 f IN = 3.0MHz MAX UNITS -64 dBc dBc -57.0 -67.0 dBc Small-Signal Bandwidth SSBW Input at -20dBFS 440 MHz Full-Power Bandwidth FPBW Input at -0.5dBFS 440 MHz Aperture Delay tAD 1.5 ns Aperture Jitter tAJ 2 psRMS 2 ns 1.5 full-scale input Overdrive Recovery Time INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN , and VCOM are Generated Internally) REFP Output Voltage VREFP - VCOM 0.256 V REFN Output Voltage VREFN - VCOM -0.256 V COM Output Voltage VCOM Differential Reference Output VREF Differential Reference Output Temperature Coefficient Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current VDD/2 - 0.15 VREFP - VREFN VDD/2 VDD/2 + 0.15 V 0.512 V VREFTC ±30 ppm/°C I SOURCE 2 mA I SINK 2 mA BUFFERED EXTERNAL REFERENCE (VREFIN = 1.024V, VREFP, VREFN, and VCOM are Generated Internally) REFIN Input Voltage VREFIN COM Output Voltage VCOM Differential Reference Output VREF Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current 1.024 VDD/2 - 0.15 VREFP - VREFN VDD/2 V VDD/2 + 0.15 V 0.512 V I SOURCE 2 mA I SINK 2 mA > 500 k -0.7 µA REFIN Input Resistance REFIN Input Current UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are Applied Externally) REFP Input Voltage VREFP - VCOM 0.256 V REFN Input Voltage VREFN - VCOM -0.256 V VDD/2 V COM Input Voltage VCOM _______________________________________________________________________________________ 3 MAX19191 ELECTRICAL CHARACTERISTICS (continued) MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Differential Reference Input Voltage SYMBOL VREF CONDITIONS MIN VREFP - VREFN TYP MAX 0.512 UNITS V REFP Input Resistance RREFP Measured between REFP and COM 4 k REFN Input Resistance RREFN Measured between REFN and COM 4 k DIGITAL INPUTS (CLK, PD0, PD1) Input High Threshold VIH Input Low Threshold VIL Input Hysteresis CLK 0.7 x VDD PD0, PD1 0.7 x OVDD CLK 0.3 x VDD 0.3 x OVDD PD0, PD1 VHYST Digital Input Leakage Current DIIN Digital Input Capacitance DCIN V 0.1 V V CLK at GND or VDD ±5 PD0 and PD1 at OGND or OVDD ±5 5 µA pF DIGITAL OUTPUTS (D7–D0, A/B) Output-Voltage Low VOL I SINK = 200µA Output-Voltage High VOH I SOURCE = 200µA Three-State Leakage Current ILEAK Three-State Output Capacitance C OUT 0.2 x OVDD 0.8 x OVDD V V ±5 5 µA pF POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage Analog Supply Current Digital Output Supply Current (Note 3) 4 VDD 2.7 OVDD 1.8 IDD I ODD 3.0 Normal operating mode, f IN = 1.875MHz at -0.5dBFS, CLK input from GND to VDD 5.1 Idle mode (three-state), fIN = 1.875MHz at -0.5dBFS, CLK input from GND to VDD 5.1 Standby mode, CLK input from GND to VDD, PD0 = OGND, PD1 = OVDD 2.9 Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND 0.6 Normal operating mode, f IN = 1.875MHz at -0.5dBFS, CL 10pF 1.7 Idle mode (three-state), DC input, CLK = GND or VDD, PD0 = OVDD, PD1 = OGND 0.1 Standby mode, DC input, CLK = GND or VDD, PD0 = OGND, PD1 = OVDD 0.1 Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND 0.1 _______________________________________________________________________________________ 3.6 V VDD V 5.8 mA 5.0 µA mA 5.0 µA 5.0 Ultra-Low-Power, 10Msps, 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 50% of CLK to 50% of data, Figure 5 (Note 4) 1 6 8.5 ns 50% of CLK to 50% of DVAL, Figure 5 (Note 4) 1 6 8.5 ns TIMING CHARACTERISTICS CLK Rise to Output Data Valid CLK Rise/Fall to DVAL Rise/Fall Time tDOA tD_DVAL PD1 Rise to Output Enable t EN PD0 = OVDD 5 ns PD1 Fall to Output Disable tDIS PD0 = OVDD 5 ns 50 % ±10 % CLK Duty Cycle CLK Duty-Cycle Variation Wake-Up Time from Shutdown Mode tWAKE, SD (Note 5) 20 µs Wake-Up Time from Standby Mode tWAKE, ST (Note 5) 5.5 µs 2 ns Digital Output Rise/Fall Time 20% to 80% Note 1: Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital output. SNR and THD are calculated using HD2 through HD6. Note 3: The power consumption of the output driver is proportional to the load capacitance (CL). Note 4: Guaranteed by design and characterization. Not production tested. Note 5: SINAD settles to within 0.5dB of its typical value. _______________________________________________________________________________________ 5 MAX19191 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = 3.0V, OVDD = 2.5V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dBFS, fCLK = 10MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) -40 -50 HD2 HD3 -30 -40 -50 HD3 -60 -10 -20 HD2 -40 -50 -60 -70 -70 -80 -80 -80 -90 -90 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -90 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD) FFT PLOT (8192 SAMPLES) FFT PLOT (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD) FFT PLOT (8192 SAMPLES) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY -40 -50 -60 HD2 HD3 50 -40 -50 HD3 -60 -70 -80 -80 -90 51 -30 -70 49 48 HD2 47 -90 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 MAX19191 toc06 -20 SNR (dB) -30 fCLK = 10.000000MHz fIN = 2.9870605MHz AIN = -0.5dBFS -10 52 MAX19191 toc05 fCLK = 10.000000MHz fIN = 1.7956543MHz AIN = -0.5dBFS -20 0 MAX19191 toc04 0 -10 0 46 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 20 40 60 80 100 FREQUENCY (MHz) FREQUENCY (MHz) fIN (MHz) SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY 51 80 75 -65 SFDR (dBc) THD (dBc) 50 49 120 MAX19191 toc09 -60 MAX19191 toc07 52 MAX19191 toc08 0 fIN2 fIN1 -30 fCLK = 10.000000MHz fIN1 = 1.7956543MHz fIN2 = 3.001709MHz AIN1 = AIN2 = -7dBFS MAX19191 toc03 0 -70 0 AMPLITUDE (dBFS) TWO-TONE IMD PLOT (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) AMPLITUDE (dBFS) -30 -60 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 fCLK = 10.000000MHz fIN = 2.9870605MHz AIN = -0.5dBFS -10 AMPLITUDE (dBFS) fCLK = 10.000000MHz fIN = 1.7956543MHz AIN = -0.5dBFS -10 0 MAX19191 toc01 0 FFT PLOT (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) FFT PLOT (8192 SAMPLES) MAX19191 toc02 FFT PLOT (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) FFT PLOT (8192 SAMPLES) SINAD (dB) MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC -70 70 48 65 -75 47 0 20 40 60 fIN (MHz) 6 60 -80 46 80 100 120 0 20 40 60 fIN (MHz) 80 100 120 0 20 40 60 fIN (MHz) _______________________________________________________________________________________ 80 100 120 Ultra-Low-Power, 10Msps, 8-Bit ADC SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT POWER fIN = 2.9902649MHz 50 40 30 fIN = 2.9902649MHz -40 40 THD (dBc) SINAD (dB) 50 -30 MAX19191 toc11 fIN = 2.9902649MHz SNR (dB) 60 MAX19191 toc10 60 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER MAX19191 toc12 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER 30 -50 -60 20 20 10 -25 -20 -15 -10 -5 0 -30 -25 -20 -15 -10 -5 -30 0 -15 -10 -5 ANALOG INPUT POWER (dBFS) SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE SIGNAL-TO-NOISE AND DISTORTION vs. SAMPLING RATE fIN = 2.9902649MHz fIN = 2.9902649MHz 50 SNR (dB) SINAD (dB) 50 60 48 50 44 44 30 -25 -20 -15 -10 -5 6 0 48 46 46 40 8 10 12 14 16 18 6 20 8 10 12 14 16 ANALOG INPUT POWER (dBFS) fCLK (MHz) fCLK (MHz) TOTAL HARMONIC DISTORTION vs. SAMPLING RATE SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE SIGNAL-TO-NOISE RATIO vs. DUTY CYCLE -70 -75 -80 75 10 12 14 fCLK (MHz) 16 18 20 fIN = 2.9902649MHz 48 70 47 60 8 50 20 49 65 -85 18 MAX19191 toc18 80 SFDR (dBc) -65 fIN = 2.9902649MHz SNR (dB) fIN = 2.9902649MHz MAX19191 toc17 85 MAX19191 toc16 -60 0 MAX19191 toc15 52 MAX19191 toc14 52 MAX19191 toc13 70 6 -20 ANALOG INPUT POWER (dBFS) fIN = 2.9902649MHz -30 -25 ANALOG INPUT POWER (dBFS) 80 SFDR (dBc) -80 0 -30 THD (dBc) -70 10 46 6 8 10 12 14 fCLK (MHz) 16 18 20 40 45 50 55 60 DUTY CYCLE (%) _______________________________________________________________________________________ 7 MAX19191 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.5V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dBFS, fCLK = 10MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.5V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dBFS, fCLK = 10MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) -65 48 47 fIN = 2.9902649MHz 80 -70 -75 60 -85 50 55 60 40 45 50 55 DUTY CYCLE (%) DUTY CYCLE (%) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.2 0 0 -0.1 -0.1 -0.2 -0.2 -0.3 32 64 96 128 160 192 224 256 0.30 0.20 0.10 -0.10 0 32 64 96 128 160 192 224 256 -40 -15 DIGITAL OUTPUT CODE 0.2 35 INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY 6 MAX19191 toc25 0.3 10 TEMPERATURE (°C) GAIN ERROR vs. TEMPERATURE SMALL-SIGNAL BANDWIDTH -20dBFS 4 2 0.1 GAIN (dB) GAIN ERROR (%FS) 0.40 0 DIGITAL OUTPUT CODE 0 0 FULL-POWER BANDWIDTH -0.5dBFS -2 -4 -0.1 -6 -0.2 -8 -0.3 -10 -40 -15 10 35 TEMPERATURE (°C) 8 60 0.50 -0.3 0 55 OFFSET ERROR vs. TEMPERATURE 0.1 DNL (LSB) 0.1 50 0.60 OFFSET ERROR (%FS) 0.2 45 DUTY CYCLE (%) 0.3 MAX19191 toc22 0.3 40 60 MAX19191 toc26 45 MAX19191 toc23 40 70 65 -80 46 75 MAX19191 toc24 THD (dBc) 49 85 MAX19191 toc21 fIN = 2.9902649MHz SFDR (dBc) fIN = 2.9902649MHz MAX19191 toc20 -60 MAX19191 toc19 50 SINAD (dB) SPURIOUS-FREE DYNAMIC RANGE vs. DUTY CYCLE TOTAL HARMONIC DISTORTION vs. DUTY CYCLE SIGNAL-TO-NOISE AND DISTORTION vs. DUTY CYCLE INL (LSB) MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC 60 85 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 60 85 Ultra-Low-Power, 10Msps, 8-Bit ADC REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX19191 toc28 0.5140 VREFP - VREFN (V) 0.5120 0.5110 0.5100 0.5090 0.5120 0.5100 0.5080 0.5060 0.5080 0.5040 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 -40 -15 ANALOG SUPPLY VOLTAGE (V) 10 35 60 85 TEMPERATURE (°C) SUPPLY CURRENT vs. SAMPLING RATE MAX19191 toc29 10 fIN = 2.9902649MHz 8 SUPPLY CURRENT (mA) VREFP - VREFN (V) 0.5160 MAX19191 toc27 0.5130 REFERENCE VOLTAGE vs. TEMPERATURE 6 A B 4 C 2 0 0 5 10 15 20 fCLK (MHz) A: ANALOG SUPPLY CURRENT (IVDD) - INTERNAL AND BUFFERED EXTERNAL REFERENCE MODES B: ANALOG SUPPLY CURRENT (IVDD) - UNBUFFERED EXTERNAL REFERENCE MODE C: DIGITAL SUPPLY CURRENT (IOVDD) - OVDD = 2.5V, ALL REFERENCE MODES _______________________________________________________________________________________ 9 MAX19191 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.5V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dBFS, fCLK = 10MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC Pin Description PIN NAME 1 IN- Negative Analog Input. For single-ended operation, connect IN- to COM. FUNCTION 2 IN+ Positive Analog Input. For single-ended operation, connect signal source to IN+. 3, 5, 6, 7, 10 GND Analog Ground. Connect all GND pins together. 4 CLK Converter Clock Input 8, 9, 28 VDD Converter Power Input. Connect to a 2.7V to 3.6V power supply. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 11 OGND Output Driver Ground 12 OVDD Output Driver Power Input. Connect to a 1.8V to VDD power supply. Bypass OVDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 13 D7 Three-State Digital Output. D7 is the most significant bit (MSB). 14 D6 Three-State Digital Output 15 D5 Three-State Digital Output 16 D4 Three-State Digital Output 17 DVAL 18 D3 Three-State Digital Output 19 D2 Three-State Digital Output 20 D1 Three-State Digital Output 21 D0 Three-State Digital Output. D0 is the least significant bit (LSB). 22 PD1 23 PD0 24 REFIN 25 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor. 26 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF capacitor. 27 REFP Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFP to GND with a 0.33µF capacitor. — EP 10 Data Valid Indicator. This digital output indicates when valid data (DVAL = 1) is present on the output. Power-Down Digital Input 1. See Table 3. Power-Down Digital Input 0. See Table 3. Reference Input. Internally pulled up to VDD. Exposed Pad. Internally connected to pin 3. Externally connect EP to GND. ______________________________________________________________________________________ Ultra-Low-Power, 10Msps, 8-Bit ADC ∑ The MAX19191 uses a seven-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles. x2 FLASH ADC DAC At each stage, flash ADCs convert the held input voltages into a digital code. The following digital-to-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all stages. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX19191 functional diagram. 1.5 BITS IN+ STAGE 1 T/H STAGE 2 STAGE 7 IN- DIGITAL ERROR CORRECTION D0–D7 Figure 1. Pipeline Architecture—Stage Blocks IN+ T/H IN- REFIN REFP COM REFN PIPELINE ADC / DEC / + T/H REFERENCE SYSTEM AND BIAS CIRCUITS VDD GND POWER CONTROL PD0 PD1 OVDD D0–D7 OUTPUT DRIVERS DVAL OGND MAX19191 TIMING CLK Figure 2. MAX19191 Functional Diagram ______________________________________________________________________________________ 11 MAX19191 Detailed Description MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC INTERNAL BIAS COM S5a S2a C1a S3a S4a IN+ OUT C2a S4c S1 OUT INS4b C2b C1b S3b S2b INTERNAL BIAS S5b COM HOLD TRACK MAX19191 CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS Figure 3. Internal T/H Circuits Input Track-and-Hold (T/H) Circuits Figure 3 displays a simplified functional diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipeline from the fast-changing inputs. The wide input bandwidth T/H amplifier allows the MAX19191 to track and sample/hold analog inputs of high frequencies (> Nyquist). The ADC inputs (IN+, IN-) can be driven either differentially or single ended. Match the impedance of IN+ and IN-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance. 12 Analog Inputs and Reference Configurations The MAX19191 full-scale analog input range is ±VREF with a common-mode input range of VDD/2 ±0.2V. VREF is the difference between V REFP and V REFN . The MAX19191 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). In internal reference mode, connect REFIN to VDD or leave REFIN unconnected. VREF is internally generated to be 0.512V ±3%. COM, REFP, and REFN are lowimpedance outputs with VCOM = VDD/2, VREFP = VDD/2 + VREF/2, and VREFN = VDD/2 - VREF/2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. In buffered external reference mode, apply a 1.024V ±10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD/2, VREFP = V DD /2 + V REFIN /4, and V REFN = V DD /2 - V REFIN /4. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. ______________________________________________________________________________________ Ultra-Low-Power, 10Msps, 8-Bit ADC VREFIN REFERENCE MODE > 0.8 x VDD Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference sources. VREF is the difference between the externally applied VREFP and VREFN. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. < 0.3V Clock Input (CLK) 62.5µA MAX19191 REFP 1.75V 4kΩ 0µA COM 1.5V 4kΩ CLK accepts a CMOS-compatible signal level. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: ⎛ ⎞ 1 SNR = 20 × log ⎜ ⎟ ⎝ 2 × π × f IN × t AJ ⎠ 62.5µA REFN 1.25V Figure 4. Unbuffered External Reference Mode Impedance In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for COM, REFP, and REFN. With their buffers shut down, these nodes become high-impedance inputs (Figure 4) and can be driven through separate, external reference sources. Drive VCOM to VDD/2 ±10%, drive VREFP to (VDD/2 +0.256V) ±10%, and drive VREFN to (VDD/2 - 0.256V) ±10%. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section. where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX19191 clock input operates with a VDD/2 voltage threshold and accepts a 50% ±10% duty cycle (see the Typical Operating Characteristics). System Timing Requirements Figure 5 shows the relationship between the clock, analog inputs, DVAL indicator, and the resulting output data. Input data is sampled on the rising edge of the clock signal (CLK). Five clock cycles later, output data is updated on the rising edge of the CLK. The DVAL indicator follows CLK with a typical delay time of 6ns and remains high when the output data is valid. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles. Output data remains valid for half a clock period. ______________________________________________________________________________________ 13 MAX19191 Table 1. Reference Modes MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC 5 CLOCK-CYCLE LATENCY IN tCLK tCL tCH CLK tDO DVAL tD_DVAL D0–D7 VALID VALID VALID VALID VALID VALID tD_DVAL D1 XX D2 XX D3 XX D4 XX D5 XX D6 XX Figure 5. System Timing Diagram Digital Output Data (D0–D7), Data Valid Indicator (DVAL) Power Modes (PD0, PD1) The MAX19191 has four power modes that are controlled with PD0 and PD1. Four power modes allow the MAX19191 to efficiently use power by transitioning to a low-power state when conversions are not required (Table 3). Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX19191 and placing the outputs in three-state. The wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 20µs. When operating in the unbuffered external reference mode, the wake-up time is dependent on the 14 2 x VREF 256 VREF VREF = VREFP - VREFN VREF VREF 1111 1111 1111 1110 1111 1101 1000 0001 1000 0000 0111 1111 (COM) VREF OFFSET BINARY OUTPUT CODE (LSB) D0–D7 and DVAL are TTL/CMOS-logic compatible. The digital output coding is offset binary (Table 2, Figure 6). The capacitive load on the digital outputs D0–D7 should be kept as low as possible (< 15pF) to avoid large digital currents feeding back into the analog portion of the MAX19191 and degrading its dynamic performance. Buffers on the digital outputs isolate them from heavy capacitive loads. To improve the dynamic performance of the MAX19191, add 100Ω resistors in series with the digital outputs close to the MAX19191. Refer to the MAX19191 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 100Ω series resistors. 1LSB = 0000 0011 0000 0010 0000 0001 0000 0000 -128 -127 -126 -125 -1 0 +1 +125 +126 +127 +128 (COM) INPUT VOLTAGE (LSB) Figure 6. Transfer Function external reference drivers. When the outputs transition from three-state to on, the last converted word is placed on the digital outputs. In standby mode, the reference and clock distribution circuits are powered up, but the pipeline ADC is unpowered and the outputs are in three-state. The wake-up time from standby mode is dominated by the ______________________________________________________________________________________ Ultra-Low-Power, 10Msps, 8-Bit ADC MAX19191 Table 2. Output Codes vs. Input Voltage DIFFERENTIAL INPUT VOLTAGE (IN+ - IN-) DIFFERENTIAL INPUT (LSB) OFFSET BINARY (D7–D0) OUTPUT DECIMAL CODE VREF × 127 128 +127 (+ full scale - 1 LSB) 1111 1111 255 VREF × 126 128 +126 (+ full scale - 2 LSB) 1111 1110 254 VREF × 1 128 +1 1000 0001 129 VREF × 0 128 0 (bipolar zero) 1000 0000 128 - VREF × 1 128 -1 0111 1111 127 - VREF × 127 128 -127 (- full scale + 1 LSB) 0000 0001 1 - VREF × 128 128 -128 (- full scale) 0000 0000 0 Table 3. Power Logic PD0 PD1 POWER MODE ADC INTERNAL REFERENCE CLOCK DISTRIBUTION OUTPUTS 0 0 Shutdown Off Off Off Three-state 0 1 Standby Off On On Three-state 1 0 Idle On On On Three-state 1 1 Normal operating On On On On 5.5µs required to activate the pipeline ADC. When the outputs transition from three-state to on, the last converted word is placed on the digital outputs. In idle mode, the pipeline ADC, reference, and clock distribution circuits are powered, but the outputs are forced to three-state. The wake-up time from idle mode is dominated by the 5ns required for the output drivers to start from three-state. When the outputs transition from three-state to on, the last converted word is placed on the digital outputs. In the normal operating mode, all sections of the MAX19191 are powered. Applications Information The circuit of Figure 7 operates from a single 3V supply and accommodates a wide 0.5V to 1.5V input commonmode voltage range for the analog interface between differential, DC-coupled signal source and a high-speed ADC. RISO isolates the op amp output from the ADC capacitive input to prevent ringing and oscillation. CIN filters high-frequency noise. Using Transformer Coupling An RF transformer (Figure 8) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX19191 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. In general, the MAX19191 provides better SFDR and THD with fully differential input signals than singleended drive, especially for high input frequencies. In differential input mode, even-order harmonics are lower as both inputs are balanced, and the ADC input only requires half the signal swing compared to singleended mode. ______________________________________________________________________________________ 15 MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC R4 600Ω R5 600Ω MAX19191 RISO 22Ω R1 600Ω VCOM = 0.5V TO 1.5V VSIG = ±85mVP-P R2 300Ω R3 600Ω IN+ CIN 5pF R6 600Ω R7 600Ω COM AV = 6V/V VCOM = VDD/2 R8 600Ω R9 600Ω RISO 22Ω CIN 5pF R10 600Ω OPERATIONAL AMPLIFIERS CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/ DUAL/QUAD 3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT. CONNECT THE POSITIVE SUPPLY RAIL (VCC) TO 3V. CONNECT THE NEGATIVE SUPPLY RAIL (VEE) TO GROUND. DECOUPLE VCC WITH A 0.1µF CAPACITOR TO GROUND. IN- R11 600Ω RESISTOR NETWORKS RESISTOR NETWORKS ENSURE PROPER THERMAL AND TOLERANCE MATCHING. FOR R1, R2, AND R3 USE A NETWORK SUCH AS VISHAY'S 3R MODEL NUMBER 300192. FOR R4–R11, USE A NETWORK SUCH AS VISHAY'S 4R MODEL NUMBER 300197. Figure 7. DC-Coupled Differential Input Driver Single-Ended AC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended application. Amplifiers such as the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. Buffered External Reference Drives Multiple ADCs The buffered external reference mode allows for more control over the MAX19191 reference voltage and allows multiple converters to use a common reference. To drive one MAX19191 in buffered external reference 16 mode, the external circuit must sink 0.7µA, allowing one reference circuit to easily drive the REFIN of multiple converters to 1.024V ±10%. Figure 10 shows the MAX6061 precision bandgap reference used as a common reference for multiple converters. The 1.248V output of the MAX6061 is divided down to 1.023V as it passes through a one-pole, 10Hz, lowpass filter to the MAX4250. The MAX4250 buffers the 1.023V reference before its output is applied to the MAX19191. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. ______________________________________________________________________________________ Ultra-Low-Power, 10Msps, 8-Bit ADC MAX19191 REFP 25Ω IN+ 22pF 1 VIN 1kΩ VIN 0.1µF T1 0.1µF MAX19191 6 RISO 50Ω IN+ MAX4108 N.C. 100Ω 5 2 3 1kΩ COM 2.2µF 4 CIN 22pF MAX19191 0.1µF COM REFN MINICIRCUITS TT1-6-KK81 0.1µF RISO 50Ω 25Ω IN- IN- 100Ω CIN 22pF 22pF Figure 9. Using an Op Amp for Single-Ended, AC-Coupled Input Drive Figure 8. Transformer-Coupled Input Drive 3V 24 0.1µF 1.248V VDD REFIN 0.1µF 1 2 27 MAX6061 3 10Hz LOWPASS FILTER N=1 REFP 0.33µF 1% 20kΩ MAX19191 26 REFN 0.33µF 1µF 1% 90.9kΩ 25 3V 5 3 NOTE: ONE FRONT-END REFERENCE CIRCUIT PROVIDES ±15mA OF OUTPUT DRIVE AND SUPPORTS OVER 1000 MAX19191s. MAX4250 4 2 COM GND 0.33µF 0.1µF 1 15Ω 1.023V 24 VDD REFIN 0.1µF 2.2µF 0.1µF 27 REFP N = 1000 0.33µF MAX19191 26 REFN 0.33µF 25 COM 0.33µF GND Figure 10. External Buffered (MAX4250) Reference Drive Using a MAX6061 Bandgap Reference ______________________________________________________________________________________ 17 MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC 3V 2.500V 1 0.1µF 2 27 MAX6066 1% 30.1kΩ 3 3 10µF 6V 0.1µF 12 1MΩ 13 14 MAX4254 1.47kΩ 10µF 6V 24 COM GND 0.1µF 27 330µF 6V 1.47kΩ VDD REFP N = 160 0.33µF 47Ω 8 MAX4254 10µF 6V 2.2µF 1.47kΩ 1.248V 1/4 11 25 0.33µF 330µF 6V 10 9 REFIN 47Ω 7 1% 10.0kΩ 4 1/4 330µF 6V MAX4254 3V UNCOMMITTED MAX19191 1.498V 1/4 1MΩ REFN 0.33µF 1% 10.0kΩ 5 6 26 47Ω 1 MAX4254 1µF NOTE: ONE FRONT-END REFERENCE CIRCUIT SUPPORTS UP TO 160 MAX19191s. N=1 0.33µF 1.748V 1/4 2 VDD REFP 26 REFN MAX19191 REFIN 24 0.33µF 1% 49.9kΩ 25 0.33µF COM GND Figure 11. External Unbuffered Reference Driving 160 ADCs with the MAX4254 and MAX6066 Unbuffered External Reference Drives Multiple ADCs The unbuffered external reference mode allows for precise control over the MAX19191 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources. Figure 11 shows the MAX6066 precision bandgap reference used as a common reference for multiple converters. The 2.500V output of the MAX6066 is followed by a 10Hz lowpass filter and precision voltage-divider. The MAX4254 buffers the taps of this divider to provide the 1.75V, 1.5V, and 1.25V sources to drive REFP, 18 REFN, and COM. The MAX4254 provides a low offset voltage and low noise level. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference-voltage and amplifier noise to a level of 3nV/√Hz. The 1.75V and 1.25V reference voltages set the differential full-scale range of the associated ADCs at ±0.5V. The common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters support as many as 160 MAX19191s. ______________________________________________________________________________________ Ultra-Low-Power, 10Msps, 8-Bit ADC The MAX19191 requires high-speed board layout design techniques. Refer to the MAX19191 evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close as possible to the device, preferably on the same side as the ADC, using surfacemount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF bipolar capacitor. Bypass OVDD to OGND with a 0.1µF ceramic capacitor in parallel with a 2.2µF bipolar capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33µF ceramic capacitor. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC’s package. Connect the MAX19191 exposed backside pad to GND. Join the two ground planes at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90° turns. Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX19191 are measured using the end-point method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL MAX19191 Grounding, Bypassing, and Board Layout CLK ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) T/H TRACK HOLD TRACK Figure 12. T/H Aperture Timing error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Offset Error Ideally, the midscale MAX19191 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. Gain Error Ideally, the full-scale MAX19191 transition occurs at 1.5 LSB below full-scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed. Dynamic Parameter Definitions Aperture Jitter Figure 12 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 12). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02 × N + 1.76 ______________________________________________________________________________________ 19 MAX19191 Ultra-Low-Power, 10Msps, 8-Bit ADC In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ± f1). The individual input tone levels are at -7dBFS. Signal-to-Noise Plus Distortion (SINAD) Third-Order Intermodulation (IM3) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the the fundamental and the DC offset. IM3 is the power of the worst third-order intermodulation product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The third-order intermodulation products are (2 x f1 ± f2), (2 x f2 ± f1). The individual input tone levels are at -7dBFS. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = Small-Signal Bandwidth SINAD - 1.76 6.02 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: ⎡ 2 2 2 2 2 ⎢ V2 + V3 + V4 + V5 + V6 THD = 20 × log ⎢ V1 ⎢⎣ Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supplies are moved ±5%. ⎤ ⎥ ⎥ ⎥⎦ where V1 is the fundamental amplitude, and V2–V6 are the amplitudes of the 2nd- through 6th-order harmonics. A small -20dBFS analog input signal is applied to an ADC in such a way that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the track/hold (T/H) performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. Chip Information Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. PROCESS: CMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 28 TQFN-EP T2855+8 21-0140 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.