TI TPS65165_12

TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
Compact LCD Bias IC With High Speed Amplifiers for TV and Monitor TFT-LCD Panels
FEATURES
•
•
•
•
•
•
•
2.5 V to 6.0 V Input Voltage Range
Vs Output Voltage up to 18 V
– 1%-Accurate Boost Converter With 4.5 A
Switch Current
– 600 kHz Fixed Frequency PWM Operation
– Overvoltage Protection
– Adjustable Softstart
Regulated Positive Charge Pump Converter
VGH
Integrated Gate Voltage Shaping of VGH
Regulated Negative Charge-Pump Driver VGL
Adjustable Sequencing for Vs and VGH
3 Integrated High-Speed Operational
•
•
•
Amplifiers
– 50 MHz 3 db Bandwidth
– Slew Rate 45 V/µs
– 215 mA Short Circuit Current
High Voltage Test Mode (HVS)
Thermal Shutdown
40-Pin 5×5-mm QFN Package
APPLICATIONS
•
•
LCD Monitor
LCD TV Panel
DESCRIPTION
The TPS65165 is a Compact LCD Bias IC with 3 high-speed operational amplifiers for gamma correction and/or
VCOM supply. The device generates all 3 voltage rails for TFT-LCD displays (Vs, VGL and VGH). The device
incorporates a high-voltage switch that can be controlled by a logic signal from the timing controller (TCON) to
provide the gate-voltage modulation for VGH. If this function is not required, the CTRL pin can be tied high.
L1
10uH
Vin
2.5V to 6.0V
Vs
15V/1.0A
Boost Converter
C2P
Positive Charge
Pump
x2 or x3
D
C2N
SUP
SUP
SW
COMP
C11
330 nF
FB
R4
220 kW
RHVS
FBP
S
POUT
HVS
High Voltage
Switch Control
CTRL
C1P
DRN
C12
330nF
C13
1 mF
C14
100 pF
C1N
POS1
R10
1kW
C9
68 pF
R1
470 kW
R2
39 kW
R3
30 kW
C10
1 nF
C8
1 mF
C7
C5
C6
22 mF 22 mF 22 mF
C4
1 mF
SW
C3
22 mF
EN
C2
22 mF
VIN
C1
22 mF
D1
R6
16 kW
PGND
1
NEG1
PGND
OUT1
DRVN
3
2
NEG2
C17 C18
C19
22 nF 22 nF 22 nF
AGND
BGND
OUT3
POS3
SS
GDLY
ADLY
C15
330 nF
D2
VGL
-5V/50mA
D3
FBN
OUT2
VGH
27.5V/50mA
VGH
POS2
R5
300
kW
R7
160 kW
REF
C16
330 nF
R8
39 kW
C20
220 nF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
The device also features a high-voltage stress test, where the output voltage of VGH is typically set to 30 V, and
the output voltage of Vs is programmable to any higher voltage. The high-voltage stress test is enabled by
pulling the HVS pin high. Adjustable sequencing is implemented, and can be programmed by selecting the
capacitor values connected to ADLY and GDLY. The device consists of a boost converter to provide the source
voltage Vs operating at a fixed switching frequency of 600 kHz. A fully integrated positive charge pump,
switching automatically between doubler and tripler mode provides an adjustable regulated TFT gate on voltage
VGH. A negative charge pump driver provides adjustable regulated output voltage VGL. To minimize external
components the charge pumps for VGH and VGL operate at a fixed switching frequency of 1.2 MHz. The device
includes safety features like overvoltage protection of the boost converter, short circuit protection of VGH and
VGL as well as thermal shutdown.
ORDERING INFORMATION (1)
(1)
TA
ORDERING
QFN PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65165RSBR
RSB
TPS65165
The TPS65165RSBR is available taped and reeled and shipped in quantities of 3000 devices per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
Input voltage range VIN (2)
–0.3 V to 7.0
V
Voltage range at EN, CTRL, HVS
–0.3 V to 7.0
V
Voltage on
SUP
22
SW
25
POUT, VGH, DRN
32
Peak switch current
ESD rating
Internally limited
V
HBM
2
kV
MM
200
V
CDM
750
V
Continuous total power dissipation
°C
Operating ambient temperature range
–40 to 85
°C
Storage temperature range
–65 to 150
°C
Operating junction temperature range
TA
Tstg
(2)
See Dissipation Rating Table
–40 to 150
TJ
(1)
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS (1)
(1)
PACKAGE
RθJA
TA < 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
40-pin QFN
30°C/W
3.3 W
1.8 W
1.3 W
Exposed thermal die is soldered to the PCB using thermal vias. Refer to Texas Instruments Application report (SLUA271) QFN/SON
PCB Attachment.
RECOMMENDED OPERATING CONDITIONS
MIN
2
NOM
MAX
UNIT
VIN
Input voltage range
2.5
6.0
V
TA
Operation ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
Submit Documentation Feedback
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
VIN=5.0V, Vs=15V, HVS=low, EN=CTRL=high, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
IQVIN
No load quiescent current into VIN
Device not switching
IQSUP
No load quiescent current into SUP
Device not switching
Shutdown current into VIN
Vin=6V
1
Shutdown current into SUP
Vin=6V, SUP = Vin-0.5V
8
ISD
VUVLO
2.5
Under-voltage lockout threshold
Thermal shutdown
6.0
V
1
1.5
mA
20
25
mA
µA
Vin rising
2.3
2.5
V
Vin falling
2.2
2.3
V
Temperature rising
155
°C
5
°C
Thermal shutdown hysteresis
LOGIC SIGNALS EN, CTRL, HVS
Vth
Threshold voltage
II
Input leakage current
Vin = 2.5 V to 6.0 V
0.4
1.4
V
±0.01
±0.1
µA
28.5
30
31.5
V
0.5
1
1.5
kΩ
100
nA
18
V
HIGH VOLTAGE STRESS TEST (HVS)
VPOUT
Positive charge pump output voltage
HVS = high
RHVS
RHVS pull down resistance
HVS = high, Vin = 2.5 V to 6.0 V,
IHVS = 100 µA
IRHVS
RHVS leackage current
HVS = low, VRHVS = 1.5 V
MAIN BOOST CONVERTER Vs
Vs
Output voltage range
VFB
Feedback regulation voltage
7
IFB
Feedback input bias current
VFB = 1.146
N-MOSFET on-resistance (Q1)
Vs = 15 V, ISW = 500 mA,
Vs = 7 V, ISW = 500 mA
75
140
P-MOSFET on-resistance (Q2)
Vs = 15 V; ISW = 100 mA,
Vs = 7 V; ISW = 100 mA
10
16
Ω
1
A
6.6
A
10
µA
1.136
RDS(ON)
IMAX
Maximum P-MOSFET peak switch current
(Q2)
ILIM
N-MOSFET switch current limit (Q1)
Ileak
Switch leakage current
VSW = 15 V
Vovp
Output overvoltage protection
FB = GND, Vout rising
fOSC
Oscilator frequency
Line regulation
Vin=3.0V to 6.0V, Iout=100mA
Load regulation
Iout=100mA to 700mA, Vin=5.0V
1.146
1.154
V
100
nA
mΩ
4.4
5.5
19.5
20
21
V
480
600
720
kHz
0.045
%/V
0.23
%/A
NEGATIVE CHARGE PUMP VGL
VGL
Output voltage range
VFB
Feedback regulation voltage
IFB
Feedback input bias current
VFB = 0 V
Vref
Reference voltage
VIN = 2.5 V to 6 V, IREF = 10µ A
RDSon
Q7 P-Channel switch RDSon
IDRVN = 40 mA
4.4
IDRN = 40 mA, VFBN = VFBNnominal– 5%
130
300
mV
IDRN = 100 mA, VFBN = VFBNnominal– 5%
280
450
mV
30
V
1.214
1.238
V
100
nA
VDropN
Current sink voltage drop (1)
–48
1.205
0
1.213
–2
V
48
mV
100
nA
1.219
V
Ω
POSITIVE CHARGE PUMP (POUT)
VPOUT
Output voltage range
VFB
Feedback regulation voltage
CTRL = GND, VGH = open
IFB
Feedback input bias current
FBO = 1.214 V
(1)
1.187
The maximum charge pump output current is half the drive current IDRNof the internal current source or sink
Submit Documentation Feedback
3
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
VIN=5.0V, Vs=15V, HVS=low, EN=CTRL=high, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
Vd
D1–D4 Schottky diode forward voltage
TEST CONDITIONS
MIN
ID1-D4 = 40 mA
TYP
MAX
UNIT
610
800
mV
Doubler Mode (x2); IPOUT = 20 mA
94
Ω
Doubler Mode (x2); IPOUT = 50 mA
63
Ω
Tripler Mode (x3); IPOUT = 20 mA
141
Ω
Tripler Mode (x3); IPOUT = 50 mA
94
Ω
POUT to VGH RDSon
CTRL = high, POUT = 27 V, I = 20 mA
8.5
16
DRN to VGH RDSon
CTRL = low, VDRN = 5 V, I = 20 mA
38
62
IDRN
DRN input current
CTRL = low, VVGH = VDRN
10
µA
tdly
CTRL to VGH propagation delay
CTRL = high to low, POUT = 27 V,
VDRN = GND
125
ns
RVGH
VGH pull down resistance
EN = low, I = 20 mA
1
kΩ
Reff
Effective output resistance
HIGH VOLTAGE SWITCH VGH
RDSon
Ω
Ω
CONTROL AND SOFTSTART ADLY, GDLY, SS
IADLY
Drive current into delay capacitor ADLY
VADLY = 1.213 V
3.5
4.8
6.2
µA
IGDLY
Drive current into delay capacitor GDLY
VADLY = 1.213 V
3.5
4.8
6.2
µA
ISS
SS charge current
VSS = 0 V
2.8
4.5
6.2
µA
–15
3
18
mV
0
3
µA
Vs
V
OPERATIONAL AMPLIFIERS 1, 2, 3
4
Vos
Input offset voltage
VCM = Vs/2
IB
Input bias current
VCM = Vs/2
VCM
Common mode input voltage range
CMRR
Common mode rejection ratio
VCM = 7.5 V
55
AVOL
Open loop gain
0.5 V ≤ Vout ≤ 14.5 V, No load
50
VOL
Output voltage swing low
IOUT = 10 mA
VOH
Output voltage swing high
IOUT = 10 mA
Isc
Short circuit current
IO
Output current
PSRR
Power supply rejection ratio
80
dB
SR
Slew rate
AV = 1, VIN = 2 Vpp
45
V/µs
BW
– 3dB Bandwidth
AV = 1, VOUT = 50 mVpp, Output High
Impedance
50
MHz
GBWP
Gain bandwidth product
26
MHz
Roff
Pull down resistor
10
kΩ
0
VOUT = 7.5V , Input offset voltage 10 mV
Submit Documentation Feedback
75
dB
dB
100
200
mV
100
Vs–200
mV
120
215
mA
90
170
mA
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
C1N
C1P
POUT
FBP
DRN
VGH
FB
COMP
RHVS
NC
PIN ASSIGNMENT
40
39
38
37
36
35
34
33
32
31
C2P
2
29
SW
BGND
3
28
PGND
SUP
4
27
PGND
POS1
5
26
NC
NEG1
6
25
EN
OUT1
7
24
VIN
OUT2
8
23
AGND
NEG2
9
22
REF
POS2
10
11
21
FBN
12
13
14
15
ADLY
GDLY
SW
NC
30
OUT3
1
POS3
C2N
Exposed
Thermal Die*
17
18
19
20
HVS
DRVN
NC
SS
CTRL
16
NOTE: The exposed thermal die is connected to AGNG. NC pin is internally not connected.
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
C2N
1
I/O
Negative terminal of the flying capacitor for the positive charge pump. Typically a 330nF flying capacitor is
required.
C2P
2
I/O
Positive terminal of the flying capacitor for the positive charge pump. Typically a 330nF flying capacitor is
required.
BGND
3
SUP
4
I
Supply input for the operational amplifier and charge pump stages. Connect to the main output Vs, with a
1-µF bypass capacitor.
POS1
5
I
Non-inverting input of Operational Amplifier 1.
NEG1
6
I
Inverting input of the Operational Amplifier 1.
OUT1
7
O
Output of Operational Amplifier 1. When the device is disabled, the output is pulled to GND via a 1-kΩ
resistor.
OUT2
8
O
Output of Operational Amplifier 2. When the device is disabled, the output is pulled to GND via a 1-kΩ
resistor.
NEG2
9
I
Inverting input of Operational Amplifier 2.
POS2
10
I
Non-inverting input of Operational Amplifier 2.
POS3
11
I
Non-inverting input of Operational Amplifier 3.
OUT3
12
O
Output of Operational Amplifier 3. When the device is disabled, the output is pulled to GND via a 1-kΩ
resistor.
NC
Low noise ground for the operational amplifier.
13, 19,
26, 31
Not connected. These pin can be connected to GND to improve the thermal resistance of the package.
ADLY
14
O
Adjustable EN high-to-start-up delay of the main boost converter, negative and positive charge pump.
Connect a capacitor from this pin to GND to set the desired delay time. (See SETTING THE DELAY TIMES
ADLY, GDLY)
GDLY
15
O
Adjustable EN high-to-enable delay of the high-voltage switch Q8 (gate voltage shaping). Connect a
capacitor from this pin to GND to set the desired delay time. (See SETTING THE DELAY TIMES ADLY,
GDLY)
CTRL
16
I
Logic control input for the internal high voltage switch (gate voltage shaping).
Submit Documentation Feedback
5
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
PIN ASSIGNMENT (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
6
NO.
I/O
DESCRIPTION
HVS
17
I
Logic control input to enable High Voltage Stress Test. With HVS=low the high voltage stress test is disabled.
With HVS=high the high voltage stress test is enabled.
DRVN
18
I/O
Drive pin for the negative charge pump converter generating VGL. Using a single stage charge pump inverts
the voltage present at the main boost converter Vs and regulates it down to the desired voltage programmed
by the feedback divider.
SS
20
O
Softstart for the main boost converter generating Vs. Connect a capacitor to this pin to set the softstart time.
FBN
21
I
Feedback of the negative charge pump converter.
REF
22
O
Reference output. Connect a 220-nF capacitor directly from REF pin to AGND to minimize possible noise
coupling into the reference of the IC.
AGND
23
I
Analog Ground , positive and negative charge pump ground.
VIN
24
I
Supply pin for the IC. Bypass this pin with a 1-µF capacitor directly to GND.
EN
25
I
Enable pin of the IC. EN=high enables the IC. EN= low disables the IC. This pin must be terminated.
PGND
27, 28
SW
29, 30
I/O
Power Ground for the boost converter.
RHVS
32
I
This resistor sets the voltage of the boost converter Vs when the High Voltage Stress test is enabled.
(HVS=high). With HVS=high the RHVS pin is pulled to GND which sets the output voltage for the boost
converter. When HVS is disabled (HVS=low) the RHVS pin is high impedance.
COMP
33
O
Compensation for the regulation loop of the boost converter generating Vs.
FB
34
I
Feedback of the boost converter generating Vs.
VGH
35
O
This is the output voltage of the internal high voltage switch, controlled by the CTRL signal.
DRN
36
I/O
Connect the discharge resistor for the Gate voltage shaping to this pin.
FBP
37
I
This is the feedback for the positive charge pump converter generating VGH
POUT
38
O
Output of the positive charge pump which is internally connected to the high voltage switch Q2. Connect a
1-µF output capacitor to this pin as well as the feedback divider to set the output voltage for the positive
charge pump respectively for VGH.
C1P
39
I/O
Positive terminal of the flying capacitor for the positive charge pump. Typically a 330-nF flying capacitor is
required.
C1N
40
I/O
Negative terminal of the flying capacitor for the positive charge pump. Typically a 330-nF flying capacitor is
required.
Switch pin of the boost regulator generating Vs
Submit Documentation Feedback
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
BLOCK DIAGRAM
L1
10uH
Vin
2.5V to 6.0V
Vs
15V/1.0A
C4
1 mF
Boost Converter
C2P
Positive Charge
Pump
x2 or x3
D
C2N
SUP
SUP
SW
SW
COMP
C11
330 nF
FB
R4
220 kW
RHVS
FBP
S
POUT
HVS
High Voltage
Switch Control
CTRL
C1P
DRN
C12
330nF
C13
1 mF
C14
100 pF
C1N
POS1
PGND
OUT1
DRVN
3
2
NEG2
C15
330 nF
D2
VGL
-5V/50mA
D3
AGND
OUT3
BGND
POS3
SS
GDLY
FBN
OUT2
VGH
27.5V/50mA
VGH
POS2
C17 C18
C19
22 nF 22 nF 22 nF
Submit Documentation Feedback
R5
300
kW
R6
16 kW
PGND
1
NEG1
ADLY
R10
1kW
C9
68 pF
R1
470 kW
R2
39 kW
R3
30 kW
C10
1 nF
C8
1 mF
C7
C5
C6
22 mF 22 mF 22 mF
EN
C3
22 mF
VIN
C1
22 mF
C2
22 mF
D1
R7
160 kW
REF
C16
330 nF
R8
39 kW
C20
220 nF
7
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
MAIN BOOST CONVERTER (Vs)
η
Efficiency, main boost converter Vs
vs Load current
Figure 1
PWM operation at nominal load current
Figure 2
PWM operation at light load current
Figure 3
Load transient response
Figure 4
Softstart boost converter VS
Figure 5
Overvoltage protection
Figure 6
SYSTEM FUCTIONALITY
Power-on sequencing
Figure 7
Gate voltage shaping VGH
Figure 8
NEGATIVE CHARGE PUMP DRIVER
VGL
vs load current
Figure 9
vs load current (doubler mode)
Figure 10
Input to output offset voltage
vs Opamp 1 load current
Figure 11
Input to output offset voltage
vs Opamp 2 load current
Figure 12
Input to output offset voltage
vs Opamp 3 load current
Figure 13
POSITIVE CHARGE PUMP
VGH
VCOM BUFFERS
EFFICIENCY, MAIN BOOST CONVERTER
vs
LOAD CURRENT
100
EFFICIENCY – %
90
VS=15
VGH=VGL=no load, switching
OpAmp operating, no load
PWM OPERATION NOMINAL LOAD CURRENT
VSW
10 V
/ div
VIN = 5.0 V
VO
50 mV
/ div
80
VIN = 3.3 V
70
IL
1A
/ div
VIN = 2.7 V
60
50
VIN = 5.0 V
VO = 15 V / 700 mA
40
0
200
400
IOUT
600
– mA
800
1000
Figure 1.
8
400 ns / div
Figure 2.
Submit Documentation Feedback
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
PWM OPERATION AT LIGHT LOAD CURRENT
VSW
10 V
/ div
LOAD TRANSIENT RESPONSE
VO1
200 mV
/ div
VO
50 mV
/ div
VIN = 5.0 V
VS = 15 V
VIN = 5.0 V
VO = 15 V / 50 mA
IL
100 mA to
600 mA
IL
1A
/ div
100 ms / div
400 ns / div
VS
10 V
/ div
Figure 3.
Figure 4.
SOFTSTART BOOST CONVERTER - VS
OVERVOLTAGE PROTECTION
VIN = 5.0 V
VO = 15 V
IOUT = 100 mA
CSS = 100 nF
VIN = 5.0 V
VO = 15 V / 100 mA
VSW
10 V
/ div
VO
2 V / div
16 V offset
VIN
5V
/ div
IL
500 mA
/ div
IL
2A
/ div
2.0 ms / div
40 ms / div
Figure 5.
Figure 6.
POWER-ON SEQUENCING
GATE VOLTAGE SHAPING - VGH
VIN
5 V / div
CTRL
5V
/ div
VS
10 V / div
VGH
10 V
/ div
VGH
20 V / div
VGL
5 V / div
VIN = 5.0 V
VO = 15 V
ADLY = 22 nF
GDLY = 47nF
DRN = 1.5 kW to VS
VGH = 1 nF capacitive load to represent panel
4.0 ms / div
2.0 ms / div
Figure 7.
Figure 8.
Submit Documentation Feedback
9
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
VGH
vs LOAD CURRENT - DOUBLER STAGE
VGL vs LOAD CURRENT
24.6
–4.80
VS = 15 V
VGL = 5 V
VS = 15 V
VGH = 24 V
COUT = 2 ´ 1 mF / 35 V
24.4
–4.85
24.2
24.0
–4.90
TA = –40°C
TA = 25°C
TA = 85°C
VGH – V
VGL – V
23.8
TA = –40°C
TA = 25°C
TA = 85°C
–4.95
–5.00
23.6
23.4
23.2
23.0
–5.05
22.8
22.6
–5.10
10
20
30
40
50
60
70
80
90
0
100
50
60
70
80
90
INPUT TO OUTPUT OFFSET VOLTAGE
vs OPAMP 1 LOAD CURRENT
INPUT TO OUTPUT OFFSET VOLTAGE
vs OPAMP 2 LOAD CURRENT
15
10
10
5
5
0
IOUT = –80
IOUT = –50
IOUT = –20
IOUT = –10
IOUT = no load
IOUT = 10
IOUT = 20
IOUT = 50
IOUT = 80
–5
–10
Unity Gain Buffer
VS = 15 V
–20
2
3
4
5
6
7
8
9
–15
Unity Gain Buffer
VS = 15 V
–20
0
1
2
3
4
5
6
7
8
9
VIN – V
Figure 11.
Figure 12.
INPUT TO OUTPUT OFFSET VOLTAGE
vs OPAMP 3 LOAD CURRENT
20
15
10
5
VOFFSET – V
IOUT = –80
IOUT = –50
IOUT = –20
IOUT = –10
IOUT = no load
IOUT = 10
IOUT = 20
IOUT = 50
IOUT = 80
–5
–10
10 11 12 13 14 15
0
IOUT = –80
IOUT = –50
IOUT = –20
IOUT = –10
IOUT = no load
IOUT = 10
IOUT = 20
IOUT = 50
IOUT = 80
–5
–10
–15
Unity Gain Buffer
VS = 15 V
–20
0
1
2
3
4
5
6
7
8
9
100
0
VIN – V
10 11 12 13 14 15
VIN – V
Figure 13.
10
40
Figure 10.
15
1
30
Figure 9.
20
0
20
IOUT – mA
20
–15
10
IOUT – mA
VOFFSET – V
VOFFSET – V
0
Submit Documentation Feedback
10 11 12 13 14 15
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
APPLICATION INFORMATION
SUP
UVLO
Undervoltage
lockout
2.3V typ
Vref
1.213V
VIN
AGND
Regulator 1
Clamps at 13.6V
Thermal
Shutdown latch
155deg°C typ
Regulator 2
4.8V typ
Driver supply
Driver Logic
supply
30uA
REF
Vin
Voltage
clamp
5.8V max
EN
Ichg
Vref
ADLY
Start Boost
converter, negative
and positive charge
pump
3.5k
Vin
Voltage
clamp
5.8V max
Ichg
GDLY
Vref
Enable Gate voltage
shaping block
3.5k
Figure 14. Control Block TPS65165
THERMAL SHUTDOWN
The thermal-shutdown feature prevents damage from excessive heat and power dissipation. Typically the
thermal-shutdown threshold is 155°C. When the device enters thermal-shutdown then the device does not
restart automatically. The device can only be restarted by cycling the input voltage below its
undervoltage-lockout threshold or by cycling the enable EN to ground.
Submit Documentation Feedback
11
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)
UNDERVOLTAGE LOCKOUT
To avoid device malfunction at low input voltages, an undervoltage lockout is included which enables the device
only when the input voltage exceeds 2.3 V.
REFERENCE OUTPUT, REF
The device provides a reference output that is used to regulate the negative charge pump. In order to have a
stable reference voltage, a 220-nF bypass capacitor is required, connected directly from REF to AGND. The
reference output has a current capability of 30 µA which should not be exceeded. Because of this, the feedback
resistor value from FBN to REF should not be smaller than 40 kΩ.
START-UP SEQUENCING
Start-up sequencing can be controlled by adjusting the delay times ADLY and GDLY. After the delay time set by
ADLY passed by, the boost converter, negative and positive charge pumps start at the same time. VGH will only
go high once the delay time, set by GDLY passed by and the signal applied to CTRL is high.
EN
VGH With CTRL = High
GDLY
ADLY
Fall time depends output
capacitor value and load
current
Vs
VGL
Figure 15. Power-On Sequencing
SETTING THE DELAY TIMES ADLY, GDLY
Connecting an external capacitor to the ADLY and GDLY pin sets the delay time. If no delay time is required
these pins can be left open. To set the delay time, the external capacitor connected to ADLY and GDLY is
charged with a constant current source (typically 5 µA). The delay time is terminated when the capacitor voltage
has reached the internal reference voltage of Vref = 1.213 V. The external delay capacitor is calculated by:
5 mA td
5 mA td
C dly +
+
Vref
1.213V
(1)
with td = Desired delay time
12
Submit Documentation Feedback
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)
BOOST CONVERTER
The TPS65165 boost converter block is shown in Figure 16. The boost converter operates with PWM (Pulse
Width Modulation) and a fixed switching frequency of 600 kHz. The converter uses a unique fast-response,
voltage-mode controller scheme with input voltage feedforward. This achieves excellent line and load regulation
(0.2%/A load regulation typical) and allows the use of small external components. To increase the flexibility in
the selection of external component values, the device uses external loop compensation. Although the boost
converter looks like a non-synchronous boost converter topology operating in discontinuous conduction mode, at
light loads, the TPS65165 maintains continuous conduction even at minimal load currents. This is achieved with
a novel architecture using an external Schottky diode with an integrated MOSFET in parallel connected between
SW pin and the SUP pin. The purpose of this MOSFET is to allow the current to go below ground, which is the
case at light load conditions. For this purpose, a small integrated P-Channel MOSFET (Q2) with a typical RDSON
of 10 Ω is sufficient. When the inductor current is positive, the external Schottky diode with the lower forward
voltage carries the current. This causes the converter to operate with a fixed frequency in continuous-conduction
mode over the entire load-current range. This avoids ringing on the switch pin as seen with a typical
non-synchronous boost converter, and allows a simpler compensation network.
SW
VIN
SW
Softstart
Vref
Q2
SS
600 kHz
Oszillator
70Ohm
SUP
Current limit
and
Soft Start
EN
Comparator
Control Logic
Q1
COMP
GM Amplifier
PGND
Sawtooth
Generator
FB
VFB
1.154V
Overvoltage
Comparator
OVP
GM Amplifier
Low Gain
SUP
PGND
Vref
VFB
1.154
RHVS
HVS
Figure 16. Boost Converter Block TPS65165
SOFTSTART BOOST CONVERTER
To minimize inrush current during start-up, an external capacitor connected to the softstart pin (SS) is used to
slowly ramp up the internal current limit of the boost converter. The larger the capacitor, the slower the ramp-up
of the current limit, and the longer the softstart time. A 22-nF capacitor is usually sufficient for typical
applications.
Submit Documentation Feedback
13
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)
HIGH VOLTAGE STRESS TEST BOOST CONVERTER AND POSITIVE CHARGE PUMP
The TPS65165 incorporates a high voltage stress test where the output voltage of the boost converter Vs and
the positive charge pump POUT are set to a higher output voltage compared to the nominal programmed output
voltage. The High Voltage Stress test is enabled by pulling the HVS pin to high. With HVS=high the voltage on
POUT, respectively VGH is regulated to a fixed output voltage of 30 V. The boost converter Vs is programmed
to a higher voltage determined by the resistor connected to RHVS. With HVS=high the RHVS pin is pulled to
GND which sets the voltage for the boost converter during the High Voltage Stress Test. The output voltage for
the boost converter during high voltage stress test is calculated as:
R1 ) R2 ø R4
R1 ) R2 ø R4
Vs HVS + VFB
+ 1.146V
R2 ø R4
R2 ø R4
R4 +
ǒ
R1
VsHVS
VFB
Ǔ
*1
R2
R2 * R1
(2)
With:
VsHVS = Boost converter output voltage with HVS=high
VFB = 1.146V
R4 = Resistor connected to pin RHVS
OVERVOLTAGE PROTECTION BOOST CONVERTER
The boost converter has an integrated overvoltage-protection circuit to prevent the switch voltage from
exceeding the absolute maximum switch voltage rating in the event of a system fault. The device protects itself if
the feedback pin is shorted to ground by clamping the boost-converter output voltage to 20 V. To implement the
overvoltage protection, the overvoltage comparator shown in Figure 16 monitors the output voltage via the SUP
pin. When the output voltage exceeds the overvoltage threshold of typically 20 V, the device stops switching
until the output voltage drops below the comparator threshold again. The typical waveform is shown in Figure 6.
INPUT CAPACITOR SELECTION VIN, SUP
Low-ESR ceramic capacitors are recommended for good input-voltage filtering. The TPS65165 has an analog
input (VIN) and a power supply input (SUP) powering all the internal rails, including the operational amplifiers.
1-µF bypass capacitors are required as close as possible from VIN to GND, and from SUP to GND. Depending
on the overall load current, two or three 22-µF input capacitors are required. For better input-voltage filtering, the
input capacitor values can be increased. Refer to Table 1 and typical applications for input capacitor
recommendations.
Table 1. Input Capacitor Selection
14
CAPACITOR
VOLTAGE RATING
COMPONENT
SUPPLIER
22µF/1210
6.3 V
Taiyo Yuden
Cin
1µF/1206
6.3 V
Taiyo Yuden
Bypass AVIN, SUP
Submit Documentation Feedback
COMMENTS
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
BOOST CONVERTER DESIGN PROCEDURE
The first step in the design procedure is to verify whether the maximum possible output current of the boost
converter supports the specific application requirements. To simplify the calculation the fastest approach is to
estimate the converter efficiency, by taking the efficiency numbers from the provided efficiency curves or to use
a worst case assumption for the expected efficiency, e.g., 80%. With the efficiency number it is possible to
calculate the steady state values of the application.
1. Converter Duty Cycle:
Vin h
D +1*
Vout
(3)
2. Maximum output current:
ǒ
Ǔ
Iout + Isw * Vin D
2 ƒs L
(1 * D)
(4)
3. Peak switch current:
I
I swpeak + Vin D ) out
2 ƒs L I * D
(5)
With:
Isw = converter switch current (minimum switch current limit=4.4 A)
fs = converter switching frequency (typical 600kHz)
L = Selected inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.8 as an estimation)
The peak switch current is the steady state peak switch current the integrated switch, inductor and external
Schottky diode has to be rated for. The calculation must be done for the minimum input voltage where the peak
switch current is highest.
INDUCTOR SELECTION
The TPS65165 typically operates with a 10-µH inductor. The main parameter for inductor selection is the
inductor saturation current. This should be higher than the peak switch current as calculated in Equation 5, with
additional margin for heavy load transients. An alternative, more conservative approach is to choose the inductor
with saturation current at least as high as the typical switch current limit of 5.5 A.
The second important parameter is the inductor DC resistance. Usually the lower the DC resistance the higher
the efficiency of the converter. The choice of an inductor can affect converter efficiency by as much as 10%.
Possible inductors are shown in Table 2.
Table 2. Inductor Selection Boost Converter
INDUCTOR VALUE
COMPONENT SUPPLIER
DIMENSIONS IN mm
Isat/DCR
10 µH
Sumida CDRH8D38-100
8.3×8.3×4.0
3.0 A / 38 mΩ
10 µH
Wuerth 744066100
10×10×3.8
4.0 A / 25 mΩ
10 µH
Coilcraft DO3316P-103
12.95×9.4×5.51
3.8 A / 3838 mΩ
Submit Documentation Feedback
15
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
OUTPUT CAPACITOR SELECTION
For best output voltage filtering, a low-ESR output capacitor is recommended. Ceramic capacitors have a low
ESR value and work best with the TPS65165. Three 22µF or six 10uF ceramic output capacitors in parallel are
sufficient for most applications. More capacitors can be added to improve the load transient regulation. Refer to
Table 3 for details on selecting output capacitors.
Table 3. Output Capacitor Selection
CAPACITOR
VOLTAGE RATING
COMPONENT SUPPLIER
22 µF / 1812
16 V
Taiyo Yuden EMK432BJ226MM
Rectifier diode selection
To achieve high efficiency, a Schottky diode should be used. The reverse voltage rating should be higher than
the maximum output voltage of the converter. The current rating for the Schottky diode is calculated as the off
time of the converter times the typical switch current of the TPS65165:
I avg + (1 * D) Isw + Vin
5.5A
Vout
(6)
where Isw = the typical switch current of the TPS65165 (5.5 A)
A Schottky diode with 2-A maximum average rectified forward current rating is sufficient for most applications.
The Schottky rectifier must have adequate power dissipation. The dissipated power is the average rectified
forward current times the diode forward voltage.
Vin
P D + I avg VF + Isw (1 * D) Vsw
VF
Vout
(7)
where Isw = typical switch current of the TPS65165 (5.5 A)
Table 4. Rectifier Diode Selection (Boost Converter)
CURRENT RATING
Iavg
Vr
Vforward
RθJA
SIZE
COMPONENT SUPPLIER
3A
20 V
0.36 V at 3 A
46°C/W
SMC
MBRS320, International Rectifier
2A
20 V
0.44 V at 2 A
75°C/W
SMB
SL22, Vishay Semiconductor
2A
20 V
0.5 V at 2 A
75°C/W
SMB
SS22, Fairchild Semiconductor
SETTING THE OUTPUT VOLTAGE AND SELECTING THE FEEDFORWARD CAPACITOR
The output voltage is set by the external resistor-divider value, and is calculated as:
V out + 1.146V
ǒ1 ) R1
Ǔ
R2
(8)
Across the upper resistor, a bypass capacitor is required to speed up the circuit during load transients. The
capacitor value is caluculated as:
1
1
Cff =
=
2 ´ p ´ fz ´ R1 2 ´ p ´ 5000 ´ R1
(9)
A standard value nearest to the calculated value should be used.
COMPENSATION (COMP)
The regulator loop can be compensated by adjusting the external components connected to the COMP pin. The
COMP pin is the output of the internal transconductance error amplifier. A single capacitor connected to this pin
sets the low-frequency gain. A 1.0-nF capacitor is sufficient for most of the applications. Adding a series resistor
sets an additional zero and increases the high-frequency gain. Equation 10 calculates the frequency where the
resistor increases the high frequency gain.
1
ƒz +
2 p Cc Rc
(10)
16
Submit Documentation Feedback
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
Lower input voltages require a higher gain, and therefore a lower compensation-capacitor value. Refer to the
typical applications for the appropriate component selection.
POSITIVE CHARGE PUMP
The fully-integrated positive charge pump automatically switches its gain between doubler and tripler mode. As
shown in Figure 17, the input voltage of the positive charge pump is the SUP pin, that is connected to the output
of the main boost converter (Vs).
The charge pump requires two 330-nF flying capacitors and a 1-µF output capacitance for stable operation. The
positive charge pump also supports the high-voltage stress test by pulling the HVS pin high. This programs the
output voltage to a fixed output voltage of 30 V by using the internal voltage divider as shown in Figure 17.
During normal operation the HVS pin is pulled low, and the output voltage is programmed with the external
voltage divider.
ǒ1 ) R5
Ǔ
R6
V out + 1.213V
R5 + R6
ǒ
Ǔ
Vout
* 1 + R6
V FB
ǒ
Ǔ
Vout
*1
1.213
(11)
To minimize noise and leakage-current sensitivity, we recommend a value of approximately 20 kΩ for the lower
feedback divider resistor R6. A 100-pF feedforward capacitor across the upper feedback resistor R5 is typically
required.
FBP
600 kHz
POUT
f clockx 2
1.2MHz
SU P
HVS
select
Q3
Vref
1 .213 V
HVS
Control Logic
Automatic
Gain select
(doubler or
tripler mode )
C1 N
Q4
Softstart
C 1P
Q6
SUP =Vs
POUT
D3
D0
I DRVP
D1
C 2P
D2
Q5
C2 N
AGND
Figure 17. Positive Charge Pump Block TPS65165
Submit Documentation Feedback
17
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
NEGATIVE CHARGE PUMP DRIVER
The negative charge pump provides a regulated output voltage set by the external resistor divider. It inverts the
voltage applied to the SUP pin (the boost-converter output voltage), and regulates it to the programmed voltage.
SUP
600 kHz
Q7
DRVN
f clock x2
1 .2MHz
Control
Logic
Softstart
I DRVN
AGND
FBN
Vref
0V
Figure 18. Negative Charge Pump Block TPS65165
The output voltage is VGL = (–Vs) + VDROP. VDROP is the voltage drop across the external diodes and internal
charge pump MOSFETs.
Setting the output voltage:
V out + *VREF R7 + *1.213V
R8
R7 + R8
ŤV outŤ
VREF
+ R8
R7
R8
(12)
ŤV outŤ
1.213
(13)
Since the reference-output driver current should typically not exceed 30 µA, the lower feedback-resistor value
R8 should be in a range of 40 kΩ to 120 kΩ. The negative charge pump requires two external Schottky diodes.
The peak current rating of the Schottky diode must be twice the load current of the output. For a 20-mA output
current, the dual Schottky diode BAT54 is a good choice.
HIGH VOLTAGE SWITCH CONTROL (Gate Voltage Shaping)
For correct operation of this block it is not recommended to connect an output capacitor to VGH. If the output
shows higher output ripple voltage than expected then the output capacitor value on POUT needs to be
increased instead. The device has an integrated high-voltage switch to provide gate-voltage modulation of VGH.
If this feature is not required, then CTRL pin must be pulled high or connected to VIN. When the device is
disabled or the input voltage is below the undervoltage lockout (UVLO), both switches (Q4 and Q5) are off, and
VGH is discharge by a 1-kΩ resistor over Q8, as shown in Figure 19.
18
Submit Documentation Feedback
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
Power Good
FB
Power Good
FBP
Power Good
FBN
UVLO
EN
POUT
CTRL
Vref
GDLY
Q4
3.5 k
I DLY
EN
VGH
Control
Voltage
clamp
5 . 8 V max
CTRL=high Q4 on, Q5 off
CTRL=low Q4 off, Q5 on
EN=low Q4 and Q5 off, Q8
on
1 kW
Q5
Vin
Q8
DRN
Vs
R10
10k
R10
1k
R10
10k
Option 1
Option 2
Figure 19. High Voltage Switch (Gate Voltage Shaping) Block TPS65165
To implement gate-voltage shaping, the control signal from the LCD timing controller (TCON) is connected to the
CTRL pin. CTRL is activated when the device is enabled, the input voltage is above the undervoltage lockout, all
the output voltages (Vs, VGL, VGH) are in regulation, and the delay time is set by the GDLY pin passed by. As
soon as one of the outputs is pulled below its Power Good level, Q4 and Q5 are turned off and VGH is
discharged via a 1-kΩ resistor over Q8.
Submit Documentation Feedback
19
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
With CTRL = high, Q4 is turned on and the charge pump output voltage is present at VGH. When the CTRL pin
is pulled low, Q4 is turned off and Q5 is turned on, discharging VGH. The slope and time for discharging VGH is
determined by the LCD capacitance and the termination on DRN. An additional output capacitor is not
recommended on VGH. There are basically two options available to terminate the DRN pin, depending on the
LCD capacitance and required overall converter efficiency.
VH
VGH
VL
CTRL
toff
T
Figure 20. High Voltage Switch (Gate Voltage Shaping) Timing Diagram
Option 1 in Figure 19 draws no current from Vs, and is therefore better in terms of converter efficiency. The
voltage level VL (the discharge level of VGH) is determined by the LCD capacitance, the resistor connected to
DRN and the off time, toff. The lower the resistor value connected to DRN, the lower the discharge voltage level
VL.
Option 2 in Figure 19 constantly draws current from Vs due to the voltage divider connected to Vs. The
advantage of this solution is that the low-level voltage VL is given by the voltage divider, assuming the feedback
resistor values are small, allowing the LCD capacitance to discharge during toff. This solution is not
recommended for very large display panels because the feedback divider resistor values must be too low,
drawing too much current from Vs.
20
Submit Documentation Feedback
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
Operational Amplifier 1, 2 and 3
The TPS65165 has three integrated operational amplifiers. OpAmp 3 is already configured as a standard buffer
as shown in Figure 21. The operational amplifiers can be used as a gamma correction buffer or as a VCOM
buffer.
SUP
Series Resistor for Driving POS1
Capacitive Loads
3.3R
EN
1
10k
NEG1
OUT1
10k
10nF
POS2
2
NEG2
10k
3
OUT3
BGND
POS3
OUT2
Figure 21. Operational Amplifier Block
The OpAmp power supply pin is the SUP pin connected to the boost converter Vs. To achieve good
performance and minimize the output noise, a 1-µF bypass capacitor is required directly from the SUP pin to
ground. When the device is disabled, the OpAmp outputs are pulled low via a 10kΩ resistor. The OpAmps are
not designed to drive capacitive loads; therefore it is not recommended to connect a capacitor directly to the
OpAmp outputs. If capacitive loads are driven we recommend using a series resistor at the output to provide
stable operation. With a 3.3-Ω series resistor, a capacitive load of 10 nF can be driven, which is usually
sufficient for typical LCD applications.
Operational Amplifier Termination
The TPS65165 has three integrated operational amplifiers. For some applications, not all of the amplifiers are
used. To minimize device quiescent current the terminals need to be terminated. For the unity gain buffer,
OpAmp 3 the positive terminal is connected to GND and the output is left open. For OpAmp 2 and 3 the
negative terminal is connected to the OpAmp output and the positive terminal is connected to GND. Using such
a termination minimizes device quiescent current and correct functionality of the device.
Submit Documentation Feedback
21
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
PCB Layout Design Guidelines:
1. Place the power components outlined in bold first on the PCB.
2. Rout the traces outlined in bold with wide PCB traces
3. Place a 1-µF bypass capacitor directly from the Vin pin to GND since this is the supply pin for internal
circuits.
4. Place a 1-µF bypass capacitor directly from the SUP pin to GND since this is the supply pin for internal
circuits.
5. Use a short and wide trace to connect the SUP pin to the output of the boost converter Vs.
6. Place the 220-nF reference capacitor directly from REF to AGND close to the IC pins.
7. The feedback resistor for the negative charge pump between FBN and REF needs to be >40kΩ.
8. Use short traces for the charge pump drive pin (DRVN) of VGL because the traces carry switching
waveforms.
9. Place the flying capacitors as close as possible to the C1P, C1N and C2P, C2N pin.
10. Solder the Power Pad of the QFN package to GND and use thermal vias to lower the thermal resistance
L1
10 mH
Vin
5.0 V
C11
C10
1 nF
330nF
29 30
33
2
COMP
FB
C2P
RHVS
C2N
FBP
HVS
POUT
17
36
5
R10
1kW
R2
39 kW
1
16
6
7
CTRL
C1P
DRN
C1N
TPS65165
POS1
PGND
NEG1
PGND
OUT1
VGH
10 POS2
9
DRVN
NEG2
14
15
20
11
3
12
AGND
OUT3
BGND
POS3
SS
GDLY
OUT2
ADLY
FBN
8
23
C17 C18
C19
22 nF 22 nF 22 nF
REF
34
Submit Documentation Feedback
R4
220 kW
32
37
38
39
40
C13
1 mF
C12
330nF
C14
100 pF
27
VGH
27.5V/50mA
35
18
21
22
C15
330 nF
D2
VGL
-5V/50mA
D3
R7
160 kW
R8
39 kW
C20
220 nF
R5
300
kW
R6
16 kW
28
Figure 22. Layout Recommendation
22
C9
68 pF
4
SUP
24 25
SW
R3
30 kW
C4
1 mF
R1
470 kW
C8
1 mF
C7
C5
C6
22 mF 22 mF 22 mF
SW
C3
22 mF
Vs
15V/1.0A
EN
C2
22 mF
VIN
C1
22 mF
D1
C16
330 nF
TPS65165
www.ti.com
SLVS723A – DECEMBER 2006 – REVISED MAY 2007
TYPICAL APPLICATION
L1
10 mH
Vin
5.0 V
29 30
C11
2
330nF
COMP
SW
33
FB
36
5
6
7
C2P
C2N
FBP
HVS
POUT
CTRL
C1P
DRN
C1N
TPS65165
POS1
PGND
NEG1
PGND
OUT1
VGH
10 POS2
9
DRVN
NEG2
14
15
20
11
3
12
AGND
OUT3
BGND
POS3
SS
GDLY
OUT2
ADLY
FBN
8
34
R4
220 kW
32
RHVS
17
R10
1kW
R2
39 kW
1
16
C9
68 pF
4
SUP
24 25
R3
30 kW
C10
1 nF
C4
1 mF
R1
470 kW
C8
1 mF
C7
C5
C6
22 mF 22 mF 22 mF
SW
C3
22 mF
Vs
15V/1.0 A
EN
C2
22 mF
VIN
C1
22 mF
D1
23
C17 C18
C19
22 nF 22 nF 22 nF
REF
37
38
39
C13
1 mF
C12
C14
100 pF
40 330 nF
27
R6
16 kW
28
VGH
27.5 V/50 mA
35
18
21
22
R5
300
kW
C15
330 nF
D2
VGL
-5 V/50 mA
D3
R7
160 kW
C16
330 nF
R8
39 kW
C20
220 nF
Figure 23. Typical application running from a 5V supply rail
Submit Documentation Feedback
23
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPS65165RSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65165
TPS65165RSBRG4
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65165
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS65165RSBR
Package Package Pins
Type Drawing
WQFN
RSB
40
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65165RSBR
WQFN
RSB
40
3000
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated