Revised March 1999 74VHC74 Dual D-Type Flip-Flop with Preset and Clear General Description The VHC74 is an advanced high speed CMOS Dual DType Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: fMAX = 170 MHz (typ) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low power dissipation: ICC = 2 µA (max) at TA = 25°C ■ Pin and function compatible with 74HC74 Ordering Code: Order Number Package Number 74VHC74M M14A 74VHC74SJ M14D 74VHC74MTC 74VHC74N Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol IEEE/IEC Truth Table Pin Descriptions Pin Names Inputs Description Outputs Function CLR PR D CK D1, D2 Data Inputs CK1, CK2 Clock Pulse Inputs CLR1, CLR2 Direct Clear Inputs PR1, PR2 Direct Preset Inputs H H L Q1, Q1, Q2, Q2 Output H H H H H X Q Q L H X X L H Clear H L X X H L Preset L L X X H (Note 1) H (Note 1) L H H L Qn Qn No Change Note 1: This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) state. © 1999 Fairchild Semiconductor Corporation DS011505.prf www.fairchildsemi.com 74VHC74 Dual D-Type Flip-Flop with Preset and Clear October 1992 74VHC74 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 3) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) Supply Voltage (VCC) 2.0V to 5.5V Input Voltage (VIN) 0V to +5.5V Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT ) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC/GND Current (ICC) ±50 mA VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) Soldering (10 seconds) 0V to VCC −40°C to +85°C Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading varaibles. Fairchild does not recommend operation outside databook specifications. 260°C Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL VCC (V) TA = 25°C Min Typ TA = −40°C to +85°C Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 VIN = VIH IOH = −50 µA 2.0 0.0 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 ICC Quiescent Supply Current www.fairchildsemi.com or VIL IOH = −4 mA V Voltage Input Leakage Current V V LOW Level Output IIN Conditions V 3.0 − 5.5 HIGH Level Output Units IOH = −8 mA VIN = VIH IOL = 50 µA V or VIL IOL = 4 mA 3.0 0.36 0.44 4.5 0.36 0.44 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 2.0 20.0 µA VIN = VCC or GND 2 V IOL = 8 mA Symbol fMAX Parameter Maximum Clock TA = 25°C Min Typ 3.3 ± 0.3 80 125 50 75 45 5.0 ± 0.5 130 170 110 90 115 Frequency tPLH Propagation Delay tPHL Time (CK-Q, Q) 3.3 ± 0.3 5.0 ± 0.5 tPLH Propagation Delay Time tPHL (CLR, PR -Q, Q) TA = −40°C to +85°C VCC (V) 3.3 ± 0.3 5.0 ± 0.5 Max Min Max 70 MHz MHz 75 6.7 11.9 1.0 14.0 9.2 15.4 1.0 17.5 4.6 7.3 1.0 8.5 6.1 9.3 1.0 10.5 7.6 12.3 1.0 14.5 10.1 15.8 1.0 18.0 4.8 7.7 1.0 9.0 6.3 9.7 1.0 11.0 10 CIN Input Capacitance 4 CPD Power Dissipation 25 Units 10 ns ns ns ns Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF pF VCC = Open pF (Note 4) Capacitance Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/2 (per F/F). AC Operating Requirements Symbol tW(L) Parameter TA = 25°C Typ TA = −40°C to +85°C Guaranteed Minimum 3.3 6.0 7.0 tW(H) 5.0 5.0 5.0 tW(L) 3.3 6.0 7.0 5.0 5.0 5.0 3.3 6.0 7.0 5.0 5.0 5.0 3.3 0.5 0.5 5.0 0.5 0.5 3.3 5.0 5.0 5.0 3.0 3.0 tS tH tREC Minimum Pulse Width (CK) VCC (V) (Note 5) Minimum Pulse Width (CLR, PR) Minimum Setup Time Minimum Hold Time Minimum Recovery Time (CLR, PR) Units ns ns ns ns ns Note 5: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V 3 www.fairchildsemi.com 74VHC74 AC Electrical Characteristics 74VHC74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 4 74VHC74 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 5 www.fairchildsemi.com 74VHC74 Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.