Revised January 2004 MM74HC423A Dual Retriggerable Monostable Multivibrator General Description Features The 74HC423A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology. They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits. ■ Typical propagation delay: 40 ns Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken LOW resets the one shot. The MM74HC423A cannot be triggered from clear. ■ Fanout of 10 LS-TTL loads The MM74HC423A is retriggerable. That is, it may be triggered repeatedly while its outputs are generating a pulse and the pulse will be extended. ■ Wide power supply range: 2V–6V ■ Low quiescent current: 80 µA maximum (74HC Series) ■ Low input current: 1 µA maximum ■ Simple pulse width formula T = RC ■ Wide pulse range: 400 ns to ∞ (typ) ■ Part to part variation: ±5% (typ) ■ Schmitt Trigger A & B inputs allow rise and fall times to be as slow as one second Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques. The output pulse equation is simply: PW = (REXT) (CEXT); where PW is in seconds, R is in ohms, and C is in farads. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Ordering Code: Order Number MM74HC423AM (Note 1) MM74HC423ASJ MM74HC423AMTC (Note 1) MM74HC423AN Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Timing Component Top View © 2004 Fairchild Semiconductor Corporation Note: Pin 6 and Pin 14 must be hard-wired to GND. DS005338 www.fairchildsemi.com MM74HC423A Dual Retriggerable Monostable Multivibrator September 1983 MM74HC423A Truth Table Inputs H L ↑ ↓ Outputs Clear A B Q L X X L H X H X L H X X L H L ↑ H ↓ H = = = = HIGH Level LOW Level Transition from LOW-to-HIGH Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant Logic Diagram www.fairchildsemi.com 2 L Q H MM74HC423A Theory of Operation FIGURE 1. TRIGGER OPERATION RETRIGGER OPERATION As shown in Figure 1 and the Logic Diagram before an input trigger occurs, the one-shot is in the quiescent state with the Q output LOW, and the timing capacitor CEXT completely charged to VCC. When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC) a valid trigger is recognized, which turns on comparator C1 and N-Channel transistor N11. At the same time the output latch is set. With transistor N1 on, the capacitor CEXT rapidly discharges toward GND until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns OFF. Comparator C1 then turns OFF while at the same time comparator C2 turns on. With transistor N1 OFF, the capacitor CEXT begins to charge through the timing resistor, REXT, toward VCC. When the voltage across CEXTequals VREF2, comparator C2 changes state causing the output latch to reset (Q goes LOW) while at the same time disabling comparator C2. This ends the timing cycle with the one-shot in the quiescent state, waiting for the next trigger. The MM74HC423A is retriggered if a valid trigger occurs 3 followed by another trigger 4 before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at pin or has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated 4, the voltage at the R/CEXT pin will again drop to VREF1 before progressing along the RC charging curve toward VCC . The Q output will remain high until time T, after the last valid retrigger. Because the trigger-control circuit flip-flop resets shortly after CX has discharged to the reference voltage of the lower reference circuit, the minimum retrigger time, trr is a function of internal propagation delays and the discharge time of CX: Another removal/retrigger time occurs when a short clear pulse is used. Upon receipt of a clear, the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger. This time is dependent on the capacitor used and is approximately: A valid trigger is also recognized when trigger input B goes from GND to VCC (while input A is at GND and input clear is at VCC2.) It should be noted that in the quiescent state CEXTis fully charged to VCC causing the current through resistor REXT to be zero. Both comparators are “OFF” with the total device current due only to reverse junction leakages. An added feature of the MM74HC423A is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CEXT, REXT, or the duty cycle of the input waveform. 3 www.fairchildsemi.com MM74HC423A Theory of Operation (Continued) RESET OPERATION These one shots may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to VCC by turning on transistor Q1 5. When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the clear input is held LOW, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Clear input, the output pulse T can be made significantly shorter than the minimum pulse width specification. Typical Output Pulse Width vs. Timing Components Typical 1ms Pulse Width Variation vs. Supply Typical Distribution of Output Pulse Width, Part to Part Minimum REXT vs. Supply Voltage Typical 1ms Pulse Width Variation vs. Temperature Note: R and C are not subjected to temperature. The C is polypropylene. www.fairchildsemi.com 4 Recommended Operating Conditions (Note 3) −0.5V to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5V to VCC +1.5V DC Output Voltage (VOUT) −0.5V to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA (Note 4) 600 mW S.O. Package only 500 mW 0 VCC V −40 +85 °C DC Electrical Characteristics Conditions 1000 ns 500 ns VCC = 6.0V 400 ns Note 3: Unless otherwise specified all voltages are referenced to ground. 260°C (Soldering 10 seconds) VCC = 2.0V VCC = 4.5V Note 2: Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) VOH V DC Input or Output Voltage (Clear Input) −65°C to +150°C Power Dissipation (PD) VIL Units (VIN, VOUT) ±50 mA per pin (ICC) VIH 6 Maximum Input Rise and Fall Time Storage Temperature Range (TSTG) Parameter Max 2 Operating Temperature Range (TA) DC VCC or GND Current, Symbol Min Supply Voltage (VCC) Note 4: Power Dissipation Temperature Derating: Plastic “N” Package: − 12mW/°C from 65°C to 85°C. (Note 5) VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 6.0V 4.2 4.2 4.2 Maximum LOW Level 2.0V 0.3 0.3 0.3 Input Voltage 4.5V 0.9 0.9 0.9 6.0V 1.2 1.2 1.2 Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 4.5V 4.5 4.4 4.4 4.4 6.0V 6.0 5.9 5.9 5.9 Units V V V VIN = VIH or VIL VOL |IOUT| ≤ 4.0 mA 4.5V 3.96 3.84 3.7 |IOUT| ≤ 5.2 mA 6.0V 5.46 5.34 5.2 Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 4.5V 0 0.1 0.1 0.1 6.0V 0 0.1 0.1 0.1 V VIN = VIH or VIL IIN |IOUT| ≤ 4 mA 4.5V 0.26 0.33 0.4 |IOUT| ≤ 5.2 mA 6.0V 0.26 0.33 0.4 VIN = VCC or GND 5.0V 0.5 5.0 5.0 µA VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA Supply Current (standby) IOUT = 0 µA Maximum Active Supply VIN = VCC or GND 2.0V 36 80 110 130 µA Current (per R/CEXT = 0.5VCC 4.5V 0.33 1.0 1.3 1.6 mA 6.0V 0.7 2.0 2.6 3.2 mA Maximum Input Current (Pins 7, 15) IIN Maximum Input Current (all other pins) ICC ICC monostable) Note 5: For a power supply of 5V ±10% the worst-case output voltages (VOH, VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 5 www.fairchildsemi.com MM74HC423A Absolute Maximum Ratings(Note 2) MM74HC423A AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPLH Parameter Conditions Maximum Trigger Propagation Delay, Typ Guatanteed Limit Units 22 33 ns 25 42 ns 20 27 ns 22 33 ns 14 26 ns A, B to Q tPHL Maximum Trigger Propagation Delay, A, B to Q tPHL Maximum Propagation Delay, Clear to Q tPLH Maximum Propagation Delay, Clear to Q tW Minimum Pulse Width, A, B or Clear tREM Minimum Clear Removal Time tWQ(MIN) Minimum Output Pulse Width CEXT = 28 pF tWQ Output Pulse Width CEXT = 1000 pF 0 ns 400 ns 10 µs REXT = 2 kΩ REXT = 10 kΩ AC Electrical Characteristics CL = 50 pF tr = tf = 6 ns (Unless otherwise specified) Symbol tPLH tPHL tPHL tPLH tW tREM tWQ Parameter VCC Conditions TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Units Guaranteed Limits Maximum Trigger Propagation 2.0V 77 169 194 210 Delay, A or B to Q 4.5V 26 42 51 57 6.0V 21 32 39 44 Maximum Trigger Propagation 2.0V 88 197 229 250 Delay, A or B to Q 4.5V 29 48 60 67 6.0V 24 38 46 51 Maximum Propagation 2.0V 54 114 132 143 Delay, Clear to Q 4.5V 23 34 41 45 6.0V 19 28 33 36 Maximum Propagation 2.0V 56 116 135 147 Delay, Clear to Q 4.5V 25 36 42 46 6.0V 20 29 34 37 Minimum Pulse Width 2.0V 57 123 144 157 A, B, Clear 4.5V 17 30 37 42 6.0V 12 21 27 30 Minimum Clear 2.0V 0 0 0 0 Removal Time 4.5V 0 0 0 0 6.0V 0 0 0 0 Min 5.0V 1 0.9 0.86 0.85 ms Max 5.0V 1 1.1 1.14 1.15 ms 2.0V 30 75 95 110 Output Pulse Width CEXT = 0.1 µF ns ns ns ns ns ns REXT = 10 kΩ tTLH, tTHL Maximum Output Rise and Fall Time CPD 4.5V 8 15 19 22 6.0V 7 13 16 19 Power Dissipation 83 ns pF Capacitance (Note 6) CIN Maximum Input 12 20 20 20 pF 6 10 10 10 pF Capacitance (Pins 7 & 15) CIN Maximum Input Capacitance (other inputs) Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + I CC. www.fairchildsemi.com 6 MM74HC423A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7 www.fairchildsemi.com MM74HC423A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 MM74HC423A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 9 www.fairchildsemi.com MM74HC423A Dual Retriggerable Monostable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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