SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993 • • • • • • • • DW OR NT PACKAGE (TOP VIEW) BiCMOS Process With TTL Inputs and Outputs BiCMOS Design Reduces Standby Current Flow-Through Pinout (All Inputs on Opposite Side From Outputs) Functionally Equivalent to SN74ALS29834 and AMD Am29834 High-Speed Bus Transceiver With Parity Generator/ Checker Parity-Error Flag With Open-Collector Output Available Register For Storage of the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT) OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB CLK description The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error flag (ERR). ERR is clocked into the register on the rising edge of the CLK input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides inverting logic. The SN74BCT29834 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUT AND I/O OEB OEA CLR CLK Ai ∑ of H’s Bi† ∑ of L’s A B PARITY ERR‡ L H X X Odd Even NA NA A H L NA H L H ↑ NA Odd Even B NA NA H L B data to A bus and check parity X X L X X X X NA NA H Clear error-flag register H H H L H H No↑ No↑ ↑ ↑ X X Odd Even X Z Z Z NC H L H Isolation§ L L X X Odd Even NA NA A L H NA A data to B bus and generate inverted parity FUNCTION A data to B bus and generate parity NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume the ERR output was previously high. § In this mode, the ERR output, when enabled, shows inverted parity of the A bus. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993 functional logic diagram (positive logic) A1 – A8 8x 8 8 B1 – B8 EN 8x 8 EN OEB PARITY 8 OEA 8 MUX 1 1 9 2k P 1 1 G1 1D CLK C1 CLR 2–2 R POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ERR SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993 error-flag waveforms OEB H L OEA H L Even Bi + PARITY Odd tsu th H L CLK tw tsu tw H L CLR tPHL tPLH H L ERR ERROR-FLAG FUNCTION TABLE INPUTS INTERNAL TO DEVICE OUTPUT PRESTATE OUTPUT FUNCTION CLR CLK POINT P ERRn–1† ERR H H H ↑ ↑ ↑ H X L H L X H L L Sample L X X X H Clear † ERRn–1 represents the state of the ERR output before any changes at CLR, CLK, or point P. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993 recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL VOH Low-level input voltage 2.4 V IOH IOL High-level output current – 24 mA Low-level output current 48 mA TA Operating free-air temperature 70 °C High-level input voltage 2 V V 0.8 High-level output voltage, ERR 0 V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VOH All inputs /outputs except ERR 5V VCC = 4 4.5 IOH VOL ERR VCC = 4.5 V, VCC = 4.5 V, II IIH‡ IIL‡ VCC = 5.5 V, VCC = 5.5 V, Data Control IOS§ ICCL MIN II = –18 mA IOH = – 15 mA TYP† V 20 0.35 VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VO = 0 Outputs open V 2 IOL = 48 mA VI = 5.5 V VI = 0 0.4 4V UNIT –1.2 2.4 IOH = – 24 mA VOH = 2.4 V VCC = 5 5.5 5V V, MAX 0.5 V 0.1 mA 20 µA – 0.2 – 0.75 –75 ICCZ VCC = 5.5 V, Outputs open † All typical values are at VCC = 5 V, TA = 25°C. ‡ These parameters include off-state output current for I/O ports only. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. µA mA – 250 mA 55 80 mA 30 45 mA timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN tw Pulse duration tsu Setup time before CLK↑ th Hold time after CLK↑ 2–4 CLK high 10 CLK low 10 CLR low 10 Bi and PARITY 12 CLR inactive 12 Bi and PARITY POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 MAX UNIT ns ns ns SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL A PARITY tPZH tPZL OEA or OEB A or B tPHZ tPLZ OEA or OEB A or B CLK tPLH tPLH tPHL CLR OEA ERR PARITY VCC = 5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† MIN TYP MAX MIN MAX 1 5 7 1 8 1.5 4 6 1.5 7 1.5 10 13 1.5 15 1.5 8 10 1.5 15 2 11 15 2 19 2 15 19 2 21 2 8 11 2 15 2 13 17 2 21 1.5 7 10 1.5 12 1.5 13 17 1.5 18 1.5 10 13 1.5 15 1.5 10 13 1.5 15 UNIT ns ns ns ns ns ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 1: Load circuits and voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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