19-3645; Rev 0; 4/05 KIT ATION EVALU E L B A IL AVA Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs The MAX1437 octal, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. This ADC is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. The MAX1437 operates from a 1.8V single supply and consumes only 768mW (96mW per channel) while delivering a 69.9dB (typ) signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1437 features a power-down mode for idle periods. An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise. Features ♦ Excellent Dynamic Performance 69.9dB SNR at 5.3MHz 96dBc SFDR at 5.3MHz 95dB Channel Isolation ♦ Ultra-Low Power 96mW per Channel (Normal Operation) ♦ Serial LVDS Outputs ♦ Pin-Selectable LVDS/SLVS (Scalable Low-Voltage Signal) Mode ♦ LVDS Outputs Support Up to 30 Inches FR-4 Backplane Connections ♦ Test Mode for Digital Signal Integrity ♦ Fully Differential Analog Inputs ♦ Wide Differential Input Voltage Range (1.4VP-P) A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip PLL generates the high-speed serial low-voltage differential signal (LVDS) clock. ♦ On-Chip 1.24V Precision Bandgap Reference The MAX1437 has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two’s complement or binary format. The MAX1437 offers a maximum sample rate of 50Msps. See the Pin-Compatible Versions table below for higherand lower-speed versions. This device is available in a small, 14mm x 14mm x 1mm, 100-pin TQFP package with exposed paddle and is specified for the extended industrial (-40°C to +85°C) temperature range. ♦ Evaluation Kit Available (Order MAX1437EVKIT) ♦ Clock Duty-Cycle Equalizer ♦ Compact, 100-Pin TQFP Package with Exposed Paddle Ordering Information PART TEMP RANGE PIN-PACKAGE MAX1437ECQ -40°C to +85°C 100 TQFP-EP* (14mm x 14mm x 1mm) *EP = Exposed paddle. Applications Pin-Compatible Versions Ultrasound and Medical Imaging Instrumentation Multichannel Communications PART SAMPLING RATE (Msps) RESOLUTION (BITS) MAX1434 50 10 MAX1436 40 12 MAX1438** 65 12 **Future product—contact factory for availability. Pin Configuration appears at the end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1437 General Description MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs ABSOLUTE MAXIMUM RATINGS AVDD to GND.........................................................-0.3V to +2.0V CVDD to GND ........................................................-0.3V to +3.6V OVDD to GND ........................................................-0.3V to +2.0V IN_P, IN_N to GND...................................-0.3V to (AVDD + 0.3V) CLK to GND .............................................-0.3V to (CVDD + 0.3V) OUT_P, OUT_N, FRAME_, CLKOUT_ to GND................................-0.3V to (OVDD + 0.3V) DT, SLVS/LVDS, LVDSTEST, PLL_, T/B, REFIO, REFADJ, CMOUT to GND .......-0.3V to (AVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 100-Pin TQFP 14mm x 14mm x 1mm (derated 47.6mW/°C above +70°C)........................3809.5mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1µF, CREFP to GND = 10µF, CREFN to GND = 10µF, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.4 ±2.5 LSB ±0.25 ±1 LSB DC ACCURACY (Note 2) Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL 12 No missing codes over temperature Bits Offset Error Gain Error -3 ±0.5 %FS +2 %FS ANALOG INPUTS (IN_P, IN_N) Input Differential Range Common-Mode Voltage Range VID Differential input VCMO Common-Mode Voltage Range Tolerance (Note 3) Differential Input Impedance RIN Differential Input Capacitance CIN Switched capacitor load 1.4 VP-P 0.76 V ±50 mV 2 kΩ 12.5 pF 4.0 MHz 6.5 Cycles CONVERSION RATE Maximum Conversion Rate fSMAX Minimum Conversion Rate fSMIN 50 Data Latency MHz DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 2) Signal-to-Noise Ratio SNR Signal-to-Noise and Distortion (First 4 Harmonics) SINAD Effective Number of Bits ENOB Spurious-Free Dynamic Range SFDR 2 fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS 69.9 66.5 fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS 69.7 69.9 66.5 69.7 fIN = 5.3MHz at -0.5dBFS 11.3 fIN = 19.3MHz at -0.5dBFS 11.3 fIN = 5.3MHz at -0.5dBFS 96 fIN = 19.3MHz at -0.5dBFS 79 94 _______________________________________________________________________________________ dB dB dB dBc Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1µF, CREFP to GND = 10µF, CREFN to GND = 10µF, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS fIN = 5.3MHz at -0.5dBFS -96 fIN = 19.3MHz at -0.5dBFS -90 IMD f1 = 5.3MHz at -6.5dBFS f2 = 6.3MHz at -6.5dBFS 90.7 dBc IM3 f1 = 5.3MHz at -6.5dBFS f2 = 6.3MHz at -6.5dBFS 98.7 dBc Aperture Jitter tAJ Figure 11 <0.4 psRMS Aperture Delay tAD Figure 11 1 ns 100 MHz Total Harmonic Distortion THD Intermodulation Distortion Third-Order Intermodulation -79 dBc Small-Signal Bandwidth SSBW Input at -20dBFS Full-Power Bandwidth LSBW Input at -0.5dBFS 100 MHz IN_P = IN_N 0.44 LSBRMS 1 Clock cycle Output Noise Over-Range Recovery Time tOR RS = 25Ω, CS = 50pF INTERNAL REFERENCE REFADJ Internal Reference-Mode Enable Voltage (Note 4) 0.1 REFADJ Low-Leakage Current REFIO Output Voltage Reference Temperature Coefficient 1.5 VREFIO 1.18 TCREFIO 1.24 V mA 1.30 120 V ppm/°C EXTERNAL REFERENCE REFADJ External ReferenceMode Enable Voltage (Note 4) AVDD 0.1V V REFADJ High-Leakage Current 200 REFIO Input Voltage 1.24 V ±5 % <1 µA 0.76 V REFIO Input Voltage Tolerance REFIO Input Current IREFIO µA COMMON-MODE OUTPUT (CMOUT) CMOUT Output Voltage VCMOUT CLOCK INPUT (CLK) Input High Voltage VCLKH Input Low Voltage VCLKL 0.8 x CVDD 0.2 x CVDD Clock Duty Cycle Clock Duty-Cycle Tolerance Input Leakage DIIN Input Capacitance DCIN V V 50 % ±30 % Input at GND 5 Input at AVDD 80 5 µA pF _______________________________________________________________________________________ 3 MAX1437 ELECTRICAL CHARACTERISTICS (continued) MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1µF, CREFP to GND = 10µF, CREFN to GND = 10µF, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, PD, T/B) Input High Threshold VIH Input Low Threshold VIL Input Leakage DIIN Input Capacitance DCIN 0.8 x AVDD V 0.2 x AVDD Input at GND 5 Input at AVDD 80 5 V µA pF LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0 Differential Output Voltage Output Common-Mode Voltage VOHDIFF RTERM = 100Ω 250 450 VOCM RTERM = 100Ω 1.125 1.375 mV V Rise Time (20% to 80%) tRL RTERM = 100Ω, CLOAD = 5pF 350 ps Fall Time (80% to 20%) tFL RTERM = 100Ω, CLOAD = 5pF 350 ps SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1 Differential Output Voltage Output Common-Mode Voltage VOHDIFF RTERM = 100Ω VOCM 205 mV RTERM = 100Ω 220 V Rise Time (20% to 80%) tRS RTERM = 100Ω, CLOAD = 5pF 320 ps Fall Time (80% to 20%) tFS RTERM = 100Ω, CLOAD = 5pF 320 ps (Note 5) 100 ms 20 ns POWER-DOWN PD Fall to Output Enable tENABLE PD Rise to Output Disable tDISABLE POWER REQUIREMENTS AVDD Supply Voltage Range AVDD 1.7 1.8 1.9 V OVDD Supply Voltage Range OVDD 1.7 1.8 1.9 V CVDD Supply Voltage Range CVDD 1.8 3.6 V 348 390 1.7 PD = 0 AVDD Supply Current IAVDD fIN = 19.3MHz PD = 0, DT = 1 at -0.5dBFS PD = 1, power-down, no clock input PD = 0 OVDD Supply Current IOVDD fIN = 19.3MHz PD = 0, DT = 1 at -0.5dBFS PD = 1, power-down, no clock input CVDD Supply Current ICVDD CVDD is used only to bias ESD-protection diodes on CLK input, Figure 2 Power Dissipation PDISS fIN = 19.3MHz at -0.5dBFS 4 348 1.16 79 mA mA 100 103 mA 960 µA 0 mA 769 _______________________________________________________________________________________ 882 mW Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, external VREFIO = 1.24V, CREFIO to GND = 0.1µF, CREFP to GND = 10µF, CREFN to GND = 10µF, fCLK = 50MHz (50% duty cycle), VDT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (Note 6) (tSAMPLE / 24) - 0.15 (tSAMPLE / 24) + 0.15 ns Data Valid to CLKOUT Rise/Fall tOD Figure 5 (Note 7) CLKOUT Output-Width High tCH Figure 5 tSAMPLE / 12 ns CLKOUT Output-Width Low tCL Figure 5 tSAMPLE / 12 ns FRAME Rise to CLKOUT Rise tCF Figure 4 (Note 7) (tSAMPLE / 24) - 0.15 (tSAMPLE / 24) + 0.15 ns Sample CLK Rise to FRAME Rise tSF Figure 4 (Note 7) (tSAMPLE / 2) + 1.1 (tSAMPLE / 2) + 2.6 ns Crosstalk (Note 2) -95 dB Gain Matching CGM fIN = 5.3MHz (Note 2) ±0.1 dB Phase Matching CPM fIN = 5.3MHz (Note 2) ±0.25 Degrees Note 1: Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization and not subject to production testing. Note 2: See definition in the Parameter Definition section at the end of this data sheet. Note 3: See the Common-Mode Output (CMOUT) section. Note 4: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal bandgap reference and enable external reference mode. Note 5: Measured using CREFP to GND = 1µF and CREFN to GND = 1µF. tENABLE time may be lowered by using smaller capacitor values. Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level. Note 7: Guaranteed by design and characterization. Not subject to production testing. Typical Operating Characteristics (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 HD2 -30 -40 -50 -60 -70 HD2 -80 HD3 -90 0 HD3 -20 -30 -40 -50 -60 -70 -80 -90 -90 -100 -100 -100 -110 -110 0 5 10 15 FREQUENCY (MHz) 20 25 MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 2 fIN(IN1) = 5.304814MHz fIN(IN2) = 24.0997118MHz CROSSTALK = 103dB -10 MAX1437 toc03 fCLK = 50.1523789MHz fIN = 24.0997118MHz AIN = -0.5dBFS SNR = 69.707dB SINAD = 69.672dB THD = -90.672dBc SFDR = 93.694dBc -20 CROSSTALK (16,384-POINT DATA RECORD) MAX1437 toc02 -20 0 -10 AMPLITUDE (dBFS) fCLK = 50.1523789MHz fIN = 5.304814MHz AIN = -0.5dBFS SNR = 69.959dB SINAD = 69.950dB THD = -96.635dBc SFDR = 96.503dBc MAX1437 toc01 0 -10 FFT PLOT (16,384-POINT DATA RECORD) AMPLITUDE (dBFS) FFT PLOT (16,384-POINT DATA RECORD) fIN(IN2) -110 0 5 10 15 FREQUENCY (MHz) 20 25 0 5 10 15 20 25 FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX1437 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) BANDWIDTH vs. ANALOG INPUT FREQUENCY -2 -3 -50 -60 -5 68 67 66 -6 -80 -7 65 -90 -8 64 -100 -9 63 -110 -10 62 5 10 15 FREQUENCY (MHz) 20 1 25 67 66 65 64 63 40 60 80 100 85 -75 -80 80 75 -85 70 -90 65 -95 60 55 0 20 40 60 80 100 120 0 20 40 60 80 100 fIN (MHz) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER 72 67 57 57 47 47 42 37 37 32 -20 -15 -10 ANALOG INPUT POWER (dBFS) -5 0 fIN = 5.304814MHz -65 -75 -80 -85 -90 -95 -100 32 -25 -60 -70 52 42 -55 THD (dBc) 62 SINAD (dB) 62 52 fIN = 5.304814MHz 120 MAX1437 toc12 fIN (MHz) fIN = 5.304814MHz 120 90 fIN (MHz) 67 -30 100 95 -70 120 80 100 MAX1437 toc11 72 20 MAX1437 toc10 0 60 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY -100 62 40 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY -65 THD (dBc) 68 20 fIN (MHz) -60 69 0 SFDR (dBc) 70 1000 MAX1437 toc08 71 100 10 ANALOG INPUT FREQUENCY (MHz) -55 MAX1437 toc07 72 SINAD (dB) 70 69 -4 SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY 6 71 -70 0 MAX1437 toc06 FULL-POWER BANDWIDTH -0.5dBFS 72 SNR (dB) -40 -1 GAIN (dB) AMPLITUDE (dBFS) -30 SMALL-SIGNAL BANDWIDTH -20.5dBFS 0 MAX1437 toc09 fIN(IN1) = 5.299375MHz fIN(IN2) = 6.299775MHz AIN1 = -6.5dBFS AIN2 = -6.5dBFS IMD = 90.7dBc IM3 = 98.7dBc -20 1 MAX1437 toc04 0 -10 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY MAX1437 toc05 TWO-TONE INTERMODULATION DISTORTION (16,384-POINT DATA RECORD) SNR (dB) MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs -105 -30 -25 -20 -15 -10 ANALOG INPUT POWER (dBFS) -5 0 -30 -25 -20 -15 -10 ANALOG INPUT POWER (dBFS) _______________________________________________________________________________________ -5 0 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 95 71 fIN = 5.304814MHz 72 70 71 69 85 68 68 75 SINAD (dB) 69 80 67 66 67 66 70 65 65 65 64 64 60 63 63 55 62 -25 -20 -15 -10 -5 0 62 10 15 20 25 30 35 40 45 50 15 10 20 25 30 35 40 ANALOG INPUT POWER (dBFS) fCLK (MHz) fCLK (MHz) TOTAL HARMONIC DISTORTION vs. SAMPLING RATE SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE SIGNAL-TO-NOISE RATIO vs. DUTY CYCLE 105 MAX1437 toc16 -75 fIN = 5.304814MHz -80 73 MAX1437 toc17 -30 fIN = 5.304814MHz 70 90 SNR (dB) SFDR (dBc) 72 MAX1437 toc15 fIN = 5.304814MHz SIGNAL-TO-NOISE PLUS DISTORTION vs. SAMPLING RATE fIN = 5.304814MHz 100 45 50 65 70 MAX1437 toc18 100 MAX1437 toc13 105 SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE MAX1437 toc14 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER fIN = 5.304814MHz 72 71 95 -90 70 SNR (dB) SFDR (dBc) THD (dBc) -85 90 -95 85 -100 80 69 68 67 66 -105 75 20 25 30 35 40 45 50 65 10 15 20 25 30 35 40 45 50 30 35 40 45 50 55 60 fCLK (MHz) DUTY CYCLE (%) SIGNAL-TO-NOISE PLUS DISTORTION vs. DUTY CYCLE TOTAL HARMONIC DISTORTION vs. DUTY CYCLE SPURIOUS-FREE DYNAMIC RANGE vs. DUTY CYCLE fIN = 5.304814MHz 72 -75 fIN = 5.304814MHz 100 -80 MAX1437 toc21 fCLK (MHz) MAX1437 toc20 73 15 MAX1437 toc19 10 fIN = 5.304814MHz 95 90 69 68 SFDR (dBc) -85 70 THD (dBc) SINAD (dB) 71 -90 85 -95 80 -100 75 67 66 65 70 -105 30 35 40 45 50 55 DUTY CYCLE (%) 60 65 70 30 35 40 45 50 55 DUTY CYCLE (%) 60 65 70 30 35 40 45 50 55 60 65 70 DUTY CYCLE (%) _______________________________________________________________________________________ 7 MAX1437 Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) fCLK = 50MHz fIN = 19.8MHz 4096-POINT DATA RECORD fCLK = 50MHz fIN = 19.8MHz 4096-POINT DATA RECORD 72 71 71 70 70 TOTAL HARMONIC DISTORTION vs. TEMPERATURE -90 MAX1437 toc24 72 73 MAX1437 toc22 73 SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE MAX1437 toc23 SIGNAL-TO-NOISE RATIO vs. TEMPERATURE -91 -92 69 68 69 68 67 67 66 66 65 -98 60 85 -100 -40 -15 10 35 60 85 -40 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE SUPPLY CURRENT vs. SAMPLING RATE (AVDD) SUPPLY CURRENT vs. SAMPLING RATE (0VDD) 360 350 85 85 MAX1437 toc27 fCLK = 50MHz fIN = 19.8MHz 4096-POINT DATA RECORD 80 340 75 90 89 88 IOVDD (mA) 330 91 IAVDD (mA) 320 310 70 65 300 87 60 290 86 85 280 -15 10 35 60 85 55 0 10 20 30 40 0 50 30 40 fCLK (MHz) OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.6 MAX1437 toc28 0.03 0.4 0.2 GAIN ERROR (%FS) 0.02 0.01 0 -0.01 -0.02 0.5 0.4 0.3 0 0.2 -0.2 0.1 -0.4 -0.6 0 -0.8 -0.2 -1.0 -0.3 -1.2 -0.4 -0.04 -1.4 10 35 TEMPERATURE (°C) 60 85 50 -0.1 -0.03 -15 20 fCLK (MHz) 0.04 -40 10 TEMPERATURE (°C) INL (LSB) -40 MAX1437 toc29 SFDR (dBc) -15 TEMPERATURE (°C) 92 8 fCLK = 50MHz fIN = 19.8MHz 4096-POINT DATA RECORD -99 MAX1437 toc30 93 35 -96 MAX1437 toc26 94 10 MAX1437 toc25 95 -15 -95 -97 65 -40 -94 THD (dBc) SINAD (dB) SNR (dB) -93 OFFSET ERROR (%FS) MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs -0.5 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE _______________________________________________________________________________________ Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 0.2 1.26 MAX1437 toc32 1.2510 MAX1437 toc31 0.3 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE AVDD = OVDD 1.2500 MAX1437 toc33 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE AVDD = OVDD 1.25 0 VREFIO (V) VREFIO (V) DNL (LSB) 0.1 1.2490 1.24 -0.1 1.2480 1.23 -0.2 1.2470 -0.3 1.8 1.9 2.0 2.1 -40 -15 10 35 SUPPLY VOLTAGE (V) TEMPERATURE (°C) INTERNAL REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT CMOUT VOLTAGE vs. SUPPLY VOLTAGE CMOUT VOLTAGE vs. TEMPERATURE 1.35 VCMOUT (V) 1.25 1.20 1.15 1.10 AVDD = OVDD 0.768 1.30 0.770 MAX1437 toc35 MAX1437 toc34 0.770 0.766 0.764 0.762 60 85 60 85 MAX1437 toc36 DIGITAL OUTPUT CODE 1.40 AVDD = OVDD 0.768 0.766 0.764 0.762 1.05 1.00 0.760 -150 -50 50 150 250 350 1.7 1.8 IREFIO (µA) 1.9 2.0 2.1 SUPPLY VOLTAGE (V) 0.760 -40 -15 10 35 TEMPERATURE (°C) CMOUT VOLTAGE vs. LOAD CURRENT 1.8 MAX1437 toc37 -350 -250 1.6 1.4 1.2 VCMOUT (V) VREFIO (V) 1.22 1.7 512 1024 1536 2048 2560 3072 3584 4096 VCMOUT (V) 0 1.0 0.8 0.6 0.4 0.2 0 0 500 1000 1500 2000 ICMOUT (µA) _______________________________________________________________________________________ 9 MAX1437 Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 50MHz (50% duty cycle), VDT = 0, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs Pin Description PIN NAME FUNCTION 1, 4, 7, 10, 16, 19, 22, 25, 26, 27, 30, 36, 89, 92, 96, 99, 100 GND Ground. Connect all GND pins to the same potential. 2 IN1P Channel 1 Positive Analog Input 3 IN1N Channel 1 Negative Analog Input 5 IN2P Channel 2 Positive Analog Input 6 IN2N Channel 2 Negative Analog Input 8 IN3P Channel 3 Positive Analog Input 9 IN3N Channel 3 Negative Analog Input 11, 12, 13, 15, 37–42, 86, 87, 88 AVDD Analog Power Input. Connect AVDD to a +1.7V to +1.9V power supply. Bypass AVDD to GND with a 0.1µF capacitor as close to the device as possible. Bypass the AVDD power plane to the GND plane with a bulk ≥2.2µF capacitor. Connect all AVDD pins to the same potential. 14, 31, 50, 51, 70, 75, 76 N.C. No Connection. Not internally connected. 17 IN4P Channel 4 Positive Analog Input 18 IN4N Channel 4 Negative Analog Input 20 IN5P Channel 5 Positive Analog Input 21 IN5N Channel 5 Negative Analog Input 23 IN6P Channel 6 Positive Analog Input 24 IN6N Channel 6 Negative Analog Input 28 IN7P Channel 7 Positive Analog Input 29 IN7N Channel 7 Negative Analog Input 32 DT Double-Termination Select. Drive DT high to select the internal 100Ω termination between the differential output pairs. Drive DT low to select no output termination. 33 SLVS/LVDS Differential Output-Signal Format-Select Input. Drive SLVS/LVDS high to select SLVS outputs. Drive SLVS/LVDS low to select LVDS outputs. 34 CVDD Clock Power Input. Connect CVDD to a +1.7V to +3.6V supply. Bypass CVDD to GND with a 0.1µF capacitor in parallel with a ≥2.2µF capacitor. Install the bypass capacitors as close to the device as possible. 35 CLK Single-Ended CMOS Clock Input Output-Driver Power Input. Connect OVDD to a +1.7V to +1.9V power supply. Bypass OVDD to GND with a 0.1µF capacitor as close to the device as possible. Bypass the OVDD power plane to the GND plane with a bulk ≥2.2µF capacitor. Connect all OVDD pins to the same potential. 43, 46, 49, 54, 57, 60, 63, 64, 67, 71, 74, 77 OVDD 44 OUT7N Channel 7 Negative LVDS/SLVS Output 45 OUT7P Channel 7 Positive LVDS/SLVS Output 47 OUT6N Channel 6 Negative LVDS/SLVS Output 48 OUT6P Channel 6 Positive LVDS/SLVS Output 52 OUT5N Channel 5 Negative LVDS/SLVS Output 53 OUT5P Channel 5 Positive LVDS/SLVS Output 55 OUT4N Channel 4 Negative LVDS/SLVS Output 56 OUT4P Channel 4 Positive LVDS/SLVS Output 10 ______________________________________________________________________________________ Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs PIN NAME FUNCTION 58 FRAMEN Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. 59 FRAMEP Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. 61 CLKOUTN Negative LVDS/SLVS Serial Clock Output 62 CLKOUTP Positive LVDS/SLVS Serial Clock Output 65 OUT3N Channel 3 Negative LVDS/SLVS Output 66 OUT3P Channel 3 Positive LVDS/SLVS Output 68 OUT2N Channel 2 Negative LVDS/SLVS Output 69 OUT2P Channel 2 Positive LVDS/SLVS Output 72 OUT1N Channel 1 Negative LVDS/SLVS Output 73 OUT1P Channel 1 Positive LVDS/SLVS Output 78 OUT0N Channel 0 Negative LVDS/SLVS Output 79 OUT0P Channel 0 Positive LVDS/SLVS Output 80 LVDSTEST LVDS Test Pattern Enable. Drive LVDSTEST high to enable the output test pattern (0000 1011 1101 MSB→ LSB). As with the analog conversion results, the test pattern data is output LSB first. Drive LVDSTEST low for normal operation. 81 PD Power-Down Input. Drive PD high to power down all channels and reference. Drive PD low for normal operation. 82 PLL3 PLL Control Input 3. See Table 1 for details. 83 PLL2 PLL Control Input 2. See Table 1 for details. 84 PLL1 PLL Control Input 1. See Table 1 for details. Output Format-Select Input. Drive T/B high to select binary output format. Drive T/B low to select two’s-complement output format. 85 T/B 90 REFN Negative Reference Bypass Output. Connect a ≥1µF (10µF typ) capacitor between REFP and REFN, and connect a ≥1µF (10µF typ) capacitor between REFN and GND. Place the capacitors as close to the device as possible on the same side of the printed circuit (PC) board. 91 REFP Positive Reference Bypass Output. Connect a ≥1µF (10µF typ) capacitor between REFP and REFN, and connect a ≥1µF (10µF typ) capacitor between REFP and GND. Place the capacitors as close to the device as possible on the same side of the PC board. 93 REFIO Reference Input/Output. For internal reference operation (REFADJ = GND), the reference output voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable reference voltage at REFIO. Bypass to GND with ≥0.1µF. 94 REFADJ Internal/External Reference-Mode-Select and Reference Adjust Input. For internal reference mode, connect REFADJ directly to GND. For external reference mode, connect REFADJ directly to AVDD. For reference-adjust mode, see the Full-Scale Range Adjustments Using the Internal Reference section. 95 CMOUT Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage for DC-coupled applications. Bypass CMOUT to GND with ≥0.1µF capacitor. 97 IN0P Channel 0 Positive Analog Input 98 IN0N Channel 0 Negative Analog Input — EP Exposed Paddle. EP is internally connected to GND. Connect EP to GND. ______________________________________________________________________________________ 11 MAX1437 Pin Description (continued) MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs Functional Diagram REFADJ REFIO REFP REFN PD REFERENCE SYSTEM POWER CONTROL CMOUT AVDD OVDD DT SLVS/LVDS OUTPUT CONTROL MAX1437 LVDSTEST T/B ICMV* T/H 12-BIT PIPELINE ADC 12:1 SERIALIZER OUT0P 12-BIT PIPELINE ADC 12:1 SERIALIZER OUT1P T/H IN0P IN0N IN1P IN1N OUT0N OUT1N LVDS/SLVS OUTPUT DRIVERS IN7P 12-BIT PIPELINE ADC T/H IN7N OUT7P 12:1 SERIALIZER OUT7N FRAMEP FRAMEN CLK CLOCK CIRCUITRY CVDD CLKOUTP PLL 6x PLL1 PLL2 CLKOUTN PLL3 GND *ICMV = INPUT COMMON-MODE VOLTAGE (INTERNALLY GENERATED). Detailed Description The MAX1437 ADC features fully differential inputs, a pipelined architecture, and digital error correction for high-speed signal conversion. The ADC pipeline architecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. The converted digital results are serialized and sent through the LVDS/SLVS output drivers. The total clock-cycle latency from input to output is 6.5 clock cycles. The MAX1437 offers eight separate fully differential channels with synchronized inputs and outputs. Configure the outputs for binary or two’s complement with the T/B digital input. Global power-down minimizes power consumption. 12 Input Circuit Figure 1 displays a simplified diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the operational transconductance amplifier (OTA), and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are ______________________________________________________________________________________ Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437 SWITCHES SHOWN IN TRACK MODE INTERNAL COMMON-MODE BIAS* AVDD INTERNALLY GENERATED COMMON-MODE LEVEL* INTERNAL BIAS* S5a S2a MAX1437 C1a S3a S4a C2a IN_P OUT S4c OTA S1 OUT IN_N S4b C2b C1b S3b GND S2b INTERNAL COMMON-MODE BIAS* INTERNAL BIAS* S5b INTERNALLY GENERATED COMMON-MODE LEVEL* *NOT EXTERNALLY ACCESSIBLE Figure 1. Internal Input Circuit then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. Analog inputs, IN_P to IN_N, are driven differentially. For differential inputs, balance the input impedance of IN_P and IN_N for optimum performance. Reference Configurations (REFIO, REFADJ, REFP, and REFN) The MAX1437 provides an internal 1.24V bandgap reference or can be driven with an external reference voltage. The full-scale analog differential input range is ±FSR. FSR (full-scale range) is given by the following equation: FSR = (0.700 × VREFIO ) 1.24V where VREFIO is the voltage at REFIO, generated internally or externally. For a VREFIO = 1.24V, the full-scale input range is ±700mV (1.4VP-P). Internal Reference Mode Connect REFADJ to GND to use the internal bandgap reference directly. The internal bandgap reference generates VREFIO to be 1.24V with a 120ppm/°C temperature coefficient in internal reference mode. Connect an external ≥0.1µF bypass capacitor from REFIO to GND for stability. REFIO sources up to 200µA and sinks up to 200µA for external circuits, and REFIO has a 75mV/mA load regulation. REFIO has >1MΩ to GND when the MAX1437 is in power-down mode. The internal reference circuit requires 100ms (CREFP to GND = CREFN to GND = 1µF) to power up and settle when power is applied to the MAX1437 or when PD transitions from high to low. To compensate for gain errors or to decrease or increase the ADC’s FSR, add an external resistor between REFADJ and GND or REFADJ and REFIO. This adjusts the internal reference value of the MAX1437 by up to ±5% of its nominal value. See the Full-Scale Range Adjustments Using the Internal Reference section. ______________________________________________________________________________________________________ 13 MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs Connect ≥1µF (10µF typ) capacitors to GND from REFP and REFN and a ≥1µF (10µF typ) capacitor between REFP and REFN as close to the device as possible on the same side of the PC board. Table 1. PLL1, PLL2, and PLL3 Configuration Table INPUT CLOCK RANGE (MHz) PLL1 PLL2 PLL3 MIN MAX 0 0 0 45.0 50.0 0 0 1 32.5 45.0 0 1 0 22.5 32.5 0 1 1 16.3 22.5 1 0 0 11.3 16.3 Clock Input (CLK) 1 0 1 8.1 11.3 The MAX1437 accepts a CMOS-compatible clock signal with a wide 20% to 80% input clock duty cycle. Drive CLK with an external single-ended clock signal. Figure 2 shows the simplified clock input diagram. 1 1 0 5.6 8.1 1 1 1 4.0 5.6 External Reference Mode The external reference mode allows for more control over the MAX1437 reference voltage and allows multiple converters to use a common reference. Connect REFADJ to AV DD to disable the internal reference. Apply a stable 1.18V to 1.30V source at REFIO. Bypass REFIO to GND with a ≥0.1µF capacitor. The REFIO input impedance is >1MΩ. Low clock jitter is required for the specified SNR performance of the MAX1437. Analog input sampling occurs on the rising edge of CLK, requiring this edge to provide the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: ⎛ ⎞ 1 SNR = 20 × log ⎜ ⎟ ⎝ 2 × π × fIN × t J ⎠ where fIN represents the analog input frequency and tJ is the total system clock jitter. PLL Inputs (PLL1, PLL2, PLL3) The MAX1437 features a PLL that generates an output clock signal with 6 times the frequency of the input clock. The output clock signal is used to clock data out of the MAX1437 (see the System Timing Requirements AVDD MAX1437 CVDD CLK GND Figure 2. Clock Input Circuitry 14 DUTY-CYCLE EQUALIZER section). Set the PLL1, PLL2, and PLL3 bits according to the input clock range provided in Table 1. System Timing Requirements Figure 3 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data output. The differential analog input (IN_P and IN_N) is sampled on the rising edge of the CLK signal and the resulting data appears at the digital outputs 6.5 clock cycles later. Figure 4 provides a detailed, two-conversion timing diagram of the relationship between the inputs and the outputs. Clock Output (CLKOUTP, CLKOUTN) The MAX1437 provides a differential clock output that consists of CLKOUTP and CLKOUTN. As shown in Figure 4, the serial output data is clocked out of the MAX1437 on both edges of the clock output. The frequency of the output clock is six times the frequency of CLK. Frame-Alignment Output (FRAMEP, FRAMEN) The MAX1437 provides a differential frame-alignment signal that consists of FRAMEP and FRAMEN. As shown in Figure 4, the rising edge of the frame-alignment signal corresponds to the first bit (D0) of the 12bit serial data stream. The frequency of the framealignment signal is identical to the frequency of the input clock. Serial Output Data (OUT_P, OUT_N) The MAX1437 provides its conversion results through individual differential outputs consisting of OUT_P and OUT_N. The results are valid 6.5 input clock cycles after the sample is taken. As shown in Figure 3, the output data is clocked out on both edges of the output clock, LSB (D0) first. Figure 5 provides the detailed serial-output timing diagram. ______________________________________________________________________________________ Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437 N+2 N+6 N+3 N (VIN_P VIN_N) N+8 N+5 N+1 N+9 N+7 N+4 tSAMPLE CLK 6.5 CLOCK-CYCLE DATA LATENCY (VFRAMEP VFRAMEN)* (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) OUTPUT DATA FOR SAMPLE N-6 OUTPUT DATA FOR SAMPLE N *DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY. Figure 3. Global Timing Diagram N+2 N (VIN_P - VIN_N) N+1 tSF tSAMPLE CLK (VFRAMEP VFRAMEN)* tCF (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) D5N-7 D6N-7 D7N-7 D8N-7 D9N-7 D10N-7 D11N-7 D0N-6 D1N-6 D2N-6 D3N-6 D4N-6 D5N-6 D6N-6 D7N-6 D8N-6 D9N-6 D10N-6 D11N-6 D0N-5 D1N-5 D2N-5 D3N-5 D4N-5 D5N-5 D6N-5 *DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY. Figure 4. Detailed Two-Conversion Timing Diagram tCH tCL (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) tOD D0 D1 tOD D2 D3 Figure 5. Serialized-Output Detailed Timing Diagram ______________________________________________________________________________________ 15 Table 2. Output Code Table (VREFIO = 1.24V) TWO’S-COMPLEMENT DIGITAL OUTPUT CODE (T/B = 0) OFFSET BINARY DIGITAL OUTPUT CODE (T/B = 1) HEXADECIMAL EQUIVALENT OF D11 → D0 DECIMAL EQUIVALENT OF D11 → D0 BINARY D11 → D0 0111 1111 1111 0x7FF +2047 1111 1111 1111 0xFFF +4095 +699.66 0111 1111 1110 0x7FE +2046 1111 1111 1110 0xFFE +4094 +699.32 0000 0000 0001 0x001 +1 1000 0000 0001 0x801 +2049 +0.34 0000 0000 0000 0x000 0 1000 0000 0000 0x800 +2048 0 1111 1111 1111 0xFFF -1 0111 1111 1111 0x7FF +2047 -0.34 1000 0000 0001 0x801 -2047 0000 0000 0001 0x001 +1 -699.66 1000 0000 0000 0x800 -2048 0000 0000 0000 0x000 0 -700.00 1 LSB = 2 x FSR 4096 HEXADECIMAL EQUIVALENT OF D11 → D0 VIN_P - VIN_N (mV) (VREFIO = 1.24V) BINARY D11 → D0 FSR = 700mV x VREFIO 1.24V FSR FSR 0x7FF 0x7FE 0x7FD 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) DECIMAL EQUIVALENT OF D11 → D0 1 LSB = 2 x FSR 4096 FSR = 700mV x VREFIO 1.24V FSR OFFSET BINARY OUTPUT CODE (LSB) TWO'S-COMPLEMENT OUTPUT CODE (LSB) MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs FSR 0xFFF 0xFFE 0xFFD 0x801 0x800 0x7FF 0x003 0x002 0x800 0x000 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 6. Two’s-Complement Transfer Function (T/B = 0) Figure 7. Binary Transfer Function (T/B = 1) Output Data Format (T/B) Transfer Functions The MAX1437 output data format is either offset binary or two’s complement, depending on the logic-input T/B. With T/B low, the output data format is two’s complement. With T/B high, the output data format is offset binary. The following equations, Table 2, and Figures 6 and 7 define the relationship between the digital output and the analog input. For two’s complement (T/B = 0): and for offset binary (T/B = 1): VIN _ P − VIN _ N = FSR × 2 × 16 CODE10 4096 VIN _ P − VIN _ N = FSR × 2 × CODE10 − 2048 4096 where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. Keep the capacitive load on the MAX1437 digital outputs as low as possible. ______________________________________________________________________________________ Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437 LVDS and SLVS Signals (SLVS/LVDS) Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high for SLVS levels at the MAX1437 outputs (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN). For SLVS levels, enable double-termination by driving DT high. See the Electrical Characteristics table for LVDS and SLVS output voltage levels. DT OUT_P/ CLKOUTP/ FRAMEP Z0 = 50Ω LVDS Test Pattern (LVDSTEST) Drive LVDSTEST high to enable the output test pattern on all LVDS or SLVS output channels. The output test pattern is 0000 1011 1101. Drive LVDSTEST low for normal operation (test pattern disabled). 100Ω 100Ω Common-Mode Output (CMOUT) CMOUT provides a common-mode reference for DCcoupled analog inputs. If the input is DC-coupled, match the output common-mode voltage of the circuit driving the MAX1437 to the output voltage at VCMOUT to within ±50mV. It is recommended that the output common-mode voltage of the driving circuit be derived from CMOUT. Double-Termination (DT) The MAX1437 offers an optional, internal 100Ω termination between the differential output pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN, FRAMEP and FRAMEN). In addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflections down the line. This feature is useful in applications where trace lengths are long (>5in) or with mismatched impedance. Drive DT high to select doubletermination, or drive DT low to disconnect the internal termination resistor (single-termination). Selecting double-termination increases the OVDD supply current (see Figure 8). Power-Down Mode (PD) The MAX1437 offers a power-down mode to efficiently use power by transitioning to a low-power state when conversions are not required. PD controls the power-down mode of all channels and the internal reference circuitry. Drive PD high to enable power-down. In power-down mode, the output impedance of all of the LVDS/SLVS outputs is approximately 342Ω, if DT is low. The output impedance of the differential LVDS/SLVS outputs is 100Ω when DT is high. See the Electrical Characteristics table for typical supply currents during power-down. The following list shows the state of the analog inputs and digital outputs in power-down mode: • • IN_P, IN_N analog inputs are disconnected from the internal input amplifier MAX1437 OUT_N/ CLKOUTN/ FRAMEN Z0 = 50Ω SWITCHES ARE CLOSED WHEN DT IS HIGH. SWITCHES ARE OPEN WHEN DT IS LOW. Figure 8. Double-Termination • OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN have approximately 342Ω between the output pairs when DT is low. When DT is high, the differential output pairs have 100Ω between each pair. When operating from the internal reference, the wakeup time from power-down is typically 100ms (CREFP to GND = CREFN to GND = 1µF). When using an external reference, the wake-up time is dependent on the external reference drivers. Applications Information Full-Scale Range Adjustments Using the Internal Reference The MAX1437 supports a full-scale adjustment range of 10% (±5%). To decrease the full-scale range, add a 25kΩ to 250kΩ external resistor or potentiometer (RADJ) between REFADJ and GND. To increase the full-scale range, add a 25kΩ to 250kΩ resistor between REFADJ and REFIO. Figure 9 shows the two possible configurations. The following equations provide the relationship between RADJ and the change in the analog full-scale range: ⎛ 1.25kΩ ⎞ FSR = 0.7V ⎜1 + RADJ ⎟⎠ ⎝ for RADJ connected between REFADJ and REFIO, and: REFIO has >1MΩ to GND ______________________________________________________________________________________________________ 17 MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 10Ω ADC FULL-SCALE = REFT - REFB REFT REFB 0.1µF G REFERENCESCALING AMPLIFIER IN_P 1 VIN 6 39pF T1 N.C. 2 5 MAX1437 0.1µF REFERENCE BUFFER REFIO 3 4 MINICIRCUITS ADT1-1WT 0.1µF 10Ω IN_N 1V REFADJ 25kΩ TO 250kΩ CONTROL LINE TO DISABLE REFERENCE BUFFER 39pF Figure 10. Transformer-Coupled Input Drive 25kΩ TO 250kΩ CVDD to GND with a 0.1µF ceramic capacitor in parallel with a ≥2.2µF ceramic capacitor. MAX1437 AVCC AVCC / 2 Figure 9. Circuit Suggestions to Adjust the ADC’s Full-Scale Range ⎛ 1.25kΩ ⎞ FSR = 0.7V ⎜1 − RADJ ⎟⎠ ⎝ for RADJ connected between REFADJ and GND. Using Transformer Coupling An RF transformer (Figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal. The MAX1437 input common-mode voltage is internally biased to 0.76V (typ) with f CLK = 50MHz. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. Grounding, Bypassing, and Board Layout The MAX1437 requires high-speed board layout design techniques. Refer to the MAX1434/MAX1436/MAX1437/ MAX1438 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass AV DD to GND with a 0.1µF ceramic capacitor in parallel with a 0.1µF ceramic capacitor. Bypass OVDD to GND with a 0.1µF ceramic capacitor in parallel with a ≥2.2µF ceramic capacitor. Bypass 18 Multilayer boards with ample ground and power planes produce the highest level of signal integrity. Connect MAX1437 ground pins and the exposed backside paddle to the same ground plane. The MAX1437 relies on the exposed-backside-paddle connection for a lowinductance ground connection. Isolate the ground plane from any noisy digital system ground planes. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1434/MAX1436/MAX1437/MAX1438 EV kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX1437, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1437, DNL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table. ______________________________________________________________________________________ Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs MAX1437 Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. For the MAX1437, the ideal midscale digital output transition occurs when there is 1/2 LSBs across the analog inputs (Figures 6 and 7). Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. CLK tAD ANALOG INPUT tAJ SAMPLED DATA Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1437, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. For the bipolar devices (MAX1437), the full-scale transition point is from 0x7FE to 0x7FF for two’s-complement output format (0xFFE to 0xFFF for offset binary) and the zero-scale transition point is from 0x800 to 0x801 for two’s complement (0x000 to 0x001 for offset binary). Crosstalk Crosstalk indicates how well each analog input is isolated from the others. For the MAX1437, a 5.3MHz, -0.5dBFS analog signal is applied to one channel while a 24.1MHz, -0.5dBFS analog signal is applied to another channel. An FFT is taken on the channel with the 5.3MHz analog signal. From this FFT, the crosstalk is measured as the difference in the 5.3MHz and 24.1MHz amplitudes. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. See Figure 11. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay. See Figure 11. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB x N x 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. T/H HOLD TRACK HOLD Figure 11. Aperture Jitter/Delay Specifications For the MAX1437, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ⎛ SINAD − 1.76 ⎞ ENOB = ⎜ ⎟ ⎝ ⎠ 6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: ⎛ V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 × log ⎜ ⎜ V1 ⎝ ⎞ ⎟ ⎟ ⎠ Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious ______________________________________________________________________________________ 19 MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). Intermodulation Distortion (IMD) IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -6.5dBFS. The intermodulation products are as follows: • 2nd-order intermodulation products (IM2): f1 + f2, f2 - f1 • 3rd-order intermodulation products (IM3): 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 • 4th-order intermodulation products (IM4): 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 • 5th-order intermodulation products (IM5): 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1 Third-Order Intermodulation (IM3) IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -6.5dBFS. The 3rd-order intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. Gain Matching Gain matching is a figure of merit that indicates how well the gain of all eight ADC channels is matched to each other. For the MAX1437, gain matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 50Msps and the maximum deviation in amplitude is reported in dB as gain matching in the Electrical Characteristics table. Phase Matching Phase matching is a figure of merit that indicates how well the phases of all eight ADC channels are matched to each other. For the MAX1437, phase matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 50Msps and the maximum deviation in phase is reported in degrees as phase matching in the Electrical Characteristics table. Small-Signal Bandwidth A small -20.5dBFS analog input signal is applied to an ADC so that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. 20 ______________________________________________________________________________________ Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs OUT0N OVDD PLL3 PD LVDSTEST OUT0P T/B PLL1 PLL2 AVDD AVDD GND AVDD REFADJ REFIO GND REFP REFN 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 N.C. GND IN0N IN0P GND CMOUT GND 100 TOP VIEW N.C. OVDD GND IN1P 1 75 2 74 IN1N GND IN2P IN2N 3 73 4 72 5 71 6 70 GND IN3P IN3N 7 69 8 68 N.C. OUT2P OUT2N 9 67 OVDD GND AVDD 10 66 11 65 AVDD AVDD 12 64 N.C. AVDD 14 OUT3P OUT3N OVDD OVDD CLKOUTP 15 61 GND IN4P 16 60 17 59 IN4N GND IN5P IN5N 18 58 19 57 20 56 21 55 GND IN6P IN6N 22 54 23 53 GND 25 13 63 MAX1437 24 62 52 EXPOSED PADDLE—CONNECTED TO GND 51 OUT1P OUT1N OVDD CLKOUTN OVDD FRAMEP FRAMEN OVDD OUT4P OUT4N OVDD OUT5P OUT5N N.C. 0VDD N.C. OUT6P OVDD OUT7N OUT7P OVDD OUT6N AVDD AVDD CVDD CLK GND AVDD AVDD AVDD AVDD SLVS/LVDS GND N.C. DT IN7N GND IN7P GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TQFP 14mm x 14mm x 1mm ______________________________________________________________________________________ 21 MAX1437 Pin Configuration Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) For the MAX1437 exposed paddle variation, the package code is C100E-2. 14x14x1.00L TQPF, EXP. PAD.EPS MAX1437 Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 22 ______________________________________________________________________________________ Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs For the MAX1437 exposed paddle variation, the package code is C100E-2. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX1437 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)