MAXIM MAX1448

19-5400; Rev 0; 9/00
KIT
ATION
EVALU
E
L
B
AVAILA
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
Lower speed, pin-compatible versions of the MAX1448
are also available. Please refer to the MAX1444 data
sheet for a 40Msps version and to the MAX1446 data
sheet for a 60Msps version.
The MAX1448 has parallel, offset binary, CMOS-compatible three-state outputs that can be operated from
+1.7V to +3.6V to allow flexible interfacing. The device
is available in a 5mm x 5mm 32-pin TQFP package and
is specified over the extended industrial (-40°C to
+85°C) temperature range.
________________________Applications
Features
♦ Single +3.0V Operation
♦ Excellent Dynamic Performance
59dB SNR at fIN = 20MHz
74dBc SFDR at fIN = 20MHz
♦ Low Power
40mA (Normal Operation)
5µA (Shutdown Mode)
♦ Fully Differential Analog Input
♦ Wide 2Vp-p Differential Input Voltage Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip +2.048V Precision Bandgap Reference
♦ CMOS-Compatible Three-State Outputs
♦ 32-Pin TQFP Package
Ordering Information
PART
MAX1448EHJ
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Functional Diagram
CLK
VDD
MAX1448
Ultrasound Imaging
GND
CONTROL
CCD Imaging
Baseband and IF Digitization
IN+
Digital Set-Top Boxes
IN-
T/H
PIPELINE ADC
D
E
C
10
OUTPUT
DRIVERS
Video Digitizing Applications
PD
REF
OVDD
REF SYSTEM +
BIAS
REFOUT REFIN REFP
COM REFN
D9–D0
OGND
OE
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX1448
General Description
The MAX1448 +3V, 10-bit analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10stage ADC architecture with wideband track-and-hold
(T/H), and digital error correction incorporating a fully
differential signal path. The ADC is optimized for lowpower, high dynamic performance in imaging and digital communications applications. The converter
operates from a single +2.7V to +3.6V supply, consuming only 120mW while delivering a 59dB (typ) signal-tonoise ratio (SNR) at a 20MHz input frequency. The fully
differential input stage has a -3dB 400MHz bandwidth
and may be operated with single-ended inputs. In addition to low operating power, the MAX1448 features a
5µA power-down mode for idle periods.
An internal +2.048V precision bandgap reference is
used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input voltage range.
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to VDD
REFIN, REFOUT, REFP,
REFN, and COM to GND..........................-0.3V to (VDD + 0.3V)
OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V)
D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFP (derate 11.1mW/°C above +70°C)...........889mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +3.0V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT
connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 15pF at digital outputs (Note 5),
fCLK = 83.3MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
INL
fIN = 7.47MHz
±0.7
±2.2
LSB
Differential Nonlinearity
DNL
fIN = 7.47MHz, no missing codes guaranteed
±0.4
±1.0
LSB
Offset Error
<±1
±1.7
%FS
Gain Error
0
±2
%FS
ANALOG INPUT
Input Differential Range
Common-Mode Voltage Range
VDIFF
Differential or single-ended inputs
VCOM
Input Resistance
RIN
Input Capacitance
CIN
Switched capacitor load
±1.0
V
VDD/2
± 0.5
V
25
kΩ
5
pF
5.5
Cycles
CONVERSION RATE
Maximum Clock Frequency
fCLK
80
Data Latency
MHz
DYNAMIC CHARACTERISTICS (fCLK = 83.3MHz, 4096-point FFT)
fIN = 7.47MHz
Signal-to-Noise Ratio
SNR
fIN = 20MHz
56.5
56
fIN = 39.9MHz (Note 1)
Signal-to-Noise Plus Distortion
(up to 5th harmonic)
SINAD
59
dB
58.5
fIN = 7.47MHz
55.8
59
fIN = 20MHz
55.3
58.8
fIN = 39.9MHz (Note 1)
2
59.1
58
_______________________________________________________________________________________
dB
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
(VDD = +3.0V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT
connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 15pF at digital outputs (Note 5),
fCLK = 83.3MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Spurious-Free Dynamic
Range
SYMBOL
SFDR
CONDITIONS
MIN
TYP
fIN = 7.47MHz
61
74
fIN = 20MHz
61
74
MAX
UNITS
dBc
fIN = 39.9MHz (Note 1)
73
fIN = 7.47MHz
74
fIN = 20MHz
74
fIN = 39.9MHz (Note 1)
73
IMDTT
f1 = 24MHz at -6.5dB FS, f2 = 26MHz at
-6.5dB FS (Note 2)
-74
dBc
Third-Order Intermodulation
Distortion
IM3
f1 = 24MHz at -6.5dB FS, f2 = 26MHz at
-6.5dB FS (Note 2)
-74
dBc
Total Harmonic Distortion
(first 5 harmonics)
THD
Third-Harmonic Distortion
Intermodulation Distortion
Two-Tone
HD3
Small-Signal Bandwidth
Full-Power Bandwidth
FPBW
Aperture Delay
tAD
Aperture Jitter
tAJ
dBc
fIN = 7.47MHz
-72
-60
fIN = 20MHz
-70
-60
fIN = 39.9MHz (Note 1)
-69
Input at -20dB FS, differential inputs
500
MHz
Input at -0.5dB FS, differential inputs
400
MHz
1
ns
dBc
2
psRMS
2
ns
±1
%
±0.25
degrees
0.2
LSBRMS
REFOUT
2.048
±1%
V
TCREF
60
ppm/°C
1.25
mV/mA
2.012
V
For 1.5 × full-scale input
Overdrive Recovery Time
Differential Gain
Differential Phase
Output Noise
IN+ = IN- = COM
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
EXTERNAL REFERENCE
Positive Reference
REFP
VREFIN = +2.048V
Negative Reference
REFN
VREFIN = +2.048V
Differential Reference Voltage
∆VREF
VREFP - VREFN, VREFIN = +2.048V
REFIN Resistance
RREFIN
0.988
0.98
1.024
>50
V
1.07
V
MΩ
DIGITAL INPUTS (CLK, PD, OE)
Input High Threshold
CLK
0.8 x
VDD
PD, OE
0.8 x
OVDD
VIH
V
_______________________________________________________________________________________
3
MAX1448
ELECTRICAL CHARACTERISTICS (continued)
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3.0V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT
connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 15pF at digital outputs (Note 5),
fCLK = 83.3MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.2 x
VDD
CLK
Input Low Threshold
VIL
Input Leakage
Input Capacitance
UNITS
V
0.2 x
OVDD
PD, OE
Input Hysteresis
MAX
VHYST
0.1
V
IIH
VIH = VDD = OVDD
±5
IIL
VIL = 0
±5
CIN
5
µA
pF
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
VOL
ISINK = 200µA
Output Voltage High
VOH
ISOURCE = 200µA
Three-State Leakage Current
ILEAK
OE = OVDD
Three-State Output Capacitance
COUT
OE = OVDD
0.2
OVDD 0.2
V
V
±10
5
µA
pF
POWER REQUIREMENTS
Analog Supply Voltage
VDD
2.7
3.0
3.6
Output Supply Voltage
OVDD
1.7
3.0
3.6
V
Operating, fIN = 20MHz at -0.5dB FS
40
47
mA
Shutdown, clock idle, PD = OE = OVDD
4
15
µA
Operating, CL = 15pF, fIN = 20MHz at
-0.5dB FS
8
Analog Supply Current
Output Supply Current
IVDD
IOVDD
Shutdown, clock idle, PD = OE = OVDD
Power-Supply Rejection
PSRR
1
V
mA
10
µA
Offset
±0.2
mV/V
Gain
±0.1
%/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Figure 6 (Note 3)
5
OE Fall to Output Enable
tENABLE
tDO
Figure 5
10
OE Rise to Output Disable
tDISABLE
Figure 5
8
ns
ns
15
ns
CLK Pulse Width High
tCH
Figure 6, clock period 12ns
6±1
ns
CLK Pulse Width Low
tCL
Figure 6, clock period 12ns
6±1
ns
(Note 4)
1.5
µs
Wake-Up Time
tWAKE
Note 1: SNR, SINAD, THD, SFDR and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3: Digital outputs settle to VIH,VIL.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
4
_______________________________________________________________________________________
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
-20
AMPLITUDE (dB)
-40
2ND HARMONIC
-60
3RD HARMONIC
2ND HARMONIC
-50
3RD HARMONIC
-60
-30
-40
-50
-80
-80
-80
-90
-90
-90
-100
-100
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
0
45
25
30
35
40
3RD HARMONIC
-70
-40
2ND HARMONIC
3RD HARMONIC
-60
-30
-40
-50
-60
-70
-70
-80
-80
-80
-90
-90
-90
-100
-100
5
10
15
20
25
30
35
40
45
f1 = 24MHz AT -6.5dB FS
f2 = 26MHz AT -6.5dB FS
3RD IMD = -74dBc
-20
-30
-50
0
-10
AMPLITUDE (dB)
AMPLITUDE (dB)
2ND HARMONIC
-60
SFDR = 67.2dBc
SNR = 58.6dB
THD = -66.5dBc
SINAD = 58dB
-10
-20
-40
-50
0
-100
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs.
ANALOG INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT FREQUENCY
59
SINGLE-ENDED
57
50
56
45
55
40
54
10
ANALOG INPUT FREQUENCY (MHz)
100
-60
DIFFERENTIAL
58
55
-55
THD (dBc)
65
SNR (dB)
60
45
MAX1448-09
61
70
-50
MAX1448-08
DIFFERENTIAL
62
MAX1448-07
80
45
MAX1448-06
TWO-TONE INTERMODULATION
(8192-POINT IMD,
DIFFERENTIAL INPUT)
-30
SFDR (dBc)
20
FFT PLOT
(fIN = 20MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
-20
1
15
FFT PLOT
(fIN = 7.5MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
-10
60
10
ANALOG INPUT FREQUENCY (MHz)
SFDR = 72.2dBc
SNR = 58.7dB
THD = -70.8dBc
SINAD = 58.4dB
75
5
ANALOG INPUT FREQUENCY (MHz)
0
0
3RD HARMONIC
ANALOG INPUT FREQUENCY (MHz)
MAX1448-04
0
2ND HARMONIC
-60
-70
-100
SFDR = 65.8dBc
SNR = 58dB
THD = -65.1dBc
SINAD = 57.2dB
-20
-70
-70
AMPLITUDE (dB)
-30
-40
0
-10
MAX1448-05
AMPLITUDE (dB)
-30
-50
SFDR = 75.2dBc
SNR = 59dB
THD = -71.8dBc
SINAD = 58.7dB
AMPLITUDE (dB)
-20
0
-10
MAX1448-02
SFDR = 75.5dBc
SNR = 59.3dB
THD = -73.9dBc
SINAD = 59.2dB
MAX1448-01
0
-10
UNDERSAMPLING FFT PLOT
(fIN = 50MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
FFT PLOT
(fIN = 20MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
MAX1448-03
FFT PLOT
(fIN = 7.5MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
SINGLE-ENDED
-65
SINGLE-ENDED
-70
DIFFERENTIAL
-75
-80
1
10
ANALOG INPUT FREQUENCY (MHz)
100
1
10
100
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
MAX1448
Typical Operating Characteristics
(VDD = +3.0V, OVDD = +2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +3.0V, OVDD = +2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.)
4
MAX1448-12
6
MAX1448-11
6
MAX1448-10
65
SMALL-SIGNAL INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY
(SINGLE-ENDED)
FULL-POWER INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY
(SINGLE-ENDED)
SIGNAL-TO-NOISE PLUS DISTORTION vs.
ANALOG INPUT FREQUENCY
VIN = 100mVp-p
4
62
2
DIFFERENTIAL
SINGLE-ENDED
56
AMPLITUDE (dB)
59
AMPLITUDE (dB)
SINAD (dB)
2
0
-2
0
-2
-4
-4
-6
-6
53
-8
-8
50
1
10
1
100
10
100
1
1000
1000
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (fIN = 20MHz)
SIGNAL-TO-NOISE RATIO
vs. INPUT POWER (fIN = 20MHz)
TOTAL HARMONIC DISTORTION
vs. INPUT POWER (fIN = 20MHz)
MAX1448-15
-50
MAX1448-14
MAX1448-13
65
-55
60
-60
65
THD (dBc)
SNR (dB)
70
55
-65
50
-70
60
45
55
50
-75
-80
40
-12
-9
-6
-3
0
-15
-12
-9
-6
-3
-12
-9
-6
-3
INPUT POWER (dB FS)
INPUT POWER (dB FS)
INPUT POWER (dB FS)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. INPUT POWER (fIN = 20MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
84
SFDR (dBc)
60
55
50
45
40
fIN = 20MHz
80
66
76
62
72
58
68
54
64
-12
-9
-6
INPUT POWER (dB FS)
-3
0
70
SNR (dB)
MAX1448-16
65
-15
-15
0
MAX1448-17
-15
0
MAX1448-18
SFDR (dBc)
100
ANALOG INPUT FREQUENCY (MHz)
75
6
10
ANALOG INPUT FREQUENCY (MHz)
80
SINAD (dB)
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
fIN = 20MHz
50
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
fIN = 20MHz
-64
fIN = 20MHz
0.8
MAX1448-21
70
MAX1448-19
-60
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
(BEST STRAIGHT LINE)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
MAX1448-20
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
0.6
66
-72
62
INL (LSB)
SINAD (dB)
THD (dBc)
0.4
-68
58
0.2
0
-0.2
-76
54
-0.4
-80
50
-15
10
35
60
85
-0.6
-40
-15
10
35
60
85
0
600
800
1000
1200
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE
EXTERNAL REFERENCE (VREFIN = +2.048V)
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (VREFIN = +2.048V)
0.04
3
2
GAIN ERROR (LSB)
0.1
0
-0.1
OFFSET ERROR (LSB)
0.03
0.2
0.02
0.01
0
-0.01
-0.02
-0.2
-0.03
-0.3
MAX1448-24
0.05
MAX1448-22
0.3
1
0
-1
-2
-0.04
-0.4
-3
-0.05
200
400
600
800
1000
1200
-40
-15
10
35
60
-15
10
35
60
DIGITAL OUTPUT CODE
TEMPERATURE (°C)
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
47
44
43
41
IVDD (mA)
45
41
38
2.85
3.00
3.15
VDD (V)
3.30
3.45
3.60
fIN = 7.5MHz
8
6
4
32
37
85
10
35
39
12
IOVDD (mA)
MAX1448-25
47
2.70
-40
85
MAX1448-26
0
MAX1448-27
DNL (LSB)
400
TEMPERATURE (°C)
0.4
IVDD (mA)
200
TEMPERATURE (°C)
MAX1448-23
-40
2
-40
-15
10
35
TEMPERATURE (°C)
60
85
1.6
2.0
2.4
2.8
3.2
3.6
OVDD (V)
_______________________________________________________________________________________
7
MAX1448
Typical Operating Characteristics (continued)
(VDD = +3.0V, OVDD = +2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +3.0V, OVDD = +2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.)
5
8
4
IVDD (µA)
10
6
3
4
2
OE = OVDD, PD = VDD
10
-40
-15
10
35
60
2.85
3.00
3.15
3.30
3.45
1.2
1.8
2.4
OVDD (V)
SFDR, SNR, THD, SINAD
vs. CLOCK FREQUENCY
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1448-32
2.10
MAX1448-31
fIN = 25.12MHz
80
2.08
75
SFDR
70
VREFOUT (V)
SFDR, SNR, THD, SINAD (dB)
3.60
VDD (V)
TEMPERATURE (°C)
85
4
0
2.70
85
6
2
1
2
PD = VDD, OE = OVDD
8
IOVDD (µA)
fIN = 7.5MHz
DIGITAL POWER-DOWN CURRENT
vs. DIGITAL POWER SUPPLY
MAX1448-29
6
MAX1448-28
12
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
MAX1448-30
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
IOVDD (mA)
THD
65
2.06
2.04
SNR
60
SINAD
2.02
55
50
2.00
75
80
85
90
95
2.70
100
2.85
3.00
CLOCK FREQUENCY (MHz)
3.15
3.30
3.45
3.60
VDD (V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OUTPUT NOISE HISTOGRAM (DC INPUT)
140000
MAX1448-33
2.10
MAX1448-34
70
129377
120000
2.08
100000
2.06
COUNTS
VREFOUT (V)
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
2.04
80000
60000
40000
2.02
20000
2.00
0
-40
-15
10
35
TEMPERATURE (°C)
8
60
85
0
965
N-2
N-1
N
730
0
N+1
N+2
DIGITAL OUTPUT NOISE
_______________________________________________________________________________________
3.0
3.6
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
PIN
NAME
FUNCTION
1
REFN
2
COM
Common-Mode Voltage Output. Bypass to GND with a >0.1µF capacitor.
3, 9, 10
VDD
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with
0.1µF.
4, 5, 8, 11,
14, 30
GND
Analog Ground
6
IN+
Positive Analog Input. For single-ended operation, connect signal source to IN+.
7
IN-
Negative Analog Input. For single-ended operation, connect IN- to COM.
12
CLK
13
PD
Power-Down Input
High: power-down mode
Low: normal operation
15
OE
Output Enable Input
High: digital outputs disabled
Low: digital outputs enabled
16–20
D9–D5
Three-State Digital Outputs D9–D5. D9 is the MSB.
21
OVDD
Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in
parallel with 0.1µF.
22
T.P.
23
OGND
Output Driver Ground
24–28
D4–D0
Three-State Digital Outputs D4–D0. D0 is the LSB.
29
REFOUT
31
REFIN
Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a >0.1µF capacitor.
32
REFP
Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF
capacitor.
Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF
capacitor.
Conversion Clock Input
Test Point. Do not connect.
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.
_______________________________________________________________________________________
9
MAX1448
Pin Description
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
_______________Detailed Description
The MAX1448 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half clock-cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC
comparator offsets in each pipeline stage and ensures
no missing codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b) through S4a and S4b. S2a and S2b set the
common mode for the amplifier input and open simulta-
neously with S1, sampling the input waveform. S4a and
S4b are then opened before S3a and S3b connect
capacitors C1a and C1b to the amplifier output, and
S4c is closed. The resulting differential voltage is held
on C2a and C2b. The amplifier is used to charge C1a
and C1b to the same values originally held on C2a and
C2b. This value is then presented to the first-stage
quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier
allows the MAX1448 to track and sample/hold analog
inputs of high frequencies beyond Nyquist. Analog
inputs (IN+ and IN-) can be driven either differentially
or single-ended. It is recommended to match the
impedance of IN+ and IN- and set the common-mode
voltage to midsupply (VDD/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1448 full-scale range is determined by the
internally generated voltage difference between REFP
(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered, low-impedance outputs.
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
MDAC
VIN
Σ
T/H
x2
VOUT
S4a
IN+
FLASH
ADC
OUT
C2a
DAC
S4c
S1
1.5 BITS
OUT
INS4b
C2b
C1b
VIN
STAGE 1
STAGE 2
S3b
STAGE 10
S2b
INTERNAL
BIAS
DIGITAL CORRECTION LOGIC
10
D9–D0
VIN = INPUT VOLTAGE BETWEEN
IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED)
Figure 1. Pipelined Architecture—Stage Blocks
10
TRACK
CLK
TRACK
HOLD
HOLD
INTERNAL
NON-OVERLAPPING
CLOCK SIGNALS
Figure 2. Internal Track-and-Hold Circuit
______________________________________________________________________________________
S5b
COM
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a
resistor (e.g., 10kΩ) or resistor-divider if an application
requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a
>10nF capacitor to GND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a >10kΩ resistor.
In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip
buffers of REFP, COM, and REFN. With their buffers
shut down, these pins become high impedance and
can be driven by external reference sources.
Clock Input (CLK)
The MAX1448 CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR performance of the ADC as follows:
SNR = 20log (1 / 2πfINtAJ)
where fIN represents the analog input frequency, and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any analog input or other digital signal lines.
The MAX1448 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR),
signal-to-noise ratio (SNR), total harmonic distortion
(THD), or signal-to-noise plus distortion (SINAD) versus
duty cycle.
Output Enable (OE), Power Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS-logic compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD high, the digital outputs
enter a high-impedance state. If OE is held low with PD
high, the outputs are latched at the last value prior to
the power down.
The capacitive load on the digital outputs D0–D9
should be kept as low as possible (<15pF) to avoid
large digital currents that could feed back into the analog portion of the MAX1448, degrading its dynamic performance. Using buffers on the ADC’s digital outputs
can further isolate the digital outputs from heavy
capacitive loads. To further improve the MAX1448’s
dynamic performance, small series resistors (e.g.,
100Ω) may be added to the digital output paths, close
to the ADC.
Figure 5 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid.
System Timing Requirements
Figure 6 shows the relationship between the clock
input, analog input, and data output. The MAX1448
samples at the falling edge of the input clock. Output
Table 1. MAX1448 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE*
DIFFERENTIAL INPUT
STRAIGHT OFFSET BINARY
VREF × 511/512
VREF × 510/512
VREF × 1/512
0
- VREF × 1/512
- VREF × 511/512
- VREF × 512/512
+Full Scale -1LSB
+Full Scale -2LSB
+1LSB
Bipolar Zero
-1LSB
Negative Full Scale + 1LSB
Negative Full Scale
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
*VREF = VREFP = VREFN
______________________________________________________________________________________
11
MAX1448
The MAX1448 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
100
-50
fIN = 25.12MHz AT -0.5dB FS
fIN = 25.12MHz AT -0.5dB FS
-55
90
THD (dBc)
SFDR (dBc)
-60
80
70
-65
-70
-75
60
-80
50
-85
20
30
40
50
60
70
20
30
CLOCK DUTY CYCLE (%)
Figure 3a. Spurious Free Dynamic Range vs. Clock Duty
Cycle (Differential Input)
50
60
70
Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle
(Differential Input)
64
fIN = 25.12MHz AT -0.5dB FS
62
62
60
60
SINAD (dB)
SNR (dB)
64
40
CLOCK DUTY CYCLE (%)
58
fIN = 25.12MHz AT -0.5dB FS
58
56
56
54
54
52
52
20
30
40
50
60
70
CLOCK DUTY CYCLE (%)
20
30
40
50
60
70
CLOCK DUTY CYCLE (%)
Figure 3b. Signal-to-Noise Ratio vs. Clock Duty Cycle
(Differential Input)
Figure 4b. Signal-to-Noise Plus Distortion vs. Clock Duty Cycle
(Differential Input)
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
age follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the
RISO and CIN values to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF
CIN capacitor acts as a small bypassing capacitor.
Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting
purposes. The input is buffered and then split to a volt-
12
______________________________________________________________________________________
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
Grounding, Bypassing,
and Board Layout
The MAX1448 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes produce the highest level of signal integrity. Consider
In general, the MAX1448 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
OE
tDISABLE
tENABLE
OUTPUT
DATA D9–D0
HIGH-Z
VALID DATA
HIGH-Z
Figure 5. Output Enable Timing
5.5 CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
ANALOG INPUT
CLOCK INPUT
tD0
DATA OUTPUT
tCH
N-6
N-5
N-4
tCL
N-3
N-2
N-1
N
N+1
Figure 6. System and Output Timing Diagram
______________________________________________________________________________________
13
MAX1448
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1448 for
optimum performance. Connecting the transformer’s
center tap to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the overall distortion.
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
+5V
0.1µF
LOWPASS FILTER
IN+
MAX4108
RISO
50Ω
0.1µF
300Ω
CIN
22pF
0.1µF
-5V
MAX1448
600Ω
300Ω
600Ω
COM
0.1µF
+5V
+5V
0.1µF
600Ω
INPUT
0.1µF
LOWPASS FILTER
MAX4108
300Ω
-5V
0.1µF
IN-
MAX4108
RISO
50Ω
300Ω
-5V
CIN
22pF
0.1µF
300Ω
300Ω
600Ω
Figure 7. Typical Application Circuit Using the Internal Reference
using a split ground plane arranged to match the physical location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC's package.
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
The two ground planes should be joined at a single
point so that the noisy digital ground currents do not
interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground
planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to
5Ω), a ferrite bead, or a direct short. Alternatively, all
ground pins could share the same ground plane if the
ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output
Static Parameter Definitions
14
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified. The
MAX1448’s static linearity parameters are measured
using the best straight-line fit method.
______________________________________________________________________________________
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
25Ω
IN+
22pF
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum A/D noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR(MAX) = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
MAX1448
0.1µF
VIN
1
N.C. 2
3
T1
6
5
COM
2.2µF
4
0.1µF
MINICIRCUITS
TT1–6
25Ω
IN22pF
Figure 8. Using a Transformer for AC Coupling
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental
and the DC offset.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
ENOB = (SINAD - 1.76dB) / 6.02dB
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
REFP
1k
VIN
0.1µF
RISO
IN+
MAX4108
100Ω
CIN
1k
MAX1448
COM
REFN
0.1µF
RISO
100Ω
RISO = 50Ω
CIN = 22pF
INCIN
Figure 9. Single-Ended AC-Coupled Input
______________________________________________________________________________________
15
MAX1448
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
CLK
ANALOG
INPUT
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale, and their envelope is at -0.5dB
full scale.
tAD
tAJ
SAMPLED
DATA (T/H)
___________________Chip Information
T/H
HOLD
TRACK
TRACK
TRANSISTOR COUNT: 5684
PROCESS: CMOS
Figure 10. Track-and-Hold Aperture Timing
Pin Configuration
REFP
REFIN
GND
REFOUT
D0
D1
D2
D3
29
28
27
26
25
REFN
1
24 D4
COM
2
23 OGND
VDD
3
22 T.P.
GND
4
21 OVDD
MAX1448
GND
5
IN+
6
19 D6
IN-
7
18 D7
GND
8
17 D8
9
10
11
12
13
14
15
16
PD
OE
D9
20 D5
GND
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
30
CLK
)
2
2
2
2
2 + V3 + V4 + V5 ) / V1
31
GND
( (V
32
VDD
THD = 20 × log
TOP VIEW
VDD
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the input
signal’s first five harmonics to the fundamental itself.
This is expressed as:
TQFP
16
______________________________________________________________________________________
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
32L,TQFP.EPS
E
______________________________________________________________________________________
17
MAX1448
Package Information
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
MAX1448
Package Information (continued)
E
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
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Printed USA
is a registered trademark of Maxim Integrated Products.