PI74ALVCH16600 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 18-Bit Universal Bus Transceiver with 3-State Outputs Product Features Product Description • • • • Pericom Semiconductors PI74ALVCH series of logic circuits are produced in the Companys advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • PI74ALVCH16600 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-State eliminating the need for external pullup resistors Industrial operation at 40°C to +85°C Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V) The PI74ALVCH16600 uses D-type latches and D-type flip-flops with 3-state outputs to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latched Enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. The clock can be controlled by the Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The PI74ALVCH16600 has Bus Hold which retains the data inputs last state whenever the data input goes to high-impedance preventing floating inputs and eliminating the need for pullup/ down resistors. Logic Block Diagram OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA A1 1 56 55 2 28 30 29 27 3 CE 1D CE 1D C1 CLK 54 B1 C1 CLK To 17 Other Channels 1 PS8157A 11/06/00 PI74ALVCH16600 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name CLKEN OE LE CLKAB Ax Bx GND VCC Truth Table(1) Description Clock Enable Input (Active LOW) Output Enable Input (Active LOW) Latch Enable (Active HIGH) Clock Input (Active LOW) Data I/O Data I/O Ground Power Inputs CLKENAB OEAB LEAB Product Pin Configuration OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 56 55 CLKENAB CLKAB 3 4 5 54 53 52 B1 6 7 8 51 56-PIN 50 V-56 49 B3 B2 VCC B4 B5 11 12 13 46 45 44 GND 14 15 16 43 42 41 17 18 40 39 B12 19 20 21 38 37 36 B13 B14 22 23 24 35 34 33 VCC 25 26 32 31 GND B18 27 28 30 29 CLKBA A-56 A X H X X X Z X L H X L L X L H X H H H L L X X BO H L L X X BO L L L ¯ L L L L L ¯ H H L L L H BO L or H Notes: 1. H = High Signal Level L = Low Signal Level Z = High Impedance ↓ = HIGH-to-LOW Transition A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Output level before the indicated steady-state input conditions were established. GND 48 47 9 10 CLKAB Outputs B B6 B7 B8 B9 B10 B11 GND B15 B16 B17 CLKENBA 2 PS8157A 11/06/00 PI74ALVCH16600 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......................................... 65°C to +150°C Ambient Temperature with Power Applied ........ 40°C to +85°C Input Voltage Range, VIN ................................ 0.5V to VCC +0.5V Output Voltage Range, VOUT ......................... 0.5V to VCC +0.5V DC Input Voltage ................................................. 0.5V to +5.0V DC Output Current ............................................................ 100mA Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Dissipation ................................................................ 1.0W Recommended Operating Conditions(1) Parame te rs De s cription Te s t Conditions M in. Typ. VCC Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage VIN Input Voltage 0 VCC VOUT Output Voltage 0 VCC IOH IOL TA High- level Output Current Low- level Output Current 2.3 M ax. VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2.0 3.6 VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 VCC = 2.3V - 12 VCC = 2.7V - 12 VCC = 3.0V - 24 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 Operating Free- Air Temperature - 40 Units 85 V mA °C Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 PS8157A 11/06/00 PI74ALVCH16600 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ±10%) Parame te rs VCC(1) M in. Min. to Max. VCC - 0.2 VIH = 1.7V 2.3V 2.0 VIH = 1.7V 2.3V 1.7 VIH = 2.0V 2.7V 2.2 VIH = 2.0V 3.0V 2.4 VIH = 2.0V 3.0V 2.0 Te s t Conditions IOH = 100µA IOH = 6mA VOH IOH = 12mA IOH = 24mA IOL = 100µA IOL = 6mA VOL IOL = 12mA IOL = 24mA II V Min. to Max. 0.2 VIL = 0.7V 2.3V 0.4 VIL = 0.7V 2.3V 0.7 VIL = 0.8V 2.7V 0.4 VIL = 0.8V 3.0V 0.55 3.6V ±5 VI = VCC or GND VI = 0.7V 2.3V VI = 1.7V II (Hold)(3) Typ.(2) M ax. Units VI = 0.8V 3.0V VI = 2.0V 45 - 45 75 - 75 µA VI = 0 to 3.6V 3.6V ±500 IOZ(4) VO = VCC or GND 3.6V ±10 ICC VI = VCC or GND 3.6V 40 ∆ICC One input at VCC - 0.6V, Other inputs at VCC or GND 3V to 3.6V 750 IO = 0 CI Control Inputs VI = VCC or GND 3.3V 4 pF CIO A or B ports VO = VCC or GND 3.3V 8 pF Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device typ e. 2. Typical values are at V CC = 3.3V, +25°C ambient and maximum loading. 3. Bus Hold maximum dynamic current required to switch the input from one state to another. 4. For I/O ports, the IOZ includes the input leakage current. 4 PS8157A 11/06/00 PI74ALVCH16600 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over Operating Range Parame te rs VCC = 2.5V ± 0.2V De s cription VCC = 2.7V VCC = 3.3V ± 0.3V M in. M ax. M in. M ax. M in. M ax. 0 150 0 150 0 150 fCLOCK Clock frequency tW Pulse Duration LE high 3.3 3.3 3.3 CLK high or low 3.3 3.3 3.3 Data before CLK 1.3 1.3 1.2 Data before LE¯ CLK high 1.2 1.1 1.1 Data before LE¯ CLK low 1.8 1.5 1.5 CLKEN before CLK 0.7 0.7 0.8 Data after CLK 1.5 1.8 1.5 Data after LE¯ CLK high 1.6 1.9 1.6 Data after LE¯ CLK low 1.2 1.6 1.3 CLKEN after CLK 1.4 1.7 1.4 tSU Setup time tH Hold time Dt/Dv(1) Input Transition Rise or Fall 0 10 0 10 Units MHz ns 0 10 ns/V Notes: 1. See test circuit and waveforms Switching Characteristics Over Operating Range(1) Parame te rs From (Input) To (Output) VCC = 2.5V ± 0.2V M in.(2) M ax. 150 fMAX tPD A or B tPD LEAB or LEBA tPD CLK AB or CLK BA tEN O EAB or O EBA tDIS O EAB or O EBA B or A A or B 1.0 VCC = 2.7V M in.(2) VCC = 3.3V ± 0.V M ax. M in.(2) 150 M ax. 150 Units MHz 5.1 4.7 1 4.0 5.9 5.5 1 4.8 7.3 6.8 1.3 5.7 6.5 6.3 1.1 5.2 5.1 4.7 1.2 4.4 ns Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA = 25ºC Parame te r CPD Power Dissipation Capacitance Te s t Conditions Outputs Enabled Outputs Disabled CL = 50pF f = 10 MHz VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical 43 56 6 6 Units pF Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8157A 11/06/00