ETC PI74ALVCHR16269A

PI74ALVCHR16269
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12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
Product Features
Product Description
· PI74ALVCHR16269 is designed for low voltage operation
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
· VCC = 2.3V to 3.6V
· Hysteresis on all inputs
· Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
· Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
· All output ports have equivalent 26W series resistors,
no external resistors are required
· Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
· Industrial operation at –40°C to +85°C
· Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
The PI7ALVCHR16269 is used in applications in which two separate
ports must be multiplexed onto, or demultiplexed from, a single port. It
is particularly suitable as an interface between synchronous DRAM’s
and high-speed microprocessors.
Data is stored on the internal B-port registers on the low-to-high
transition of the clock (CLK) input when the appropriate clock-enable
(CLKENA) inputs are low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit word on the B-port.
For data transfer in the B-to-A direction, a single storage register is
provided. The select (SEL) line selects 1B or 2B data for the A outputs.
The register on the A output permits the fastest possible data transfer,
thus extending the period during which the data is valid on the bus. The
control terminals are registered so that all transactions are synchronous
with CLK. Data flow is controlled by the active-low output enables
(OEA, OEB1, and OEB2).
To ensure the high-impedance state during power up or power down,
a clock pulse should be applied as soon as possible and OE should
be tied to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
Due to OE being routed through a register, the active state of the
outputs cannot be determined prior to the arrival of the first clock
pulse.
Logic Block Diagram
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
All outputs are designed to sink up to 12mA and include 26-ohm
resistors to reduce overshoot and undershoot.
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PS8372
12/17/99
PI74ALVCHR16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
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Product Pin Description
Pin Name
OE
CLK
SEL
CLKEN
A,1B,2B
GND
VCC
Truth Tables(1)
Description
Output Enable Input (Active LOW)
Clock
Select (Active Low)
Clock Enable (Active Low)
3-State Outputs
Ground
Power
Inputs
Product Pin Configuration
Outputs
CLK
OEA
OEB
A
1B,2B
↑
H
H
Z
Z
↑
H
L
Z
Active
↑
L
H
Active
Z
↑
L
L
Active
Active
A to B STORAGE (OEB = L)
INPUTS
OEA
OEB1
2B3
GND
2B2
1
2
56
55
OEB2
3
4
54
53
52
2B4
51
50
49
2B6
5
2B1
6
VCC
A1
7
8
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
NC
SEL
9
10
11
12
13
56-Pin 48
A, V 47
46
45
CLK ENA1 CLK ENA2
CLKENA2
GND
2B5
VCC
2B7
2B8
2B9
GND
2B10
44
2B11
14
15
16
43
42
2B12
41
17
18
40
39
1B11
1B10
19
20
21
38
37
36
1B9
22
23
24
35
34
33
VCC
1B6
25
26
32
31
GND
27
28
30
29
1B12
OUTPUTS
CLK
A
1B
2B
L
H
↑
L
L
2B0(2)
L
H
↑
H
H
2B0(2)
L
L
↑
L
L
L
L
L
↑
H
H
H
H
L
↑
L
1B0(2)
L
H
L
↑
H
1B0(2)
H
H
H
X
X
1B0(2)
2B0(2)
B to A STORAGE (OEA = L)
Inputs
CLK
SEL
1B
2B
Outputs
A
1B8
X
H
X
X
A0(2)
1B7
X
L
X
X
A0(2)
↑
H
L
X
L
↑
H
Η
X
H
1B4
↑
L
X
L
L
CLKENA1
↑
L
X
H
H
GND
1B5
CLK
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
↑ = Transition, Low to High
2. Output level before indicated steady state input conditions established
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PS8372
12/17/99
PI74ALVCHR16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................ –65°C to +150°C
Supply Voltage Range, VCC ................................................. –0.5V to 4.6V
Input Voltage Range,VI: Except
I/O ports(1) ................................................................................ –0.5V to 4.6V
I/O ports(1,2) ............................................................... –0.5V to VCC + 0.5V
Output Voltage Range, VO(1,2) .............................. –0.5V to VCC + 0.5V
Input Clamp current, IIK (VI < 0) ............................................ –50mA
Output Clamp current, IOK (VO < 0) ....................................... –50mA
Continous Output Current, IO .................................................. ±50mA
Continous Current through each VCC or GND ...................... ±100mA
Maximum Power Dissipation:
A package ........................................................................................ 1W
V package .....................................................................................1.4W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Notes:
1. The input and output negative-voltage ratings maybe exceeded if the input and
outputclamp-current ratings are observed.
2. This value is limited to 4.6V maximum.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs
VCC
D e s cription
Supply Voltage
Input HIGH Voltage
VIL(1)
Input LO W Voltage
VIN
M in.
2.3
VIH(1)
(1)
Te s t Conditions
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
Typ.
M ax.
3.6
VCC = 2.3V to 2.7V
0.7
VCC = 2.7V to 3.6V
0.8
Input Voltage
0
VCC
VOUT(1)
O utput Voltage
0
VCC
IOH(1)
HIGH- level
O utput Current
IOL(1)
LO W- level
O utput Current
Units
V
–6
–8
VCC = 3.0V
–12
VCC = 2.3V
6
VCC = 2.7V
8
VCC = 3.0V
12
TA
O perating Free- Air Temperature
At/DV
Input Transition Rise or Fall Rate
- 40
mA
85
ºC
10
ns/V
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
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PS8372
12/17/99
PI74ALVCHR16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
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DC Electrical Characteristics-Continued (Over the Operating Range, TA = -40ºC to +85ºC, VCC = 3.3V ± 10%
VCC(1)
M in.
Min. to Max.
VCC - 0.2
VIH = 1.7V
2.3V
1.9
VIH = 2.0V
2.7V
2.2
VIH = 1.7V
2.3V
1.7
VIH = 2.0V
3.0V
2.4
IOH = - 8mΑ
VIH = 2.0V
2.7V
2.0
IOH = - 12mΑ
VIH = 2.0V
3.0V
2.0
Parame te rs
Te s t Conditions
IOH = - 100µΑ
IOH = - 4mΑ
VOH
IOH = - 6mΑ
IOL= 100µΑ
II
0.2
VIL = 0.7V
2.3V
0.4
VIL = 0.8V
2.7V
0.4
VIL = 0.7V
2.3V
0.55
VIL = 0.8V
3.0V
0.55
IOL = 8mΑ
VIL = 0.8V
2.7V
0.6
IOL = 12mΑ
VIL = 0.8V
3.0V
0.8
3.6V
±5
IOL = 6mΑ
VI = VCC or GND
VI = 0.7V
2.3V
VI = 1.7V
II (Hold)(3)
VI = 0.8V
3.0V
VI = 2.0V
IOZ(4)
ICC
∆ΙCC
M ax.
Min. to Max.
IOL = 4mΑ
VOL
Typ.(2)
V
45
- 45
75
- 75
VI = 0 to 3.6V
3.6V
±500
VO = VCC or GND
3.6V
±10
VI = VCC or GND, IO = 0
3.6V
40
3V to 3.6V
750
O ne input at VCC - 0.6V, O ther
inputs at VCC or GND
Units
CI Control Inputs
VI = VCC or GND
3.3V
3.5
CIO A or B Ports
VO = VCC or GND
3.3V
8.5
µΑ
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25ºC ambient and maximum loading.
3. Bus hold maximum dynamic current required to switch the input from one state to another
4. For I/O ports, the IOZ includes the input leakage current.
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PS8372
12/17/99
PI74ALVCHR16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
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Timing Requirements over Operating Range
Parame te rs
D e s cription
VCC = 2.7V
VCC = 3.3V ±
0.3V
M in.
M in.
M in.
M ax.
Clock frequency
fCLOCK
tW
VCC = 2.5V ±
0.2V
95
Pulse duration, CLK
High or Low
tSU
tH
Setup time
Hold time
M ax.
M ax.
Units
135
MHz
115
5.2
4.3
3.3
A data before CLK↑
1.4
1.4
1
B data before CLK↑
1.6
1.5
1.1
SEL before CLK↑
0.8
1.1
1.3
CLK ENA1 or CLK ENA2
before CLK ↑
0.8
1
0.8
O E data before CLK ↑
1.7
1.6
1.2
A data after CLK↑
0.9
0.9
1.2
B data after CLK↑
0.8
0.6
1
SEL after CLK↑
1.1
0.8
1.7
CLK ENA1 or CLK ENA2
after CLK ↑
1.4
1
1.6
O E after CLK↑
0.9
0.8
1.2
ns
Switching Characteristics over Operating Range(1)
Parame te rs
From
(Input)
To
(Output)
M in.(2)
M ax.
95
fMAX
tPD
tEN
VCC = 2.5V ± 0.2V
CLK
tDIS
VCC = 2.7V
M in.(2)
VCC = 3.3V ± 0.3V
M in.(2)
M ax.
115
Units
M ax.
135
B
2.3
7.7
6.9
2.2
5.8
A
1.9
6.4
5.8
2
5.2
B
2.5
7.7
6.9
2.3
5.8
A
2.2
6.7
6
2.1
5.3
B
3.3
8.1
6.7
2.4
6
A
2.7
8
6.2
2.1
6
ns
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA = 25°C
Te s t
Conditions
Parame te r
CPD Power Dissipation Capacitance
per Exchanger
Outputs Enabled
Outputs Disabled
CL= 0pF,
F = 10 MHz
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Typical
Units
142
172
115
129
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8372
12/17/99