ETC PI74ALVCH16601V

PI74ALVCH16601
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18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Features
Product Description
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Pericom Semiconductor’s PI74ALVCH series of logic
circuits are produced using the Company’s advanced
0.5 micron CMOS technology, achieving industry
leading speed.
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PI74ALVCH16601 is designed for low voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
The PI74ALVCH16601 uses D-type latches and Dtype flip-flops with 3-state outputs to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by Output
Enable (OEAB and OEBA), Latched Enable (LEAB
and LEBA), and Clock (CLKAB and CLKBA) inputs.
The clock can be controlled by the Clock Enable
(CLKENAB and CLKENBA) inputs. For A-to-B data
flow, the device operates in the transparent mode when
LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a high or low logic level.
If LEAB is low, the A-bus is stored in the latch/flip-flop
on the low-to-high transition of CLKAB. When OEAB
is low, the outputs are active. When OEAB is HIGH, the
outputs are in the high-impedance state.
Logic Block Diagram
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA, and CLKENBA.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
The PI74ALVCH16601 has “Bus Hold” which retains
the data input’s last state whenever the data input goes
to high-impedance preventing “floating” inputs and
eliminating the need for pullup/down resistors.
1
PS8134A
02/23/98
PI74ALVCH16601
18-Bit
Universal
Bus Transceiver
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Product Pin Description
Pin Name
CLKEN
OE
LE
CLK
Ax
Bx
GND
VCC
Truth Table(1)†
Description
Clock Enable Input (Active LOW)
Output Enable Input (Active LOW)
Latch Enable (Active HIGH)
Clock Input (Active HIGH)
Data I/O
Data I/O
Ground
Power
Inputs
CLKENAB OEAB LEAB
Product Pin Configuration
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
1
2
56
55
CLKENAB
3
4
5
54
53
52
B1
6
7
8
51
50
49
B3
9
10
48
47
B5
B6
11
12
13
46
45
44
GND
GND
B2
17
18
40
39
B12
A13
38
37
36
B13
A15
19
20
21
VCC
A16
A17
22
23
24
35
34
33
GND
25
26
32
31
GND
27
28
30
29
CLKBA
CLKENBA
A18
OEBA
LEBA
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B0‡
H
L
L
X
X
B0‡
L
L
L
↑
L
L
L
L
L
↑
H
H
L
L
L
L
X
B0‡
L
L
L
H
X
B0§
B8
A12
GND
A14
X
B7
A11
V-56
Output B
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, CLKBA, and CLKENBA.
‡ Output level before the indicated steady-state input
conditions were established.
§ Output level before the indicated steady-state input
conditions were established, provided that CLKAB is
HIGH before LEAB goes LOW.
VCC
B4
B9
A10
A
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
CLKAB
14
43
15 56-PIN 42
A-56 41
16
A9
CLKAB
B10
B11
GND
B14
B15
VCC
B16
B17
B18
2
PS8134A
02/23/98
PI74ALVCH16601
18-Bit
Universal
Bus Transceiver
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Storage Temperature ........................................ –65°C to +150°C
Ambient Temperature with Power Applied ........ –10°C to +85°C
Input Voltage Range,VIN ............................. –0.5V to VCC + 0.5V
Output Voltage Range, VOUT ...................... –0.5V to VCC + 0.5V
DC Input Voltage ................................................ –0.5V to + 0.5V
DC Output Current .......................................................... 100mA
Power Dissipation ............................................................... 1.0W
Recommended Operating Conditions(1)
Parame te rs
De s cription
VCC
Supply Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIN
Input Voltage
0
VCC
VOUT
Output Voltage
0
VCC
IOH
IOL
TA
High- level Output Current
Low- level Output Current
Te s t Conditions
M in.
Typ.
2.3
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
M ax.
3.6
VCC = 2.3V to 2.7V
0.7
VCC = 2.7V to 3.6V
0.8
VCC = 2.3V
- 12
VCC = 2.7V
- 12
VCC = 3.0V
- 24
VCC = 2.3V
12
VCC = 2.7V
12
VCC = 3.0V
24
Operating Free- Air Temperature
- 40
Units
85
V
mA
°C
Note: Unused control inputs must be held HIGH or LOW to prevent them from floating.
3
PS8134A
02/23/98
PI74ALVCH16601
18-Bit
Universal
Bus Transceiver
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs
VCC(1)
M in.
Min. to
Max.
VCC - 0.2
VIH = 1.7V
2.3V
2.0
VIH = 1.7V
2.3V
1.7
VIH = 2.0V
2.7V
2.2
VIH = 2.0V
3.0V
2.4
VIH = 2.0V
3.0V
2.0
Min. to
Max.
VCC - 0.2
Te s t Conditions
IOH = - 100µA
IOH = - 6mA
VOH
IOH = - 12mA
IOH = - 24mA
IOH = - 100µA
VOL
IOH = 6mA
IOH = 12mA
IOH = 24mA
II
M ax.
0.2
2.3V
0.4
VIH = 0.7V
2.3V
0.7
VIH = 0.8V
2.7V
0.4
VIH = 0.8V
3.0V
0.55
3.6V
±5
VI = VCC or GND
2.3V
VI = 1.7V
VI = 0.8V
3.0V
VI = 2.0V
45
- 45
75
- 75
µA
VI = 0 to 3.6V
3.6V
±500
IOZ(4)
VO = VCCor GND
3.6V
±10
ICC
VI = VCC or GND
3.6V
40
∆ICC
One input at VCC - 0.6V, Other inputs at VCC or GND
3V to 3.6V
750
IO = 0
Units
V
VIH = 0.7V
VI = 0.7V
II (Hold)(3)
Typ.(2)
CI Control Inputs VI = VCC or GND
3.3V
4
CIO A or B ports VO = VCC or GND
3.3V
8
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. Bus Hold maximum dynamic current required to switch the input from one state to another.
4. For I/O ports, the IOZ includes the input leakage current.
4
PS8134A
02/23/98
PI74ALVCH16601
18-Bit
Universal
Bus Transceiver
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Timing Requirements over Operating Range
Parame te rs
D e s cription
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
M in.
M ax.
M in.
M ax.
M in.
M ax.
0
150
0
150
0
150
fCLOCK
Clock frequency
tW Pulse
Duration
LE high
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
Data before CLK high
2.3
2.4
2.1
Data before LE low, CLK high
2.0
1.6
1.6
Data before LE low, CLK low
1.3
1.2
1.1
CLK EN before CLK high
2.0
2.0
1.7
Data after CLK high
0.7
0.7
0.8
Data after LE low, CLK high
1.3
1.6
1.4
Data after LE low, CLK low
1.7
2.0
1.7
CLK EN after CLK high
0.3
0.5
0.6
tSUSetup
time
tH Hold
time
∆t/∆v(1)
Input Transition Rise or Fall
0
10
0
10
Units
MHz
ns
0
10
ns/V
Note: Unused control inputs must be held HIGH or LOW to prevent them from floating.
Switching Characteristics over Operating Range(1)
Parame te rs
From
(INPUT)
To
(OUTPUT)
fMAX
VCC = 2.5V ±0.2V
M in.(2)
M ax.
150
tPD
A or B
tPD
LEBA or
LEBA
tPD
CLKAB or
CLKBA
tEN
tDIS
B or A
VCC = 2.7V
M in.(2)
M ax.
150
VCC = 3.3 V ± 0.3V
M in.(2)
M ax.
150
MHz
1.3
4.9
4.6
1
4.1
1.2
5.6
5.3
1
4.7
1.7
6.2
5.8
1.4
5
OEAB or
OEBA
1.2
6.1
6.1
1.1
5.2
OEAB or
OEBA
2.1
5.4
4.8
1.6
4.4
A or B
Units
ns
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA = 25ºC
Parame te r
CPD Power Dissipation
Capacitance
Te s t Conditions
Outputs Enabled
Outputs Disabled
CL = 50pF,
f = 10 MHz
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Typical
41
52
6
6
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8134A
02/23/98