ETC UMC2NT1/D

UMC2NT1, UMC3NT1,
UMC5NT1
Preferred Devices
Dual Common
Base-Collector Bias
Resistor Transistors
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NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
3
1
R1
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base–emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the UMC2NT1 series, two
complementary BRT devices are housed in the SOT–353 package
which is ideal for low power surface mount applications where board
space is at a premium.
•
•
•
•
2
R2
Q2
R2
Q1
R1
4
5
MARKING
DIAGRAM
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch/3000 Unit Tape and Reel.
5
Ux
MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1
and Q2, – minus sign for Q1 (PNP) omitted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
IC
100
mAdc
Collector Current
SC–88A/SOT–323
CASE 419A
STYLE 6
1
2
3
Ux = Device Marking
x = 2, 3 or 5
ORDERING INFORMATION
THERMAL CHARACTERISTICS
RθJA
833
°C/W
TJ, Tstg
–65 to
+150
°C
PD
*150
mW
Thermal Resistance – Junction-to-Ambient
(surface mounted)
Operating and Storage Temperature
Range
4
Total Package Dissipation
@ TA = 25°C (Note 1.)
DEVICE MARKING AND RESISTOR VALUES
Transistor 1 – PNP
Transistor 2 – NPN
Device
Marking
R1 (K)
R2 (K)
R1 (K)
R2 (K)
UMC2NT1
UMC3NT1
UMC5NT1
U2
U3
U5
22
10
4.7
22
10
10
22
10
47
22
10
47
Device
Package
Shipping
UMC2NT1
SOT–323
3000/Tape & Reel
UMC3NT1
SOT–323
3000/Tape & Reel
UMC5NT1
SOT–323
3000/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
1. Device mounted on a FR-4 glass epoxy printed circuit board using the
minimum recommended footprint.
 Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 1
1
Publication Order Number:
UMC2NT1/D
UMC2NT1, UMC3NT1, UMC5NT1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Collector-Base Cutoff Current (VCB = 50 V, IE = 0)
ICBO
–
–
100
nAdc
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0)
ICEO
–
–
500
nAdc
Emitter-Base Cutoff Current
(VEB = 6.0, IC = 5.0 mA)
IEBO
–
–
–
–
–
–
0.2
0.5
1.0
mAdc
Collector-Base Breakdown Voltage (IC = 10 µA, IE = 0)
V(BR)CBO
50
–
–
Vdc
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0)
V(BR)CEO
50
–
–
Vdc
hFE
60
35
20
100
60
35
–
–
–
VCE(SAT)
–
–
0.25
Vdc
Output Voltage (on) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k)
VOL
–
–
0.2
Vdc
Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k)
VOH
4.9
–
–
Vdc
k
Q1 TRANSISTOR: PNP
OFF CHARACTERISTICS
UMC2NT1
UMC3NT1
UMC5NT1
ON CHARACTERISTICS
DC Current Gain
(VCE = 10 V, IC = 5.0 mA)
UMC2NT1
UMC3NT1
UMC5NT1
Collector–Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA)
Input Resistor
UMC2NT1
UMC3NT1
UMC5NT1
R1
15.4
7.0
3.3
22
10
4.7
28.6
13
6.1
Resistor Ratio
UMC2NT1
UMC3NT1
UMC5NT1
R1/R2
0.8
0.8
0.38
1.0
1.0
0.47
1.2
1.2
0.56
Collector-Base Cutoff Current (VCB = 50 V, IE = 0)
ICBO
–
–
100
nAdc
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0)
ICEO
–
–
500
nAdc
Emitter-Base Cutoff Current
(VEB = 6.0, IC = 5.0 mA)
IEBO
–
–
–
–
–
–
0.2
0.5
0.1
mAdc
Collector-Base Breakdown Voltage (IC = 10 µA, IE = 0)
V(BR)CBO
50
–
–
Vdc
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0)
V(BR)CEO
50
–
–
Vdc
hFE
60
35
80
100
60
140
–
–
–
Q2 TRANSISTOR: NPN
OFF CHARACTERISTICS
UMC2NT1
UMC3NT1
UMC5NT1
ON CHARACTERISTICS
DC Current Gain
(VCE = 10 V, IC = 5.0 mA)
UMC2NT1
UMC3NT1
UMC5NT1
Collector–Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA)
VCE(SAT)
–
–
0.25
Vdc
Output Voltage (on) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k)
VOL
–
–
0.2
Vdc
Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k)
VOH
4.9
–
–
Vdc
k
Input Resistor
UMC2NT1
UMC3NT1
UMC5NT1
R1
15.4
7.0
33
22
10
47
28.6
13
61
Resistor Ratio
UMC2NT1
UMC3NT1
UMC5NT1
R1/R2
0.8
0.8
0.8
1.0
1.0
1.0
1.2
1.2
1.2
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2
UMC2NT1, UMC3NT1, UMC5NT1
PD , POWER DISSIPATION (MILLIWATTS)
250
200
150
100
50
0
-50
RθJA = 833°C/W
0
50
100
TA, AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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3
150
UMC2NT1, UMC3NT1, UMC5NT1
1000
10
VCE = 10 V
IC/IB = 10
1
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — UMC2NT1 PNP TRANSISTOR
25°C
TA=-25°C
75°C
0.1
0.01
0
40
20
IC, COLLECTOR CURRENT (mA)
TA=75°C
100
10
50
10
1
Figure 3. DC Current Gain
100
IC, COLLECTOR CURRENT (mA)
3
2
1
10
20
30
40
VR, REVERSE BIAS VOLTAGE (VOLTS)
TA=-25°C
10
1
0.1
0.01
0.001
50
Figure 4. Output Capacitance
100
25°C
75°C
f = 1 MHz
lE = 0 mA
TA = 25°C
V in , INPUT VOLTAGE (VOLTS)
Cob , CAPACITANCE (pF)
4
0
VO = 5 V
0
1
2
3
4
5
6
7
Vin, INPUT VOLTAGE (VOLTS)
VO = 0.2 V
10
25°C
75°C
1
0
10
8
9
Figure 5. Output Current versus Input Voltage
TA=-25°C
0.1
100
IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) versus IC
0
25°C
-25°C
20
30
IC, COLLECTOR CURRENT (mA)
40
Figure 6. Input Voltage versus Output Current
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4
50
10
UMC2NT1, UMC3NT1, UMC5NT1
1
1000
IC/IB = 10
VCE = 10 V
TA=-25°C
25°C
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — UMC2NT1 NPN TRANSISTOR
0.1
75°C
0.01
0.001
0
20
40
IC, COLLECTOR CURRENT (mA)
TA=75°C
25°C
-25°C
100
10
50
1
10
IC, COLLECTOR CURRENT (mA)
Figure 7. VCE(sat) versus IC
Figure 8. DC Current Gain
100
IC, COLLECTOR CURRENT (mA)
2
1
0
0
10
20
30
40
VR, REVERSE BIAS VOLTAGE (VOLTS)
25°C
75°C
f = 1 MHz
IE = 0 mA
TA = 25°C
1
0.1
0.01
0.001
50
TA=-25°C
10
VO = 5 V
0
1
2
3
4
5
6
7
Vin, INPUT VOLTAGE (VOLTS)
10
VO = 0.2 V
TA=-25°C
25°C
75°C
1
0.1
0
10
8
9
10
Figure 10. Output Current versus Input Voltage
Figure 9. Output Capacitance
V in , INPUT VOLTAGE (VOLTS)
Cob , CAPACITANCE (pF)
4
3
100
20
30
IC, COLLECTOR CURRENT (mA)
40
Figure 11. Input Voltage versus Output
Current
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5
50
UMC2NT1, UMC3NT1, UMC5NT1
1000
1
TA=-25°C
0.1
25°C
75°C
0.01
0
20
25°C
100
10
-25°C
10
IC, COLLECTOR CURRENT (mA)
Figure 12. VCE(sat) versus IC
Figure 13. DC Current Gain
50
1
100
IC, COLLECTOR CURRENT (mA)
f = 1 MHz
lE = 0 mA
TA = 25°C
3
2
1
0
10
20
30
40
VR, REVERSE BIAS VOLTAGE (VOLTS)
TA=-25°C
10
1
0.1
0.01
0.001
50
100
VO = 5 V
0
1
2
3
4
5
6
7
Vin, INPUT VOLTAGE (VOLTS)
VO = 0.2 V
TA=-25°C
25°C
75°C
1
0
10
8
9
Figure 15. Output Current versus Input
Voltage
10
0.1
100
25°C
75°C
Figure 14. Output Capacitance
V in , INPUT VOLTAGE (VOLTS)
0
TA=75°C
IC, COLLECTOR CURRENT (mA)
40
4
Cob , CAPACITANCE (pF)
VCE = 10 V
IC/IB = 10
hFE , DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — UMC3NT1 PNP TRANSISTOR
20
30
IC, COLLECTOR CURRENT (mA)
40
Figure 16. Input Voltage versus Output
Current
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6
50
10
UMC2NT1, UMC3NT1, UMC5NT1
1000
1
25°C
TA=-25°C
0.1
75°C
0.01
0.001
0
20
TA=75°C
25°C
-25°C
100
10
50
40
1
100
10
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 17. VCE(sat) versus IC
Figure 18. DC Current Gain
4
100
3
IC, COLLECTOR CURRENT (mA)
f = 1 MHz
IE = 0 mA
TA = 25°C
2
1
75°C
25°C
TA=-25°C
10
1
0.1
0.01
VO = 5 V
0
0
0.001
50
10
20
30
40
VR, REVERSE BIAS VOLTAGE (VOLTS)
Figure 19. Output Capacitance
2
0
4
6
Vin, INPUT VOLTAGE (VOLTS)
VO = 0.2 V
TA=-25°C
10
25°C
75°C
1
0.1
0
10
8
10
Figure 20. Output Current versus Input Voltage
100
V in , INPUT VOLTAGE (VOLTS)
Cob , CAPACITANCE (pF)
VCE = 10 V
IC/IB = 10
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — UMC3NT1 NPN TRANSISTOR
20
30
40
IC, COLLECTOR CURRENT (mA)
Figure 21. Input Voltage versus Output
Current
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7
50
UMC2NT1, UMC3NT1, UMC5NT1
1000
1
VCE = 10 V
IC/IB = 10
TA=75°C
0.1
0.01
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — UMC5NT1 PNP TRANSISTOR
25°C
-25°C
0
10
20
30
50
40
100
1
60
1
10
100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 22. VCE(sat) versus IC
Figure 23. DC Current Gain
1000
100
IC, COLLECTOR CURRENT (mA)
f = 1 MHz
IE = 0 mA
TA = 25°C
10
Cob , CAPACITANCE (pF)
25°C
-25°C
10
12
8
6
4
SERIES 1
2
0
TA=75°C
0
5
10
20
30
15
25
35
VR, REVERSE BIAS VOLTAGE (VOLTS)
40
1
Figure 24. Output Capacitance
VO = 5 V
0.1
0.01
45
75°C
10
TA=-25°C
25°C
0
2
4
6
8
Vin, INPUT VOLTAGE (VOLTS)
10
12
Figure 25. Output Current versus Input Voltage
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8
UMC2NT1, UMC3NT1, UMC5NT1
10
1000
VCE = 10 V
IC/IB = 10
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — UMC5NT1 NPN TRANSISTOR
1
25°C
TA=-25°C
75°C
0.1
0.01
0
TA=75°C
25°C
-25°C
100
10
50
20
40
IC, COLLECTOR CURRENT (mA)
10
IC, COLLECTOR CURRENT (mA)
1
Figure 26. VCE(sat) versus IC
1
100
IC, COLLECTOR CURRENT (mA)
0.4
0.2
0
0
25°C
75°C
0.6
TA=-25°C
10
1
0.1
0.01
0.001
50
10
20
30
40
VR, REVERSE BIAS VOLTAGE (VOLTS)
VO = 5 V
0
2
4
6
Vin, INPUT VOLTAGE (VOLTS)
100
VO = 0.2 V
TA=-25°C
10
25°C
75°C
1
0.1
0
10
8
10
Figure 29. Output Current versus Input Voltage
Figure 28. Output Capacitance
V in , INPUT VOLTAGE (VOLTS)
Cob , CAPACITANCE (pF)
Figure 27. DC Current Gain
f = 1 MHz
IE = 0 mA
TA = 25°C
0.8
100
20
30
40
50
IC, COLLECTOR CURRENT (mA)
Figure 30. Input Voltage versus Output Current
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9
UMC2NT1, UMC3NT1, UMC5NT1
INFORMATION FOR USING THE SOT–353 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–353
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.65 mm 0.65 mm
0.4 mm (min)
0.5 mm (min)
1.9 mm
SOT–353 POWER DISSIPATION
one can calculate the power dissipation of the device which
The power dissipation of the SOT–353 is a function of
in this case is 150 milliwatts.
the pad size. This can vary from the minimum pad size for
soldering to the pad size given for maximum power
150°C – 25°C
PD =
= 150 milliwatts
dissipation. Power dissipation for a surface mount device is
833°C/W
determined by TJ(max), the maximum rated junction
The 833°C/W for the SOT–353 package assumes the use
temperature of the die, RθJA, the thermal resistance from
of the recommended footprint on a glass epoxy printed
the device junction to ambient; and the operating
circuit board to achieve a power dissipation of 150
temperature, TA. Using the values provided on the data
milliwatts. There are other alternatives to achieving higher
sheet, PD can be calculated as follows:
power dissipation from the SOT–353 package. Another
TJ(max) – TA
alternative would be to use a ceramic substrate or an
PD =
RθJA
aluminum core board such as Thermal Clad. Using a
The values for the equation are found in the maximum
board material such as Thermal Clad, an aluminum core
ratings table on the data sheet. Substituting these values
board, the power dissipation can be doubled using the same
into the equation for an ambient temperature TA of 25°C,
footprint.
SOLDERING PRECAUTIONS
• The soldering temperature and time should not exceed
The melting temperature of solder is higher than the rated
260°C for more than 10 seconds.
temperature of the device. When the entire device is heated
• When shifting from preheating to soldering, the
to a high temperature, failure to complete soldering within
maximum temperature gradient should be 5°C or less.
a short time could result in device failure. Therefore, the
• After soldering has been completed, the device should
following items should always be observed in order to
be allowed to cool naturally for at least three minutes.
minimize the thermal stress to which the devices are
Gradual cooling should be used as the use of forced
subjected.
cooling will increase the temperature gradient and
• Always preheat the device.
result in latent failure due to mechanical stress.
• The delta temperature between the preheat and
•
Mechanical stress or shock should not be applied
soldering should be 100°C or less.*
during cooling.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
* Soldering a device without preheating can cause
temperature ratings as shown on the data sheet. When
excessive thermal shock and stress which can result in
using infrared heating with the reflow soldering
damage to the device.
method, the difference should be a maximum of 10°C.
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10
UMC2NT1, UMC3NT1, UMC5NT1
SOLDER STENCIL GUIDELINES
or stainless steel with a typical thickness of 0.008 inches.
The stencil opening size for the surface mounted package
should be the same as the pad size on the printed circuit
board, i.e., a 1:1 registration.
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass
TYPICAL SOLDER HEATING PROFILE
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 31 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
RAMP"
200°C
150°C
STEP 2
STEP 3
VENT
HEATING
SOAK" ZONES 2 & 5
RAMP"
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
SPIKE"
SOAK"
205° TO 219°C
PEAK AT
SOLDER JOINT
170°C
160°C
150°C
140°C
100°C
100°C
50°C
STEP 6 STEP 7
VENT COOLING
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TMAX
TIME (3 TO 7 MINUTES TOTAL)
Figure 31. Typical Solder Heating Profile
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UMC2NT1, UMC3NT1, UMC5NT1
PACKAGE DIMENSIONS
SC–88A/SOT–323
5–LEAD PACKAGE
CASE 419A–01
ISSUE E
A
G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
5
DIM
A
B
C
D
G
H
J
K
N
S
V
4
–B–
S
1
2
3
D 5 PL
0.2 (0.008)
M
B
M
N
J
C
H
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
0.012
0.016
STYLE 6:
PIN 1.
2.
3.
4.
5.
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
0.30
0.40
EMITTER 2
BASE 2
EMITTER 1
COLLECTOR 1
BASE 1/COLLECTOR 2
K
Thermal Clad is a trademark of the Bergquist Company
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET)
Email: ONlit–[email protected]
French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET)
Email: ONlit–[email protected]
English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT)
Email: [email protected]
CENTRAL/SOUTH AMERICA:
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–[email protected]
Toll–Free from Mexico: Dial 01–800–288–2872 for Access –
then Dial 866–297–9322
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 1–303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
001–800–4422–3781
Email: ONlit–[email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy, UK, Ireland
For additional information, please contact your local
Sales Representative.
http://onsemi.com
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