LM1267 150 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs General Description The LM1267 pre-amp is an integrated CMOS CRT pre-amp. The IC is I2C compatible, and allows control of all the parameters necessary to directly setup and adjust the gain and contrast in the CRT display. Brightness and bias can be controlled through the DAC outputs, and is well matched to the LM2479 and LM2480 integrated bias clamp IC. The LM1267 pre-amp is designed to work in cooperation with the LM246X high gain driver family. Black level clamping of the signal is carried out directly on the AC coupled input signal into the high impedance preamplifier input, thus eliminating the need for additional black level clamp capacitors. The IC is packaged in an industry standard 24-lead DIP molded plastic package. n Programmable 110 MHz to 150 MHz bandwidth preamplifier with full video signal parametric control n 4 external 8-bit DACs for bus controlled Bias and Brightness n Suitable for use with discrete or integrated clamp, with software configurable Brightness mixer n Power Save (Green) Mode, 80% power reduction n Matched to LM246X driver Applications n Low end 15’ and 17’ bus controlled monitors with OSD n 1024 X 768 displays up to 85 Hz requiring OSD capability n Very low cost system with LM246X driver Features n I2C compatible interface Block and Connection Diagram DS200050-1 FIGURE 1. Order Number LM1267NA See NS Package Number N24D © 2002 National Semiconductor Corporation DS200050 www.national.com LM1267 150 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs May 2002 LM1267 Absolute Maximum Ratings (Notes 1, 3) Thermal Resistance to Case (θJC) Junction Temperature (TJ) ESD Susceptibility (Note 4) ESD Machine Model (Note 5) Storage Temperature Lead Temperature (Soldering, 10 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, Pin 9 Peak Video Output Source Current (Any One Amp) Pins 18, 19, or 20 Voltage at Any Input Pin (VIN) Power Dissipation (PD) (Above 25˚C Derate based on θJA and TJ) Thermal Resistance to Ambient (θJA) 6.0V 28 mA VCC +0.5 > VIN > −0.5V 32˚C/W 150˚C 3.5 kV 350V −65˚C to +150˚C 265˚C Operating Ratings (Note 2) Temperature Range Supply Voltage (VCC) Video Inputs 2.4W 51˚C/W 0˚C to 70˚C 4.75V < VCC < 5.25V 0.0V < VIN < 1.0VP-P Active Video Signal Electrical Characteristics Unless otherwise noted: TA = 25˚C, VCC = +5V, VIN = 0.7V, VABL = VCC, CL = 8 pF, Video Output = 2 VP-P. Symbol Parameter Conditions Min (Note 7) Typ (Note 6) Max (Note 7) Units IS Maximum Supply Current Test Setting 1, RL = ∞ (Note 8) 210 235 mA IS-PS Maximum Supply Current, Power Save Mode Test Setting 1, RL = ∞, Bit 1 of Reg. 9 = 1 (Note 8) 45 60 mA LE Linearity Error Test Setting 4, Triangular signal input source (Note 9) 5 VO Blk Typ Typical Video Black Level Output Test Setting 4, No AC Input Signal, DC = 5 Hex, or 0.5V Offset 1.05 1.25 1.45 VDC VO Blk Step Video Black Level Step Size Test Setting 4, No AC Input Signal 60 90 120 mV ∆VO/∆VCC Variation in Output Video Black Level vs VCC Variations Test Setting 1 & 3, No AC Input Signal, 4.75 < VCC < 5.25 −50 0 50 mV/V VO White-Max White Level Video Output Voltage Test Setting 3, Video in = 0.7V 4.0 4.2 0 0.2 VBlank Blanked Output Level Test Setting 4, AC Input Signal tr Rise Time 10% to 90%, Test Setting 4, AC Input Signal (Note 10) OSR Overshoot (Rising Edge) Test Setting 4, AC Input Signal (Note 10) tf Fall Time 90% to 10%, Test Setting 4, AC Input Signal (Note 10) OSF Overshoot (Falling Edge) Test Setting 4, AC Input Signal (Note 10) f(−3 dB) Video Amplifier Bandwidth (Note 13) Test Setting 8, Register 0Bh Bits 2-0 Set to 111, VO = 3.5 VP-P Vsep 10 kHz Video Amplifier 10 kHz Isolation Test Setting 8 (Note 14) Vsep 10 MHz Video Amplifier 10 MHz Isolation Test Setting 8 (Note 14) AV Max Maximum Voltage Gain AV Contrast @ 50% Level Maximum Contrast Attenuation % V 0.5 V 3.0 ns 8 % 3.0 ns 8 % 150 MHz −70 dB −50 dB Test Setting 8, AC Input Signal 4 V/V Test Setting 5, AC Input Signal −10 dB Test Setting 2, AC Input Signal −20 dB Gain @ 50% Level Test Setting 6, AC Input Signal −5 dB AV Gain Min Maximum Gain Attenuation Test Setting 7, AC Input Signal −10 dB AV Match Absolute Gain Match @ AV Test Setting 3, AC Input Signal ± 0.5 dB ⁄ 12 AV Min AV Gain ⁄ 12 www.national.com Max 2 LM1267 Active Video Signal Electrical Characteristics (Continued) Unless otherwise noted: TA = 25˚C, VCC = +5V, VIN = 0.7V, VABL = VCC, CL = 8 pF, Video Output = 2 VP-P. Symbol AV Track Parameter Conditions Min (Note 7) Typ (Note 6) Max (Note 7) Units Gain Change between Amplifiers Tracking when Changing from Test Setting 8 to Test Setting 5 (Note 11) ± 0.5 dB VABL TH ABL Control Upper Limit Test Setting 4, AC Input Signal (Note 12) 5 V VABL Range ABL Control Voltage Active Range Test Setting 4, AC Input Signal (Note 12) 2 V ∆AABL ABL Control Range Test Setting 4, AC Input Signal (Note 12) −8 dB IABL Active ABL Input Bias Current during ABL Test Setting 4, AC Input Signal, VABL = 2V(Note 12) 0 IABL Max ABL Input Current Clamp Sink Capability Test Setting 4, AC Input Signal (Note 12) VClamp Max Clamp Gate Low Input Voltage Clamp Comparators Off VClamp Min Clamp Gate High Input Voltage Clamp Comparators On 2.6 IClamp Clamp Gate Input Current V23 = 0V to VCC − 1V −5 tPW Clamp Back Porch Clamp Pulse Width (Note 15) 200 ns tClamp-Video End of Clamp Pulse to Start of Active Video Limit is guaranteed by design 200 nsec 10 µA 1 mA 1.4 V 10 µA V 0.1 RIn-Video Input Resistance Test Setting (4) 20 IIn-Video Input Bias Current Test Setting (4) 0.1 10 µA VRefOut VRef Output Voltage 10 kΩ, 1% Resistor; Pin 10 to GND 1.25 1.40 1.55 V VSpot Spot Killer Voltage VCC Adjusted to Activate 3.6 4.0 4.25 V MΩ OSD Electrical Characteristics Unless otherwise noted: TA = 25˚C, VCC = +5V, VIN = 0.7V, VABL = VCC, CL = 8 pF, Video Signal Output = 2 VP-P, Test Setting 8. Symbol Parameter Conditions VOSD-L OSD Input Low Input Operating Range OSD Inputs are Selected VOSD-H OSD Input High Input Operating Range OSD Inputs are Selected IOSD OSD Input Current VOSD = 0V to VCC − 1V VOSD-Sel-L OSD Select Low Input Operating Range Video Inputs are Selected VOSD-Sel-H OSD Select High Input Operating Range OSD Inputs are Selected IOSD-Sel OSD Select Input Current VOSD-Sel = 0V to VCC − 1V ∆VO-OSD(Blk) OSD ∆Black Level Output Voltage, Difference from Video Output Register 08 = 18, Minimum Video Black Level Range of OSD Black Level Output Voltage between the 3 Channels Register 08 = 18, Minimum Video Black Level OSD Output Voltage, Percent of Maximum Video Out VO-OSD(Blk) VOSD-out Min (Note 7) Typ (Note 6) Max (Note 7) Units 1.2 V 2.5 −5 V 0.1 10 µA 1.2 V 2.5 0.1 10 µA ± 45 ± 150 mV −100 0 +100 mV Register 08 = 18, Minimum Video Black Level 75 88 100 % 58 63 68 % ± 3.0 ± 5.0 % ∆VOSD-out OSD Output VP-P Attenuation Register 08 = 08 VOSD-out (Track) Output Variation between Channels Register 08 Changed from 18 to 08 3 −5 V www.national.com LM1267 OSD Electrical Characteristics (Continued) Unless otherwise noted: TA = 25˚C, VCC = +5V, VIN = 0.7V, VABL = VCC, CL = 8 pF, Video Signal Output = 2 VP-P, Test Setting 8. Symbol Parameter Conditions Min (Note 7) Typ (Note 6) Max (Note 7) Units ∆tOSD/OSD S Output Skew Time between OSD and OSD Select Measured from 50% Point on all Waveforms ± 2.0 ns Vfeed 10 kHz Video Feedthrough into OSD OSD Inputs = 0V −70 dB Vfeed 10 MHz Video Feedthrough into OSD OSD Inputs = 0V −60 dB External DAC Signals Electrical Characteristics Unless otherwise noted: TA = 25˚C, VCC = +5V, VIN = 0.7V, VABL = VCC, CL = 8 pF, Video Signal Output = 2 VP-P. The following apply for all four external DACs. Symbol Parameter Conditions Min (Note 7) Typ (Note 6) Max (Note 7) Units 0.5 0.75 V VMin DAC Min DAC Output Voltage Value = 00h VMax DAC Mode 00 Max DAC Output Voltage Value = FFh, DCF[1:0] = 00h (no load) 3.6 4.2 VMax DAC Mode 11 Max Output Voltage of DACs 1–3 in DCF Mode 11 Value = FFh, DCF[1:0] = 11h, DAC4 Value = 00h 1.85 2.1 ∆VMax DAC (Temp) Variation of any DAC output voltage with temperature 0˚C < T < 70˚C ambient ∆VMax DAC (VCC) Variation of any DAC output voltage with VCC 4.75V < VCC < 5.25V Linearity Linearity of DAC Over its Range Monotonicity Monotonicity of the DAC Excluding dead zones at limits of DAC V 2.35 V ± 0.5 mV/deg ± 50 mV/V 5 % ± 0.5 LSB External Interface Signals Electrical Characteristics Unless otherwise noted: TA = 25˚C, VCC = +5V, VIN = 0.7V, VABL = VCC, CL = 8 pF, Video Output = 2 VP-P. Symbol 2 Vl(I C) 2 Parameter Conditions Min (Note 7) Typ (Note 6) Max (Note 7) Units 2 SDA or SCL Inputs −0.5 0.5 1.5 V 2 I C Low Input Voltage Vh(I C) I C High Input Voltage SDA or SCL Inputs 3.0 4.0 5.0 V Il(I2C) I2C Low Input Current SDA or SCL Inputs, Input Voltage = 0V 1.9 2.2 2.5 µA Ih(I2C) I2C High Input Current SDA or SCL Inputs, Input Voltage = 5V 0.3 0.6 0.9 µA tH-Blank on H-Blank Time Delay from Zero Crossing Point of H Flyback Rising Edge of the Flyback Signal 50 ns tH-Blank off H-Blank Time Delay from Zero Crossing Point of H Flyback Falling Edge of the Flyback Signal 50 ns IIn Threshold IIn H-Blank Detection Threshold −20 µA IIn-Operating Minimum — Insure Normal Operation Maximum — Should Not Exceed in Normal Operation Lowest Operating Horizontal Frequency in Given Application (Note 17) Peak Current during Flyback Period, Recommended Design Range Operating Range for all Horizontal Scan Frequencies, Maximum Current Should Not Exceed 2 mA (Note 17) IIn Flyback −30 0.5 1.5 −300 µA 2.0 mA Note 1: Limits of Absolute Maximum Ratings indicate limits below which damage to the device must not occur. Note 2: Limits of operating ratings indicate required boundaries of conditions for which the device is functional, but may not meet specific performance limits. www.national.com 4 LM1267 External Interface Signals Electrical Characteristics (Continued) Note 3: All voltages are measured with respect to GND, unless otherwise specified. Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 5: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω). Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: The supply current specified is the quiescent current for VCC with RL = ∞. Load resistors are not required and are not used in the test circuit, therefore all the supply current is used by the pre-amp. Note 9: Linearity Error is the variation in step height of a 16 step staircase input signal waveform with 0.7 VP-P level at the input, subdivided into 16 equal steps, with each step approximately 100 ns in width. Note 10: Input from signal generator: tr, tf < 1 ns. Scope and generator response used for testing: tr = 1.1 ns, tf = 0.9 ns. Using the RSS technique the scope and generator response have been removed from the output rise and fall times. Note 11: ∆AV track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in gain change between any two amplifiers with the contrast set to AV 1⁄2 and measured relative to the AV max condition. For example, at AV max the three amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to AV 1⁄2. This yields a typical gain change of 10.0 dB with a tracking change of ± 0.2 dB. Note 12: ABL should provide smooth decrease in gain over the operational range of 0 dB to –6 dB ∆AABL = A(VABL = VABL Max Gain) − A(VABL = VABL Min Gain) Beyond –6 dB the gain characteristics, linearity, pulse response, and/or behavior may depart from normal values. Note 13: Adjust input frequency from 10 MHz (AV max reference level) to the −3 dB corner frequency (f−3 dB). Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at fIN = 10 MHz for Vsep 10 MHz. Note 15: A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer clamp pulse may be required. Note 16: The video black level is used for this test. OSD amplitude is measured from the video black level to the OSD white level. Note 17: Limits met by matching the external resistor going to pin 24 to the H Flyback voltage. Typical Performance Characteristics VCC = 5V, TA = 25˚ unless otherwise specified. Gain Attenuation Contrast Attenuation DS200050-2 ABL Attenuation DS200050-3 Output Waveform DS200050-5 DS200050-4 5 www.national.com LM1267 Typical Performance Characteristics VCC = 5V, TA = 25˚ unless otherwise specified. (Continued) Contrast vs Frequency, Bandwidth = 0 Contrast vs Frequency, Bandwidth = 7 DS200050-6 Gain vs Frequency, Bandwidth = 0 DS200050-7 Gain vs Frequency, Bandwidth = 7 DS200050-8 DS200050-9 Test Circuit DS200050-10 Note: 8 pF load includes parasitic capacitance. www.national.com 6 No. of Bits Basic Test Setting 1 Basic Test Setting 2 Basic Test Setting 3 Basic Test Setting 4 Basic Test Setting 5 Basic Test Setting 6 Basic Test Setting 7 Basic Test Setting 8 Contrast 7 Max (Hex 7F) Min (Hex 00) Max (Hex 7F) Max (Hex 7F) 50% (Hex 40) Max (Hex 7F) Max (Hex 7F) Max (Hex 7F) R, G, B Gain 7 Max (Hex 7F) Max (Hex 7F) Max (Hex 7F) Set Video Output to 2VP-P Max (Hex 7F) 50% (Hex 40) Min (Hex 00) Max (Hex 7F) Video DC Offset & OSD Contrast 5 Min (Hex 18) Min + 0.5V (Hex 1D) Max (Hex 07) Min + 0.5V (Hex 1D) Min + 0.5V (Hex 1D) Min + 0.5V (Hex 1D) Min + 0.5V (Hex 1D) Min + 0.5V (Hex 1D) Control Timing Diagrams DS200050-11 FIGURE 2. Blanking Propagation Delay 7 www.national.com LM1267 Test Settings LM1267 Timing Diagrams (Continued) DS200050-12 FIGURE 3. OSD Output Skew Pin Descriptions Pin No. Pin Name 1 2 3 Red OSD Input Green OSD Input Blue OSD Input These inputs accept standard TTL or CMOS inputs. Each color is either fully on (logic high) or fully off (logic low). Unused pins should be connected to ground with a 47k resistor. 4 OSD Select This input accepts a standard TTL or CMOS input. H = OSD L = Video Connect to ground with a 47k resistor if not using OSD. www.national.com Schematic Description 8 LM1267 Pin Descriptions (Continued) Pin No. Pin Name 5 6 7 Red Video In Green Video In Blue Video In Schematic Video inputs. These inputs must be AC coupled with a 4.7 nF cap. DC restoration is done at these inputs. A series resistor of about 33Ω and external ESD protection diodes should also be used for ESD protection. Description 8 Analog Ground Ground Pin for the analog circuits of the LM1267. 9 VCC Power supply pin for LM1267. 10 VrefRext Sets the internal current sources through a 10 kΩ 1% external resistor. Resistor value and accuracy is critical for optimum operation of the LM1267. 11 SDA The I2C data line. A pull-up resistor of about 2 kΩ should be connected between this pin and +5V. A 300Ω resistor should be connected in series with the data line for protection against arcing. 12 SCL The I2C Clock line. A pull-up resistor of about 2 kΩ should be connected between this pin and +5V. A 300Ω resistor should be connected in series with the clock line for protection against arcing. 13 14 15 16 DAC4 DAC3 DAC2 DAC1 DAC outputs for cathode cut-off adjustments and brightness control. DAC 4 can be set to change the outputs of the other three DACs, acting as the brightness control. The DACs are set through the I2C bus. 17 Digital Ground Ground Pin for the digital circuits of the LM1267. 9 www.national.com LM1267 Pin Descriptions (Continued) Pin No. Pin Name 18 19 20 Blue Video Out Green Video Out Red Video Out Video outputs of the LM1267. The ideal driver for this part is the LM246X CRT driver family, which has the necessary gain of 26 dB or 20 V/V. 21 VRef Out A 0.1 µF capacitor must be placed close to this pin for decoupling the internal VRef. This pin may be used for an external voltage reference with proper buffering. 22 ABL The Auto Beam Limit control reduces the gain of the video amplifier in response to a control voltage proportional to the CRT beam current. The ABL acts identically on all three channels. ABL is required for CRT life and X-ray protection. 23 Clamp Pulse This input accepts a standard TTL or CMOS input. The signal can be either positive or negative going. The polarity is set in register 0Bh bit-3. The signal activates the clamp pulse for DC restoration of the video input. The AC coupling capacitors at the video inputs are used for holding the DC correction voltage, eliminating the need for additional capacitors. 24 H Flyback H flyback is an analog signal input from the monitor horizontal scan. The LM1267 is able to generate an accurate blanking pulse in the video outputs from this input. The horizontal flyback from the monitor must be a clean signal, with no ringing or other noise on the signal. www.national.com Schematic Description 10 All functions of the LM1267 are controlled through the I2C Bus. Details on the internal registers are covered in the I2C Interface Registers Section. Figure 1 shows the block diagram of the LM1267. The I2C signals come in on pins 11 and 12 and go to the I2C Interface. Both the internal blocks with an “R” and the four external DACs are controlled by the I2C Interface. The video and OSD blocks are shown for the red channel in Figure 1. The blocks for both the green and blue channels are not shown; however, they are identical to the red channel. Proper operation of the LM1267 does require a very accurate reference voltage. This voltage is generated in the VRef block. To insure an accurate voltage over temperature, an external resistor is used to set the current in the VRef stage. The external resistor is connected to pin 10. This resistor should be 1% and have a temperature coefficient under 100 ppm/˚C. ALL VIDEO SIGNALS MUST BE KEPT AWAY FROM PIN 10. This pin has a very high input impedance and will pick up any high frequency signals routed near it. The board layout shown in Figure 10 is a good example of trace routing near pin 10. The output of the VRef stage goes to a number of blocks in the video section and also to pin 21. This pin allows capacitor filtering on the VRef output and offers an accurate external reference. A buffer must be used with this reference, the maximum current loading should be only 100 µA. Following the “OSD Mixer” is the “Gain” block. Each video channel has its own independent control of this block so the user can balance the color of the CRT display. Registers 00h, 01h, 02h are used for the gain attenuation. These registers are 7 bits with the maximum attenuation of −10 dB occurring when all zeros are loaded. The final block in the video path is the “Output Buffer Amp”. This stage provides the drive needed for the inputs of a CRT driver. The recommended driver for this pre-amp is one of the LM246X family. Horizontal blanking is also added to the video signal from the “H Blank” stage. This block is covered in more detail below. DC offset of the output is set by the “DC DACs Offset” stage. Bits 0 through 2 in register 08 control this stage. This gives 8 different black levels ranging from 0.75V to 1.55V. When using one of the LM246X CRT driver family it is recommended that the black level be set to 1.25V. ABL: The Auto Beam Limit control reduces the gain of the video amplifiers in response to a control voltage proportional to the CRT beam current. The ABL acts on all three channels in an identical manner. This is required for CRT life and X-ray protection. The beam current limit circuit application is as shown in Figure 4: when no current is being drawn by the EHT supply, current flows from the supply rail through the ABL resistor and into the ABL input of the IC. The IC clamps the input voltage to a low impedance voltage source (the 5V supply rail). When current is drawn from the EHT supply, some of the current passing through the ABL resistor goes to the EHT supply, which reduces the current flowing into the ABL input of the IC. When the EHT current is high enough, the current flowing into the ABL input of the IC drops to zero. This current level determines the ABL threshold and is given by: Note: Any noise injected into pin 21 will appear on the video. The voltage reference must be kept very clean for best performance of the LM1267. The video inputs are pins 5, 6, and 7. Looking at the red channel (pin 5) note that the “Clamp DC Restore Amp” is connected to this pin. Since the video must be AC coupled to the LM1267, the coupling cap is also used to store the reference voltage for DC restoration. The “Clamp DC Restore Amp” block charges the input capacitor to the correct voltage when the clamp pulse (pin 23) is active. The “Hi Z Input Buffer Amp” buffers the video signal for internal processing. Input impedance to this stage is typically 20 MΩ. With such a high impedance the DC restoration can appear to be working for a number of minutes after the clamp pulse is removed. The output of the Buffer Amp goes to the Contrast stage. The 7 bit contrast register (03h) sets the contrast level through the I2C bus. This register controls the Contrast stage in each video channel. Contrast adjustment range is up to −20 dB. Loading all zeros in the contrast register gives −20 dB attenuation. All ones will give no attenuation. The output of this stage is used as the feedback for the DC restoration loop. “Auto Beam Limit Amp” or ABL is the next block in the video path. This is a voltage controlled gain stage which gives no attenuation with 5V at pin 22 and gives about −10 dB attenuation with 2V at pin 2. ABL is covered in more detail later in this section. Next in the video path is the “OSD Mixer”. The OSD Select signal at pin 4 controls this stage, selecting OSD with a high at pin 4, and video with a low at pin 4. Since the DC restoration feedback is at the Contrast output, the video black level will match the OSD black level. The OSD signal is mixed with the video signal at the output of this stage. The OSD goes through the “OSD Contrast” stage before entering the “OSD Mixer” block. Bits 3 and 4 of register 08h control the OSD contrast giving four video levels for the OSD Where: VS is the external supply (usually the CRT driver supply rail, about 80V) VABL TH is the threshold ABL voltage of the IC RABL is the ABL resistor value IABL is the ABL limit When the voltage on the ABL input drops below the ABL threshold of the pre-amp, the gain of the pre-amp reduces, which reduces the beam current. A feedback loop is thus established which acts to prevent the average beam current exceeding IABL. 11 www.national.com LM1267 window. Maximum video level for the OSD window occurs with both bits set to one. Minimum video level will occur with both bits set to a zero. Functional Description LM1267 Functional Description (Continued) DS200050-26 FIGURE 4. ABL H Flyback: H Flyback is an analog signal input from the monitor horizontal scan. The “H Blank” section uses this signal to add horizontal blanking to the output video signal. This enables the user to blank at the cathodes during horizontal flyback. An optional capacitor and/or resistor to ground may be needed if noise interferes with the H Flyback signal. This feature gives very accurate timing for the horizontal blanking; however, the flyback signal must be very clean. There should be no ringing or other noise on the flyback signal. RLIMIT is used to limit the input current into the IC to a typical value of + 1 mA during flyback and −100 µA during normal forward scan. For example if an H flyback with a peak of 100V is used, RLIMIT = 100 kΩ. The internal input impedance of pin 24 is low to limit the maximum voltage swing at the input to within the supply rail and ground. The IC interface circuit creates a digital signal from this waveform, which is used as the blanking signal at the “Output Buffer Amp”. This signal adds blanking to the video output signal. Figure 5 shows the H flyback waveforms and the location of RLIMIT. A 56 pF capacitor has been added to the H Flyback pin on the demo board for filtering noise on the H Flyback signal. DS200050-27 FIGURE 5. H Flyback Input Pulse H Blank: Some customers may still prefer to use a standard logic signal for the horizontal blanking. Pin 24 can be adapted to accept a logic input. It is necessary for the current flow into pin 24 to reverse for proper operation. Therefore the logic signal must be AC coupled into pin 24. Figure 6 shows the recommended circuit for a logic signal input. The blank signal must be a positive pulse. DS200050-28 FIGURE 6. Standard Logic H Blank Power Save Mode: There are two modes of power save: 1. Blanking the video 2. Turning off most of the power for maximum power savings. In the first mode the video is completely blanked. By setting bit-0 in register 9 to a 1 the video will be completely blanked. This gives some power savings since there is no beam current in the monitor. Maximum power saving is obtained in the second mode. Bits 0 and 1 in register 9 should be set to a 1. Bit 1 in register 9 turns off the video output stage of the www.national.com 12 maximum capacitance of 4 pF, which will have little effect on the response of the video system due to the low impedance of the input video. (Continued) LM1267, giving a high impedance at the output pin. After bits 0 and 1 of register 9 are set to a 1, the power supplies to the CRT driver and CRT can be turned off. The ESD cells of the LM1267 also provide good protection against arc-over, however good PCB layout is necessary. The LM1267 should not be exposed directly to the voltages that may occur during arc-over. The main vulnerability of the LM1267 to arc-over is though the ground traces on the PCB. For proper protection all ground connections associated with the LM1267, including the grounds to the bypass capacitors, must have short returns to the ground pins. A significant ground plane should be used to connect all the LM1267 grounds. Figure 10, which shows the demo board layout, is an excellent example of an effective ground plane. The list below should be followed to ensure a PCB with good grounding: Note: The 5V supply must remain on for proper operation. Since the LM1267 is a CMOS device its power consumption will be minimal. External DACs: Four DACs with external outputs are provided in the LM1267. Normally these DACs will be used for color balance and brightness control. If the brightness control is done at G1, then three DACs would be used for color balance and the last DAC would be used for controlling the G1 voltage. There is also a provision to set the brightness at the cathodes. DAC 4 can be set to vary the outputs of the other three DACs after the color balance is completed. This is accomplished by adding the output of DAC 4 to the other 3 DACs. Bits 3 and 4 of register 9 are set to a 1 for brightness control at the cathodes. Bit 3 sets the output range of DAC 1–3 to 50% of their full range. Bit 4 adds 50% of DAC 4 to the other three DACs. These two adjustments keeps the overall output voltage of DAC 1–3 in the proper range and still allows brightness control. For either mode of brightness control, the DACs are ideally set to work with the LM2479 or LM2480 for DC restoration at the cathodes of the CRT. ESD and Arc-Over Protection • All grounds associated with the LM1267 should be connected together through a large ground plane. • CRT driver ground is connected to the video pre-amp ground at one point. • CRT and arc protection grounds are connected directly to the chassis or main ground. There is no arc-over current flow from these grounds through the LM1267 grounds. • Input signal traces for SDA, SCL, H Flyback, and Clamp should be kept away from the CRT driver and all traces that could carry the arc current. • Output signal traces of the LM1267 should be kept away from the traces that carry the output signals of the CRT driver. If any one of the above suggestions is not followed the LM1267 may become more vulnerable to arc-over. Improper grounding is by far the most common cause of video preamp failure during arc-over. The LM1267 incorporates full ESD protection with special consideration given to maximizing arc-over robustness. The monitor designer must still use good circuit design and PCB layout techniques. The human body model ESD susceptibility of the LM1267 is 3.5 kV, however many monitor manufacturers are now testing their monitors to the level 4 of the IEC 801-2 specification which requires the monitor to survive an 8 kV discharge. External ESD protection is needed to survive this level of ESD. The LM1267 provides excellent protection against both ESD and arc-over, but this is not a substitute for good PCB layout. Figure 7 shows the recommended input protection for the LM1267. This provides the best protection against ESD. When this protection is combined with good PCB layout the LM1267 will easily survive the IEC 801-2 level 4 testing (8 kV ESD). It is strongly recommended that the protection diodes be added as shown in Figure 7. The 1N4148 diode has a DS200050-29 FIGURE 7. Recommended Video Input ESD Protection 13 www.national.com LM1267 Functional Description FIGURE 8. LM126X/LM246X Neck Board Schematic DS200050-30 LM1267 Schematic www.national.com 14 DS200050-34 (Continued) LM1267 FIGURE 9. LM126X/LM246X Neck Board Schematic Schematic 15 www.national.com LM1267 PCB Layout DS200050-31 FIGURE 10. LM126X/LM246X System Neck Board mented into the next address location. See Figure 11. Note that each data byte is followed by an acknowledge bit. Micro-Controller Interface The micro-controller interfaces to the LM1267 pre-amp via an I2C interface. The protocol of the interface begins with the Start Pulse followed by a byte comprised of a seven-bit Slave Device Address and a Read/Write bit as the LSB. Therefore the address of the LM1267 for writing is DCh (1101 1100) and the address for reading is DDh (1101 1101). Figures 11, 12 show a write and read sequence across the I2C interface. Read Sequence Read sequences are comprised of two I2C transfer sequences. The first is a write sequence that only transfers the address to be accessed. The second is a read sequence that starts at the address transferred in the previous address write access and incrementing to the next address upon every data byte read. This is shown in Figure 12. The write sequence consists of the Start Pulse, the Slave Device Address including the Read/Write bit (a zero, indicating a write), then its Acknowledge bit. The next byte is the address to be accessed, followed by its Acknowledge bit and the stop bit indicating the end of the address only write access. Next the read data access is performed beginning with the Start Pulse, the Slave Device Address including the Read/ Write bit (a one, indicating a read) and the Acknowledge bit. The next 8 bits will be the data read from the address indicated by the write sequence. Subsequent read data bytes will correspond to the next increment address locations. Each data byte is separated from the other data bytes by an Acknowledge bit. Write Sequence The write sequence begins with a start condition which consists of the master pulling SDA low while SCL is held high. The slave device address is next sent. The address byte is made up of an address of seven bits (7–1) and the read/write bit (0). Bit 0 is low to indicate a write operation. Each byte that is sent is followed by an acknowledge. When SCL is high the master will release the SDA line. The slave must pull SDA low to acknowledge. The address of the register to be written to is sent next. Following the register address and the acknowledge bit the data for the register is sent. If bit 0 of register 0Ah is set low (default value) then the LM1267 is set for the increment mode. In this mode when more than one data byte is sent it is automatically incre- www.national.com 16 LM1267 Micro-Controller Interface (Continued) DS200050-33 2 FIGURE 11. I C Write Sequence DS200050-32 FIGURE 12. I2C Read Sequence 17 www.national.com LM1267 I2C Interface Registers I2C IC ADDRESS Slave Address of the LM1267 is DCh when writing to the registers and DD when reading from the registers. LM1267 Pre-Amp Interface Registers (all numbers in Hex) Register Address Default Format R Gain Control 00 60h X R Gain [6:0] B Gain Control 01 60h X B Gain [6:0] G Gain Control 02 60h X G Gain [6:0] Contrast Cont. 03 60h X Contrast [6:0] DAC1 04 80h DAC 1[7:0] DAC2 05 80h DAC 2[7:0] DAC3 06 80h DAC 3[7:0] DAC4 07 80h DC Offset/ OSD Cont. 08 15h X X X Global Control 09 00h X X O DCF4 Increment Mode 0A 00h X X X X X Clamp/BW 0B 04h X X X X CLMP Software Reset 0F 00h X X X X X DAC 4[7:0] Pre-Amp Interface Registers RSV RG5 RG4 RG3 RG2 RG1 RSV RG0 BG5 BG4 BG3 BG2 BG1 GG5 GG4 GG3 GG2 GG1 BANDWIDTH[2:0] X X SRST Bit 0 CG6 CG5 CG4 CG3 CG2 CG1 CG0 Bit 0 DAC 2 Register (I2C address 05h) Register name: DAC 2 (05h) Bit 7 Bit 0 D2–7 D2–6 D2–5 D2–4 D2–3 D2–2 D2–1 D2–0 GG0 Bits 7–0: DAC 2. These eight bits determine the output voltage of DAC 2. Bits 6–0: Green Channel Gain Control. These seven bits determine the gain for the Green Channel. Bit 7: Reserved. www.national.com INCR Bits 7–0: DAC 1. These eight bits determine the output voltage of DAC 1. Bit 0 GG6 O D1–7 D1–6 D1–5 D1–4 D1–3 D1–2 D1–1 D1–0 Green Channel Gain Control Register (I2C address 02h) Register name: G Gain Control (02h) RSV X Bit 7 BG0 Bits 6–0: Blue Channel Gain Control. These seven bits determine the gain for the Blue Channel. Bit 7: Reserved. Bit 7 BV DAC 1 Register (I2C address 04h) Register name: DAC 1 (04h) Bit 0 BG6 PS DAC Interface Register Definitions Blue Channel Gain Control Register (I2C address 01h) Register name: B Gain Control (01h) RSV O Bits 6–0: Contrast Control. These seven bits vary the gain of all three channels. Bit 7: Reserved. Bits 6–0: Red Channel Gain Control. These seven bits determine the gain for the Red Channel. Bit 7: Reserved. Bit 7 DCF1–3 Bit 7 Bit 0 RG6 DC_Offset [2:0] Contrast Control Register (I2C address 03h) Register name: Contrast Control (03h) Red Channel Gain Control Register (I2C address 00h) Register name: R Gain Control (00h) Bit 7 OSD_Cont. [1:0] DAC 3 Register (I2C address 06h) 18 Bit 4: DAC4 Configuration. When this bit is a zero the DAC4 output is not mixed with the other DAC outputs. When the bit is one, 50% of the DAC4 output is added to DAC1–3. Bit 5: MUST BE SET TO “0” FOR PROPER OPERATION. (Continued) Register name: DAC 3 (06h) Bit 7 Bit 0 D3–7 D3–6 D3–5 D3–4 D3–3 D3–2 D3–1 D3–0 Bits 7–6: Reserved. Bits 7–0: DAC 3. These eight bits determine the output voltage of DAC 3. Increment Mode Register (I2C address 0Ah) Register name: Increment Mode (0Ah) DAC 4 Register (I2C address 07h) Register name: DAC 4 (07h) Bit 7 Bit 7 RSV Bit 0 DC Offset and OSD Contrast Control Register (I2C address 08h) Register name: DC Offset/OSD Cont. (08h) RSV RSV RSV OSDC1 OSDC0 DC2 DC1 DC0 RSV Bit 1: Bit 2: Bit 3: 0 DCF4 DCF1–3 0 PS TST INCR RSV Bit 0 RSV RSV RSV CLMP BW1 BW2 BW0 Bits 2–0: Bandwidth. Used to set the bandwidth of the preamp. The default is 100. When all bits are set to “1”, the LM1267 will have maximum bandwidth, when all bits are set to “0” the LM1267 will have minimum bandwidth. Bit 3: Determines the polarity of the clamp signal used by the LM1267, “0” (default) is a positive clamp signal, “1” is a negative going clamp signal. Bits 7–4: Reserved. Bit 0 RSV RSV Bit 7 Global Video Control Register (I2C address 09h) Register name: Global Control (09h) Bit 0: RSV Clamp Polarity and Bandwidth (I2C address 0Bh) Register name: Clamp/BW (0Bh) Bits 2–0: DC Offset Control. These three bits determine the active video DC offset to all three channels. Bits 4–3: OSD Contrast Control. These two bits determine the contrast level of the OSD information. Bits 7–5: Reserved. Bit 7 RSV Increment Enable. When set to a “0”, the default value, the increment mode is enabled. This allows the registers to be updated sequentially by sending another block of data. Bit 1: MUST BE SET TO “0” FOR PROPER OPERATION. Bits 7–2: Reserved. Bits 7–0: DAC 4. These eight bits determine the output voltage of DAC 4. Bit 0 RSV Bit 0: D4–7 D4–6 D4–5 D4–4 D4–3 D4–2 D4–1 D4–0 Bit 7 Bit 0 RSV BV Blank Video. When this bit is a one, blank the video output. When this bit is a zero allow normal video out. Power Save. When this bit is a one, shut down the analog circuits to support sleep mode. When this bit is a zero enable the analog circuits for normal operation. MUST BE SET TO “0” FOR PROPER OPERATION. DAC1–3 Configuration. When this bit is a zero the DAC outputs of DAC1–3 are full scale (0V–4.5V). When this bit is 1, the range of DAC1–3 are halved (0V–2.25V). Software Reset Register (I2C address 0Fh) Register name: Software Reset (0Fh) Bit 7 RSV Bit 0 RSV RSV RSV RSV RSV RSV SRST Bit 0: Software Reset. Setting this bit causes a software reset. All registers (except this one) are loaded with their default values. All operations currently in progress are aborted (except for I2C transactions). This bit automatically clears itself when the reset has been completed. Bits 7–1: Reserved. 19 www.national.com LM1267 DAC Interface Register Definitions LM1267 150 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs Physical Dimensions inches (millimeters) unless otherwise noted Order Number LM1267NA NS Package Number N24D LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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