19-1056; Rev 0; 11/07 DVI/HDMI 2:4 Low-Frequency Fan Out Switch Features The MAX4814E high-definition multimedia interface (HDMI) switch provides routing for low-frequency signals. The MAX4814E operates from a single +5.0V ±10% supply voltage and is ideal for connecting multiple HDMI sources to multiple loads. The MAX4814E is a bidirectional 2:4 HDMI switch. Each switch consists of five single-pole/single-throw (SPST) channels. Two channels have a low 3Ω (typ) on-resistance to route +5V and drain (ground return), and three channels to route data. The device features a mode input to control the device through an I2C interface or direct-control logic inputs. The MAX4814E is available in a 64-pin (10mm x 10mm) TQFP package and operates over the -40°C to +85°C extended temperature range. ♦ +5V/Drain Switched ♦ HPD (Hot-Plug Detect) Switching ♦ DDC (Display Data Channel) Switching ♦ Direct Entry or I2C Control ♦ Low 1µA Quiescent Current ♦ ±6kV Human Body Model (HBM) ESD Protection on Switch I/Os ♦ Companion IC to the MAX3845 ♦ Provides I2C Control for the MAX3845 ♦ Compact 64-Pin, 10mm x 10mm TQFP Package ♦ Optimized Layout to Support 4:4 or 2:8 Configuration with Two Devices Applications Ordering Information Commercial/Industrial HDMI/DVI Switch Boxes PART High-End Consumer Switchers AV Receivers with Switching TEMP RANGE MAX4814EECB+ -40°C to +85°C PINPACKAGE 64 TQFP-EP* PKG CODE C64E-10 +Denotes a lead-free package. *EP = Exposed paddle. Pin Configuration appears at end of data sheet. Typical I2C Operating Circuit 4.5V TO 5.5V 0.1μF 5 DVI/HDMI 1 MODE VDD SW0 A SW1 5 DVI/HDMI 2 SW2 B SW3 VDD DVI/HDMI 1 OR DVI/HDMI 2 5 5 5 DVI/HDMI 1 OR DVI/HDMI 2 5 DVI/HDMI 1 OR DVI/HDMI 2 MAX4814E μCONTROLLER SCL DVI/HDMI 1 OR DVI/HDMI 2 SDA AD2 ADDRESS SELECTION* AD1 DO 4 MAX3845 AD0 GND EFN 0.1μF *SEE DEVICE ADDRESS SECTION. ________________________________________________________________ Maxim Integrated Products For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX4814E General Description MAX4814E DVI/HDMI 2:4 Low-Frequency Fan Out Switch ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND. Note 1.) VDD, A_, B_, SW_, EFN..........................................-0.3V to +6.0V All Other Pins (except GND).........................-0.3V to VDD + 0.3V Continuous Current, A_, B_ ..............................................±60mA Continuous Current, VDD or GND...................................±100mA Continuous Power Dissipation (TA = +70°C) 64-Pin TQFP (derate 31.3mW/°C above +70°C)........2508mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering) .........................................+300°C Note 1: EFN must be either connected to VDD or left unconnected. EFN must not be connected to ground. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5V ±10%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VDD = +5V. Note 2.) PARAMETER SYMBOL Power-Supply Voltage VDD Power-Supply Current IDD EFN Leakage Current IL CONDITIONS MIN TYP MAX UNIT 4.5 5 5.5 V 10 µA +2 µA EFN = unconnected; all inputs = 0; all outputs high or low, no loads VEFN = VDD - 0.2V -2 LOGIC INPUTS (DA_, DB_, MODE, AD_) Input Low Voltage DA_, DB_ VIL MODE = 0V Input High Voltage DA_, DB_ VIH MODE = 0V VHYST MODE = 0V Input-Voltage Hysteresis DA_, DB_ Input Low Voltage AD_ VIL MODE = VDD Input High Voltage AD_ VIH MODE = VDD VHYST MODE = VDD Input-Voltage Hysteresis AD_ Input Low Voltage MODE VIL Input High Voltage MODE VIH Input-Voltage Hysteresis MODE 0.8 2 150 mV 0.8 2 V V 150 mV 0.8 2 VHYST V V V V 150 mV Input Leakage Current DA_, DB_ IL MODE = 0V ±1 µA Input Leakage Current AD_ IL MODE = VDD ±1 µA Input Leakage Current MODE IL ±1 µA 0.5 V LOGIC OUTPUTS DO_ Output-Voltage Low VOL MODE = VDD, ISINK = 30µA Output-Voltage High VOH MODE = VDD, ISOURCE = 26µA Output Leakage Current IL MODE = VDD, output at high impedance, VIN = 1.5V Output Rise Time tR VOUT from 0.8V to 2.2V, CLOAD = 10pF Output Short-Circuit Current ISC 2 2 V ±1 600 ns ISOURCE -1 ISINK +3 _______________________________________________________________________________________ µA mA DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V ±10%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VDD = +5V. Note 2.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT ANALOG SWITCHES On-Resistance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] RON VIN = 2.5V, IIN = ±10mA 12 Ω VIN = 0.8V, 2.5V, 3.7V 2.5 Ω On-Resistance-Flatness Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] RFLAT On-Channel -3dB Bandwidth Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] BW RS = RL = 50Ω, CL = 35pF, Figure 1 190 MHz Off-Isolation Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] VISO RS = RL = 50Ω, f = 1MHz, Figure 1 65 dB Crosstalk Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] VCT RS = RL = 50Ω, f = 1MHz, Figure 1 75 dB On-Capacitance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] CON VDD = 4.5V, f = 1MHz, Figure 2 37 pF Off-Capacitance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] COFF VDD = 4.5V, f = 1MHz, Figure 2 15 pF VGEN = 1.5V, RGEN = 0Ω, CL = 100pF, Figure 3 13 pC VDD = 4.5V, VIN = 0V or VDD 3 Ω Charge Injection Q On-Resistance +5V/Drain: A[0], A[4], B[0], B[4] RON Switch Leakage Current IL 2 I C SPECIFICATIONS (SDA, SCL, MODE = VDD) ±10 µA Input Low Voltage 0.8 V VIL Input High Voltage VIH Input-Voltage Hysteresis Input Leakage Current Output-Voltage Low SDA 2.4 VHYST V 450 IL VOL ISINK = 3mA mV ±1 µA 0.4 V TIMING CHARACTERISTICS (Figure 4), MODE = VDD Serial Clock Frequency Hold Time (Repeated) START Condition (after this period the first clock pulse is generated) Low Period of the SCL Clock fSCL VDD = 4.5V 100 400 kHz tHD,STA fSCL = 100kHz 4 µs tLOW fSCL = 100kHz 4.7 µs _______________________________________________________________________________________ 3 MAX4814E DVI/HDMI 2:4 Low-Frequency Fan Out Switch ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V ±10%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VDD = +5V. Note 2.) PARAMETER High Period of the SCL Clock SYMBOL CONDITIONS MIN TYP MAX UNIT tHIGH fSCL = 100kHz 4 µs Setup Time for a Repeated START Condition tSU,STA fSCL = 100kHz 4.7 µs Data Hold Time tHD,DAT fSCL = 100kHz 25 µs Data Setup Time tSU,DAT fSCL = 100kHz 250 ns ESD PROTECTION (HUMAN BODY MODEL) SW_, A_, B_ All Other I/Os ESD Referenced to GND ±6 ±2 Note 2: Limits at TA = -40°C are guaranteed by design. 4 _______________________________________________________________________________________ kV DVI/HDMI 2:4 Low-Frequency Fan Out Switch OFF-ISOLATION = 20log VOUT VIN ON-LOSS = 20log VOUT VIN NETWORK ANALYZER VDD B_ 50Ω VIN A_ MAX4814E MEAS VOUT SW_ 50Ω 50Ω GND V CROSSTALK = 20log OUT VIN REF 50Ω MAX4814E +5V 0.1μF 50Ω MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN SW_ AND "OFF" A_ OR B_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN SW_ AND "ON" A_ OR B_TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED. Figure 1. On-Loss, Off-Isolation, and Crosstalk 0.1μF +5V VDD SW_ CAPACITANCE METER MAX4814E DB_ DA_ OR SDA SCL A_ OR B_ f = 1MHz VIL OR VIH GND Figure 2. Channel Off-/On-Capacitance +5V 0.1μF ΔVOUT MAX4814E VDD RGEN A_ OR B_ SW_ VOUT CL V GEN GND DB_ SDA OR SCL DA_ VINL TO VINH VOUT DB_ DA_ OR SDA SCL DB_ DA_ OR SDA SCL OFF OFF ON ON OFF OFF Q = (ΔV OUT )(C L ) IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 3. Charge Injection _______________________________________________________________________________________ 5 Typical Operating Characteristics (VDD = +5V, TA = +25°C, unless otherwise noted.) 12 10 VDD = 5.0V 8 VDD = 4.5V VDD = 5.0V 6 TA = +25°C 14 12 10 TA = -40°C 8 TA = +85°C TA = +25°C 6 +5V/DRAIN OFF-LEAKAGE 10,000 TA = -40°C STD. SWITCH OFF-LEAKAGE 1000 +5V/DRAIN ON-LEAKAGE 100 10 4 4 1 2 2 VDD = 5.5V - - - - +5V/DRAIN 0 0 1 2 3 4 5 0 0 6 STD. SWITCH ON-LEAKAGE - - - - +5V/DRAIN 1 0.1 2 3 4 SUPPLY CURRENT (μA) 0.35 0.3 0.25 0.2 0.15 VDD = 4.5V 0.1 0 VDD = 5.0V MAX4814E toc05 20 0 FREQUENCY RESPONSE (dB) VDD = 5.5V 0.4 OFF-ISOLATION -20 ON-LOSS -40 -60 CROSS-TALK -80 SWITCH I/O_ = 0V -40 -15 10 10 FREQUENCY RESPONSE MAX4814E toc04 0.45 -15 -100 35 TEMPERATURE (°C) 60 85 35 TEMPERATURE (°C) SUPPLY CURRENT vs. TEMPERATURE 0.5 0.05 -40 5 VA OR VB (V) VA OR VB (V) 6 100,000 LEAKAGE CURRENT (pA) 14 TA = +85°C 16 ON-RESISTANCE (Ω) VDD = 4.5V MAX4814E toc02 MAX4814E toc01 VDD = 5.5V 16 LEAKAGE CURRENT vs. TEMPERATURE ON-RESISTANCE vs. VA OR VB 18 MAX4814E toc03 ON-RESISTANCE vs. VA OR VB 18 ON-RESISTANCE (Ω) MAX4814E DVI/HDMI 2:4 Low-Frequency Fan Out Switch 0.1 1 10 100 1000 FREQUENCY (MHz) _______________________________________________________________________________________ 60 85 DVI/HDMI 2:4 Low-Frequency Fan Out Switch PIN NAME 1, 16, 24, 25, 33, 48, 56, 57 GND Ground. Must connect all GND pins together. FUNCTION 2, 15, 34 I.C. Internally Connected. Leave I.C. unconnected 3 A[0] Switch A I/O 0. A[0] has a 3Ω (typ) resistance to switch 5V or drain. 4 A[1] Switch A I/O 1. A[1] has a 12Ω (typ) resistance to switch data. 5 A[2] Switch A I/O 2. A[2] has a 12Ω (typ) resistance to switch data. 6 A[3] Switch A I/O 3. A[3] has a 12Ω (typ) resistance to switch data. 7 A[4] Switch A I/O 4. A[4] has a 3Ω (typ) resistance to switch 5V or drain. 8, 9, 17, 32, 40, 41, 49, 64 VDD Positive-Supply Voltage Input. Connect VDD to a +5V supply voltage. Bypass VDD to GND with a 0.1µF capacitor. Must connect all VDD pins together. 10 B[0] Switch B I/O 0. B[0] has a 3Ω (typ) resistance to switch 5V or drain. 11 B[1] Switch B I/O 1. B[1] has a 12Ω (typ) resistance to switch data. 12 B[2] Switch B I/O 2. B[2] has a 12Ω (typ) resistance to switch data. 13 B[3] Switch B I/O 3. B[3] has a 12Ω (typ) resistance to switch data. 14 B[4] Switch B I/O 4. B[4] has a 3Ω (typ) resistance to switch 5V or drain. 18 MODE 19 SDA I2C-Compatible Serial Data I/O 20 SCL I2C-Compatible Serial Clock Input 21 AD0 Programmable I2C Address Bit. AD[0] sets the I2C address of the device. Userselectable device address bit, LSB, LSB+1, MSB (see Figure 5). 22 AD1 Programmable I2C Address Bit. AD[1] sets the I2C address of the device. Userselectable device address bit, LSB, LSB+1, MSB (see Figure 5). 23 AD2 Programmable I2C Address Bit. AD[2] sets the I2C address of the device. Userselectable device address bit, LSB, LSB+1, MSB (see Figure 5). 26 SW3[4] Switch 3 I/O 4 27 SW3[3] Switch 3 I/O 3 28 SW3[2] Switch 3 I/O 2 29 SW3[1] Switch 3 I/O 1 30 SW3[0] Switch 3 I/O 0 31, 50 EFN 35 SW2[4] Switch 2 I/O 4 36 SW2[3] Switch 2 I/O 3 37 SW2[2] Switch 2 I/O 2 38 SW2[1] Switch 2 I/O 1 39 SW2[0] Switch 2 I/O 0 42 SW1[4] Switch 1 I/O 4 43 SW1[3] Switch 1 I/O 3 44 SW1[2] Switch 1 I/O 2 MODE Selection Input. Connect MODE to VDD (MODE = 1) to select I2C control mode. Connect MODE to GND (MODE = 0) to select direct-control mode. ESD Protection. Connect EFN with an external 0.1µF capacitor to GND for ±15kV ESD HBM protection. The capacitor from EFN to GND provides an additional discharge path for the ESD energy. _______________________________________________________________________________________ 7 MAX4814E Pin Description DVI/HDMI 2:4 Low-Frequency Fan Out Switch MAX4814E Pin Description (continued) PIN NAME 45 SW1[1] Switch 1 I/O 1 FUNCTION 46 SW1[0] Switch 1 I/O 0 47 N.C. 51 SW0[4] Switch 0 I/O 4 No Connection. Not internally connected. 52 SW0[3] Switch 0 I/O 3 53 SW0[2] Switch 0 I/O 2 54 SW0[1] Switch 0 I/O 1 55 SW0[0] Switch 0 I/O 0 58 DA0/DO0 Direct-Control Bit I/O. In mode 0, DA0/DO0 is set as an input, DA0, to control switch connections. In mode 1, DA0/DO0 is set as an output, DO0. The output bits are used to drive the MAX3845. 59 DA1/DO1 Direct-Control Bit I/O. In mode 0, DA1/DO1 is set as an input, DA1, to control switch connections. In mode 1, DA1/DO1 is set as an output, DO1. The output bits are used to drive the MAX3845. 60 DA2/DO2 Direct-Control Bit I/O. In mode 0 DA2/DO2 is set as an input, DA2, to control switch connections. In mode 1, DA1/DO1 is set as an output, DO2. The output bits are used to drive the MAX3845. 61 DB0/DO3 Direct-Control Bit I/O. In mode 0 DB0/DO3 is set as an input, DB0, to control switch connections. In mode 1, DB0/DO3 is set as an output, DO3. The output bits are used to drive the MAX3845. 62 DB1 Direct-Control Bit I/O. In mode 0, DB1 is set as an input. In mode 1, DB1 is high impedance. 63 DB2 Direct-Control Bit I/O. In mode 0, DB1 is set as an input. In mode 1, DB1 is high impedance. EP EP Exposed Pad. Connect exposed pad to ground. For enhanced thermal dissipation, connect EP to a copper area as large as possible. Do not use EP as a sole ground connection. Detailed Description The MAX4814E provides routing for low-frequency DVI/HDMI signals. The MAX4814E is a bidirectional 2:4 DVI/HDMI switch. Each switch consists of five singlepole/single-throw (SPST) channels. The channels have a low 3Ω (typ) on-resistance to route +5V and drain, and three channels to route data. Channels A0, A4, B0, B4, SW_0, and SW_4 have a 3Ω (typ) on-resistance to route +5V and drain, and the remaining channels A1–A3, B1–B3, SL0_3, and SW_1 have a 12Ω (typ) on-resistance to route data. The device features a mode input to control the device using direct-control logic inputs or an I2C interface. Connect MODE to GND to control the device using the direct-control bits. Connect MODE to VDD to control the device using I2C. In I2C mode, the MAX4814E controls the MAX3845 (see Figure 5). 8 Analog Signal Levels Signal inputs over the full voltage range (0V to VDD) are passed through the switch with minimal change in onresistance (see the Typical Operating Characteristics). The switches are bidirectional. Therefore, switch A_, switch B_, and switch SW_ can be either inputs or outputs. Switch Control The MAX4814E features a mode input to control the device through either an I2C interface or through directcontrol logic inputs. Connect MODE to GND (mode 0) to control the device using the direct-control inputs DA_ and DB_ (see Table 1 and Figure 6). Connect MODE to VDD (mode 1) to control the device using the I2C interface. Direct Control Method (Mode 0) In mode 0, DA0/DO0 becomes input DA0, DA1/DO1 _______________________________________________________________________________________ DVI/HDMI 2:4 Low-Frequency Fan Out Switch VDD 5 A_ 5 A1 5 A2 5 A3 5 SW0_ SW1_ SW2_ SW3_ B0 5 B_ A0 B1 B2 MAX4814E B3 B_ A_ DECODER 6 MUX 6 6 DO[3:0] 4 HI-Z 4 6 4 DB0 DA_ 4 I.C. I2C SERIAL PORT AND REGISTERS N.C. EFN EN GND MODE EN SDA EN SCL becomes input DA1, DA2/DO2 becomes input DA2, and DB0/DO3 becomes input DB0. Inputs DB1 and DB2 are enabled. In mode 0, the direct-control inputs DA_ and DB_ are used to control the connection of the switches. DA2 is EN AD0 EN AD1 AD2 DB_ DA_ used as the enable for switch A, and DB2 is used as the enable for switch B. Connecting DA2 to VDD enables switch A, and connecting DA2 to GND disables switch A. Connecting DB2 to VDD enables switch B, and connecting DB2 to GND disables switch B. Inputs DA0 and _______________________________________________________________________________________ 9 MAX4814E Functional Diagram MAX4814E DVI/HDMI 2:4 Low-Frequency Fan Out Switch DA1 select the connections of switch A to switch SW_ and inputs DB0 and DB1. Select the connections of switch B to SW_. See Table 3a for the pin configuration and Table 3b for a complete summary. select the connections of switch B to switch SW_, as summarized in Table 6. I2C Register R0 Two LSB Bits The two LSBs are hard coded as 00. Register R0 ignores any value written to the two LSBs; anytime register R0 is read the hard-coded values are returned. I2C Interface Method (Mode 1) In mode 1, the switch connections are controlled through the I2C interface. Inputs SDA and SCL program registers R0 and R1. Register R0, bits [7 to 2], select the connection of switch A and switch B to switch SW_ (see the I2C Registers and Bit Descriptions section). The bits of register R1 transfer data to the output DO_. The data on output DO_ is used to communicate with the MAX3845. In mode 1, DA0/DO0 becomes output DO0, DA1/DO1 becomes output DO1, DA2/DO2 becomes output DO2, and DB0/DO3 becomes output DO3. DB1 and DB2 are high impedance. See Table 3a for the pin configuration. See Table 4 for register R1 to DO_ output mapping. I2C Registers and Bit Descriptions Bank A Enable (BAEN) and Bank B Enable (BBEN) Bits 1 = Enable 0 = Disable Bank A Select (BASEL1/BASEL0) and Bank B Select (BBSEL1/BBSEL0) Bits Bits BASEL1 and BASEL0 select the switch SW_ that switch A is connected to. Bits BBSEL1 and BBSEL0 select the switch SW_ that switch B is connected to (see Table 6). Power-On Default States When power is applied to the MAX4814E internal power-on reset (POR), circuitry sets registers R0 and R1 to their default states. Register R0 is set to all zeros, or 00h, and register R1 is set to 10101010, or AAh, as shown in Table 2. Two internal registers (RO and R1) program the MAX4814E. Table 2 lists both registers, their addresses, and power-up default states. Both registers are read/write registers. Having all zeros in register R0 disables both banks A and B; see Table 6 for register R0 to switch mapping. Setting register R1 to AAh forces the outputs at DO_ to be high impedance. Note: The output, DO_ is used to communicate with the MAX3845 when the MAX4814E is being used without its companion. The MAX3845 and the MAX4814E use the I2C interface (MODE = 1). All DO_ outputs need to be connected through a 10kΩ resistor to GND. In register R0, bit BAEN is used as the enable for switch A, and bit BBEN is used as the enable for switch B. Writing 1 to bit BAEN enables switch A; and writing 0 to bit BAEN disables switch A. Writing 1 to bit BBEN enables switch B, and writing 0 to bit BBEN disables switch B. BASEL1 and BASEL0 select the connections of switch A to switch SW_, while BBSEL1 and BBSEL0 Table 1. Mode Configuration INPUT PIN OPERATION MODE 0 Puts the device in mode 0. The direct-control inputs DA_ and DB_ control the switches. 1 Puts the device in mode 1. The switches are controlled by the I2C interface. DO_ becomes an active output. Inputs DB1 and DB2 are high impedance. Table 2. I2C Register Map BIT REGISTER 7 6 R0 BBEN BBSE L1 5 BBSEL0 R1 DO3 High Impedance DO3 Data DO2 High Impedance 4 POWER-UP 3 2 BAEN BASEL1 BASE L0 1 0 X X DO2 Data DO1 High Impedance DO1 Data DO0 High Impedance DO0 Data ADDRESS BINARY HEX 0x00 0000 0000 00 0x01 1010 1010 AA X = Hardwired code, not programmable by user. 10 ______________________________________________________________________________________ DVI/HDMI 2:4 Low-Frequency Fan Out Switch PIN CONFIGURATION MODE DA0/DO0 DA1/DO1 DA2/DO2 DB0/DO3 DB1 DB2 0 DA0, Input DA1, Input DA2, Input DB0, Input DB1, Input DB2, Input 1 DO0, Output DO1, Output DO2, Output DO3, Output High Impedance High Impedance Table 3b. Mode 0 Direct-Control Configurations PIN CONNECTION OPERATION DA2 0 Bank A switches are disabled 1 Bank A switches are enabled. Switch A connections depend on the DA0 and DA1 inputs. PIN CONNECTION OPERATION DB2 0 Bank B switches are disabled 1 Bank B switches are enabled. Switch B connections depend on the DB0 and DB1 inputs. PIN CONNECTION OPERATION DB1 DB0 DA1 DA0 0 0 0 0 Connect A to SW0 B is high impedance 0 0 0 1 Connect A to SW1 Connect B to SW0 0 0 1 0 Connect A to SW2 Connect B to SW0 0 0 1 1 Connect A to SW3 Connect B to SW0 0 1 0 0 Connect A to SW0 Connect B to SW1 0 1 0 1 Connect A to SW1 B is high impedance 0 1 1 0 Connect A to SW2 Connect B to SW1 0 1 1 1 Connect A to SW3 Connect B to SW1 1 0 0 0 Connect A to SW0 Connect B to SW2 1 0 0 1 Connect A to SW1 Connect B to SW2 1 0 1 0 Connect A to SW2 B is high impedance 1 0 1 1 Connect A to SW3 Connect B to SW2 1 1 0 0 Connect A to SW0 Connect B to SW3 1 1 0 1 Connect A to SW1 Connect B to SW3 1 1 1 0 Connect A to SW2 Connect B to SW3 1 1 1 1 Connect A to SW3 B is high impedance Note: When switch A and switch B are connected to the same SW_, switch A takes precedence and switch B is high impedance. I2C Interface Device Address The MAX4814E features an I 2 C interface using a repeated start. The MAX4814E I2C interface refers to the I2C bus specification (version 2.1, Jan 2000). The MAX4814E has selectable device addresses through external inputs. The slave address consists of four fixed bits (B7–B4, set to 0111) followed by three pinprogrammable bits (AD2–AD0), as shown on Table 7. ______________________________________________________________________________________ 11 MAX4814E Table 3a. Input/Output Configurations for DA_, DB_, and DO_ MAX4814E DVI/HDMI 2:4 Low-Frequency Fan Out Switch Table 4. I2C Register R1 (0X01) to DO_ Mapping PIN REGISTER R1 (0x01) OUTPUT PIN CONFIGURATION MODE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 — — — — — — 0 0 DO0 1 — — — — — — 0 1 DO0 1 1 — — — — — — 1 X DO0 Hi-Z 1 — — — — 0 0 — — DO1 0 1 — — — — 0 1 — — DO1 1 1 — — — — 1 X — — DO1 Hi-Z 1 — — 0 0 — — — — DO2 0 1 — — 0 1 — — — — DO2 1 1 — — 1 X — — — — DO2 Hi-Z 1 0 0 — — — — — — DO3 0 1 0 1 — — — — — — DO3 1 1 1 X — — — — — — DO3 Hi-Z 0 X = Don’t care. Table 5. I2C Register R0 (0x00) REGISTER R0 (0x00) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BBEN BBSEL1 BBSEL0 BAEN BASEL1 BASEL0 X X X = hardwired, not programmed by user. For example: If AD0, AD1, and AD2 are hardwired to ground, then the complete address is 0111000. The full address is defined as the seven most significant bits followed by the read/write bit. Set the read/write bit to 1 to configure the MAX4814E to read mode. Set the read/write bit to 0 to configure the MAX4814E to write mode. The address is the first byte of information sent to the MAX4814E after the START condition. . Applications Information ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. Switch A, switch B, and switch SW_ are further protected against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD up to ±6kV without 12 damage. The ESD structures withstand high ESD in normal operation, and when the device is powered down. ESD protection can be tested in various ways. The ESD protection of switch A, switch B, and switch SW_ are characterized for ±6kV (Human Body Model) using the MIL-STD-883. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 7 shows the Human Body Model, and Figure 8 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the test device through a 1.5kΩ resistor. ______________________________________________________________________________________ DVI/HDMI 2:4 Low-Frequency Fan Out Switch DA_, DB_ INPUTS/REGISTER R0 BITS SWITCH A AND B TO SW_ CONNECTIONS DB2/ BBEN DB1/ BBSEL1 DB0/ BBSEL0 DA2/ BAEN DA1/ DA0/ BASEL1 BASEL0 B TO SW3 B TO SW2 B TO SW1 B TO SW0 A TO SW3 A TO SW2 A TO SW1 A TO SW0 0 X X 0 X 0 X X 1 0 X — — — — — — — — 0 — — — — — — — 0 X X 1 1 0 1 — — — — — — 1 — 0 X X 0 X X 1 1 0 — — — — — 1 — — 1 1 1 — — — — 1 — — 1 0 0 — 0 X X — — — 1 — — — — 1 0 0 1 0 0 — — — 0 1 0 0 1 0 1 — — — 1 — — — 1 — — 1 — 1 0 0 1 1 0 — — — 1 — 1 — — 1 0 0 1 1 1 — — — 1 1 — — — 1 0 1 0 X X — — 1 — — — — — 1 0 1 1 0 0 — — 1 — — — — 1 1 0 1 1 0 1 — — 0 — — — 1 — 1 0 1 1 1 0 — — 1 — — 1 — — 1 0 1 1 1 1 — — 1 — 1 — — — 1 1 0 0 X X — 1 — — — — — — 1 1 0 1 0 0 — 1 — — — — — 1 1 1 0 1 0 1 — 1 — — — — 1 — 1 1 0 1 1 0 — 0 — — — 1 — — 1 1 0 1 1 1 — 1 — — 1 — — — 1 1 1 0 X X 1 — — — — — — — 1 1 1 1 0 0 1 — — — — — — 1 1 1 1 1 0 1 1 — — — — — 1 — 1 1 1 1 1 0 1 — — — — 1 — — 1 1 1 1 1 1 0 — — — 1 — — — — = Denotes no connection. 1 = Denotes switch connection. 0 = Denotes switch B is high impedance. X = Don’t care. Table 7. MAX4814E Device Address B7 B6 0 1 B5 B4 B3 1 1 AD2 Fixed Power-Supply Biasing and Sequencing Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings, since stresses beyond the listed ratings can cause permanent damage to the device. Always B2 B1 B0 AD1 AD0 R/W User Selected — sequence VDD on first, followed by the switch inputs and the logic inputs. Bypass at least one VDD input to ground with a 0.1µF capacitor as close as possible to the device. Use the smallest physical size possible for optimal performance. ______________________________________________________________________________________ 13 MAX4814E Table 6. Switch Selection Truth Table MAX4814E DVI/HDMI 2:4 Low-Frequency Fan Out Switch SDA tSU, STA tSU, DAT tHD, DAT tLOW SCL tHIGH tHD, STA tr tf REPEATED START CONDITION START CONDITION Figure 4. 2-Wire Interface Timing Diagram MODE = 1: I2C CONTROL MAX4814E 18 19 20 23 22 3-STATE CONTROL 58 96 59 65 60 61 61 30 MODE = 0: DIRECT CONTROL MAX3845 MAX4814E 21 18 SETS 3 LSBs OF I2C ADDRESS. AS SHOWN ADDRESS = 0111 + LSB = 0111000. THERE ARE 8 POSSIBLE I2C ADDRESSES. BY HARDWIRING PINS 23, 22, AND 21 TO 1 OR 0 USER CAN CHANGE ADDRESS. VDD SDA SCL MODE = 0 Figure 5. Mode 1: I2C Control RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR 22 23 61 62 DA0 DA1 DA2 DB0 DB1 DB2 Figure 6. Mode 0: Direct Control RD 1500Ω IP 100% 90% DISCHARGE RESISTANCE Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES HIGHVOLTAGE DC SOURCE Cs 100pF STORAGE CAPACITOR DEVICE UNDER TEST 36.8% 10% 0 0 Figure 7. Human Body ESD Test Model 14 63 SEE TABLE 3b FOR CONTROL FUNCTIONS. SEE TABLE 4 FOR I2C REGISTERS. I2C CONTROL 21 tRL TIME tDL CURRENT WAVEFORM Figure 8. Human Body Current Waveform ______________________________________________________________________________________ DVI/HDMI 2:4 Low-Frequency Fan Out Switch GND I.C. SW2[4] SW2[2] SW2[3] SW2[1] SW2[0] VDD VDD SW1[4] SW1[3] SW1[2] SW1[1] N.C. SW1[0] GND TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD 49 32 VDD EFN 50 31 EFN SW0[4] 51 30 SW3[0] SW0[3] 52 29 SW3[1] SW0[2] 53 28 SW3[2] SW0[1] 54 27 SW3[3] SW0[0] 55 26 SW3[4] 25 GND GND 56 MAX4814E GND 57 24 GND DA0/DO0 58 23 AD2 DA1/DO1 59 22 AD1 DA2/DO2 60 21 AD0 20 SCL DB0/DO3 61 *EP DB1 62 19 SDA A[4] 10 11 12 13 14 15 16 GND A[3] 9 I.C. A[1] A[2] 8 B[4] 7 B[3] 6 B[2] 5 B[1] 4 B[0] 3 VDD 2 VDD 1 A[0] 17 VDD I.C. 18 MODE VDD 64 GND DB2 63 TQFP *CONNECT EXPOSED PADDLE TO GND. It is also recommended to bypass more than one VDD input. A good strategy is to bypass one VDD input with a 0.1µF capacitor and at least a second VDD input with a 1nF to 10nF capacitor (use a 0603 or smaller physical size ceramic capacitor). Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 15 MAX4814E Pin Configuration Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 64L, TQFP.EPS MAX4814E DVI/HDMI 2:4 Low-Frequency Fan Out Switch PACKAGE OUTLINE, 64L TQFP, 10x10x1.0mm EP OPTION 21-0084 16 ______________________________________________________________________________________ C 1 2 DVI/HDMI 2:4 Low-Frequency Fan Out Switch PACKAGE OUTLINE, 64L TQFP, 10x10x1.0mm EP OPTION 21-0084 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2007 Maxim Integrated Products SPRINGER is a registered trademark of Maxim Integrated Products, Inc. MAX4814E Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)