HB56UW873E-A Series 64MB Buffered EDO DRAM DIMM 8-Mword × 72-bit, 4k Refresh, 1 Bank Module (9 pcs of 8M × 8 components) ADE-203-821B (Z) Rev. 2.0 Nov. 20, 1997 Description The HB56UW873E-A belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56UW873E-A is a 8M × 72 dynamic RAM module, mounted 9 pieces of 64-Mbit DRAM (HM5165805A) sealed in TSOP package and 2 pieces of 16-bit BiCMOS line driver sealed in TSSOP package. The HB56UW873E-A offers Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56UW873E-A is 168-pin socket type package (dual lead out). Therefore, the HB56UW873E-A makes high density mounting possible without surface mount technology. The HB56UW873E-A provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the its module board. Features • 168-pin socket type package (Dual lead out) Lead pitch: 1.27 mm • Single 3.3 V supply: 3.3 V +0.3 V/–0.15 V (HB56UW873E-5AR) 3.3 V ± 0.3 V (HB56UW873E-6A/7A) • High speed Access time: tRAC = 50 ns /60 ns /70 ns (max) Access time: tCAC = 18 ns /20 ns /23 ns (max) • Low power dissipation Active mode: 6.32 mW/5.38 W/4.73 W (max) Standby mode (TTL): 100 mW (max) • Buffered input except RAS and DQ • 4 byte interleave enabled, dual address input (A0/B0) • EDO page mode capability • 4,096 refresh cycle: 64 ms • 2 variations of refresh RAS-only refresh CAS-before-RAS refresh This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Ordering Information Type No. Access time Package Contact pad HB56UW873E-5AR HB56UW873E-6A HB56UW873E-7A 50 ns 60 ns 70 ns 168-pin dual lead out socket type Gold Pin Arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin Pin Arrangement (cont) Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 43 VSS 85 VSS 127 VSS 2 DQ0 44 OE2 86 DQ36 128 NC 3 DQ1 45 RE2 87 DQ37 129 NC 4 DQ2 46 CE4 88 DQ38 130 NC 5 DQ3 47 NC 89 DQ39 131 NC 6 VCC 48 WE2 90 VCC 132 PDE 7 DQ4 49 VCC 91 DQ40 133 VCC 8 DQ5 50 NC 92 DQ41 134 NC 9 DQ6 51 NC 93 DQ42 135 NC 10 DQ7 52 DQ18 94 DQ43 136 DQ54 11 DQ8 53 DQ19 95 DQ44 137 DQ55 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ20 97 DQ45 139 DQ56 2 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Pin Arrangement (cont) Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 14 DQ10 56 DQ21 98 DQ46 140 DQ57 15 DQ11 57 DQ22 99 DQ47 141 DQ58 16 DQ12 58 DQ23 100 DQ48 142 DQ59 17 DQ13 59 VCC 101 DQ49 143 VCC 18 VCC 60 DQ24 102 VCC 144 DQ60 19 DQ14 61 NC 103 DQ50 145 NC 20 DQ15 62 NC 104 DQ51 146 NC 21 DQ16 63 NC 105 DQ52 147 NC 22 DQ17 64 NC 106 DQ53 148 NC 23 VSS 65 DQ25 107 VSS 149 DQ61 24 NC 66 DQ26 108 NC 150 DQ62 25 NC 67 DQ27 109 NC 151 DQ63 26 VCC 68 VSS 110 VCC 152 VSS 27 WE0 69 DQ28 111 NC 153 DQ64 28 CE0 70 DQ29 112 NC 154 DQ65 29 NC 71 DQ30 113 NC 155 DQ66 30 RE0 72 DQ31 114 NC 156 DQ67 31 OE0 73 VCC 115 NC 157 VCC 32 VSS 74 DQ32 116 VSS 158 DQ68 33 A0 75 DQ33 117 A1 159 DQ69 34 A2 76 DQ34 118 A3 160 DQ70 35 A4 77 DQ35 119 A5 161 DQ71 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 PD1 121 A9 163 PD2 38 A10 80 PD3 122 A11 164 PD4 39 NC 81 PD5 123 NC 165 PD6 40 VCC 82 PD7 124 VCC 166 PD8 41 NC 83 ID0 (VSS) 125 NC 167 ID1 (VSS) 42 NC 84 VCC 126 B0 168 VCC 3 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Pin Description Pin name Function A0 to A11, B0 Address input (D0 to D8) Row address (D0 to D8) Column address (D0 to D8) Refresh address (D0 to D8) DQ0 to DQ71 Data-in/Data-out RE0, RE2 Row address strobe (RAS) CE0, CE4 Column address strobe (CAS) WE0, WE2 Read/Write enable OE0, OE2 Output enable VCC Power supply VSS Ground PD1 to PD8 Presence detect ID0, ID1 ID bit PDE Presence detect enable NC Non connection : : : : A0 to A11, B0 A0 to A11, B0 A0 to A10, B0 A0 to A11, B0 Presence Detect Pin Assignment PDE = Low PDE = High Pin name Pin No. 50 ns 60 ns 70ns All PD1 79 1 1 1 High-Z PD2 163 0 0 0 High-Z PD3 80 1 1 1 High-Z PD4 164 1 1 1 High-Z PD5 81 1 1 1 High-Z PD6 165 0 1 0 High-Z PD7 82 0 1 1 High-Z PD8 166 0 0 0 High-Z 1 : High level (driver output) 0 : Low level (driver output) 4 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Block Diagram RE0 CE0 WE0 OE0 RE2 CE4 WE2 OE2 CAS RAS WE I/O I/O I/O D0 I/O I/O I/O I/O I/O OE DQ36 DQ37 DQ38 DQ39 DQ0 DQ1 DQ2 DQ3 CAS RAS WE I/O I/O I/O D1 I/O I/O I/O I/O I/O OE DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 CAS RAS WE I/O I/O I/O D2 I/O I/O I/O I/O I/O OE DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 CAS RAS WE I/O I/O I/O D3 I/O I/O I/O I/O I/O OE DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 CAS RAS WE I/O I/O I/O D4 I/O I/O I/O I/O I/O OE DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 A0 D0 to D4 B0 D5 to D8 A1 to A11 D0 to D8 VCC VSS CAS RAS WE OE DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D6 I/O I/O I/O I/O I/O OE DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CAS RAS WE I/O I/O I/O D7 I/O I/O I/O I/O I/O OE DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CAS RAS WE I/O I/O I/O D8 I/O I/O I/O I/O I/O OE DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 D5 PD1 to PD8 VCC PD1 VSS PD2 VCC PD3 VCC PD4 VCC PD5 VCC VSS VCC VSS VSS PD6 PD7 PD8 D0 to D8, 16-bit line driver 0.22 µF × 11 pcs D0 to D8,16-bit line driver * D0 to D8 : HM5165805 : 16-bit line driver 5 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –0.5 to +4.6 V Supply voltage relative to VSS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation Pt 10 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to 70°C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC (HB56UW873E-5AR) 3.15 3.3 3.6 V 1, 2 VCC (HB56UW873E-6A/7A) 3.0 3.3 3.6 V 1, 2 Input high voltage VIH 2.0 — VCC + 0.3 V 1 Input low voltage –0.3 — 0.8 1 Note: VIL V 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 6 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V +0.3 V/–0.15 V, VSS = 0 V) (HB56UW873E-5AR) (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB56UW873E-6A/7A) HB56UW873E-A 50 ns Parameter 60 ns 70 ns Symbol Min Max Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — 1765 — 1495 — 1315 mA t RC = min Standby current I CC2 — 28 — 28 — 28 mA TTL interface RAS, CAS = VIH Dout = High-Z — 19 — 19 — 19 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 1765 — 1495 — 1315 mA t RC = min Standby current* I CC5 — 55 55 55 RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 1540 — 1270 — 1090 mA t RC = min EDO page mode current*1, * 3 I CC7 — 1360 — 1135 — 1000 mA t HPC = min Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA 1 RAS-only refresh current*2 1 — — mA Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC . Capacitance (Ta = 25˚C, VCC = 3.3 V +0.3 V/–0.15 V, VSS = 0 V) (HB56UW873E-5AR) (Ta = 25˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB56UW873E-6A/7A) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 20 pF 1 Input capacitance (CAS, WE, OE) CI2 — 20 pF 1 Input capacitance (RAS) CI3 — 55 pF 1 I/O capacitance (DQ) CI/O — 20 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 7 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series AC Characteristics*1, *2 , *17 (Ta = 0 to +70°C, VCC = 3.3 V +0.3 V/–0.15 V, VSS = 0 V) (HB56UW873E-5AR) (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB56UW873E-6A/7A) Test Conditions • • • • • Input rise and fall times: 2 ns Input levels: VIL = 0 V, V IH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load:1 TTL gate + C L (50 pF) (Including scope and jig) (HB56UW873E-5AR) 1 TTL gate + CL (100 pF) (Including scope and jig) (HB56UW873E-6A/7A) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 84 — 104 — 124 — ns RAS precharge time t RP 30 — 40 — 50 — ns CAS precharge time t CP 8 — 10 — 13 — ns RAS pulse width t RAS 50 10000 60 10000 70 10000 ns CAS pulse width t CAS 8 10000 10 10000 13 10000 ns Row address setup time t ASR 5 — 5 — 5 — ns Row address hold time t RAH 8 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 8 — 10 — 13 — ns RAS to CAS delay time t RCD 12 32 20 40 20 47 ns 3 RAS to column address delay time t RAD 10 20 14 25 14 30 ns 4 RAS hold time t RSH 18 — 20 — 23 — ns CAS hold time t CSH 40 — 48 — 58 — ns CAS to RAS precharge time t CRP 10 — 10 — 10 — ns OE to Din delay time t OED 18 — 20 — 23 — ns 5 OE delay time from Din t DZO 0 — 0 — 0 — ns 6 CAS delay time from Din t DZC 0 — 0 — 0 — ns 6 Transition time (rise and fall) tT 2 50 2 50 2 50 ns 7 8 This Material Copyrighted by Its Respective Manufacturer Notes 21 HB56UW873E-A Series Read Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 — 70 ns 8, 9 Access time from CAS t CAC — 18 — 20 — 23 ns 9, 10, 16 Access time from address t AA — 30 — 35 — 40 ns 9, 11, 16 Access time from OE t OEA — 18 — 20 — 23 ns 9 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — 0 — ns Read command hold time from RAS t RCHR 50 — 60 — 70 — ns Read command hold time to RAS t RRH 5 — 0 — 0 — ns Column address to RAS lead time t RAL 30 — 35 — 40 — ns Column address to CAS lead time t CAL 15 — 18 — 23 — ns CAS to output in low-Z t CLZ 2 — 2 — 2 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 20 — 20 — 20 ns 13, 20 Output buffer turn-off to OE t OEZ — 18 — 20 — 20 ns 13 CAS to Din delay time t CDD 18 — 20 — 23 — ns 5 Output data hold time from RAS t OHR 3 — 3 — 3 — ns 20 Output buffer turn-off to RAS t OFR — 13 — 15 — 15 ns 13, 20 Output buffer turn-off to WE t WEZ — 18 — 20 — 20 ns 13 WE to Din delay time t WED 18 — 20 — 23 — ns RAS to Din delay time t RDD 13 — 15 — 18 — ns 12 12 20 Write Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 14 Write command hold time t WCH 8 — 10 — 13 — ns Write command pulse width t WP 8 — 10 — 10 — ns Write command to RAS lead time t RWL 18 — 20 — 23 — ns Write command to CAS lead time t CWL 10 — 10 — 13 — ns Data-in setup time t DS 0 — 0 — 0 — ns Data-in hold time t DH 13 — 15 — 18 — ns 9 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Read-Modify-Write Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 111 — 154 — 180 — ns RAS to WE delay time t RWD 72 — 83 — 96 — ns 14 CAS to WE delay time t CWD 30 — 33 — 39 — ns 14 Column address to WE delay time t AWD 42 — 48 — 56 — ns 14 OE hold time from WE t OEH 13 — 15 — 18 — ns Refresh Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 10 — 10 — 10 — ns CAS hold time (CBR refresh cycle) t CHR 8 — 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 5 — 5 — 5 — ns WE hold time (CBR refresh cycle) t WRH 10 — 10 — 10 — ns RAS precharge to CAS hold time t RPC 5 — 0 — 0 — ns Notes EDO Page Mode Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 30 ns 19 EDO page mode RAS pulse width t RASP — 100000 — 100000 — 100000 ns 15 Access time from CAS precharge t CPA — 33 — 40 — 45 ns 9, 16 RAS hold time from CAS precharge t CPRH 33 — 40 — 45 — ns Output data hold time from CAS low t DOH 3 — 3 — 3 — ns CAS hold time referred OE t COL 8 — 10 — 13 — ns CAS to OE setup time t COP 8 — 10 — 10 — ns Read command hold time from CAS precharge t RCHC 28 — 35 — 40 — ns Write pulse width during CAS precharge t WPE 8 — 10 — 10 — ns OE precharge time 8 — 10 — 10 — ns 10 This Material Copyrighted by Its Respective Manufacturer t OEP — — 9 HB56UW873E-A Series EDO Page Mode Read-Modify-Write Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit EDO page mode read- modify-write cycle time t HPRWC 57 — 68 — 79 — ns WE delay time from CAS precharge t CPW 45 — 54 — 62 — ns Notes 14 Refresh Parameter Symbol Max Unit Notes Refresh period t REF 64 ms 4096 cycles Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 50 pF (HB56UW873E-5AR) and 1 TTL loads and 100 pF (HB56UW873/EJE-6A/7A). 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t RASP defines RAS pulse width in EDO page mode cycles. 16. Access time is determined by the longest among t AA , t CAC and t CPA. 17. All the V CC and VSS pins shall be supplied with the same voltages. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 11 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series 19. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 20. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between tOFR and t OFF. 21. t CSH (min) can be achieved when tRCD ≤ tCSH (min) – tCAS (min). 22. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 12 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Timing Waveform *22 Read Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tT tRSH tCAS CAS tRAD tASR Address tRAH tRAL tCAL tASC tCAH Column Row tRRH tRCHR tRCS tRCH WE tDZC tCDD tWED tRDD High-Z Din tDZO tOEA tOED OE tOEZ tOHO tOFF tOH tOFR tOHR tCAC tAA tRAC tCLZ tWEZ Dout Dout 13 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din Dout tDH Din High-Z* * t WCS 14 This Material Copyrighted by Its Respective Manufacturer t WCS (min) HB56UW873E-A Series Delayed Write Cycle *18 tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH tASC Row tCAH Column tCWL tRWL tWP tRCS WE tDS tDZC Din High-Z Din tOED tDZO tDH tOEH tOEP OE tOEZ tCLZ High-Z Dout Invalid Dout 15 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Read-Modify-Write Cycle *18 tRWC tRAS tRP RAS tT tRCD tCAS tCRP CAS tRAD tASR Address tASC tRAH Row tCAH Column tCWL tCWD tRCS tRWL tWP tAWD tRWD WE tDZC tDS High-Z Din Din tDH tOED tDZO tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout tCLZ 16 This Material Copyrighted by Its Respective Manufacturer High-Z HB56UW873E-A Series RAS-Only Refresh Cycle tRC tRAS tRP RAS tT tRPC tCRP tCRP CAS tASR tRAH Row Address tOFR tOFF High-Z Dout 17 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR t CHR t RPC tT CAS t CP t WRP t WRH t CP WE Address t OFR t OFF Dout 18 This Material Copyrighted by Its Respective Manufacturer High-Z t CRP HB56UW873E-A Series EDO Page Mode Read Cycle t RP t HPC t RASP RAS tT t CSH t CP t HPC t CAS CAS t HPC t CPRH t CP t t CRP RSH t CAS t RCHR t RCS t CP tCAS tCAS t RCHC t RCH t RCS t RRH t RCH WE tASR Address tRAH tASC Row tCAH Column 1 t WPE t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC High-Z Din tCOL tDZO tCOP t OEP tOED tOEP OE tAA tCAC tCAC tAA tWEZ tCPA tAA tCAC tOEZ tOHO tDOH Dout 2 Dout 2 tOHO Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 Dout 1 tAA tOEZ tOEA tRAC Dout tOFR tOHR tOEZ tCPA tCPA tOEA 19 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series EDO Page Mode Early Write Cycle tRP tRASP RAS tT tCSH tHPC tCAS tRCD tCP tRSH tCAS tCP tCAS tCRP CAS tASR Address tRAH Row tASC tCAH Column 1 tWCS tWCH tASC tCAH Column 2 tWCS tWCH tASC tCAH Column N tWCS tWCH WE tDS Din Dout tDH Din 1 tDS tDH Din 2 tDS tDH Din N High-Z* * t WCS 20 This Material Copyrighted by Its Respective Manufacturer t WCS (min) HB56UW873E-A Series EDO Page Mode Delayed Write Cycle *18 tRASP tRP RAS tT tCP tRCD tCRP tCP tCSH tHPC tCAS tCAS tRSH tCAS CAS tRAD tASR tASC tCAH tASC tCAH Column 1 Column 2 tRAH Address Row tASC tCAH tCWL Column N tCWL tCWL tRWL tRCS tRCS tRCS WE tWP tDZC tDS tWP tDZC tDS tWP tDZC tDS tDH tDH Din 1 Din tDZO tOED tDH Din 2 tDZO tOED tOEP tOEH tDZO tOED tOEP tOEH tOEP tOEH Din N OE tCLZ tCLZ tOEZ tCLZ tOEZ tOEZ Dout Invalid Dout Invalid Dout High-Z Invalid Dout 21 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series EDO Page Mode Read-Modify-Write Cycle *18 t RASP t RP RAS tT t HPRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t ASC t CAH Column 2 t RWD t CWL t AWD t CPW t CWL t CPW t AWD t RCS t CWD Column N t CWL t AWD t RCS t CWD t RWL t CWD WE t RCS t WP t t DZC DS t WP t t DZC DS t WP t t DZC DS t DH t DH Din 1 Din t DZO t OED t OEP t OEH t DH Din 2 t OED t DZO t OEP t OEH Din N t OED t DZO t OEP t OEH OE t OHO t OHO t OHO t OEA t CAC t OEA t CAC t AA t OEA t CAC t AA t CPA t RAC t OEZ t CLZ t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 22 This Material Copyrighted by Its Respective Manufacturer Dout 2 Dout N HB56UW873E-A Series EDO Page Mode Mix Cycle (1) * 19 t RP t RASP RAS tT t CAS CAS t CRP t CP t CP t CP t CAS tCAS tCAS t CSH tRSH t RCD t WCS t WCH tCPW tAWD WE t ASC tRAH tASR Address Row tCAH Column 1 t RRH t RCH t RCS t RCS t ASC t CAH tASC t CAH Column 2 Column 3 tWP tASC t RAL t CAH Column 4 t CAL t DS Din Din 1 tRDD tCDD t CAL t DH t DH t DS High-Z Din 3 tOED tOEP tWED OE tCPA tAA tCAC Dout tOFR tWEZ tCPA tCPA tAA tOEA t DOH Dout 2 t OEZ tCAC t OHO Dout 3 tAA tOEZ tCAC tOHO tOEA tOFF tOH Dout 4 23 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series EDO Page Mode Mix Cycle (2) * 19 t RP t RASP RAS tT t CSH t CAS CAS t RCD t CAS tCAS t RCH tWCS t WCH tRAH Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL t RRH t RCH tWP tCPW t ASC tRSH t RCS t RCS WE Address tCAS t RCHR t RCS tASR t CRP t CP t CP t CP t RAL t CAH tASC Column 4 t CAL t CAL t DS t DS High-Z Din t DH tRDD tCDD t DH Din 2 Din 3 t OEP t OEP tOED tOED tCOP tWED tCOL OE t OEA tAA tOEA tCAC tOEZ tCPA tAA tCAC tRAC tOEZ t OHO t OHO Dout 24 This Material Copyrighted by Its Respective Manufacturer Dout 1 tOFR tWEZ tCPA Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 HB56UW873E-A Series Physical Outline HB56UW873E-A Series Unit: mm inch Front side 133.35 5.250 3.00 0.118 4.00 max 0.157 max 4.00 min 0.157 min 127.35 5.014 3.00 0.118 Component area (Front) 1 84 B C 11.43 8.89 0.350 0.450 A 36.83 1.450 1.27 ± 0.10 0.050 ±0.004 54.61 2.150 Back side Detail B and C 1.27 0.050 3.175 0.125 3.125 ± 0.125 0.123 ± 0.005 0.25 max 0.010 max 2.54 min 0.100 min 1.00 ± 0.05 0.039 ± 0.002 25.40 1.000 85 Detail A 17.78 0.700 168 Component area (Back) 4.00 0.157 2 – φ 3.00 2 – φ 0.118 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004 25 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 26 This Material Copyrighted by Its Respective Manufacturer HB56UW873E-A Series Revision Record Rev. Date 1.0 Contents of Modification Sep. 12, 1997 Initial issue Drawn by Approved by Y. Saitou K. Tsuneda (referred to HM5164805A/5165805A Series rev. 1.0) 2.0 Nov. 20, 1997 (referred to HM5164805A/5165805A Series rev. 2.0) Addition of HB56UW873E-5AR Series Deletion of driver name 74LVT16244 from Description Recommended DC operating conditions Addition of note 2 Block Diagram 74LVT16244 to 16-bit line driver AC Characteristics t RAD min: 14/15 ns to 10/14/14 ns Timing waveforms Correct errors: EDO page mode mix cycle (1) 27 This Material Copyrighted by Its Respective Manufacturer