HB56AW873E-5/6 64MB Buffered FP DRAM DIMM 8-Mword × 72-bit, 4k Refresh, 1 Bank Module (9 pcs of 8M × 8 components) ADE-203-858A (Z) Rev.1.0 Jul. 31, 1998 Description The HB56AW873E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56AW873E is a 8M × 72 dynamic RAM module, mounted 9 pieces of 64-Mbit DRAM (HM5165800) sealed in TSOP package and 2 pieces of 16-bit BiCMOS line driver sealed in TSSOP package. An outline of the HB56AW873E is 168-pin socket type package (dual lead out). Therefore, the HB56AW873E makes high density mounting possible without surface mount technology. The HB56AW873E provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the its module board. Features • 168-pin socket type package (Dual lead out) Lead pitch: 1.27 mm • Single 3.3 V supply: 3.3 V ± 0.3 V • High speed Access time: tRAC = 50/60 ns (max) Access time: tCAC = 18/20 ns (max) • Low power dissipation Active mode: 4.41/3.76 W (max) Standby mode (TTL): 100.8 mW (max) • Buffered input except RAS and DQ • 4 byte interleave enabled, dual address input (A0/B0) • Fast page mode capability • 4,096 refresh cycle: 64 ms • 2 variations of refresh RAS-only refresh CAS-before-RAS refresh This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Ordering Information Type No. Access time Package Contact pad HB56AW873E-5 50 ns 168-pin dual lead out socket type Gold HB56AW873E-6 60 ns Pin Arrangement Front side Back side 1 pin 10 pin 11 pin 85 pin 94 pin 95 pin 40 pin 41 pin 124 pin 125 pin 84 pin 168 pin Pin Arrangement Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 43 VSS 85 VSS 127 VSS 2 DQ0 44 OE2 86 DQ36 128 NC 3 DQ1 45 RE2 87 DQ37 129 NC 4 DQ2 46 CE4 88 DQ38 130 NC 5 DQ3 47 NC 89 DQ39 131 NC 6 VCC 48 WE2 90 VCC 132 PDE 7 DQ4 49 VCC 91 DQ40 133 VCC 8 DQ5 50 NC 92 DQ41 134 NC 9 DQ6 51 NC 93 DQ42 135 NC 10 DQ7 52 DQ18 94 DQ43 136 DQ54 11 DQ8 53 DQ19 95 DQ44 137 DQ55 12 VSS 54 VSS 96 VSS 138 VSS 2 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Pin Arrangement (cont) Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 13 DQ9 55 DQ20 97 DQ45 139 DQ56 14 DQ10 56 DQ21 98 DQ46 140 DQ57 15 DQ11 57 DQ22 99 DQ47 141 DQ58 16 DQ12 58 DQ23 100 DQ48 142 DQ59 17 DQ13 59 VCC 101 DQ49 143 VCC 18 VCC 60 DQ24 102 VCC 144 DQ60 19 DQ14 61 NC 103 DQ50 145 NC 20 DQ15 62 NC 104 DQ51 146 NC 21 DQ16 63 NC 105 DQ52 147 NC 22 DQ17 64 NC 106 DQ53 148 NC 23 VSS 65 DQ25 107 VSS 149 DQ61 24 NC 66 DQ26 108 NC 150 DQ62 25 NC 67 DQ27 109 NC 151 DQ63 26 VCC 68 VSS 110 VCC 152 VSS 27 WE0 69 DQ28 111 NC 153 DQ64 28 CE0 70 DQ29 112 NC 154 DQ65 29 NC 71 DQ30 113 NC 155 DQ66 30 RE0 72 DQ31 114 NC 156 DQ67 31 OE0 73 VCC 115 NC 157 VCC 32 VSS 74 DQ32 116 VSS 158 DQ68 33 A0 75 DQ33 117 A1 159 DQ69 34 A2 76 DQ34 118 A3 160 DQ70 35 A4 77 DQ35 119 A5 161 DQ71 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 PD1 121 A9 163 PD2 38 A10 80 PD3 122 A11 164 PD4 39 NC 81 PD5 123 NC 165 PD6 40 VCC 82 PD7 124 VCC 166 PD8 41 NC 83 ID0 (VSS) 125 NC 167 ID1 (VSS) 42 NC 84 VCC 126 B0 168 VCC 3 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Pin Description Pin name Function A0 to A11, B0 Address Input (D0 to D8) : Row Address (D0 to D8) : Column Address (D0 to D8) : Refresh Address (D0 to D8) : DQ0 to DQ71 Data-in/Data-out RE0, RE2 Row Address Strobe (RAS) CE0, CE4 Column Address Strobe (CAS) WE0, WE2 Read/Write Enable OE0, OE2 Output Enable VCC Power Supply VSS Ground PD1 to PD8 Presence Detect ID0, ID1 ID bit PDE Presence Detect Enable NC Non Connection A0 to A11, B0 A0 to A11, B0 A0 to A10, B0 A0 to A11, B0 Presence Detect Pin Assignment PDE = Low PDE = High Pin name Pin No. 50 ns 60 ns All PD1 79 1 1 High-Z PD2 163 0 0 High-Z PD3 80 1 1 High-Z PD4 164 1 1 High-Z PD5 81 0 0 High-Z PD6 165 0 1 High-Z PD7 82 0 1 High-Z PD8 166 0 0 High-Z 1 : High Level (Driver Output) 0 : Low Level (Driver Output) 4 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Block Diagram RE0 CE0 WE0 OE0 RE2 CE4 WE2 OE2 CAS RAS WE I/O I/O I/O D0 I/O I/O I/O I/O I/O OE DQ36 DQ37 DQ38 DQ39 DQ0 DQ1 DQ2 DQ3 CAS RAS WE I/O I/O I/O D1 I/O I/O I/O I/O I/O OE DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 CAS RAS WE I/O I/O I/O D2 I/O I/O I/O I/O I/O OE DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 CAS RAS WE I/O I/O I/O D3 I/O I/O I/O I/O I/O OE DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 CAS RAS WE I/O I/O I/O D4 I/O I/O I/O I/O I/O OE DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 A0 D0 to D4 B0 D5 to D8 A1 to A11 D0 to D8 OE I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS CAS RAS WE I/O I/O I/O D6 I/O I/O I/O I/O I/O OE DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CAS RAS WE I/O I/O I/O D7 I/O I/O I/O I/O I/O OE DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CAS RAS WE I/O I/O I/O D8 I/O I/O I/O I/O I/O OE DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 D5 PD1 to PD8 VCC PD1 VSS PD2 VCC PD3 VCC PD4 VCC PD5 VCC VSS VCC VSS VSS PD6 PD7 PD8 D0 to D8, 16-bit line driver VCC VSS WE DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 0.22 µF × 11 pcs D0 to D8,16-bit line driver * D0 to D8 : HM5165800 : 16-bit line driver 5 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Absolute Maximum Ratings Parameter Symbol Value Unit Terminal voltage on any pin relative to V SS VT –0.5 to +4.6 V Power supply voltage relative to V SS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation Pt 10 W Storage temperature range Tstg –55 to +125 °C DC Operating Conditions Parameter Symbol Min Typ Max Unit Note Supply voltage VCC 3.0 3.3 3.6 V 1, 2 VSS 0 0 0 V 2 Input high voltage VIH 2.0 — VCC + 0.3 V 1 Input low voltage VIL –0.3 — 0.8 V 1 Ambient temperature Ta 0 — 70 °C Note: 1. All voltage referenced to V SS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 6 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 DC Characteristics 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Test condition Note Operating current I CC1 — 1225 — 1045 mA t RC = min 1, 2 Standby current I CC2 — 28 — 28 mA TTL interface RAS, CAS = VIH Dout = High-Z — 14.5 — 14.5 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z RAS-only refresh current I CC3 — 1225 — 1045 mA t RC = min 2 Standby current I CC5 — 55 — 55 mA RAS = VIH, CAS = VIL Dout = enable 1 CAS-before-RAS refresh current I CC6 — 1225 — 1045 mA t RC = min Fast page mode current I CC7 — 910 — 820 mA RAS = VIL , CAS cycle, t PC = tPC min Input leakage current I LI –5 5 –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO –5 5 –5 5 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA 1, 3 Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per fast page mode cycle, t PC. Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 20 pF 1 Input capacitance (CAS, WE, OE) CI2 — 20 pF 1 Input capacitance (RAS) CI3 — 55 pF 1 I/O capacitance (DQ) CI/O — 20 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 7 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 AC Characteristics (Ta = 0 to 70°C, VCC = 3.3 V ±0.3 V, VSS = 0 V)*1, *2, *19 Test Conditions • • • • • Input rise and fall times: 5 ns Input levels: VIL = 0 V, V IH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Random read or write cycle time t RC 90 — 110 — ns RAS precharge time t RP 30 — 40 — ns CAS precharge time t CP 8 — 10 — ns RAS pulse width t RAS 50 10000 60 10000 ns CAS pulse width t CAS 13 10000 15 10000 ns Row address setup time t ASR 5 — 5 — ns Row address hold time t RAH 8 — 10 — ns Column address setup time t ASC 0 — 0 — ns Column address hold time t CAH 8 — 10 — ns RAS to CAS delay time t RCD 18 32 20 40 ns 3 RAS to column address delay time t RAD 13 20 15 25 ns 4 RAS hold time t RSH 18 — 20 — ns CAS hold time t CSH 50 — 60 — ns CAS to RAS precharge time t CRP 10 — 10 — ns OE to Din delay time t OED 18 — 20 — ns 5 OE delay time from Din t DZO 0 — 0 — ns 6 CAS delay time from Din t DZC 0 — 0 — ns 6 Transition time (rise and fall) tT 3 50 3 50 ns 7 8 This Material Copyrighted by Its Respective Manufacturer Notes HB56AW873E-5/6 Read Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 ns 8, 9 Access time from CAS t CAC — 18 — 20 ns 9, 10, 17 Access time from address t AA — 30 — 35 ns 9, 11, 17 Access time from OE t OEA — 18 — 20 ns 9 Read command setup time t RCS 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — ns 12 Read command hold time to RAS t RRH 0 — 0 — ns 12 Column address to RAS lead time t RAL 30 — 35 — ns Column address to CAS lead time t CAL 25 — 30 — ns CAS to output in low-Z t CLZ 2 — 2 — ns Output data hold time t OH 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — ns Output buffer turn-off time t OFF — 18 — 20 ns 13 Output buffer turn-off to OE t OEZ — 18 — 20 ns 13 CAS to Din delay time t CDD 18 — 20 — ns 5 Write Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — ns 14 Write command hold time t WCH 8 — 10 — ns Write command pulse width t WP 8 — 10 — ns Write command to RAS lead time t RWL 18 — 20 — ns Write command to CAS lead time t CWL 13 — 15 — ns Data-in setup time t DS 0 — 0 — ns 15 Data-in hold time t DH 13 — 15 — ns 15 9 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Read-Modify-Write Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 131 — 155 — ns RAS to WE delay time t RWD 73 — 85 — ns 14 CAS to WE delay time t CWD 36 — 40 — ns 14 Column address to WE delay time t AWD 48 — 55 — ns 14 OE hold time from WE t OEH 13 — 15 — ns Refresh Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 10 — 10 — ns CAS hold time (CBR refresh cycle) t CHR 8 — 10 — ns WE setup time (CBR refresh cycle) t WRP 5 — 5 — ns WE hold time (CBR refresh cycle) t WRH 8 — 10 — ns RAS precharge to CAS hold time t RPC 5 — 5 — ns Notes Fast Page Mode Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Fast page mode cycle time t PC 35 — 40 — ns Fast page mode RAS pulse width t RASP — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 35 — 40 ns 9, 17 RAS hold time from CAS precharge t CPRH 35 — 40 — ns Fast Page Mode Read-Modify-Write Cycle 50 ns Parameter Min Max Min Max Unit Fast page mode read-modify-write cycle t HPRWC time 76 — 85 — ns WE delay time from CAS precharge 53 — 60 — ns 10 This Material Copyrighted by Its Respective Manufacturer Symbol 60 ns t CPW Notes 14 HB56AW873E-5/6 Refresh Parameter Symbol Min Unit Notes Refresh period t REF 64 ms 4096 cycles Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS, t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 20. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 11 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Timing Waveform *20 Read Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tRAD tASR Address tRAH tRAL tCAL tASC Row tCAH Column tRRH tRCS tRCH WE tDZC tCDD High-Z Din tDZO tOEA tOED OE tOEZ tOHO tCAC tAA tRAC tCLZ Dout 12 This Material Copyrighted by Its Respective Manufacturer tOFF tOH Dout HB56AW873E-5/6 Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din Dout tDH Din High-Z* * t WCS t WCS (min) 13 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Delayed Write Cycle *18 tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH tASC Row tCAH Column tCWL tRWL tWP tRCS WE tDS tDZC Din High-Z Din tOED tDZO tDH tOEH OE tOEZ tCLZ High-Z Dout Invalid Dout 14 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Read-Modify-Write Cycle *18 tRWC tRAS tRP RAS tT tRCD tCAS tCRP CAS tRAD tASR Address tASC tRAH Row tCAH Column tCWL tCWD tRCS tRWL tWP tAWD tRWD WE tDZC tDS High-Z Din Din tDH tOED tDZO tOEH tOEA OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ 15 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP t RPC CAS t ASR Address t RAH Row t OFF Dout 16 This Material Copyrighted by Its Respective Manufacturer High-Z t CRP HB56AW873E-5/6 CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RC t RP t RAS t RP RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR CAS t WRP t WRH t WRP t WRH WE Address t OFF High-Z Dout 17 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD t PC t CAS t CP t RSH t CAS t CP t CRP t CAS CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH t CAL t ASC t CAH t CAL t ASC t CAH Column 1 Column 2 Column N t RCS tRCS tRCH t RCS t RRH t RCH tRCH WE t DZC Din t DZC t CDD High-Z High-Z t OED t DZO t OED t CDD High-Z t DZO t OED t DZO t DZC t CDD OE t RAC t AA t OH t OEA 18 This Material Copyrighted by Its Respective Manufacturer t OHO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t CPA t AA Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N HB56AW873E-5/6 Fast Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH Address Row t ASC t CAH t ASC t CAH t ASC t CAH Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS t WCS (min) 19 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Fast Page Mode Delayed Write Cycle *18 t RASP t RP RAS tT t CP t CSH t RCD t CRP t CP t PC t CAS t RSH t CAS t CAS CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS WE t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din Din 2 t DZO Din N t DZO t DZO t DH t OED t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t OEZ t CLZ t OEZ t OEZ High-Z Dout Invalid Dout 20 This Material Copyrighted by Its Respective Manufacturer Invalid Dout Invalid Dout HB56AW873E-5/6 Fast Page Mode Read-Modify-Write Cycle *18 t RASP t RP RAS tT t PRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t ASR t RAD t ASC t RAH Address t ASC t CAH t CAH Row Column 1 t ASC t CAH Column 2 t RWD t CWL t AWD t CPW t CWL t AWD t RCS t CWD Column N t CPW t AWD t RCS t CWD t CWL t RWL t CWD WE t RCS t WP t t DZC DS t WP t t DZC DS t WP t t DZC DS t DH t DH Din 1 Din t DZO t OED t DH Din 2 t OED t DZO t OED t DZO t OEH t OEH t OEH Din N OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t OEA t CAC t AA t CPA t RAC t OEZ t CLZ t OHO t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 Dout 2 Dout N 21 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Physical Outline HB56AW873E Series Unit: mm inch Front side 133.35 5.250 3.00 0.118 4.00 max 0.157 max 4.00 min 0.157 min 127.35 5.014 3.00 0.118 Component area (Front) 1 84 B C 11.43 8.89 0.350 0.450 A 36.83 1.450 1.27 ± 0.10 0.050 ±0.004 54.61 2.150 Back side 22 This Material Copyrighted by Its Respective Manufacturer 3.175 0.125 3.125 ± 0.125 0.123 ± 0.005 0.25 max 0.010 max 2.54 min 0.100 min 1.00 ± 0.05 0.039 ± 0.002 Detail B and C 1.27 0.050 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004 25.40 1.000 85 Detail A 17.78 0.700 168 Component area (Back) 4.00 0.157 2 – φ 3.00 2 – φ 0.118 HB56AW873E-5/6 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA 94005-1897 Tel: <1> (800) 285-1601 Fax: <1> (303) 297-0447 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 23 This Material Copyrighted by Its Respective Manufacturer HB56AW873E-5/6 Revision Record Rev. Date 0.0 Nov. 19, 1997 Contents of Modification Drawn by Approved by Initial issue S.Tsukui K.Yoshizaki (referred to HM5164800/HM5165800 Series rev. 0.0) 1.0 Jul. 31, 1998 Deletion of Preliminary (referred to HM5164800/HM5165800 Series rev. 1.0) 24 This Material Copyrighted by Its Respective Manufacturer