HB56UW232D Series HB56UW432D Series 2,097,152-word × 32-bit High Density Dynamic RAM Module 4,194,304-word × 32-bit High Density Dynamic RAM Module ADE-203-784A (Z) Rev.1.0 May. 20, 1997 Description The HB56UW232D is a 2M × 32 dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 4 pieces of 16-Mbit DRAM (HM51W17805) sealed in TSOP package. The HB56UW432D is a 4M × 32 dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 8 pieces of 16-Mbit DRAM (HM51W17805) sealed in TSOP package. The HB56UW232D, HB56UW432D offer Extended Data Out (EDO) page mode as a high speed access mode. An outline of the HB56UW232D, HB56UW432D is 72-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the HB56UW232D, HB56UW432D make high density mounting possible without surface mount technology. The HB56UW232D, HB56UW432D provide common data inputs and outputs. Decoupling capacitors are mounted on the module board. Features • 72-pin Zig Zag Dual tabs socket type Outline: 59.69 mm (Length) × 25.40 mm (Height) × 2.42/3.80 mm (Thickness) Lead pitch: 1.27 mm • Single 3.3 V (±0.3 V) supply • High speed Access time: tRAC = 50/60/70 ns (max) tCAC = 13/15/18 ns (max) • Low power dissipation Active mode: 1.59/1.44/1.30 W (max) (HB56UW232D Series) 1.66/1.51/1.36 W (max) (HB56UW432D Series) Standby mode (TTL): 28.8/57.6 mW (max) (CMOS): 2.16/4.32 mW (max) (L-version) • EDO page mode capability • Refresh period 2048 refresh cycles: 32 ms 128 ms (L-version) • 4 variations of refresh This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) Ordering Information Type No. Access time Package Contact pad HB56UW232D-5 HB56UW232D -6 HB56UW232D -7 50 ns 60 ns 70 ns 72-pin small outline DIMM Gold HB56UW232D -5L HB56UW232D -6L HB56UW232D -7L 50 ns 60 ns 70 ns HB56UW432D -5 HB56UW432D -6 HB56UW432D -7 50 ns 60 ns 70 ns HB56UW432D -5L HB56UW432D -6L HB56UW432D -7L 50 ns 60 ns 70 ns 2 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Pin Arrangement 1 pin 71 pin Front side Back side 2 pin Front side 72 pin Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 37 DQ18 2 DQ0 38 DQ19 3 DQ1 39 VSS 4 DQ2 40 CE0 5 DQ3 41 CE2 6 DQ4 42 CE3 7 DQ5 43 CE1 8 DQ6 44 RE0 10 VCC 46 NC 9 DQ7 45 RE1(NC)* 11 PD1 47 WE 12 A0 48 NC 13 A1 49 DQ20 14 A2 50 DQ21 15 A3 51 DQ22 16 A4 52 DQ23 17 A5 53 DQ24 18 A6 54 DQ25 19 A10 55 NC 20 NC 56 DQ27 21 DQ9 57 DQ28 22 DQ10 58 DQ29 23 DQ11 59 DQ31 24 DQ12 60 DQ30 25 DQ13 61 VCC 26 DQ14 62 DQ32 27 DQ15 63 DQ33 28 A7 64 DQ34 29 NC 65 NC 30 VCC 66 PD2 31 A8 67 PD3 32 A9 68 PD4 33 RE3(NC)* 69 PD5 34 RE2 70 PD6 35 DQ16 71 PD7 36 NC 72 VSS 1 2 Notes: 1. RE3: HB56UW432D, NC: HB56UW232D 2. RE1: HB56UW432D, NC: HB56UW232D 3 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Pin Description Pin name Function A0 to A10 Address inputs: • Row address: A0 to A10 • Column address: A0 to A9 • Refresh address: A0 to A10 DQ0 to DQ7, DQ9 to DQ16, DQ18 to DQ25, DQ27 to DQ34 Data-in/Data-out RE0 to RE3 Row address strobe (RAS) CE0 to CE3 Column address strobe (CAS) WE Read/Write enable VCC Power supply VSS Ground PD1 to PD7 Presence detect NC No connection Presence Detect Pin Arrangement Function Pin No. Pin name 50 ns 60 ns 70 ns 11 PD1 VSS VSS VSS 66 PD2 NC NC NC 67 PD3 VSS VSS VSS 68 PD4 (HB56UW232D) NC NC NC PD4 (HB56UW432D) VSS VSS VSS 69 PD5 VSS NC VSS 70 PD6 VSS NC NC 71 PD7 NC NC NC PD7 (L-version) VSS VSS VSS 4 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Block Diagram (HB56UW232D) RE0 CE0 WE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O CAS I/O I/O I/O I/O I/O I/O I/O I/O CAS I/O I/O I/O I/O I/O I/O I/O I/O CAS I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE D0 OE CE1 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 RAS WE D1 OE RE2 CE2 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 RAS WE D2 OE CE3 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 RAS D3 A0 to A10 VCC VSS WE OE D0 to D3 0.22 µF × 4 pcs D0 to D3 D0 to D3 * D0 to D3: HM51W17805 5 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Block Diagram (HB56UW432D) WE RE1 RE0 CE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE D0 OE I/O I/O I/O I/O I/O I/O I/O I/O CAS I/O I/O I/O I/O I/O I/O I/O I/O CAS I/O I/O I/O I/O I/O I/O I/O I/O CAS I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE D4 OE CE1 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE D1 OE RAS WE D5 OE RE3 RE2 CE2 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE D2 OE RAS WE D6 OE CE3 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS D3 A0 to A10 VCC VSS * D0 to D7 WE OE D0 to D7 0.22 µF × 8 pcs : HM51W17805 6 This Material Copyrighted by Its Respective Manufacturer D0 to D7 D0 to D7 RAS WE D7 OE HB56UW232D Series, HB56UW432D Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –0.5 to +4.6 V Supply voltage relative to VSS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation Pt 4 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VSS 0 0 0 V VCC 3.0 3.3 3.6 V 1 Input high voltage VIH 2.0 — VCC +0.3 V 1 Input low voltage VIL –0.3 — 0.8 V 1 Note: Note 1. All voltage referred to VSS . 7 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series DC Characteristics (Ta = 0 to 70°C, VCC = 3.3 V ± 0.3V, VSS = 0 V) (HB56UW232D) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating current I CC1 — 440 — 400 — 360 mA t RC = min 1, 2 Standby current I CC2 — 8 — 8 — 8 mA TTL interface RAS, CAS = VIH Dout = High-Z — 4 — 4 — 4 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z — 0.6 — 0.6 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z Standby current (Lversion) I CC2 — 0.6 RAS-only refresh current I CC3 — 440 — 400 — 360 mA t RC = min 2 Standby current I CC5 — 20 20 20 RAS = VIH, CAS = VIL Dout = enable 1 CAS-before-RAS refresh current I CC6 — 440 — 400 — 360 mA t RC = min EDO page mode current I CC7 — 400 — 360 — 340 mA t HPC = min 1, 3 Battery backup current I CC10 (Standby with CBR refresh) (L-version) — 1.6 — 1.6 — 1.6 mA CMOS interface Dout = High-Z CBR refresh: t RC = 62.5 µs t RAS ≤ 0.3 µs 4 Self refresh mode current (L-version) I CC11 — 1 — 1 — 1 mA CMOS interface RAS, CAS ≤ 0.2 V Dout = High-Z Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 4.6 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 4.6 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA — — mA Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (≤ 0.2 V) while RAS = L (≤ 0.2 V). 8 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series DC Characteristics (Ta = 0 to 70°C, VCC = 3.3 V ± 0.3V, VSS = 0 V) (HB56UW432D) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating current I CC1 — 460 — 420 — 380 mA t RC = min 1, 2 Standby current I CC2 — 16 — 16 — 16 mA TTL interface RAS, CAS = VIH Dout = High-Z — 8 — 8 — 8 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z — 1.2 — 1.2 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z Standby current (Lversion) I CC2 — 1.2 RAS-only refresh current I CC3 — 460 — 420 — 380 mA t RC = min 2 Standby current I CC5 — 40 40 40 RAS = VIH, CAS = VIL Dout = enable 1 CAS-before-RAS refresh current I CC6 — 460 — 420 — 380 mA t RC = min EDO page mode current I CC7 — 420 — 380 — 360 mA t HPC = min 1, 3 Battery backup current I CC10 (Standby with CBR refresh) (L-version) — 3.2 — 3.2 — 3.2 mA CMOS interface Dout = High-Z CBR refresh: t RC = 62.5 µs t RAS ≤ 0.3 µs 4 Self refresh mode current (L-version) I CC11 — 2 — 2 — 2 mA CMOS interface RAS, CAS ≤ 0.2 V Dout = High-Z Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 4.6 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 4.6 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA — — mA Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (≤ 0.2 V) while RAS = L (≤ 0.2 V). 9 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HB56UW232D) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI! — 40 pF 1 Input capacitance (WE) CI2 — 48 pF 1 Input capacitance (RAS) CI3 — 30 pF 1 Input capacitance (CAS) CI4 — 23 pF 1 I/O capacitance (DQ) CI/O — 23 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HB56UW432D) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI! — 60 pF 1 Input capacitance (WE) CI2 — 76 pF 1 Input capacitance (RAS) CI3 — 30 pF 1 Input capacitance (CAS) CI4 — 30 pF 1 I/O capacitance (DQ) CI/O — 30 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to 70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2 , *18 Test Conditions • • • • • Input rise and fall times: 2 ns Input level: 0 V, 3.0V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) 10 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Read, Write, and Refresh Cycles (Common parameters) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 84 — 104 — 124 — ns RAS precharge time t RP 30 — 40 — 50 — ns CAS precharge time t CP 8 — 10 — 13 — ns RAS pulse width t RAS 50 10000 60 10000 70 10000 ns CAS pulse width t CAS 8 10000 10 10000 13 10000 ns Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 8 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 8 — 10 — 13 — ns RAS to CAS delay time t RCD 12 37 14 45 14 52 ns 3 RAS to column address delay time t RAD 10 25 12 30 12 35 ns 4 RAS hold time t RSH 10 — 13 — 13 — ns CAS hold time t CSH 35 — 40 — 45 — ns CAS to RAS precharge time t CRP 5 — 5 — 5 — ns CAS delay time from Din 0 — 0 — 0 — ns Transition time (rise and fall) t T 2 50 2 50 2 50 ns Refresh period (2,048 cycles) t REF — 32 — 32 — 32 ms Refresh period (2,048 cycles) (L-version) t REF — 128 — 128 — 128 ms t DZC Notes 5 11 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Read Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 — 70 ns 6, 7 Access time from CAS t CAC — 13 — 15 — 18 ns 7, 8, 15 Access time from address t AA — 25 — 30 — 35 ns 7, 9, 15 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to t RCH CAS 0 — 0 — 0 — ns Read command hold time from RAS 50 — 60 — 70 — ns Read command hold time to t RRH RAS 5 — 5 — 5 — ns Column address to RAS lead time t RAL 25 — 30 — 35 — ns Column address to CAS lead time t CAL 15 — 18 — 23 — ns CAS to output in low-Z t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns 19 Output buffer turn-off time t OFF — 13 — 15 — 15 ns 11, 19 CAS to Din delay time t CDD 13 — 15 — 18 — ns Output data hold time from RAS t OHR 3 — 3 — 3 — ns 19 Output buffer turn-off time to t OFR RAS — 13 — 15 — 15 ns 19 Output buffer turn-off to WE t WEZ — 13 — 15 — 15 ns WE to Din delay time t WED 13 — 15 — 18 — ns RAS to Din delay time t RDD 13 — 15 — 18 — ns 50 — 60 — 70 — ns t RCHR RAS to next CAS delay time t RNCD 10 10 Write Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 12 Write command hold time t WCH 8 — 10 — 13 — ns Write command pulse width t WP 8 — 10 — 10 — ns Data-in setup time t DS 0 — 0 — 0 — ns 13 Data-in hold time t DH 8 — 10 — 13 — ns 13 12 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Refresh Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 5 — 5 — 5 — ns CAS hold time (CBR refresh cycle) t CHR 8 — 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 0 — 0 — 0 — ns WE hold time (CBR refresh cycle) t WRH 8 — 10 — 10 — ns RAS precharge to CAS hold t RPC time 5 — 5 — 5 — ns Notes EDO Page Mode Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 — 30 — ns 16 EDO page mode RAS pulse t RASP width — 100000 — 100000 — 100000 ns 14 Access time from CAS precharge t CPA — 30 — 35 — 40 ns 7, 15 RAS hold time from CAS precharge t CPRH 30 — 35 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — 3 — ns Read command hold time from CAS precharge t RCHC 30 — 35 — 40 — ns 7, 15 Self Refresh Mode (L-version) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit RAS pulse width (Self refresh) t RASS 100 — 100 — 100 — µs RAS precharge time (Self refresh) t RPS 90 — 110 — 130 — ns –50 — –50 — –50 — ns CAS hold time (Self refresh) t CHS Notes 13 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD ≥ tRCD (max) + tAA (max) - tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 8. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 9. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) defines the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. Early write cycle only (tWCS ≥ tWCS (min)). 13. These parameters are referred to CAS leading edge in early write cycles. 14. t RASP defines RAS pulse width in EDO page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA. 16. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. 17. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / VSS line noise, which causes to degrade V IH min./ V IL max level. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH , and between t OFR and t OFF. 20. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use tRPS instead of tRP. 21. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 22. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 2048 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 23. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 24. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 14 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Timing Waveforms*24 Read Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t RAD t ASR Address t RAH t RAL t ASC t CAL t CAH Column Row t RRH t RCHR t RCH t RCS WE t WED t DZC t CDD t RDD High-Z Din t CAC t OFF t OH t OFR t OHR t AA t RAC t CLZ t WEZ Dout Dout 15 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Early Write Cycle t RC t RP t RAS RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t RAH Row t ASC t CAH Column t WP t WCS t WCH WE t DS Din Dout t DH Din High-Z* * t WCS 16 This Material Copyrighted by Its Respective Manufacturer t WCS (min) HB56UW232D Series, HB56UW432D Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP t RPC t CRP CAS t ASR Address t RAH Row t OFR t OFF High-Z Dout 17 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR t CHR t RPC tT CAS t CP t WRP t WRH t CP WE Address t OFR t OFF Dout 18 This Material Copyrighted by Its Respective Manufacturer High-Z t CRP HB56UW232D Series, HB56UW432D Series Hidden Refresh Cycle t RC t RC t RP t RAS t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD CAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t WRH t WRP t WRP tWRH t RRH t RCH t RCS t RRH WE t WED t DZC t CDD t RDD High-Z Din t CAC t AA t WEZ t RAC t OFF t OH t CLZ Dout Dout t OFR t OHR 19 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series EDO Page Mode Read Cycle t RP t RNCD t HPC t RASP RAS tT t CSH t CP t HPC t CAS CAS t HPC t CPRH t CP t t CRP RSH t CAS t RCHR t RCS t CP tCAS tCAS t RCHC t RCH t RCS t RRH t RCH WE tASR Address tRAH tASC Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL tASC t RAL t CAH t WED Column 4 t CAL t CAL tRDD tCDD tDZC High-Z Din tOFR tOHR tCPA tCPA tCPA tAA tCAC tAA tCAC tCAC tAA tWEZ tRAC Dout 20 This Material Copyrighted by Its Respective Manufacturer t AA t CAC tDOH Dout 1 Dout 2 tOFF tOH tDOH Dout 3 Dout 4 HB56UW232D Series, HB56UW432D Series EDO Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t CP t HPC t CAS t RSH t CAS t CP t CRP CAS t ASR t RAH Address Row t ASC t CAH t ASC tCAH t ASC t CAH Column 1 Column 2 Column N t WP t WP t WP t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS t WCS (min) 21 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Self Refresh Cycle (L-version)* 20, 21, 22, 23 t RASS t RP t RPS RAS tT t RPC t CP t CRP t CSR t CHS CAS t WRP t WRH WE t OFR t OFF Dout 22 This Material Copyrighted by Its Respective Manufacturer High-Z HB56UW232D Series, HB56UW432D Series Physical Outline HB56UW232D Series Unit : 51.66 2.034 Component area 1 7.62 0.300 71 44.45 1.750 A 3.00 min 0.118 min 44.45 1.750 72 2 Back side 8.25 0.325 1.80 0.071 2.00 0.079 2 – Ø1.80 2 – Ø0.071 1.00 ± 0.10 0.039 ± 0.004 17.78 0.700 25.40 1.000 3.18 0.125 2.42 max 0.095 max 3.18 min 0.125 min 5.00 0.197 2 – R3.00 min 2 – R0.118 min R2.00 R0.079 3.00 min 0.118 min 59.69 2.350 Front side mm inch 2 – R2.00 ± 0.10 2 – R0.079 ± 0.004 1.00±0.05 0.039±0.002 0.25 max 0.010 max 2.54 min 0.100 min Detail A 1.27 typ 0.050 typ 23 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Physical Outline HB56UW432D Series Unit : Component area (front) 1 7.62 0.300 71 44.45 1.750 A 3.00 min 0.118 min 8.25 0.325 44.45 1.750 2 2 – Ø1.80 2 – Ø0.071 72 Back side 1.80 0.071 2.00 0.079 Component area (back) 2 – R2.00 ± 0.10 2 – R0.079 ± 0.004 1.00±0.05 0.039±0.002 0.25 max 0.010 max 2.54 min 0.100 min Detail A 1.27 typ 0.050 typ 24 This Material Copyrighted by Its Respective Manufacturer 17.78 0.700 25.40 1.000 3.18 0.125 3.80 max 0.150 max 3.18 min 0.125 min 51.66 2.034 3.18 min 0.125 min 5.00 0.197 2 – R3.00 min 2 – R0.118 min R2.00 R0.079 3.00 min 0.118 min 59.69 2.350 Front side mm inch 1.00 ± 0.10 0.039 ± 0.004 HB56UW232D Series, HB56UW432D Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 25 This Material Copyrighted by Its Respective Manufacturer HB56UW232D Series, HB56UW432D Series Revision Record Rev. Date 1.0 Contents of Modification May. 20, 1997 (referred to HM51W17805 rev 3.0) Initial issue 26 This Material Copyrighted by Its Respective Manufacturer Drawn by Approved by