ETC NTMS3P03R2

NTMS3P03R2
Power MOSFET
-3.05 Amps, -30 Volts
P–Channel SO–8
Features
•
•
•
•
•
•
•
High Efficiency Components in a Single SO–8 Package
High Density Power MOSFET with Low RDS(on)
Miniature SO–8 Surface Mount Package – Saves Board Space
Diode Exhibits High Speed with Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for the SO–8 Package is Provided
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–3.05 AMPERES
–30 VOLTS
0.085 @ VGS = –10 V
Applications
• DC–DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery–Powered Products, i.e.:
P–Channel
D
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
G
Symbol
Value
Unit
–30
V
Gate–to–Source Voltage – Continuous
VDSS
VGS
±20
V
Thermal Resistance –
Junction–to–Ambient (Note 1.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4.)
RθJA
PD
ID
ID
IDM
171
0.73
–2.34
–1.87
–8.0
°C/W
W
A
A
A
Thermal Resistance –
Junction–to–Ambient (Note 2.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4.)
RθJA
PD
ID
ID
IDM
100
1.25
–3.05
–2.44
–12
°C/W
W
A
A
A
RθJA
PD
ID
ID
IDM
TJ, Tstg
62.5
2.0
–3.86
–3.1
–15
°C/W
W
A
A
A
Rating
Drain–to–Source Voltage
Thermal Resistance –
Junction–to–Ambient (Note 3.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4.)
Operating and Storage
Temperature Range
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = –30 Vdc, VGS = –4.5 Vdc, Peak
IL = –7.5 Apk, L = 5 mH, RG = 25 Ω)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS
–55 to
+150
°C
140
mJ
July, 2001 – Rev. 1
MARKING
DIAGRAM
SO–8
CASE 751
STYLE 13
8
E3P03
LYWW
1
E3P03
L
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
PIN ASSIGNMENT
N.C.
1
8
Drain
Source
2
7
Drain
Source
3
6
Drain
Gate
4
5
Drain
Top View
TL
°C
260
1. Minimum FR–4 or G–10 PCB, t = Steady State.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t = steady state.
3. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
 Semiconductor Components Industries, LLC, 2001
S
1
ORDERING INFORMATION
Device
NTMS3P03R2
Package
Shipping
SO–8
2500/Tape & Reel
Publication Order Number:
NTMS3P03R2/D
NTMS3P03R2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5.)
Symbol
Characteristic
Min
Typ
Max
Unit
–30
–
–
–30
–
–
–
–
–
–
–1.0
–10
–
–
–100
–
–
100
–1.0
–
–1.7
3.6
–2.5
–
–
–
0.063
0.090
0.085
0.115
gFS
–
5.0
–
Mhos
Ciss
–
520
750
pF
Coss
–
170
325
Crss
–
70
135
td(on)
–
12
22
tr
–
16
30
td(off)
–
45
80
tf
–
45
80
td(on)
–
16
–
OFF CHARACTERISTICS
V(BR)DSS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = –250 µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = –30 Vdc, VGS = 0 Vdc, TJ = 25°C)
(VDS = –30 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current
(VGS = –20 Vdc, VDS = 0 Vdc)
IGSS
Gate–Body Leakage Current
(VGS = +20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = –250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–State Resistance
(VGS = –10 Vdc, ID = –3.05 Adc)
(VGS = –4.5 Vdc, ID = –1.5 Adc)
RDS(on)
Forward Transconductance (VDS = –15 Vdc, ID = –3.05 Adc)
Vdc
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = –24
24 Vd
Vdc, VGS = 0 Vd
Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 6. & 7.)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = –24 Vdc, ID = –3.05 Adc,
VGS = –10 Vdc,
Vdc
RG = 6.0 Ω)
Fall Time
Turn–On Delay Time
(VDD = –24 Vdc, ID = –1.5 Adc,
–4 5 Vdc,
Vdc
VGS = –4.5
RG = 6.0 Ω)
Rise Time
Turn–Off Delay Time
Fall Time
Total Gate Charge
(VDS = –24 Vdc,
VGS = –10 Vdc,
ID = –3.05
3 05 Adc)
Ad )
Gate–Source Charge
Gate–Drain Charge
ns
ns
tr
–
42
–
td(off)
–
32
–
tf
–
35
–
Qtot
–
16
25
Qgs
–
2.0
–
Qgd
–
4.5
–
VSD
–
–
–0.96
–0.78
–1.25
–
Vdc
trr
–
34
–
ns
ta
–
18
–
tb
–
16
–
QRR
–
0.03
–
nC
BODY–DRAIN DIODE RATINGS (Note 6.)
Diode Forward On–Voltage
(IS = –3.05 Adc, VGS = 0 V)
(IS = –3.05 Adc, VGS = 0 V, TJ = 125°C)
Reverse Recovery Time
(IS = –3.05
3 05 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
5. Handling precautions to protect against electrostatic discharge is mandatory.
6. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%.
7. Switching characteristics are independent of operating junction temperature.
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2
µC
NTMS3P03R2
TYPICAL ELECTRICAL CHARACTERISTICS
–ID, DRAIN CURRENT (AMPS)
VGS = –4 V
VGS = –4.6 V
VGS = –6 V
4
VGS = –4.8 V
TJ = 25°C
3
VGS
2
VGS = –3.6 V
VGS = –2.8 V
VGS = –3.2 V
= –5 V
VGS = –2.6 V
VGS = –3 V
1
0
0.25
0.5
0.75
1
1.25
1.5
1.75
TJ = 25°C
2
TJ = –55°C
1
1
2
3
4
5
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.6
0.5
0.4
0.3
0.2
0.1
5
4
6
7
8
0.7
ID = –1.5 A
TJ = 25°C
0.6
0.5
0.4
0.3
0.2
0.1
0
2
4
3
5
6
7
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 3. On–Resistance vs. Gate–to–Source
Voltage
Figure 4. On–Resistance vs. Gate–to–Source
Voltage
0.25
TJ = 25°C
0.2
VGS = –4.5 V
0.15
VGS = –10 V
0.1
0.05
1
TJ = 100°C
3
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
ID = –3.05 A
TJ = 25°C
3
4
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0.7
0
VDS > = –10 V
5
0
2
2
3
4
5
6
RDS(on), DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
VGS = –4.4 V
VGS = –8 V
5
0
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
6
VGS = –10 V
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
–ID, DRAIN CURRENT (AMPS)
6
1.6
1.4
ID = –3.05 A
VGS = –10 V
1.2
1
0.8
0.6
–50
–25
0
25
50
75
100
125
–ID, DRAIN CURRENT (AMPS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance vs. Drain Current and
Gate Voltage
Figure 6. On Resistance Variation with
Temperature
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3
150
NTMS3P03R2
10000
C, CAPACITANCE (pF)
IDSS, LEAKAGE (nA)
VGS = 0 V
TJ = 150°C
1000
TJ = 125°C
100
1200
VDS = 0 V
1000
Ciss
VGS = 0 V
800
Ciss
Crss
600
400
Coss
200
Crss
TJ = 25°C
0
10
10
14
10
22
18
26
30
0
5
–VDS
10
15
20
25
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE
VOLTAGE (VOLTS)
Figure 7. Drain–to–Source Leakage Current
vs. Voltage
Figure 8. Capacitance Variation
12
30
30 1000
QT
10
VDS = –24 V
ID = –3.05 A
VGS = –10 V
25
VDS
8
20
VGS
6
15
Q1
4
tf
tr
td(on)
5
ID = –3.05 A
TJ = 25°C
0
2
4
6
8
10
12
1
0
16
14
10
1
100
Qg, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (Ω)
Figure 9. Gate–to–Source and
Drain–to–Source Voltage vs. Total Charge
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
3
100
tr
tf
1
10
IS, SOURCE CURRENT (AMPS)
VDS = –24 V
ID = –1.5 A
VGS = –4.5 V
10
td(off)
10
10
Q2
2
0
100
1000
t, TIME (ns)
5
–VGS
t, TIME (ns)
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
6
td(off)
td(on)
100
VGS = 0 V
TJ = 25°C
2.5
2
1.5
1
0.5
0
0.2
0.4
0.6
0.8
1
RG, GATE RESISTANCE (Ω)
–VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
Figure 12. Diode Forward Voltage vs. Current
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4
1.2
NTMS3P03R2
VGS = 12 V
SINGLE PULSE
TA = 25°C
10
1.0 ms
di/dt
10 ms
IS
dc
1.0
ta
trr
tb
TIME
0.1
RDS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
10
1.0
0.25 IS
tp
IS
100
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
Figure 14. Diode Reverse Recovery Waveform
1.0
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESPONSE
–ID, DRAIN CURRENT (AMPS)
100
D = 0.5
0.2
0.1
0.1
Normalized to RθJA at Steady State (1″ pad)
Chip
Junction 2.32 Ω
18.5 Ω
50.9 Ω
37.1 Ω
56.8 Ω
0.05
0.02
0.01
1E–03
0.0014 F
0.01
0.0073 F
0.022 F
0.105 F
0.484 F
3.68 F
Ambient
Single Pulse
1E–02
24.4 Ω
1E–01
1E+00
1E+01
t, TIME (s)
Figure 15. FET Thermal Response
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5
1E+02
1E+03
NTMS3P03R2
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self–align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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NTMS3P03R2
TYPICAL SOLDER HEATING PROFILE
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177–189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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NTMS3P03R2
PACKAGE DIMENSIONS
SO–8
CASE 751–07
ISSUE W
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
STYLE 13:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
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8
N.C.
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
NTMS3P03R2
Notes
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9
NTMS3P03R2
Notes
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10
NTMS3P03R2
Notes
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11
NTMS3P03R2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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For additional information, please contact your local
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NTMS3P03R2/D