TN2540 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► The Supertex TN2540 is a low threshold enhancementmode transistor that utilizes an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors, and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Low threshold — 2.0V max High input impedance Low input capacitance — 125pF max Fast switching speeds Low ON-resistance Free from secondary breakdown Low input and output leakage Complementary N and P-channel devices Applications ► ► ► ► ► ► ► Logic level interfaces — ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic devices Analog switches General purpose line drivers Telecom switches Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Switching Waveforms and Test Circuit VDD 10V 90% INPUT 0V PULSE GENERATOR 10% t(ON) td(ON) VDD t(OFF) tr 10% td(OFF) tF D.U.T. 10% INPUT 90% OUTPUT RGEN OUTPUT 0V RL 90% TN2540 Ordering Information Package Options Device TN2540 BVDSS/BVDGS RDS(ON) VGS(th) ID(ON) (max) (V) (min) (A) 2.0 1.0 TO-92 TO-243AA (SOT-89) Die* (V) (max) (Ω) TN2540N3-G TN2540N8-G TN2540ND 400 12 -G indicates package is RoHS compliant (‘Green’) * MIL visual screening available. Pin Configuration DRAIN Absolute Maximum Ratings Parameter Value Drain to source voltage BVDSS Drain to gate voltage BVDGS Gate to source voltage ±20V Operating and storage temperature S -55°C to +150°C Soldering temperature* G GATE D DRAIN SINK TO-92 TO-243AA (SOT-89) (front view) (top view) 300°C Product Marking * Distance of 1.6mm from case for 10 seconds. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. TN 2540 YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging TO-92 (N3) TN5DW W = Code for week sealed TO-243AA (SOT-89) (N8) Thermal Characteristics ID ID Power Dissipation Package (continuous) (mA) (pulsed) (A) @TA = 25OC (W) ( C/W) TO-92 175 2.0 1.0 TO-243AA (SOT-89) 260 1.8 1.6‡ Notes: † ID (continuous) is limited by max rated TJ . ‡ Mounted on FR5 board, 25mm x 25mm x 1.57mm. 2 ( C/W) IDR† (mA) IDRM (A) 125 170 175 2.0 15 78‡ 260 1.8 θjc O θja O TN2540 Electrical Characteristics (@ 25°C unless otherwise specified) Symbol Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage 400 - - V VGS = 0V, ID = 100µA VGS(th) Gate threshold voltage 0.6 - 2.0 V VGS = VDS, ID = 1.0mA VGS(th) change with temperature - -2.5 -4.0 mV/OC VGS = VDS, ID = 1.0mA Gate body leakage current - - 100 nA VGS = ±20V, VDS = 0V - - 10 µA VGS = 0V, VDS = Max rating - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC 0.3 0.5 - ΔVGS(th) IGSS IDSS Zero gate voltage drain current ID(ON) ON-state drain current RDS(ON) ΔRDS(ON) A 0.75 1.0 - - 8.0 12 8.0 12 Change in RDS(ON) with temperature - - 0.75 %/OC VGS = 10V, ID = 500mA 125 200 - mmho VDS = 25V, ID = 100mA Input capacitance - 95 125 COSS Common source output capacitance - 20 70 CRSS Reverse transfer capacitance - 10 25 td(ON) Turn-ON delay time - - 20 Rise time - - 15 VSD trr VGS = 4.5V, ID = 150mA - CISS tf VGS = 10V, VDS = 25V Ω Forward transconductance td(OFF) VGS = 4.5V, VDS = 25V Static drain-to-source ON-state resistance GFS tr Conditions VGS = 10V, ID = 500mA pF VGS = 0V, VDS = 25V, f = 1.0MHz ns VDD = 25V, ID = 1.0A, RGEN = 25Ω Turn-OFF delay time - - 25 Fall time - - 20 Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 200mA Reverse recovery time - 300 - ns VGS = 0V, ISD = 1.0A Notes: 1.All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. 3 TN2540 Typical Performance Curves ° ° ° ° ° 4 TN2540 Typical Performance Curves (cont.) BVDSS Variation with Temperature On-Resistance vs. Drain Current 1.1 50 V GS = 4.5V RDS(ON) (ohms) BVDSS (normalized) 40 1.0 VGS = 10V 30 20 10 0 0.9 -50 0 50 100 150 0 0.4 0.8 Tj (° C) 1.2 1.6 2.0 ID (amperes) Transfer Characteristics V(th) and RDS Variation with Temperature 2.5 1.5 1.4 R DS(ON) @ 10V, 0.5A VGS(th) (normalized) ID (amperes) 1.2 TA = -55° C 0.9 25°C 0.6 0.3 2.0 V(th) @ 1mA 1.2 1.5 1.0 1.0 0.8 0.5 125°C 0.6 0 0 2 4 6 8 10 -50 0 50 100 150 Tj (° C) VGS (volts) Capacitance vs. Drain-to-Source Voltage Gate Drive Dynamic Characteristics 200 10 f = 1MHz 8 VDS = 10V VGS (volts) C (picofarads) 150 CISS 100 6 VDS = 40V 4 260 pF 50 2 COSS CRSS 95pF 0 0 0 10 20 30 40 0 0.4 0.8 1.2 QG (nanocoulombs) VDS (volts) 5 1.6 2.0 RDS(ON) (normalized) VDS = 25V TN2540 3-Lead TO-92 Package Outline (N3) D A 1 Seating Plane 2 3 L b C e1 e Side View Front View E1 E 3 1 2 Bottom View Symbol Dimension (inches) A b C D E E1 e e1 L MIN .170 .014 .014 .175 .125 .800 .095 .045 .500 NOM - - - - - - - - - MAX .210 .022 .022 .205 .165 .105 .105 .055 - Drawings not to scale. 6 TN2540 3-Lead TO-243AA (SOT-89) Package Outline (N8) D D1 C 4 E1 E H 1 3 2 L b e b1 A e1 Top View Symbol MIN Dimensions (mm) Side View A b b1 C D D1 E E1 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.13 NOM - - - - - - - - MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 e e1 1.50 BSC 3.00 BSC H L 3.94 0.89 - - 4.25 1.20 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TN2540 A082307 7