TOSHIBA TMP93PW46A

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93PW46A
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION**
How to release the HALT mode
Usually, interrupts can release all halts status. However, the interrupts = ( NMI ,
INT0), which can release the HALT mode may not be able to do so if they are
input during the period CPU is shifting to the HALT mode (for about 3 clocks of
fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In
this case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
TMP93PW46A
Low Voltage/Low Power
CMOS 16-Bit Microcontroller
TMP93PW46AF
1.
Outline and Device Characteristics
The TMP93PW46A is OTP type MCU which includes 128-Kbyte One-time PROM. Using the
adapter-socket, you can write and verify the data for the TMP93CW46A by general EPROM
programmer.
The TMP93PW46A has the same pin-assignment as the TMP93CW46A (Mask ROM type).
Writing the program to built-in PROM, the TMP93PW46A operates as the same way as the
TMP93CW46A.
000000H
Internal I/O
000080H
Internal RAM
001080H
External area
008000H
Internal ROM
(128 Kbytes)
028000H
External area
= Internal area
FFFF00H
Reserved
FFFFFFH
Figure 1.1 Memory map of TMP93CW46A/TMP93PW46A
MCU
ROM
RAM
Package
Adapter Socket
TMP93PW46AF
OTP 128 Kbytes
4 Kbytes
P-LQFP100-1414-0.50F
BM11129
030619EBP1
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
93PW46A-1
2004-02-10
TMP93PW46A
PA0 to PA6
PA7 (SCOUT)
P50 to P57
(AN0 to AN7)
AVCC
AVSS
VREFH
VREFL
900/L CPU
10-bit 8-ch
AD
converter
(TXD0) P90
(RXD0) P91
(SCLK0/ CTS0 ) P92
Serial I/O
(Channel 0)
(TXD1) P93
(RXD1) P94
(SCLK1) P95
Serial I/O
(Channel 1)
(TXD2) P60
(RXD2) P61
(SCLK2/ CTS2 ) P62
(TXD3) P63
(RXD3) P64
(SCLK3/ CTS3 ) P65
Serial I/O
(Channel 2)
(TXD4) P66
(RXD4) P67
Serial I/O
(Channel 4)
8-bit timer
(Timer 0)
(TO1) P71
8-bit timer
(Timer 1)
(TO3) P73
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
32 bits
F
SR
Highfrequency
OSC
Lowfrequency
OSC
X1
X2
CLK
XT1
XT2
AM8/ AM16
EA
RESET
ALE
TEST2, TEST1
P C
Serial I/O
(Channel 3)
(TI0) P70
(TO2) P72
VCC [3]
VSS [3]
Port A
4-Kbyte RAM
Interrupt
controller
P87 (INT0)
Watchdog
timer
WDTOUT
NMI
Port 0
P00 to P07
(AD0/ to AD7)
Port 1
P10 to P17
(AD8 to AD15/A8 to A15)
Port 2
P20 to P27
(A0 to A7/A16 to A23)
8-bit PWM
(Timer 2)
P30 ( RD )
8-bit PWM
(Timer 3)
P32 ( HWR )
P31 ( WR )
P33 ( WAIT )
Port 3
(INT4/TI4) P80
(INT5/TI5) P81
(TO4) P82
(TO5) P83
16-bit timer
(Timer 4)
(INT6/TI6) P84
(INT7/TI7) P85
(TO6) P86
16-bit timer
(Timer 5)
P34 ( BUSRQ )
P35 ( BUSAK )
128-Kbyte ROM
P36 ( R / W )
P37 ( RAS )
CS/WAIT
controller
(3 blocks)
P40 ( CS0 / CAS0 )
P41 ( CS1 / CAS1 )
P42 ( CS2 / CAS2 )
Figure 1.2 TMP93PW46A Block Diagram
93PW46A-2
2004-02-10
TMP93PW46A
2.
Pin Assignment and Functions
The assignment of input/output pins for the TMP93PW46A their names and outline functions
are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93PW46AF.
○
○
Timer
ADC
Clock, Mode
SIO
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
TMP93PW46A
Pin
no.
Pin
no.
TMP93PW46A
○
○
○
○
○
○
88 P65/ CTS3 /SCLK3
P66/TXD4
89
P67/RXD4
90
VSS
91
P50/AN0
92
P51/AN1
93
P52/AN2
94
P53/AN3
95
P54/AN4
96
80 P40/ CS 0 / CAS 0
P55/AN5
97
79 P37/ RAS
P56/AN6
98
78 P36/ R / W
P57/AN7
99
77 P35/ BUSAK
VREFH
100
76 P34/ BUSRQ
VREFL
AVSS
AVCC
1
2
3
75 P33/ WAIT
NMI
4
P70/TI0
5
P71/TO1
P72/TO2
6
7
P73/TO3
P80/INT4/TI4
P81/INT5/TI5
P82/TO4
P83/TO5
P84/INT6/TI6
8
9
10
11
12
13
P85/INT7/TI7
P86/TO6
P87/INT0
P90/TXD0
P91/RXD0
14
15
16
17
18
72
71
70
69
68
67
66
65
64
63
62
87 P64/RXD3
86 P63/TXD3
85 P62/ CTS2 /SCLK2
84 P61/RXD2
83 P60/TXD2
82 P42/ CS2 / CAS2
○
○
○
○
○
○
○
○
74 P32/ HWR
73 P31/ WR
Top view
LQFP100
P30/ RD
P27/A7/A23
P26/A6/A22
P25/A5/A21
P24/A4/A20
P23/A3/A19
P22/A2/A18
P21/A1/A17
P20/A0/A16
VCC
VSS
SIO
○
81 P41/ CS1 / CAS1
○
○
○
○
○
○
○
○
61 WDTOUT
P95/SCLK1
22
AM8/ AM16
23
CLK
VCC
24
25
60
59
58
57
56
55
54
53
52
51
VSS
26
50 P05/AD5
X1
27
49 P04/AD4
X2
28
48 P03/AD3
EA
29
47 P02/AD2
RESET
30
46 P01/AD1
P96/XT1
31
45 P00/AD0
P97/XT2
32
44 VCC
TEST1
33
43 ALE
TEST2
34
42 PA7/SCOUT
PA0
35
41 PA6
PA1
36
40 PA5
PA2
37
39 PA4
P92/ CTS 0 /SCLK0 19
P93/TXD1
P94/RXD1
Programmable
Pull Pull
down up
Memory interface
Programmable
Pull Pull
up down
20
21
P17/AD15/A15
P16/AD14/A14
P15/AD13/A13
P14/AD12/A12
P13/AD11/A11
P12/AD10/A10
P11/AD9/A9
P10/AD8/A8
P07/AD7
P06/AD6
38 PA3
Figure 2.1.1 Pin Assignment (100-Pin LQFP)
93PW46A-3
2004-02-10
TMP93PW46A
2.2
Pin Names and Functions
(1) Pin function of TMP93PW46A in MCU mode.
Table 2.2.1 Name and Function in MCU Mode (1/4)
Pin Name
Number
of Pins
I/O
Function
P00 to P07
AD0 to AD7
8
I/O
3 states
Port 0: I/O port that allows selection of I/O on a bit basis address/data (lower):
Bits 0 to 7 for address/data bus
P10 to P17
AD8 to AD15
A8 to A15
8
I/O
3 states
Output
Port 1: I/O port that allows selection of I/O on a bit basis
Address data (upper): Bits 8 to 15 of address/data bus
Address: Bits 8 to 15 of address bus
P20 to P27
8
I/O
Port 2: I/O port that allows selection of I/O on a bit basis
(with pull-down resistor)
Output
Output
Address: Bits 0 to 7 of address bus
Address: Bits 16 to 23 of address bus
1
Output
Output
Port 30: Output port
Read: Strobe signal for reading external memory
1
Output
Output
Port 31: Output port
Write: Strobe signal for writing data on pins AD0 to AD7
1
I/O
Output
Port 32: I/O port (with pull-up resistor)
High write: Strobe signal for writing data on pins AD8 to AD15
1
I/O
Input
Port 33: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait
1
I/O
Input
Port 34: I/O port (with pull-up resistor)
Bus request: Signal used to request high impedance for AD0 to AD15,
A0 to A23, RD , WR , HWR , R/ W , RAS , CS0 , CS1 , and CS2 pins.
(For external DMAC)
1
I/O
Output
Port 35: I/O port (with pull-up resistor)
Bus acknowledge: Signal indicating that AD0 to AD15, A0 to A23, RD , WR ,
HWR , R / W , RAS , CS0 , CS1 , and CS2 pins are at high impedance after
receiving BUSRQ. (For external DMAC)
1
I/O
Output
Port 36: I/O port (with pull-up resistor)
Read/write: 1 represents read or dummy cycle.
0 represents write cycle.
1
I/O
Output
Port 37: I/O port (with pull-up resistor)
Row address strobe: Outputs “ RAS ” strobe for DRAM.
1
I/O
Output
Output
Port 40: I/O port (with pull-up resistor)
Chip select 0: Outputs 0 when address is within specified address area.
Column address strobe 0: Outputs CAS strobe for DRAM when address is
within specified address area.
A0 to A7
A16 to A23
P30
RD
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
P36
R/W
P37
RAS
P40
CS0
CAS0
Note: This device’s built-in memory or built-in I/O cannot be accessed with the external DMA controller
using the BUSRQ and BUSAK signals.
93PW46A-4
2004-02-10
TMP93PW46A
Table 2.2.2 Name and Function in MCU Mode (2/4)
Pin Name
P41
Number
of Pins
I/O
Function
1
I/O
Output
Output
Port 41: I/O port (with pull-up resistor)
Chip select 1: Outputs 0 if address is within specified address area.
Column address strobe 1: Outputs CAS strobe for DRAM if address is within
specified address area.
1
I/O
Output
Output
Port 42: I/O port (with pull-down resistor)
Chip select 2: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within
specified address area.
P50 to P57
AN0 to AN7
8
Input
Input
Port 5: Input port
Analog input: Analog signal input for AD converter
VREFH
1
Input
Pin for high level reference voltage input to AD converter
VREFL
1
Input
P60
TXD2
1
I/O
Output
Port 60: I/O port (with pull-up resistor)
Serial send data 2
P61
RXD2
1
I/O
Input
Port 61: I/O port (with pull-up resistor)
Serial receive data 2
P62
1
I/O
Input
I/O
Port 62: I/O port (with pull-up resistor)
Serial data send enable 2 (Clear to send)
Serial clock I/O 2
P63
TXD3
1
I/O
Output
Port 63: I/O port (with pull-up resistor)
Serial send data 3
P64
RXD3
1
I/O
Input
Port 64: I/O port (with pull-up resistor)
Serial receive data 3
P65
1
I/O
Input
I/O
Port 65: I/O port (with pull-up resistor)
Serial data send enable 3 (Clear to send)
Serial clock I/O 3
P66
TXD4
1
I/O
Output
Port 66: I/O port (with pull-up resistor)
Serial send data 4
P67
RXD4
1
I/O
Input
Port 67: I/O port (with pull-up resistor)
Serial receive data 4
P70
TI0
1
I/O
Input
Port 70: I/O port (with pull-up resistor)
Timer input 0: Timer 0 input
P71
TO1
1
I/O
Output
Port 71: I/O port (with pull-up resistor)
Timer output 1: Timer 0 or 1 output
P72
TO2
1
I/O
Output
Port 72: I/O port (with pull-up resistor)
PWM output 2: 8-bit PWM timer 2 output
P73
TO3
1
I/O
Output
Port 73: I/O port (with pull-up resistor)
PWM output 3: 8-bit PWM timer 3 output
CS1
CAS1
P42
CS2
CAS2
CTS2
SCLK2
CTS3
SCLK3
Pin for low level reference voltage input to AD converter
93PW46A-5
2004-02-10
TMP93PW46A
Table 2.2.3 Name and Function in MCU Mode (3/4)
Pin Name
Number
of Pins
I/O
Function
P80
TI4
INT4
1
I/O
Input
Input
Port 80: I/O port (with pull-up resistor)
Timer input 4: Timer 4 count/capture trigger signal input
Interrupt request pin 4: Interrupt request pin with programmable rising/falling
edge
P81
TI5
INT5
1
I/O
Input
Input
Port 81: I/O port (with pull-up resistor)
Timer input 5: Timer 4 count/capture trigger signal input
Interrupt request pin 5: Interrupt request pin with rising edge
P82
TO4
1
I/O
Output
Port 82: I/O port (with pull-up resistor)
Timer output 4: Timer 4 output pin
P83
TO5
1
I/O
Output
Port 83: I/O port (with pull-up resistor)
Timer output 5: Timer 4 output pin
P84
TI6
INT6
1
I/O
Input
Input
Port 84: I/O port (with pull-up resistor)
Timer input 6: Timer 5 count/capture trigger signal input
Interrupt request pin 6: Interrupt request pin with programmable rising/falling
edge
P85
TI7
INT7
1
I/O
Input
Input
Port 85: I/O port (with pull-up resistor)
Timer input 7: Timer 5 count/capture trigger signal input
Interrupt request pin 7: Interrupt request pin with rising edge
P86
TO6
1
I/O
Output
P87
INT0
1
I/O
Input
P90
TXD0
1
I/O
Output
Port 90: I/O port (with pull-up resistor)
Serial send data 0
P91
RXD0
1
I/O
Input
Port 91: I/O port (with pull-up resistor)
Serial receive data 0
P92
1
I/O
Input
I/O
Port 92: I/O port (with pull-up resistor)
Serial data send enable 0 (Clear to send)
Serial clock I/O 0
P93
TXD1
1
I/O
Output
Port 93: I/O port (with pull-up resistor)
Serial send data 1
P94
RXD1
1
I/O
Input
Port 94: I/O port (with pull-up resistor)
Serial receive data 1
P95
SCLK1
1
I/O
I/O
Port 95: I/O port (with pull-up resistor)
Serial clock I/O 1
PA0 to PA5
6
I/O
Port A0 to A5: I/O ports (Large current output)
PA6
1
I/O
Port A6: I/O port
CTS0
SCLK0
Port 86: I/O port (with pull-up resistor)
Timer output 6: Timer 5 output pin
Port 87: I/O port (with pull-up resistor)
Interrupt request pin 0: Interrupt request pin with programmable level/rising
edge
93PW46A-6
2004-02-10
TMP93PW46A
Table 2.2.4 Name and Function in MCU Mode (4/4)
Pin Name
Number
of Pins
I/O
Function
PA7
SCOUT
1
I/O
Output
Port A7: I/O port
System clock output: Outputs system clock or 2 oscillation clock for
synchronizing to external circuit.
Watchdog timer output pin
WDTOUT
1
Output
NMI
1
Input
CLK
1
Output
EA
1
Input
Fixed to “1”.
AM8/ AM16
1
Input
Fixed to “1”.
ALE
1
Output
RESET
1
Input
X1/X2
2
I/O
High-frequency oscillator connecting pin
XT1
P96
1
Input
I/O
Low-frequency oscillator connecting pin
Port 96: I/O port (Open-drain output)
XT2
P97
1
Output
I/O
Low-frequency oscillator connecting pin
Port 97: I/O port (Open-drain output)
TEST1/TEST2
2
Output/Input
VCC
3
Non-maskable interrupt request pin: Interrupt request pin with falling edge.
Can also be operated at rising edge by program.
Clock output: Outputs “System clock ÷ 2” clock.
Pulled up during reset.
Can be disabled for reducing noise.
Address latch enable
(Can be disabled for reducing noise.)
Reset: Initializes LSI. (with pull-up resistor)
TEST1 should be connected with TEST2 pin. Do not connect to any other pins.
Power supply pin
VSS
3
GND pin (0 V)
AVCC
1
Power supply pin for AD converter
AVSS
1
GND pin for AD converter (0 V)
Note: Built-in pull-up/pull-down resistors can be released from the pins other than the RESET pin by
software.
93PW46A-7
2004-02-10
TMP93PW46A
2.3
PROM Mode
Table 2.3.1 Name and Function of PROM Mode
Pin Function
Number of
Pins
Input/
Output
A7 to A0
8
Input
A15 to A8
8
Input
A16
1
Input
D7 to D0
8
I/O
CE
1
OE
1
PGM
Function
Pin Name (MCU mode)
P27 to P20
Memory address of program
P17 to P10
Memory data of program
P07 to P00
Input
Chip enable
P32
Input
Output enable
P30
1
Input
Program control
P31
VPP
1
Power
supply
12.75 V/5 V (Power supply of program)
EA
VCC
4
Power
supply
6.25 V/5 V
VCC, AVCC
VSS
4
Power
supply
0V
VSS, AVSS
Number of
Pins
Input/
Output
Pin Function
P34
1
Input
RESET
1
Input
CLK
1
Input
ALE
1
Output
X1
1
Input
X2
1
Output
P42 to P40
P37 to P35
AM8/ AM16
7
Input
TEST1, TEST2
2
Input/
Output
48
I/O
P57 to P50
P67 to P60
P73 to P70
P87 to P80
P97 to P90
PA7 to PA0
VREFH
VREFL
P33
Pin State
Fix to low level (Security pin)
Fix to low level (PROM mode)
Open
Self oscillation with resonator
Fix to high level
TEST1 should be connected with TEST2 pin.
Do not connect to any other pins.
Open
NMI
WDTOUT
93PW46A-8
2004-02-10
TMP93PW46A
3.
Operation
This section describes the functions and basic operational blocks of the TMP93PW46A.
The TMP93PW46A has PROM in place of the mask ROM which is included in the
TMP93CW46A. The other configuration and functions are the same as the TMP93CW46A.
Regarding the function of the TMP93PW46A, which is not described herein, see the
TMP93CW46A.
The TMP93PW46A has two operational modes: MCU mode and PROM mode.
3.1
MCU Mode
(1) Mode setting and function
The MCU mode is set by releasing the CLK pin (Pin open). In the MCU mode, the
operation is the same as TMP93CW46A.
(2) Memory map
The memory map of TMP93PW46A is the same as that of TMP93CW46A. The memory
map in MCU mode is shown in Figure 3.2.1, and the memory map in PROM mode is shown
in Figure 3.2.2.
3.2
Memory Map
Figure 3.2.1 and 3.2.2 are the memory map of the TMP93PW46A.
000000H
0000H
Internal I/O
000080H
Internal RAM
001080H
Internal PROM
(128 Kbytes)
External area
008000H
Internal PROM
(128 Kbytes)
028000H
1FFFFH
External area
= Internal area
FFFF00H
Reserved
FFFFFFH
Figure 3.2.1 Memory Map in MCU Mode
93PW46A-9
Figure 3.2.2 Memory Map in PROM Mode
2004-02-10
TMP93PW46A
3.3
PROM Mode
(1) Mode setting and programming
PROM mode is set by setting the RESET and CLK pins to the “L” level. The
programming and verification for the internal PROM is achieved by using a general PROM
programmer with the adaptor socket.
1.
OTP adaptor
BM11129: TMP93PW46AF adaptor
2.
Setting OTP adaptor
Set the switch (SW1) to N side.
3.
Setting PROM programmer
i)
Set PROM type to TC571000D.
Size: 1 Mbits (128 K × 8 bits)
VPP: 12.75 V
tPW: 100 µs
The electric signature mode (Hereinafter referred to as “signature”) is not
supported. Therefore using signature with PROM programmer applies voltage of
12.75 V to pin 9 (A9) of the address, and the device is damaged. Do not use
signature.
ii) Transferring the data (Copy)
In TMP93PW46A, PROM is placed on addresses 00000H to 1FFFFH in PROM
mode, and addresses 08000H to 27FFFH in MCU mode. Therefore data should be
transferred to addresses 00000H to 1FFFFH in PROM mode using the object
converter (tuconv) or the block transfer mode. (See instruction manual of PROM
programmer.)
iii) Setting program address
Start address: 00000H
End address: 1FFFFH
4.
Programming
Program/verify according to the procedures of PROM programmer.
93PW46A-10
2004-02-10
TMP93PW46A
VPP (12.75 V/5 V)
VCC
EA
TEST1
TEST2
A16
to
A0
P33
P17
to
P10
P27
to
P20
AVCC, VCC
P30
P32
P31
P07
to
P00
CE
PGM
D7
to
D0
RESET
CLK
VCC
X1
X2
VSS
AVSS
OE
P42 to P40,
P37 to P35,
AM8/ AM16
P34
* Use the 10 MHz resonator in
case of programming and
verification by a general
EPROM programmer.
Security
Figure 3.3.1 PROM Mode Pin Setting
(2) Programming flow chart
The programming mode is set by applying 12.75 V (Programming voltage) to the VPP pin
when the following pins are set as follows,
(VCC: 6.25 V, RESET : “L” level, CLK: “L” level).
While address and data are fixed and CE pin is set to “L” level, 0.1 ms of “L” level pulse is
applied to PGM pin to program the data.
Then the data in the address is verified.
If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin.
This programming procedure is repeated until correct data is read from the address (25
times maximum).
Subsequently, all data are programmed in all addresses.
The verification for all data is done under the condition of VPP = VCC = 5 V after all data
were written.
Figure 3.3.2 shows the programming flowchart.
93PW46A-11
2004-02-10
TMP93PW46A
High speed program writing.
Start
VCC = 6.25 V ± 0.25 V
VPP = 12.75 V ± 0.25 V
Address = Start address
X=0
Program 0.1 ms pulse
X=X+1
X > 25?
Yes
No
Error
Address = Address + 1
Verify
OK
No
Last address?
Yes
VCC = 5 V
VPP = 5 V
Read all data
Error
OK
Pass
Failure
Figure 3.3.2 Flowchart
93PW46A-12
2004-02-10
TMP93PW46A
(3) Security bit
The TMP93PW46A has a security bit in PROM cell. If the security bit is programmed to
“0”, the content of the PROM is disable to be read in PROM mode.
How to program the security bit
1)
Set the PROM mode.
2)
Set the security pin (Port 34) to “1”.
3)
Set programming address to “00000H”.
4)
Set programming data to “FEH”.
93PW46A-13
2004-02-10
TMP93PW46A
4.
Electrical Characteristic
4.1
“X” used in an expression shows a frequency of clock fFPH
selected by SYSCR1<SYSCK>. If a clock gear or a low speed
oscillator is selected, a value of “X” is different. The value as an
example is calculated at fc, gear = 1/fc (SYSCR1<SYSCK,
GEAR2:0> = “0000”).
Maximum Ratings
Parameter
Rating
Power supply voltage
VCC
− 0.5 to 6.5
Input voltage
VIN
− 0.5 to VCC + 0.5
Output current (Per one pin), ports PA0 to PA5
IOL1
20
Output current (Per one pin), excluding ports
PA0 to PA5
IOL2
2
Output current (Total of ports PA0 to PA5)
ΣIOL1
80
Output current (Total)
ΣIOL
120
Output current (Total)
ΣIOH
− 80
Power dissipation (Ta = 85°C)
PD
600
Soldering temperature (10 s)
TSOLDER
260
Storage temperature
TSTG
− 65 to 150
Operating temperature
TOPR
− 40 to 85
Note:
4.2
Symbol
Unit
V
mA
mW
°C
The maximum ratings are rated values which must not be exceeded during operation,
even for an instant. Any one of the ratings must not be exceeded. If any maximum
rating is exceeded, a device may break down or its performance may be degraded,
causing it to catch fire or explode resulting in injury to the user. Thus, when designing
products which include this device, ensure that no maximum rating value will ever be
exceeded.
DC Characteristics (1/2) (VSS = 0 V, Ta = −40 to 85°C)
Parameter
Symbol
Condition
fc = 4 to 20 MHz
Input low voltage
VCC
AD0 to AD15
VIL
Port 2 to port A (except P87)
VIL1
RESET , NMI , INT0
VIL2
EA , AM8/ AM16
VIL3
X1
VIL4
Input high voltage
Power supply voltage
AVCC = VCC
AVSS = VSS
AD0 to AD15
VIH
Port 2 to port A (except P87)
VIH1
RESET , NMI , INT0
VIH2
EA , AM8/ AM16
VIH3
X1
VIH4
fc = 4 to 12.5 MHz
fs = 30 to
34 kHz
Min
Typ. (Note)
Max
Unit
5.5
V
4.5
2.7
VCC ≥ 4.5 V
0.8
VCC < 4.5 V
0.6
− 0.3
VCC = 2.7 to 5.5 V
0.3 VCC
0.25 VCC
0.3
0.2 VCC
VCC ≥ 4.5 V
VCC < 4.5 V
2.2
2.0
0.7 VCC
VCC = 2.7 to 5.5 V
V
0.75 VCC
VCC + 0.3
VCC − 0.3
0.8 VCC
Note: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted.
93PW46A-14
2004-02-10
TMP93PW46A
4.2
DC Characteristics (2/2) (VSS = 0 V, Ta = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ. (Note 1)
Max
Unit
0.45
V
Output low voltage
VOL
IOL = 1.6 mA
(VCC = 2.7 to 5.5 V)
Output low current (PA0 to PA5)
IOLA
VOL = 1.0 V
(VCC = 2.7 to 5.5 V)
10
VOH1
IOH = − 400 µA
(VCC = 3 V ± 10%)
2.4
VOH2
IOH = − 400 µA
(VCC = 5 V ± 10%)
4.2
Darlington drive current
(8 output pins max)
IDAR
(Note 2)
VEXT = 1.5 V
REXT = 1.1 kΩ
(Vcc = 5 V ± 10% only)
− 1.0
Input leakage current
ILI
0.0 ≤ VIN ≤ VCC
0.02
±5
Output leakage current
ILO
0.2 ≤ VIN ≤ VCC − 0.2
0.05
±10
Power down voltage
(at STOP, RAM backup)
VSTOP
VIL2 = 0.2 VCC,
VIH2 = 0.8 VCC
2.0
6.0
RESET pull-up resistor
RRST
Vcc = 5 V ± 10%
50
150
Vcc = 3 V ± 10%
80
200
Pin capacitance
CIO
Schmitt width
RESET , NMI , INT0
VTH
Programmable
Pull-down resistor
RKL
Programmable
Pull-up resistor
RKH
Output high voltage
V
−3.5
fc = 1 MHz
10
0.4
1.0
10
80
VCC = 3 V ± 10%
30
150
VCC = 5 V ± 10%
50
150
VCC = 3 V ± 10%
100
42
30
37
IDLE2
18
25
IDLE1
3.5
5
11
16
VCC = 3 V ± 10%
fc = 12.5 MHz
(Typ.: VCC = 3.0 V)
NORMAL (Note 3)
RUN
IDLE2
IDLE1
SLOW (Note 3)
RUN
IDLE2
ICC
VCC = 3 V ± 10%
fs = 32.768 kHz
(Typ.: VCC = 3.0 V)
STOP
9
13.5
5.5
7.5
1
1.5
35
50
28
42
20
33
9
IDLE1
Ta ≤ 50°C
Ta ≤ 70°C
Ta ≤ 85°C
VCC =
2.7 to 5.5 V
µA
V
kΩ
pF
kΩ
300
35
RUN
mA
V
VCC = 5 V ± 10%
VCC = 5 V ± 10%
fc = 20 MHz
NORMAL (Note 3)
mA
15
mA
µA
10
0.2
20
50
Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted.
Note 2: IDAR is guranteed for total of up to 8 ports.
93PW46A-15
2004-02-10
TMP93PW46A
4.3
AC Characteristics
(1) VCC = 5 V ± 10%
No.
Parameter
Variable
Symbol
16 MHz
Min
Max
Min
33.3 µs
Max
20 MHz
Min
Max
Unit
1
Osc. period ( = x)
tOSC
50 ns
62.5 ns
50
ns
2
CLK pulse width
tCLK
2x − 40
85
60
ns
3
A0 to A23 valid → CLK hold
tAK
0.5x − 20
11
5
ns
4
CLK valid → A0 to A23 hold
tKA
1.5x − 70
24
5
ns
5
A0 to A15 valid → ALE fall
tAL
0.5x − 15
16
10
ns
6
ALE fall → A0 to A15 hold
tLA
0.5x − 20
11
5
ns
7
ALE high pulse width
tLL
x − 40
23
10
ns
8
ALE fall → RD / WR fall
TLC
0.5x − 25
6
0
ns
9
RD / WR rise → ALE rise
tCL
0.5x − 20
11
5
ns
10
A0 to A15 valid → RD / WR fall
tACL
x − 25
38
25
ns
11
A0 to A23 valid → RD / WR fall
tACH
1.5x − 50
44
25
ns
0.5x − 25
12
RD / WR rise → A0 to A23 hold
TCA
13
A0 to A15 valid → D0 to D15 input
tADL
3.0x − 55
133
95
ns
14
A0 to A23 valid → D0 to D15 input
tADH
3.5x − 65
154
110
ns
15
RD fall → D0 to D15 input
tRD
2.0x − 60
65
40
ns
16
RD low pulse width
tRR
2.0x − 40
85
60
17
RD rise → D0 to D15 hold
tHR
0
0
0
ns
18
RD rise → A0 to A15 output
tRAE
x − 15
48
35
ns
19
WR low pulse width
tWW
2.0x − 40
85
60
ns
20
D0 to D15 valid → WR rise
tDW
2.0x − 55
70
45
ns
21
WR rise → D0 to D15 hold
tWD
0.5x − 15
16
10
22
A0 to A23 valid → WAIT input
(1 + N) WAIT
mode
tAWH
23
A0 to A15 valid → WAIT input
(1 + N) WAIT
mode
tAWL
24
RD / WR fall → WAIT hold
(1 + N) WAIT
mode
25
A0 to A23 valid → Port input
tAPH
26
A0 to A23 valid → Port hold
tAPH2
tCW
6
3.5x − 90
129
3.0x − 80
2.0x + 0
0
2.5x − 120
2.5x + 50
ns
ns
85
108
125
ns
70
100
36
206
ns
ns
ns
5
175
ns
ns
27
WR rise → Port valid
28
A0 to A23 valid → RAS fall
tASRH
1.0x − 40
23
10
29
A0 to A15 valid → RAS fall
tASRL
0.5x − 15
16
10
30
RAS fall → D0 to D15 input
tRAC
31
RAS fall → A0 to A15 hold
tRAH
0.5x − 15
16
10
ns
32
RAS low pulse width
tRAS
2.0x − 40
85
60
ns
33
RAS high pulse width
tRP
2.0x − 40
85
60
ns
34
CAS fall → RAS rise
tRSH
1.0x − 40
23
10
ns
35
RAS rise → CAS rise
tRSC
0.5x − 25
6
0
ns
36
RAS fall → CAS fall
tRCD
1.0x − 40
23
10
ns
37
CAS fall → D0 to D15 input
tCAC
38
CAS low pulse width
tCAS
tCP
200
200
2.5x − 70
86
1.5x − 65
1.5x − 30
200
ns
ns
55
29
64
10
40
ns
ns
ns
ns
AC measuring conditions
•
Output level: High 2.2 V/Low 0.8 V, CL = 50 pF
(However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , R / W , CLK,
RAS , CAS0 to CAS2 )
•
Input level: High 2.4 V/Low 0.45 V (AD0 to AD15)
High 0.8 × VCC/Low 0.2 × VCC (except for AD0 to AD15)
93PW46A-16
2004-02-10
TMP93PW46A
(2) VCC = 3 V ± 10%
No.
Parameter
Variable
Symbol
12.5 MHz
Min
Max
Min
33.3 µs
80 ns
Max
Unit
1
Osc. period ( = x)
tOSC
80 ns
2
CLK pulse width
tCLK
2x − 40
120
ns
3
A0 to A23 valid → CLK hold
tAK
0.5x − 30
10
ns
4
CLK valid → A0 to A23 hold
tKA
1.5x − 80
40
ns
5
A0 to A15 valid → ALE fall
tAL
0.5x − 35
5
ns
6
ALE fall → A0 to A15 hold
tLA
0.5x − 35
5
ns
7
ALE high pulse width
tLL
x − 60
20
ns
8
ALE fall → RD / WR fall
tLC
0.5x − 35
5
ns
9
RD / WR rise → ALE rise
tCL
0.5x − 40
0
ns
10
A0 to A15 valid → RD / WR fall
tACL
x − 50
30
ns
11
A0 to A23 valid → RD / WR fall
tACH
1.5x − 50
70
ns
12
RD / WR rise → A0 to A23 hold
tCA
0.5x − 40
0
13
A0 to A15 valid → D0 to D15 input
tADL
3.0x − 110
130
ns
14
A0 to A23 valid → D0 to D15 input
tADH
3.5x − 125
155
ns
15
RD fall → D0 to D15 input
tRD
2.0x − 115
45
ns
16
RD low pulse width
tRR
2.0x − 40
17
RD rise → D0 to D15 hold
tHR
0
0
ns
18
RD rise → A0 to A15 output
tRAE
x − 25
55
ns
19
WR low pulse width
tWW
2.0x − 40
120
ns
20
D0 to D15 valid → WR rise
tDW
2.0x − 120
40
ns
tWD
0.5x − 40
ns
120
ns
21
WR rise → D0 to D15 hold
22
A0 to A23 valid → WAIT input
((1 + N) WAIT
mode
tAWH
23
A0 to A15 valid → WAIT input
(1 + N) WAIT
mode
tAWL
24
RD / WR fall → WAIT hold
(1 + N) WAIT
mode
25
A0 to A23 valid → Port input
tAPH
26
A0 to A23 valid → Port hold
tAPH2
27
WR rise → Port valid
tCP
28
A0 to A23 valid → RAS fall
tASRH
1.0x − 60
20
29
A0 to A15 valid → RAS fall
tASRL
0.5x − 40
0
30
RAS fall → D0 to D15 input
tRAC
31
RAS fall → A0 to A15 hold
tRAH
0.5x − 25
15
ns
32
RAS low pulse width
tRAS
2.0x − 40
120
ns
33
RAS high pulse width
tRP
2.0x − 40
120
ns
34
CAS fall → RAS rise
tRSH
1.0x − 55
25
ns
35
RAS rise → CAS rise
tRSC
0.5x − 25
15
ns
36
RAS fall → CAS fall
tRCD
1.0x − 40
40
ns
37
CAS fall→ D0 to D15 input
tCAC
38
CAS low pulse width
tCAS
tCW
0
3.5x − 130
3.0x − 100
2.0x + 0
ns
140
ns
160
2.5x − 195
2.5x + 50
ns
5
ns
200
ns
250
200
2.5x − 90
ns
ns
ns
110
1.5x − 120
1.5x − 40
ns
150
0
80
ns
ns
ns
AC measuring conditions
•
Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF
•
Input level: High 0.9 × VCC/Low 0.1 × VCC
93PW46A-17
2004-02-10
TMP93PW46A
(1) Read cycle
tOSC
X1
tCLK
CLK
tKA
tAK
A0 to A23
CS0 to CS2
R/W
tAWH
tCW
tAWL
WAIT
tAPH
tAPH2
Port input (Note)
tASRH
tRP
tRSH
RAS
tRAS
tASRL
tRAH
tRCD
CAS0 to CAS2
tRAC
tCAS
tCAC
tCA
tADH
tACH
RD
tRR
tACL
tLC
A0 to A15
AD0 to AD15
tAL
ALE
Note:
tRSC
tRD
tADL
tRAE
tHR
D0 to D15
tLA
tCL
tLL
Since the CPU accesses the internal area to read data from a port, the control signals of external
pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics
of port input/output shown above are typical representation. For details, contact your local
Toshiba sales representative.
93PW46A-18
2004-02-10
TMP93PW46A
(2) Write cycle
X1
CLK
A0 to A23
CS0 to CS2
R/W
WAIT
Port output (Note)
tCP
RAS
CAS0 to CAS2
WR
,
HWR
tWW
tDW
AD0 to AD15
A0 to A15
tWD
D0 to D15
ALE
Note:
Since the CPU accesses the internal area to write data to a port, the control signals of external
pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics
of port input/output shown above are typical representation. For details, contact your local
Toshiba sales representative.
93PW46A-19
2004-02-10
TMP93PW46A
AD Conversion Characteristics (VSS = 0 V, Ta = −40 to 85°C, AVCC = VCC, AVSS = VSS)
4.4
Parameter
Analog reference voltage (+)
Symbol
VREFH
Analog reference voltage (−)
VREFL
Analog input voltage range
VAIN
Analog current for analog
reference voltage
<VREFON> = 1
Power Supply
Min
Typ.
Max
VCC = 5 V ± 10%
VCC − 1.5
VCC
VCC
VCC = 3 V ± 10%
VCC − 0.2
VCC
VCC
VCC = 5 V ± 10%
VSS
VSS
VSS + 0.2
VCC = 3 V ± 10%
VSS
VSS
VSS + 0.2
VREFL
IREF (VREFL = 0 V)
<VREFON> = 0
Note 1: 1LSB = (VREFH − VREFL)/2
10
V
VREFH
VCC = 5 V ± 10%
0.5
1.5
VCC = 3 V ± 10%
0.3
0.9
mA
VCC = 2.7 to 5.5 V
0.02
5.0
VCC = 5 V ± 10%
±1.0
±3.0
VCC = 3 V ± 10%
±1.0
±3.0
−
Error
Unit
µA
LSB
[V]
Note 2: Minimum operation frequency
The operation of the AD converter is guaranteed only when fc (High-frequency oscillator) is used.
(It is not guaranteed when fs is used.) Additionally, it is guaranteed with fFPH ≥ 4 MHz.
Note 3: The value Icc includes the current which flows through AVCC pin.
Note 4: Error excludes quantizing errors.
4.5
Serial Channel Timing (I/O interface mode)
(1) SCLK input mode
Parameter
32.768 kHz
Variable
Symbol
12.5 MHz
(Note)
Min
Max
Min
Max
Min
Max
Min
tSCY
16X
488 µs
Output data → Rising edge of SCLK
tOSS
tSCY/2 − 5X − 50
91.5 µs
190 ns
100 ns
SCLK rising edge → Output data hold
tOHS
5X − 100
152 µs
300 ns
150 ns
SCLK rising edge → Input data hold
tHSR
0
SCLK rising edge → Effective data input
tSRD
SCLK cycle
1.28 µs
20 MHz
0
0
tSCY − 5X − 100
Max
0.8 µs
0
336 µs
780 ns
450 ns
(2) SCLK output mode
Parameter
Variable
Symbol
32.768 kHz
(Note)
12.5 MHz
Min
Max
Min
Max
Min
Max
8192X
488 µs
250 ms
1.28 µs
655.36 µs
20 MHz
Min
Max
0.8 µs
409.6 µs
SCLK cycle (Programmable)
tSCY
16X
Output data → SCLK rising edge
tOSS
tSCY − 2X − 150
427 µs
970 ns
550 ns
SCLK rising edge → Output data hold
tOHS
2X − 80
60 µs
80 ns
20 ns
SCLK rising edge → Input data hold
tHSR
0
0
0
SCLK rising edge → Effective data input
tSRD
tSCY − 2X − 150
0
428 µs
970 ns
550 ns
(3) SCLK input mode (UART mode)
Parameter
Symbol
Variable
Min
Max
32.768 kHz
(Note)
Min
Max
12.5 MHz
Min
Max
20 MHz
Min
SCLK cycle
tSCY
4X + 20
122 µs
340 ns
SCLK Low level pulse width
tSCYL
2X + 5
6 µs
165 ns
105 ns
SCLK High level pulse width
tSCYH
2X + 5
6 µs
165 ns
105 ns
Max
220 ns
Note: When fs is used as system clock (fSYS) or fs is used as input clock to prescaler.
93PW46A-20
2004-02-10
TMP93PW46A
4.6
Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7)
Parameter
Variable
Symbol
Min
12.5 MHz
Max
Min
Max
20 MHz
Min
Max
Unit
Clock cycle
tVCK
8X + 100
740
500
Low level clock pulse width
tVCKL
4X + 40
360
240
ns
High level clock pulse width
tVCKH
4X + 40
360
240
ns
4.7
ns
Interrupt and Capture
(1) NMI , INT0 interrupt
Parameter
Variable
Symbol
Min
12.5 MHz
Max
Min
Max
20 MHz
Min
Max
Unit
NMI , INT0 low level pulse width
tINTAL
4X
320
200
ns
NMI , INT0 high level pulse width
tINTAH
4X
320
200
ns
(2) INT4 to INT7 interrupt, capture
Parameter
Variable
Symbol
Min
12.5 MHz
Max
Min
Max
20 MHz
Min
Max
Unit
INT4 to INT7 low level pulse width
tINTBL
4X + 100
420
300
ns
INT4 to INT7 high level pulse width
tINTBH
4X + 100
420
300
ns
4.8
SCOUT Pin AC Characteristics
Parameter
Symbol
High to level pulse
width
VCC = 5 V ± 10%
High to level pulse
width
VCC = 3 V ± 10%
Low to level pulse
width
VCC = 5 V ± 10%
Low to level pulse
width
VCC = 3 V ± 10%
Variable
Min
12.5 MHz
Max
Min
Max
20 MHz
Min
0.5X − 10
30
15
0.5X − 20
20
−
0.5X − 10
30
15
0.5X − 20
20
−
Max
Unit
ns
tSCH
−
ns
tSCL
−
Measurement condition
•
Output level: High 2.2 V/Low 0.8 V, CL = 10 pF
tSCH
tSCL
SCOUT
93PW46A-21
2004-02-10
Input data
RXD
Output data
TXD
SCLK
93PW46A-22
0
Valid
tOHS
tSR
Note: SCLK is reversed in SCLK input falling mode.
tOSS
1
Valid
tHS
2
Valid
3
Valid
4.9
tSCY
TMP93PW46A
Timing Chart for I/O Interface Mode
2004-02-10
TMP93PW46A
4.10 Timing Chart for Bus Request ( BUSRQ )/Bus Acknowledge ( BUSAK )
(Note 1)
CLK
tBRC
BUSRQ
tBRC
tCBAL
tCBAH
BUSAK
tBAA
(Note 2)
tABA
AD0 to AD15, A0 to A23,
CS0 to CS2 , R / W , RAS ,
CAS0 to CAS2
(Note 2)
RD , WR , HWR
ALE
Parameter
Symbol
Variable
Min
Max
Max
Max
tBRC
tCBAL
CLK → BUSAK rising edge
tCBAH
65
ns
Output buffer is off to BUSAK
tABA
0
80
0
80
0
80
ns
tBAA
0
80
0
80
0
80
ns
1.5x + 120
120
Unit
BUSRQ set to up time to CLK
to output buffer is on.
120
20 MHz
Min
CLK → BUSAK falling edge
BUSAK
120
12.5 MHz
Min
240
0.5x + 40
ns
195
80
ns
Note 1:
The bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during
“Wait” cycle.
Note 2:
This line only shows the output buffer is off to state.
It doesn’t indicate the signal level is fixed.
Just after the bus is released, the signal level which is set before the bus is released is kept
dynamically by the external capacitance. Therefore, to fix the signal level by an external resistor
during bus releasing, designing is executed carefully because the level to fix will be delayed.
The internal programmable pull-up/pull-down resistor is switched active/non-active by an internal
signal.
93PW46A-23
2004-02-10
TMP93PW46A
4.11 Read Operation in PROM Mode
DC/AC characteristics
Ta = 25 ± 5°C VCC = 5 V ± 10%
Symbol
Condition
Min
Max
VPP read voltage
Parameter
VPP
−
4.5
5.5
Unit
Input high voltage (A0 to A16, CE , OE , PGM )
VIH1
−
2.2
VCC + 0.3
Input low voltage (A0 to A16, CE , OE , PGM )
VIL1
−
−0.3
0.8
Address to output delay
tACC
CL = 50 PF
−
2.25 TCYC + α
V
ns
TCYC = 400 ns (10 MHz Clock)
α = 200 ns
4.12 Program Operation in PROM Mode
DC/AC characteristics
Ta = 25 ± 5°C VCC = 6.25 V ± 0.25 V
Symbol
Condition
Min
Typ.
Max
Programming supply voltage
Parameter
VPP
−
12.50
12.75
13.00
Input high voltage
(D0 to D7, A0 to A16, CE , OE , PGM )
VIH
−
2.6
VCC + 0.3
Input low voltage
(D0 to D7, A0 to A16, CE , OE , PGM )
VIL
−
−0.3
0.8
VCC supply current
ICC
fc = 10 MHz
−
50
VPP supply current
IPP
VPP = 13.00 V
−
50
PGM program pulse width
tPW
CL = 50 PF
0.095
0.1
0.105
Unit
V
mA
ms
4.13 Timing Chart of Read Operation in PROM Mode
A0 to A16
CE
OE
PGM
tACC
D0 to D7
Data output
93PW46A-24
2004-02-10
TMP93PW46A
4.14 Timing Chart of Program Operation in PROM Mode
High-speed programming formula
A0 to A16
CE
OE
D0 to D7
Unknown
Data-in stable
Data-out valid
tPW
PGM
VPP
Note 1: The power supply of VPP (12.75 V) must be turned on at the same time or the later time for a
power supply of VCC and must be clear power-on at the same time or early time for a power
supply of VCC.
Note 2: The pull-up/pull-down device on condition of VPP = 12.75 V suffers a damage for the device.
Note 3: The maximum spec of VPP pin is 14.0 V. Be careful a overshoot at the programming.
93PW46A-25
2004-02-10
TMP93PW46A
5.
Package Dimensions
P-LQFP100-1414-0.50F
Unit: mm
93PW46A-26
2004-02-10