TOSHIBA TMP93PW40

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93PW40
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION**
How to release the HALT mode
Usually, interrupts can release all halts status. However, the interrupts = ( NMI ,
INT0), which can release the HALT mode may not be able to do so if they are
input during the period CPU is shifting to the HALT mode (for about 3 clocks of
fFPH) with IDLE1 or STOP mode (IDLE2, RUN is not applicable to this case). (In
this case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
TMP93PW40
Low Voltage/Low Power
CMOS 16-Bit Microcontrollers
TMP93PW40DF
1.
Outline and Device Characteristics
The TMP93PW40 is OTP type MCU which includes 128-Kbyte One-time PROM. Using the
adapter-socket, you can write and verify the data for TMP93PW40.TMP93PW40 has the same
pin-assignment with TMP93CW40 (Mask ROM type) .
Writing the program to built-in PROM, the TMP93PW40 operates as the same way with
TMP93CW40.
000000H
Internal I/O
000080H
001080H
Internal RAM
External area
008000H
Internal ROM
(128 Kbytes)
028000H
External area
FFFF00H
FFFFFFH
= Internal area
Reserved
Figure 1.1 Memory Map of TMP93CW40/PW40
MCU
ROM
RAM
Package
Adapter Socket
TMP93PW40DF
OTP 128 Kbytes
4 Kbytes
P-LQFP100-1414-0.50F
BM11129
030619EBP1
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
93PW40-1
2004-02-10
TMP93PW40
PA0 to PA6
PA7 (SCOUT)
Port A
P50 to P57
(AN0 to AN7)
AVCC
AVSS
VREFH
VREFL
10-bit
8-channel
AD
converter
(TXD0) P90
(RXD0) P91
(SCLK0/ CTS0 ) P92
Serial I/O
(channel 0)
(TXD1) P93
(RXD1) P94
(SCLK1) P95
Serial I/O
(channel 1)
(PG 00) P60
(PG 01) P61
(PG 02) P62
(PG 03) P63
(PG 10) P64
(PG 11) P65
(PG 12) P66
(PG 13) P67
CPU
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
32 bits
F
SR
VCC [3]
VSS [3]
High
frequency
OSC
CLK
Low
frequency
OSC
RESET
Watchdog
timer
4-Kbyte RAM
AM8/ AM16
ALE
TEST1
TEST2
Interrupt
controller
Pattern
generator
(channel 1)
XT1
XT2
EA
P C
Pattern
generator
(channel 0)
X1
X2
P87 (INT0)
NMI
WDTOUT
Port 0
P00 to P07
(AD0 to AD7)
(TI0) P70
8-bit timer
(timer 0)
Port 1
P10 to P17
(AD8 to AD15/A8 to A15)
(TO1) P71
8-bit timer
(timer 1)
Port 2
P20 to P27
(A0 to A7/A16 to A23)
(TO2) P72
8-bit PWM
(timer 2)
(TO3) P73
8-bit PWM
(timer 3)
(INT4/TI4) P80
(INT5/TI5) P81
(TO4) P82
(TO5) P83
16-bit timer
(timer 4)
(INT6/TI6) P84
(INT7/TI7) P85
(TO6) 86
16-bit timer
(timer 5)
Port 3
128-Kbyte PROM
P30 ( RD )
P31 ( WR )
P32 ( HWR )
P33 ( WAIT )
P34 ( BUSRQ )
P35 ( BUSAK )
P36 ( R / W )
P37 ( RAS )
CS/WAIT
controller
(3 block)
P40 ( CS0 / CAS0 )
P41 ( CS1 / CAS1 )
P42 ( CS2 / CAS2 )
Figure 1.2 TMP93PW40 Block Diagram
93PW40-2
2004-02-10
TMP93PW40
2.
Pin Assignment and Functions
The assignment of input/output pins for TMP93PW40, their name and outline functions are
described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of TMP93PW40.
Timer
ADC
Clock, Mode
SIO
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
Pin
no.
TMP93PW40
Programmable
Pull Pull
down up
○
○
○
○
○
○
88 P65/PG11
P66/PG12
89
87 P64/PG10
P67/PG13
90
86 P63/PG03
VSS
91
85 P62/PG02
P50/AN0
92
84 P61/PG01
P51/AN1
93
83 P60/PG00
P52/AN2
94
82 P42/ CS2 / CAS2
P53/AN3
95
81 P41/ CS1 / CAS1
P54/AN4
96
80 P40/ CS0 / CAS0
P55/AN5
97
79 P37/ RAS
P56/AN6
98
78 P36/ R / W
P57/AN7
99
77 P35/ BUSAK
VREFH
100
76 P34/ BUSRQ
VREFL
AVSS
AVCC
1
2
3
75 P33/ WAIT
NMI
4
72 P30/ RD
P70/TI0
P71/TO1
5
6
71 P27/A7/A23
70 P26/A6/A22
P72/TO2
P73/TO3
P80/INT4/TI4
7
8
9
69 P25/A5/A21
68 P24/A4/A20
P81/INT5/TI5
P82/TO4
10
11
P83/TO5
P84/INT6/TI6
12
13
P85/INT7/TI7
P86/TO6
P87/INT0
P90/TXD0
P91/RXD0
14
15
16
17
18
○
○
○
○
○
○
○
○
○
74 P32/ HWR
73 P31/ WR
Top view
LQFP100
67
66
65
64
63
P23/A3/A19
P22/A2/A18
P21/A1/A17
P20/A0/A16
VCC
Stepping
motor control
○
○
TMP93PW40
Pin
no.
Memory interface
Programmable
Pull Pull
up down
○
○
○
○
○
○
○
○
62 VSS
61 WDTOUT
60 P17/AD15/A15
59 P16/AD14/A14
58 P15/AD13/A13
P92/ CTS0 /SCLK0 19
P93/TXD1
20
57 P14/AD12/A12
56 P13/AD11/A11
P94/RXD1
P95/SCLK1
21
22
55 P12/AD10/A10
54 P11/AD9/A9
AM8/ AM16
23
CLK
24
53 P10/AD8/A8
52 P07/AD7
VCC
25
51 P06/AD6
VSS
26
50 P05/AD5
X1
27
49 P04/AD4
X2
28
48 P03/AD3
EA
29
47 P02/AD2
RESET
30
46 P01/AD1
P96/XT1
31
45 P00/AD0
P97/XT2
32
44 VCC
TEST1
33
43 ALE
TEST2
34
42 PA7/SCOUT
PA0
35
41 PA6
PA1
36
40 PA5
PA2
37
39 PA4
38 PA3
Figure 2.1.1 Pin Assignment (100-Pin LQFP)
93PW40-3
2004-02-10
TMP93PW40
2.2
Pin Names and Functions
The names of the input/output pins and their functions are described below.
(1) Pin names and functions of TMP93PW40 in MCU mode. (Table 2.2.1 to Table 2.2.4)
Table 2.2.1 Names and Functions in MCU Mode (1/4)
Pin Names
Number
of Pins
I/O
Functions
P00 to P07
AD0 to AD7
8
I/O
3 state
Port 0: I/O port that allows I/O to be selected on a bit basis.
Address/data (lower) : 0 to 7 for address/data bus.
P10 to P17
AD8 to AD15
A8 to A15
8
I/O
3 state
Output
Port 1: I/O port that allows I/O to be selected on a bit basis.
Address/data (upper): 8 to 15 for address/data bus.
Address: 8 to 15 for address bus.
P20 to P27
8
I/O
Output
Output
Port 2: I/O port that allows selection of I/O on a bit basis
(with pull-down resistor).
Address: 0 to 7 for address bus.
Address: 16 to 23 for address bus.
1
Output
Output
Port 30: Output port.
Read: Strobe signal for reading external memory.
1
Output
Output
Port 31: Output port.
Write: Strobe signal for writing data on pins AD0 to AD7.
1
I/O
Output
Port 32: I/O port (with pull-up resistor).
High write: Strobe signal for writing data on pins AD8 to AD15.
1
I/O
Input
Port 33: I/O port (with pull-up resistor).
Wait: Pin used to request CPU bus wait.
1
I/O
Input
Port 34: I/O port (with pull-up resistor).
Bus request: Signal used to request high impedance for AD0 to AD15, A0 to
A23, RD , WR , HWR , R / W , RAS , CS0 , CS1 , and CS2 pins.
(for external DMAC)
1
I/O
Output
Port 35: I/O port (with pull-up resistor).
Bus acknowledge: Signal indicating that AD0 to AD15, A0 to A23, RD , WR ,
HWR , R / W , RAS , CS0 , CS1 , and CS2 pins are at high impedance after
receiving BUSRQ . (for external DMAC)
1
I/O
Output
Port 36: I/O port (with pull-up resistor).
Read/write: 1 represents read or dummy cycle; 0, write cycle.
1
I/O
Output
Port 37: I/O port (with pull-up resistor).
Row address strobe: Outputs RAS strobe for DRAM.
1
I/O
Output
Output
Port 40: I/O port (with pull-up resistor).
Chip select 0: Outputs 0 when address is within specified address area.
Column address strobe 0: Outputs CAS strobe for DRAM when address is
within specified address area.
A0 to A7
A16 to A23
P30
RD
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
P36
R/W
P37
RAS
P40
CS0
CAS0
Note:
With the external DMA controller, this device’s built-in memory or built-in I/O cannot be accessed
using the BUSRQ and BUSAK pins.
93PW40-4
2004-02-10
TMP93PW40
Table 2.2.2 Names and Functions in MCU Mode (2/4)
Pin Names
Number
of Pins
I/O
Functions
1
I/O
Output
Output
Port 41: I/O port (with pull-up resistor).
Chip select 1: Outputs 0 if address is within specified address area.
Column address strobe 1: Outputs CAS strobe for DRAM if address is within
specified address area.
1
I/O
Output
Output
Port 42: I/O port (with pull-down resistor).
Chip select 2: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within
specified address area.
P50 to P57
AN0 to AN7
8
Input
Input
Port 5: Input port.
Analog input: Input to AD converter.
VREFH
1
Input
Pin for reference voltage input to AD converter (H).
VREFL
1
Input
P60 to P63
4
I/O
P41
CS1
CAS1
P42
CS2
CAS2
PG00 to PG03
P64 to P67
Output
4
PG10 to PG13
I/O
Output
Pin for reference voltage input to AD converter (L).
Ports 60 to 63: I/O ports that allow selection of I/O on a bit basis
(with pull-up resistor).
Pattern generator ports: 00 to 03.
Ports 64 to 67: I/O ports that allow selection of I/O on a bit basis
(with pull-up resistor).
Pattern generator ports: 10 to 13.
P70
TI0
1
I/O
Input
Port 70: I/O port (with pull-up resistor).
Timer input 0: Timer 0 input.
P71
TO1
1
I/O
Output
Port 71: I/O port (with pull-up resistor).
Timer output 1: Timer 0 or 1 output.
P72
TO2
1
I/O
Output
Port 72: I/O port (with pull-up resistor).
PWM output 2: 8-bit PWM timer 2 output.
P73
TO3
1
I/O
Output
Port 73: I/O port (with pull-up resistor).
PWM output 3: 8-bit PWM timer 3 output.
P80
TI4
INT4
1
I/O
Input
Input
Port 80: I/O port (with pull-up resistor).
Timer input 4: Timer 4 count/capture trigger signal input.
Interrupt request pin 4: Interrupt request pin with programmable rising/falling
edge.
P81
TI5
INT5
1
I/O
Input
Input
Port 81: I/O port (with pull-up resistor).
Timer input 5: Timer 4 count/capture trigger signal input.
Interrupt request pin 5: Interrupt request pin with rising edge.
P82
TO4
1
I/O
Output
Port 82: I/O port (with pull-up resistor).
Timer output 4: Timer 4 output pin.
P83
TO5
1
I/O
Output
Port 83: I/O port (with pull-up resistor).
Timer output 5: Timer 4 output pin.
93PW40-5
2004-02-10
TMP93PW40
Table 2.2.3 Names and Functions in MCU Mode (3/4)
Pin names
Number
of pins
I/O
Functions
P84
TI6
INT6
1
I/O
Input
Input
Port 84: I/O port (with pull-up resistor).
Timer input 6: Timer 5 count/capture trigger signal input.
Interrupt request pin 6: Interrupt request pin with programmable rising/falling
edge.
P85
TI7
INT7
1
I/O
Input
Input
Port 85: I/O port (with pull-up resistor).
Timer input 7: Timer 5 count/capture trigger signal input.
Interrupt request pin 7: Interrupt request pin with rising edge.
P86
TO6
1
I/O
Output
P87
INT0
1
I/O
Input
P90
TXD0
1
I/O
Output
Port 90: I/O port (with pull-up resistor).
Serial send data 0.
P91
RXD0
1
I/O
Input
Port 91: I/O port (with pull-up resistor).
Serial receive data 0.
P92
1
I/O
Input
I/O
Port 92: I/O port (with pull-up resistor).
Serial data send enable 0 (Clear to send).
Serial clock I/O 0.
P93
TXD1
1
I/O
Output
Port 93: I/O port (with pull-up resistor).
Serial send data 1.
P94
RXD1
1
I/O
Input
Port 94: I/O port (with pull-up resistor).
Serial receive data 1.
P95
SCLK1
1
I/O
I/O
Port 95: I/O port (with pull-up resistor).
Serial clock I/O 1.
CTS0
SCLK0
Port 86: I/O port (with pull-up resistor).
Timer output 6: Timer 5 output pin.
Port 87: I/O port (with pull-up resistor).
Interrupt request pin 0: Interrupt request pin with programmable level/rising
edge.
PA0 to PA6
7
I/O
PA7
SCOUT
1
I/O
Output
Port A7: I/O port.
System clock output: Outputs system clock or 1/2 oscillation clock for
synchronizing to external circuit.
Watchdog timer output pin.
WDTOUT
1
Output
NMI
1
Input
CLK
1
Output
EA
1
Input
Port A: I/O ports.
Non-maskable interrupt request pin: Interrupt request pin with falling edge.
Can also be operated at rising edge by program.
Clock output: Outputs “system clock ÷ 2” clock.
Pulled-up during reset.
Can be set to output disable for reducing noise.
External access: “1” should be inputted with TMP93PW40.
93PW40-6
2004-02-10
TMP93PW40
Table 2.2.4 Names and Functions in MCU Mode (4/4)
Pin Names
Number
of Pins
I/O
Functions
AM8/ AM16
1
Input
ALE
1
Output
Address mode: Selects external data bus width.
“1” should be inputted. The data bus width for external
access is set by chip select/wait control register, port 1
control register.
Address latch enable
Can be set to output disable for reducing noise.
RESET
1
Input
X1/X2
2
Input/Output
High-frequency oscillator connecting pin.
XT1
P96
1
Input
I/O
Low-frequency oscillator connecting pin.
Port 96: I/O port (open-drain output).
XT2
P97
1
Output
I/O
Low-frequency oscillator connecting pin.
Port 97: I/O port (open-drain output).
TEST1/TEST2
2
Output/Input
VCC
3
VSS
3
GND pin (0 V).
AVCC
1
Power supply pin for AD converter.
AVSS
1
GND pin for AD converter (0 V).
Note:
Reset: Initializes LSI. (with pull-up resistor)
TEST1 should be connected with TEST2 pin.
Do not connect to any other pins.
Power supply pin.
Pull-up/pull-down resistor can be released from the pin by software (except RESET pin).
93PW40-7
2004-02-10
TMP93PW40
(2) PROM mode
Table 2.2.5 Names and Functions of PROM Mode
Pin Function
Pin
Number
Input/
Output
A7 to A0
8
Input
A15 to A8
8
Input
A16
1
Input
Function
Pin Name (MCU Mode)
P27 to P20
Memory address of program
P17 to P10
P33
D7 to D0
8
I/O
Memory data of program
P07 to P00
CE
1
Input
Chip enable
P32
Output control
P30
Program control
P31
12.75 V/5 V (Power supply of program)
EA
6.25 V/5 V
VCC, AVCC
0V
VSS, AVSS
OE
1
Input
PGM
1
VPP
1
VCC
4
VSS
4
Input
Power
supply
Power
supply
Power
supply
Pin
Number
Input/
Output
Pin Function
P34
1
Input
RESET
1
Input
CLK
1
Input
ALE
1
Output
X1
1
Input
X2
1
Output
P42 to P40
P37 to P35
AM8/ AM16
7
Input
TEST1, TEST2
2
Input/
Output
48
I/O
P57 to P50
P67 to P60
P73 to P70
P87 to P80
P97 to P90
PA7 to PA0
VREFH
VREFL
Disposal of Pin
Fix to low level (security pin)
Fix to low level (PROM mode)
Open
Crystal
Fix to high level
TEST1 should be connected with TEST2 pin.
Do not connect to any other pins.
Open
NMI
WDTOUT
93PW40-8
2004-02-10
TMP93PW40
3.
Operation
This section describes in blocks the functions and basic operations of TMP93PW40.
The TMP93PW40 has ROM in place of the mask ROM which is included in the TMP93CW40.
The other configuration and functions are the same as the TMP93CW40. Regarding the function of
the TMP93PW40, which is not described herein, see the TMP93CW40.
The TMP93PW40 has two operational modes: MCU mode and PROM mode.
3.1
MCU Mode
(1) Mode setting and function
The MCU mode is set by opening the CLK pin (Output status). In the MCU mode, the
operation is same as TMP93CW40.
3.2
Memory Map
Figure 3.2.1 are memory map of the TMP93PW40.
000000H
00000H
Internal I/O
000080H
Internal RAM
001080H
External area
008000H
Internal PROM
(128 Kbytes)
Internal
PROM
(128 Kbytes)
028000H
External area
FFFF00H
1FFFFH
Reserved
FFFFFFH
Memory map in MCU mode
Memory map in PROM mode
Figure 3.2.1 Memory Map
93PW40-9
2004-02-10
TMP93PW40
3.3
PROM Mode
(1) Mode setting and function
PROM mode is set by setting the RESET and CLK pins to the “L” level. The
programming and verification for the internal PROM is achieved by using a general PROM
programmer with the adaptor socket.
a.
OTP adaptor
BM11129: TMP93PS40DF, TMP93PW40DF adaptors
b.
Setting OTP adaptor
Set the switch (SW1) to N side.
c.
Setting PROM programmer
i)
Set PROM type to TC571000D.
Size: 1 Mbits (128 K × 8 bits)
VPP: 12.75 V
tpw: 100 µs
The electric signature mode (Hereinafter referred to as “signature”. ) is not
supported. Therefore if signature is used, the device is damaged because 12.75 V
is applied to A9 of address. Do not use signature.
ii) Transferring the data (copy)
In TMP93PW40, PROM is placed on addresses 00000 to 1FFFFH in PROM
mode, and addresses 08000H to 27FFFH in MCU mode. Therefore data should be
transferred to addresses 00000 to 1FFFFH in PROM mode using the object
converter (tuconv) or the block transfer mode (see instruction manual of PROM
programmer.) or making the object data.
iii) Setting the programming address
Start address: 00000H
End address: 1FFFFH
93PW40-10
2004-02-10
TMP93PW40
d.
Programming
Program/verify according to the procedures of PROM programmer.
VPP(12.75 V/5 V)
VCC
EA
TEST1
P30
OE
TEST2
P32
CE
P31
PGM
P07
to
P00
D7
to
D0
P33
A16
to
A0
AVCC, VCC
P17
to
P10
P27
to
P20
RESET
CLK
VCC
X1
X2
P42 to P40,
P37 to P35,
AM8/ AM16
* Use the 10 MHz
resonator in case of
programming and
verification by a general
EPROM programmer.
VSS
AVSS
P34
SECURITY
Figure 3.3.1 PROM Mode Pin Setting
(2) Programming flow chart
The programming mode is set by applying 12.75 V (programming voltage) to the VPP pin
when the following pins are set as follows,
(VCC: 6.25 V, RESET : “L” level, CLK: “L” level).
While address and data are fixed and CE pin is set to “L” level, 0.1 ms of “L” level pulse is
applied to PGM pin to program the data.
Then the data in the address is verified.
If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin.
This programming procedure is repeated until correct data is read from the address. (25
times maximum)
Subsequently, all data are programmed in all addresses.
The verification for all data is done under the condition of VPP = VCC = 5 V after all data
were written.
Figure 3.3.2 shows the programming flow chart.
93PW40-11
2004-02-10
TMP93PW40
High Speed Program Writing
Start
VCC = 6.25 V ± 0.25 V
VPP = 12.75 V ± 0.25 V
Address = Start address
X=0
Program 0.1 ms pulse
X=X+1
X > 25?
Yes
No
Error
Address = Address + 1
Verify
OK
No
Last address?
Yes
VCC = 5 V
VPP = 5 V
Read all byte
Error
OK
Pass
Failure
Figure 3.3.2 Flow Chart
93PW40-12
2004-02-10
TMP93PW40
(3) Security bit
The TMP93PW40 has a security bit.
If the security bit is programmed to “0”, the content of the PROM can not be read in
PROM mode.
(Outputs data FFH)
How to program the security bit.
The difference from the programming procedures described in section 3.3 (1) are follows.
a.
Setting OTP adapter
Set the switch (SW1) to S side.
b.
Setting PROM programmer
ii) Transferring the data
iii) Setting programming address
The security bit is in bit 0 of address 00000H.
Set the start address 00000H and the end address 00000H.
Set the data FEH at the address 00000H.
93PW40-13
2004-02-10
TMP93PW40
4.
Electrical Characteristics
4.1
“X” used in an expression shows a frequency of clock fFPH
selected by SYSCR1<SYSCK>. If a clock gear or a low
speed oscillator is selected, a value of “X” is different. The
value in an example is calculated at fc, gear = 1/fc
(SYSCR1 < SYSCK, GEAR2:0 > = “0000” ).
Maximum Ratings (TMP93PW40DF)
Parameter
Symbol
Rating
Unit
Power supply voltage
VCC
−0.5 to 6.5
V
Input voltage
VIN
−0.5 to VCC + 0.5
V
Output current (total)
ΣIOL
120
Output current (total)
ΣIOH
−80
mA
Power dissipation (Ta = 85°C)
PD
600
mW
Soldering temperature (10 s)
TSOLDER
260
°C
Storage temperature
TSTG
−65 to 150
°C
Operating temperature
TOPR
−40 to 85
°C
mA
Note: The maximum ratings are rated values which must not be exceeded during
operation, even for an instant. Any one of the ratings must not be exceeded. If any
maximum rating is exceeded, a device may break down or its performance may be
degraded, causing it to catch fire or explode resulting in injury to the user. Thus,
when designing products which include this device, ensure that no maximum rating
value will ever be exceeded.
4.2
DC Characteristics (1/2)
Ta = −40 to 85°C
Parameter
Input high voltage
Input low voltage
Power supply voltage
AVCC = VCC
AVCC = VSS = 0 V
Symbol
Condition
fc = 4 to 20 MHz
VCC
AD0 to AD15
VIL
Port 2 to port A
(except P87)
VIL1
fc = 4 to 12.5 MHz
fs = 30 to
34 kHz
Min
Typ. (Note)
Max
Unit
5.5
V
4.5
2.7
VCC ≥ 4.5 V
0.8
VCC < 4.5 V
0.6
−0.3
VCC = 2.7 to 5.5 V
0.3 VCC
RESET , NMI , INT0
VIL2
EA , AM8/ AM16
VIL3
0.3
X1
VIL4
0.2 VCC
AD0 to AD15
VIH
Port 2 to port A
(except P87)
VIH1
RESET , NMI , INT0
VIH2
EA , AM8/ AM16
VIH3
X1
VIH4
Output low voltage
0.25 VCC
VCC ≥ 4.5 V
2.2
VCC < 4.5 V
2.0
0.7 VCC
VCC = 2.7 to 5.5 V
VCC + 0.3
0.75 VCC
VCC − 0.3
0.8 VCC
VOL
IOL = 1.6 mA
(VCC = 2.7 to 5.5 V)
VOH1
IOH = −400 µA
(VCC = 3 V ± 10%)
2.4
VOH2
IOH = −400 µA
(VCC = 5 V ± 10%)
4.2
Output high voltage
V
0.45
V
Note: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted.
93PW40-14
2004-02-10
TMP93PW40
4.2
DC Characteristics (2/2)
Parameter
Symbol
Darlington drive current
(8 output pins max)
IDAR
(Note 2)
Condition
VEXT = 1.5 V
REXT = 1.1 kΩ
(when VCC = 5 V ± 10%)
Min
Typ.
(Note 1)
−1.0
Max
Unit
−3.5
mA
Input leakage current
ILI
0.0 ≤ VIN ≤ VCC
0.02
±5
Output leakage current
ILO
0.2 ≤ VIN ≤ VCC − 0.2
0.05
±10
Powerdown voltage
(at STOP, RAM back-up)
RESET pull-up resistor
VSTOP
RRST
Pin capacitance
CIO
Schmitt width
RESET , NMI , INT0
VTH
Programmable
pull-down resistor
RKL
Programmable
pull-up resistor
RKH
VIL2 = 0.2 VCC,
VIH2 = 0.8 VCC
2.0
6.0
VCC = 5 V ± 10%
50
150
VCC = 3 V ± 10%
80
200
fc = 1 MHz
10
0.4
1.0
VCC = 5 V ± 10%
10
80
30
150
VCC = 5 V ± 10%
50
150
VCC = 3 V ± 10%
100
25
30
RUN
17
25
IDLE2
10
15
VCC = 3 V ± 10%
fc = 12.5 MHz
(Typ. : VCC = 3.0 V )
NORMAL (Note 3)
NORMAL2 (Note 4)
RUN
IDLE2
ICC
IDLE1
SLOW (Note 3)
RUN
IDLE2
VCC = 3 V ± 10%
fs = 32.768 kHz
(Typ. :VCC = 3.0 V )
IDLE1
Ta ≤ 70°C
mA
3.5
5
6.5
10
9.5
13
5.0
9
3.0
5
0.8
1.5
20
45
16
40
10
30
5
25
Ta ≤ 50°C
STOP
kΩ
300
24
IDLE1
kΩ
V
19
NORMAL2 (Note 4)
V
pF
VCC = 3 V ± 10%
VCC = 5 V ± 10%
fc = 20 MHz
NORMAL (Note 3)
µA
mA
µA
10
0.2
Ta ≤ 85°C
20
µA
50
Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted.
Note 2: IDAR is guranteed for total of up to 8 ports.
Note 3: The condition of measurement of ICC (NORMAL/SLOW).
Only CPU operates. Output ports are open and Input ports fixed.
Note 4: The condition of measurement of ICC (NORMAL 2).
CPU and all peripherals operate. Output ports are open and input ports fixed.
93PW40-15
2004-02-10
TMP93PW40
4.3
AC Characteristics
(1) VCC = 5 V ± 10%
No.
Parameter
Variable
Symbol
16 MHz
Min
Max
Min
31250
Max
20 MHz
Min
Unit
Max
1
Osc. period ( = x)
tOSC
50
62.5
50
ns
2
CLK pulse width
tCLK
2x − 40
85
60
ns
3
A0 to A23 valid → CLK hold
tAK
0.5x − 20
11
5
ns
4
CLK valid → A0 to A23 hold
tKA
1.5x − 70
24
5
ns
5
A0 to A15 valid → ALE fall
tAL
0.5x − 15
16
10
ns
6
ALE fall → A0 to A15 hold
tLA
0.5x − 20
11
5
ns
7
ALE high pulse width
tLL
x − 40
23
10
ns
8
ALE fall → RD / WR fall
tLC
0.5x − 25
6
0
ns
9
RD / WR rise → ALE rise
tCL
0.5x − 20
11
5
ns
10
A0 to A15 valid → RD / WR fall
tACL
x − 25
38
25
ns
11
A0 to A23 valid → RD / WR fall
tACH
1.5x − 50
44
25
ns
12
RD / WR rise → A0 to A23 hold
tCA
0.5x − 25
6
0
13
A0 to A15 valid → D0 to D15 input
tADL
14
A0 to A23 valid → D0 to D15 input
15
RD fall → D0 to D15 input
16
RD low pulse width
tRR
2.0x − 40
85
60
17
RD rise → D0 to D15 hold
tHR
0
0
0
ns
18
RD rise → A0 to A15 output
tRAE
x − 15
48
35
ns
19
WR low pulse width
tWW
2.0x − 40
85
60
ns
20
D0 to D15 valid → WR rise
tDW
2.0x − 55
70
45
ns
21
WR rise → D0 to D15 hold
tWD
0.5x − 15
16
10
22
A0 to A23 valid → WAIT input
(1 + N) WAIT
mode
23
A0 to A15 valid → WAIT input
(1 + N) WAIT
mode
24
RD / WR fall → WAIT hold
(1 + N) WAIT
mode
tCW
25
tAPH
26
A0 to A23 valid → Port input
A0 to A23 valid → Port hold
27
WR rise → Port valid
tCP
28
tASRH
1.0x − 40
23
10
ns
29
A0 to A23 valid → RAS fall
A0 to A15 valid → RAS fall
tASRL
0.5x − 15
16
10
ns
30
RAS fall → D0 to D15 input
tRAC
31
RAS fall → A0 to A15 hold
tRAH
0.5x − 15
16
10
ns
32
RAS low pulse width
tRAS
2.0x − 40
85
60
ns
33
RAS high pulse width
tRP
2.0x − 40
85
60
ns
34
CAS fall → RAS rise
tRSH
1.0x − 40
23
10
ns
35
RAS rise → CAS rise
tRSC
0.5x − 25
6
0
ns
36
RAS fall → CAS fall
tRCD
1.0x − 40
23
10
ns
37
CAS fall → D0 to D15 input
tCAC
38
CAS low pulse width
tCAS
ns
3.0x − 55
133
95
ns
tADH
3.5x − 65
154
110
ns
tRD
2.0x − 60
65
40
ns
ns
ns
tAWH
3.5x − 90
129
85
ns
tAWL
3.0x − 80
108
70
ns
5
ns
tAPH2
2.0x + 0
125
2.5x − 120
2.5x + 50
100
36
206
200
55
29
64
ns
200
86
1.5x − 65
1.5x − 30
175
200
2.5x − 70
ns
10
40
ns
ns
ns
ns
AC measuring conditions
•
Output level: High 2.2 V/Low 0.8 V, CL = 50 pF
(However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR ,
R/ W , CLK, RAS , CAS0 to CAS2 )
•
Input level: High 2.4 V/Low 0.45 V (AD0 to AD15)
High 0.8 VCC/Low 0.2 VCC (Except for AD0 to AD15)
93PW40-16
2004-02-10
TMP93PW40
(2) VCC = 3 V ± 10%
No.
Parameter
Symbol
Variable
Min
Max
31250
12.5 MHz
Min
Max
Unit
1
Osc. period ( = x)
tOSC
80
80
ns
2
CLK pulse width
tCLK
2x − 40
120
ns
3
A0 to A23 valid → CLK hold
tAK
0.5x − 30
10
ns
4
CLK valid → A0 to A23 hold
tKA
1.5x − 80
40
ns
5
A0 to A15 valid → ALE fall
tAL
0.5x − 35
5
ns
6
ALE fall → A0 to A15 hold
tLA
0.5x − 35
5
ns
7
ALE high pulse width
tLL
x − 60
20
ns
8
ALE fall → RD / WR fall
tLC
0.5x − 35
5
ns
9
RD / WR rise → ALE rise
tCL
0.5x − 40
0
ns
10
A0 to A15 valid → RD / WR fall
tACL
x − 50
30
ns
11
A0 to A23 valid → RD / WR fall
tACH
1.5x − 50
70
ns
12
RD / WR rise → A0 to A23 hold
tCA
0.5x − 40
0
13
A0 to A15 valid → D0 to D15 input
tADL
14
A0 to A23 valid → D0 to D15 input
15
RD fall → D0 to D15 input
16
RD low pulse width
tRR
2.0x − 40
17
RD rise → D0 to D15 hold
tHR
0
18
RD rise → A0 to A15 output
tRAE
19
WR low pulse width
20
D0 to D15 valid → WR rise
21
WR rise → D0 to D15 hold
22
A0 to A23 valid → WAIT input
(1 + N) WAIT
mode
tAWH
23
A0 to A15 valid → WAIT input
(1 + N) WAIT
mode
tAWL
24
RD / WR fall → WAIT hold
(1 + N) WAIT
mode
25
A0 to A23 valid → Port input
A0 to A23 valid → Port hold
tAPH
26
27
WR rise → Port valid
tCP
28
tASRH
1.0x − 60
20
29
A0 to A23 valid → RAS fall
A0 to A15 valid → RAS fall
tASRL
0.5x − 40
0
30
RAS fall → D0 to D15 input
tRAC
31
RAS fall → A0 to A15 hold
tRAH
0.5x − 25
15
ns
32
RAS low pulse width
tRAS
2.0x − 40
120
ns
33
RAS high pulse width
tRP
2.0x − 40
120
ns
34
CAS fall → RAS rise
tRSH
1.0x − 55
25
ns
35
RAS rise → CAS rise
tRSC
0.5x − 25
15
ns
36
RAS fall → CAS fall
tRCD
1.0x − 40
40
ns
37
CAS fall → D0 to D15 input
tCAC
38
CAS low pulse width
tCAS
ns
3.0x − 110
130
ns
tADH
3.5x − 125
155
ns
tRD
2.0x − 115
45
ns
120
ns
0
ns
x − 25
55
ns
tWW
2.0x − 40
120
ns
tDW
2.0x − 120
40
ns
tWD
0.5x − 40
0
tCW
tAPH2
3.5x − 130
3.0x − 100
2.0x + 0
ns
150
ns
140
ns
160
2.5x − 195
2.5x + 50
ns
5
250
200
ns
0
80
ns
ns
110
1.5x − 120
1.5x − 40
ns
200
2.5x − 90
ns
ns
ns
ns
AC measuring conditions
•
Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF
•
Input level:
High 0.9 × VCC/Low 0.1 × VCC
93PW40-17
2004-02-10
TMP93PW40
(1) Read cycle
tOSC
X1
tCLK
CLK
tKA
tAK
A0 to A23
CS0 to CS2
R/W
tAWH
tCW
tAWL
WAIT
tAPH
tAPH2
Port input (Note)
tASRH
tRP
tRSH
RAS
tRAS
tASRL
tRAH
tRCD
CAS0 to CAS2
tRAC
tCAS
tCAC
tCA
tADH
RD
tACH
tRR
tACL
tLC
A0 to A15
AD0 to AD15
tAL
ALE
Note:
tRSC
tRD
tADL
tRAE
tHR
D0 to D15
tLA
tCL
tLL
Since the CPU accesses the internal area to read data from a port, the control signals of external
pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics of
port input/output shown above are typical representation. For details, contact your local Toshiba
sales representative.
93PW40-18
2004-02-10
TMP93PW40
(2) Write cycle
X1
CLK
A0 to A23
CS0 to CS2
R/ W
WAIT
Port output (Note)
tCP
RAS
CAS0 to CAS2
tWW
WR , HWR
tWD
tDW
AD0 to AD15
A0 to A15
D0 to D15
ALE
Note:
Since the CPU accesses the internal area to write data to a port, the control signals of external pins
such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded
as depicting internal operation. Please also note that the timing and AC characteristics of port
input/output shown above are typical representation. For details, contact your local Toshiba sales
representative.
93PW40-19
2004-02-10
TMP93PW40
4.4
AD Conversion Characteristics
AVCC = VCC, AVSS = VSS
Parameter
Analog reference voltage (+)
Symbol
VREFH
Analog reference voltage (−)
VREFL
Analog input voltage range
VAIN
Analog current for analog reference
voltage
<VREFON> = 1
<VREFON> = 0
Error (excluding quantizing
error)
Power Supply
Min
Typ.
Max
VCC = 5 V ± 10%
VCC − 1.5 V
VCC
VCC
VCC = 3 V ± 10%
VCC − 0.2 V
VCC
VCC
VCC = 5 V ± 10%
VSS
VSS
VSS + 0.2 V
VCC = 3 V ± 10%
VSS
VSS
VSS + 0.2 V
VREFL
IREF
(VREFL = 0 V)
–
Unit
V
VREFH
VCC = 5 V ± 10%
0.5
1.5
VCC = 3 V ± 10%
0.3
0.9
mA
VCC = 2.7 to 5.5 V
0.02
5.0
VCC = 5 V ± 10%
±1.0
±3.0
µA
VCC = 3 V ± 10%
±1.0
±3.0
LSB
Note 1: 1LSB = (VREFH − VREFL) /2 [V]
10
Note 2: Minimum operation frequency
The operation of the AD converter is guaranteed only when fc (high-frequency oscillator) is used. (It
is not guaranteed when fs is used.) Additionally, it is guaranteed with 4 MHz or more.
Note 3: The value ICC includes the current which flows through the AVCC pin.
93PW40-20
2004-02-10
TMP93PW40
4.5
Serial Channel Timing
(1) I/O interface mode
a.
SCLK input mode
Parameter
32.768 kHz
(Note 1)
Variable
Symbol
Min
Max
Min
Max
12.5 MHz
Min
Max
20 MHz
Min
Unit
Max
SCLK cycle
tSCY
16X
488 µs
1280
800
ns
Output data
→ Rising edge or falling edge (Note 2) of
SCLK
tOSS
tSCY/2 − 5X − 50
91.5 µs
190
100
ns
SCLK rising edge or falling edge (Note 2)
→ Output data hold
tOHS
5X − 100
152 µs
300
150
ns
SCLK rising edge or falling edge (Note 2)
→ Input data hold
tHSR
0
0
0
0
ns
SCLK rising edge or falling edge (Note 2)
→ Effective data input
tSRD
tSCY − 5X − 100
336 µs
780
450
ns
Note 1: When fs is used as system clock (fSYS) or fs is used as input clock to prescaler.
Note 2: SCLK rising/falling timing … SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK.
b.
SCLK output mode
Parameter
Variable
Symbol
32.768 kHz
(Note)
12.5 MHz
20 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
SCLK cycle (programmable)
tSCY
16X
8192X
488
250 ms
1.28
655.36
0.8
409.6
Output data → SCLK rising edge
tOSS
tSCY − 2X − 150
427 µs
970
550
ns
SCLK rising edge → Output data hold
tOHS
2X − 80
60 µs
80
20
ns
SCLK rising edge → Input data hold
tHSR
0
0
0
0
SCLK rising edge → Effective data input
tSRD
tSCY − 2X − 150
428 µs
µs
ns
970
550
ns
Note: When fs is used as system clock (fSYS) or fs is used as input clock to prescaler.
tSCY
SCLK
Output mode/
Input rising mode
SCLK
(Input falling mode)
Output data
TxD
tOHS
tOSS
0
1
2
tSRD
Input data
RxD
3
tHSR
0
1
2
3
Valid
Valid
Valid
Valid
93PW40-21
2004-02-10
TMP93PW40
4.6
Timer/Counter Input Clock (TI0, TI4, TI5, TI6 and TI7)
Variable
Parameter
12.5 MHz
20 MHz
Unit
Symbol
Min
Max
Min
Max
Min
Max
Clock cycle
tVCK
8X + 100
740
500
ns
Low level clock pulse width
tVCKL
4X + 40
360
240
ns
High level clock pulse width
tVCKH
4X + 40
360
240
ns
4.7
Interrupt and Capture
(1) NMI and INT0 interrupts
Parameter
Variable
12.5 MHz
20 MHz
Unit
Symbol
Min
Max
Min
Max
Min
Max
NMI , INT0 low level pulse width
tINTAL
4X
320
200
ns
NMI , INT0 high level pulse width
tINTAH
4X
320
200
ns
(2) INT4 to 7 interrupts and capture
Input pulse width of INT4 to 7 depends on the operation clock of CPU and Timer (9 bit
prescaler). The following shows the pulse width in each clock.
System Clock Prescaler Clock tINTBL (INT4 to 7 low-level pulse width) tINTBH (INT4 to 7 high-level pulse width)
Selected
Selected
Unit
Variable
20 MHz
Variable
20 MHz
<SYSCK>
<PRCK1:0>
Min
Min
Min
Min
0 (fc)
1 (fs)
(Note 2)
00 (fFPH)
8X + 100
500
8X + 100
500
01 (fs)
8XT + 0.1
244.3
8XT + 0.1
244.3
10 (fc/16)
128X + 0.1
6.5
128X + 0.1
6.5
00 (fFPH)
8XT + 0.1
244.3
8XT + 0.1
244.3
01 (fs)
ns
µs
Note 1: XT represents the cycle of the low frequency clock fs. Calculated at fs = 32.768 kHz.
Note 2: When fs is used as the system clock, fc/16 can not be selected for the prescaler clock.
4.8
SCOUT Pin AC Characteristics
Parameter
Variable
Min
High-level pulse
width
VCC = 5 V ± 10%
Low-level pulse
width
VCC = 5 V ± 10%
VCC = 3 V ± 10%
VCC = 3 V ± 10%
12.5 MHz
20 MHz
Symbol
tSCH
tSCL
Max
Min
Max
Min
0.5X − 10
30
15
0.5X − 20
20
−
0.5X − 10
30
15
0.5X − 20
20
−
Unit
Max
−
−
ns
ns
Measurement condition
•
Output level: High 2.2 V/Low 0.8 V, CL = 10 pF
tSCH
tSCL
SCOUT
93PW40-22
2004-02-10
TMP93PW40
4.9
Timing Chart for Bus Request ( BUSRQ )/Bus Acknowledge ( BUSAK )
(Note 1)
CLK
tBRC
tBRC
tCBAL
BUSRQ
tCBAH
BUSAK
tBAA
(Note 2)
tABA
AD0 to AD15, A0 to A23,
CS0 to CS2 , R/ W , RAS
CAS0 to CAS2
(Note 2)
RD , WR , HWR
ALE
Parameter
Variable
Symbol
Min
Max
Min
Max
Min
Max
120
Unit
BUSRQ set-up time to CLK
tBRC
tCBAL
1.5x + 120
240
195
CLK → BUSAK rising edge
tCBAH
0.5x + 40
80
65
ns
Output Buffer off to BUSAK
tABA
0
80
0
80
0
80
ns
tBAA
0
80
0
80
0
80
ns
to Output Buffer on
120
20 MHz
CLK → BUSAK falling edge
BUSAK
120
12.5 MHz
ns
ns
Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during
“Wait” cycle.
Note 2: This line only shows the output buffer is off-state.
It doesn’t indicate the signal level is fixed.
Just after the bus is released, the signal level which is set before the bus is released is kept
dynamically by the external capacitance. Therefore, to fix the signal level by an external resistor
during bus releasing, designing is executed carefully because the level-fix will be delayed.
The internal programmable pull-up/pull-down resistor is switched active/non-active by an internal
signal.
93PW40-23
2004-02-10
TMP93PW40
4.10 Read Operation in PROM Mode
DC/AC characteristics
Ta = 25 ± 5°C, VCC = 5V ± 10%
Symbol
Condition
Min
Max
Unit
VPP read voltage
Parameter
VPP
−
4.5
5.5
V
Input high voltage
(A0 to A16, CE , OE , PGM )
VIH1
−
2.2
VCC + 0.3
V
Input low voltage
(A0 to A16, CE , OE , PGM )
VIL1
−
−0.3
0.8
V
VACC
CL = 50 pF
−
2.25TCYC + α
ns
Address to output delay
TCYC = 400 ns (10 MHz clock)
α = 200 ns
4.11 Program Operation in PROM Mode
DC/AC characteristics
Ta = 25 ± 5°C, VCC = 6.25 V ± 0.25 V
Parameter
Symbol
Condition
Min
Typ.
Max
Unit
Programming supply voltage
VPP
−
12.50
12.75
13.00
V
Input high voltage
(D0 to D7, A0 to A16, CE , OE , PGM )
VIH
−
2.6
VCC + 0.3
V
Input low voltage
(D0 to D7, A0 to A16, CE , OE , PGM )
VIL
−
−0.3
0.8
V
VCC supply current
ICC
fc = 10 MHz
−
50
mA
VPP supply current
IPP
VPP = 13.00 V
−
50
mA
PGM program pulse width
tPW
CL = 50 pF
0.095
0.105
ms
93PW40-24
0.1
2004-02-10
TMP93PW40
4.12 Timing Chart of Read Operation in PROM Mode
A0 to A16
CE
OE
PGM
tACC
Data output
D0 to D7
93PW40-25
2004-02-10
TMP93PW40
4.13 Timing Chart of Program Operation in PROM Mode
A0 to A16
CE
OE
D0 to D7
Unknown
Data-in stable
Data-out valid
tPW
PGM
VPP
Note 1: The power supply of VPP (12.75 V) must be turned on at the same time or the later time for a power
supply of VCC and must be turned off at the same time or early time for a power supply of VCC.
Note 2: The device suffers a damage taking out and putting in on the condition of VPP = 12.75 V.
Note 3: The maximum spec of VPP pin is 14.0 V. Be carefull a overshoot at the programming.
93PW40-26
2004-02-10
TMP93PW40
5. Package Dimensions
P-LQFP100-1414-0.50F
Unit: mm
93PW40-27
2004-02-10
TMP93PW40
93PW40-28
2004-02-10