TOSHIBA TLCS-90 Series TMP90PH44 CMOS 8–Bit Microcontrollers The function of this device is exactly the same as the TMP90C844 by programming to the internal PROM. The different points between TMP90PH44 and TMP90C844 are the memory size (ROM/RAM). The TMP90PH44N is in a Shrink Dual Inline Package. (SDIP64-P-750) The TMP90PH44F is in a Quad Flat Package. (QFP64-P-1420A) The following are the memory map of TMP90PH44 and TMP90C844. TMP90PH44N/TMP90PH44F 1. Outline and Characteristics The TMP90PH44 is a system evaluation LSI having a built-in One-Time PROM for (16K byte) for TMP90C844. A programming and verification for the internal PROM is achieved by using a general EPROM programmer with an adapter socket. Figure 1.1. TMP90PH44 Parts No. TMP90PH44N TMP90PH44F ROM OTP 16384 x 8bit Figure 1.2. TMP90C844 RAM Package Adapter Socket No. 64-SDIP BM1148 (Under Development) 64-QFP BM1149 (Under Development) 512 x 8bit The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA. TOSHIBA CORPORATION 1/20 TMP90PH44 Figure 1. 3. TMP90PH44 Block Diagram 2/20 TOSHIBA CORPORATION TMP90PH44 2. Pin Assignment and Functions The TMP90PH44 pin assignment input/output pins name and functions are shown below. 2.1 Pin Assignment Diagram The TMP90PH44N pin assignment are shown in Figure 2.1 (1). Figure 2.1 (1). Pin Assignment (Shrink DIP) TOSHIBA CORPORATION 3/20 TMP90PH44 The TMP90PH44F pin assignment are shown in Figure 2.1 (2). Figure 2.1 (2). Pin Assignment (Flat Package) 4/20 TOSHIBA CORPORATION TMP90PH44 2.2 Pin Names and Functions The TMP90PH44 has MCU mode and PROM mode. (1) MCU Mode (The TMP90C844 and the TMP90PH44 are pin compatible). Table 2.2 Pin Names and Functions (1/2) Pin Name No. of pins P00 ~ P07 /AD0 ~ AD7 8 P10 ~ P17 /A8 ~ A15 8 P20 ~ P27 8 I/O or tristate I/O /Tristate I/O Output (8) /WAIT (1) Address/Data bus: Operates as an 8-bit bidirectional address bus or data bus when using external memory Port 1: An 8-bit I/O port. Each bit can be set for input or output. Address bus:Operates as an address bus (upper 8 bits) when using external memory. Slave bus: When used a s a slave processor, operates as the slave bue for the transfer data to and from the master processor. /Input Wait: Used as an input pin when memory or perpheral LSIs with slow access times are controlled. Port 3: 8-bit I/O port which allows I/O selection on bit basis (with programmable pull-up resistor). P30 ~ P37 8 I/O /SWR (1) /Input /SRD Port 0: An 8-bit I/O port. Each bit can be set for input or output. Port 2: An 8-bit I/O port. Each bit can be set for input or output. I/O /SB0 ~ SB7 Function Slave write: The strobe signal input to write data from the master processor. Slave read: The strobe signal used by the master processor to read data. (1) /Input /SCS (1) /Input Slave chip select: The chip select signal input from the master processor. Command/data: The command/data select signal input from the master processor. C/D (1) Input /STA (1) /Output RxD (1) Input /SCLK (1) /I/O /TxD (1) /Output Status output: Used to report the slave bus status to the master processor. Serial receive data Serial clock Serial transmit data P40 ~ P47 8 I/O Port 4: 8-bit I/O port which allows I/O section on bit basis (with programmable pull-up resistor). /TO1, 3, 4, 5 (4) /Output Timer outputs 1, 3, 4, and 5: Output for timer 0, or timer 1, timer 2, timer 3 and timer 4 (2 lines). /TI0, 2, 4, 5 (4) /Input Timer inputs 0, 2, 4, and 5: Input for timer 0, or timer 1, timer 2 and timer 4 (2 lines). /INT0 (1) /Input Interrupt request terminal 0: Interrupt request pin 0: Level/rise edge programmable interrupt request pin /INT1 (1) /Input Interrupt request terminal 1: Interrupt request pin 1: Rise/fall edge programmable interrupt request pin. INT2 (1) /Input P50 ~ P53 /AN0 ~ AN3 4 Input P56 /RD 1 Output TOSHIBA CORPORATION Interrupt request terminal 2: Interrupt request pin 2: Rise edge interrupt request pin. Port 50 ~ 53: 1-bit output ports. Analog input: 4 analog inputs to A/D converter. Port 56: A 1-bit output port. Read: Strobe signal output for reading external memory. 5/20 TMP90PH44 Table 2.2 Pin Names and Functions (2/2) (2) Pin name No. of pins I/O or tristate P57 /WR 1 Output P60 ~ P63 /M00 ~ M03 4 I/0 /Output P70 ~ P73 /M10 ~ M13 4 I/O Output Function Port 57: A 1-bit output port. Write: Strobe signal output for writing external memory. Port 6: 4-bit I/O port which allows I/O selection on bit basis. Stepping motor control port 0 or pattern generation port 0. Port 7: 4-bit I/O port which allows I/O selection on bit basis. Stepping motor control port 0 or pattern generation port 1. ALE 1 Output Address latch enable CLK 1 Output Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is pulled up internally during resetting. EA 1 Input External access: Connects with VCC pin in the TMP90PH44 built ROM is used. Reset: Initializes the TMP90PH44. (pull-up resistance is built-in). RESET 1 Input X1, X2 2 I/O Crystal oscillator connection pin VREF 1 – Input of reference voltage to A/D converter AGND 1 – GND pin for A/D converter VCC 1 – Power supply (+5V +/- 10%) GND 1 – GND pin (0V) PROM Mode Table 2.3 Pin Function Name No. of pins I/O A7 ~ A0 8 Input A13 ~ A8 6 Input 2 Input D7 ~ D0 8 I/0 OE 1 Input Output Enable Input P26 CE 1 Input Chip Enable Input P27 VPP 1 Power Supply 12.5V/5V (Programming Power Supply) EA VCC 1 Power Supply 5V VCC VSS 1 Power Supply 0V VSS Pin Name No. of pins I/O P20 ~ P27 8 Input Be fixed to “L” level. P40 ~ P44 5 Input Be fixed to “L or H” level. P45, P46 2 Input Be fixed to “H” level. P47 1 Input Be fixed to “L or H” level. P50 ~ P53 P30 ~ P37 4 8 Input Be fixed to “L or H” level. A14 A15 6/20 Function Program Memory Address Input Pin Name (MCU mode) P73 ~ P70 P63 ~ P60 P15 ~ P10 P16 Be fixed to “L” level , P17 Data Input/Output P07 ~ P00 Pin Setting VREF 1 – Be fixed to “L” level. AGND 1 – Be fixed to “L” level. RESET 1 Input Be fixed to “L” level. CLK 1 Input Be fixed to “L” level. ALE 1 Output Open X1 1 Input X2 1 Output Resonator connection pin TOSHIBA CORPORATION TMP90PH44 3. Operation The TMP90PH44 is the OTP version of the TMP90C844 that is replaced an internal ROM from Mask ROM to EPROM. The function of TMP90PH44 is exactly the same as that of TMP90C844 except the internal ROM/RAM size. Refer to the TMP90C844 except the functions which are not described this section. The following is an explanation of the hardware configuration and operation in the relation to the TMP90PH44. The TMP90PH44 has an MCU mode and a PROM mode. 3.1 MCU Mode (1) Mode Setting and Function The MCU mode is set by opening the CLK pin (Output status). In the MCU mode, the operation is the same as that of TMP90C844. (2) Memory Map Figure 1.1 and Figure 1.2 show the memory map of TMP90PH44 and TMP90C844. Figure 3.1 shows the memory map of TMP90PH44, and the accessing area by the respective addressing mode. Figure 3.1. TMP90PH44 Memory Map 3.2 PROM Mode (1) Mode Setting and Function PROM mode is set by setting the RESET and CLK pins to the “L” level. TOSHIBA CORPORATION The programming and verification for the internal PROM is achieved by using a general EPROM programmer with the adaptor socket. The device selection (ROM Type) should be “27256” with following conditions. size: 256K-bit (32K x 8-bit) VPP: 12.5V TPW: 1msec Figure 3.2 shows the setting of pins in PROM mode. 7/20 TMP90PH44 Figure 3.2. PROM Mode Pin Setting (2) Programming Flow Chart The programming mode is set by applying 12.5V (programming voltage) to the VPP pin when the following pins are set as follows, (Vcc : 6.0V) *These conditions can be (RESET): “L” level) obtained by using adaptor (CLK) : “L” level) socket. After the address and data have been fixed, a data on the Data Bus is programmed when the CE pin is set to “Low” (1ms plus is required). General programming procedure of an EPROM programmer is as follows, 8/20 • Write a data to a specified address for 1ms. • Verify the data. If the read-out data does not match the expected data, another writing is performed until the correct data is written (Max. 25 times). After the correct data is written, an additional writing is performed by using three times longer programming pulse width (1ms x programming times), or using three times more programming pulse number. Then, verify the data and increment the address. The verification for all data is done under the condition of Vpp = Vcc = 5V after all data were written. Figure 3.3 shows the programming flow chart. TOSHIBA CORPORATION TMP90PH44 Figure 3.3. Flow Chart TOSHIBA CORPORATION 9/20 TMP90PH44 4. Electrical Characteristics (Preliminary) TMP90PH44N/TMP90PH44F 4.1 Absolute Maximum Ratings Symbol Parameter VCC Power supply voltage VIN Input voltage Unit -0.5 ~ + 7 V -0.5 ~ VCC + 0.5 V F 500 Power dissipation (Ta = 85°C) PD Rating mW N 600 260 °C TSTG Storage temperature -65 ~ 150 °C TOPR Operating temperature -40 ~ 85 °C TSOLDER Soldering temperature (10s) 4.2 DC Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C (1 ~ 16MHz) Typical values are for TA = 25°C and Vcc = 5V. Symbol Parameter Min Max Unit Test Conditions VIL Input Low Voltage (P0) -0.3 0.8 V – VIL1 P1, P2, P3, P4, P5, P6, P7 -0.3 0.3VCC V – VIL2 RESET, P45 (INTO) -0.3 0.25VCC V – VIL3 EA -0.3 0.3 V – VIL4 X1 -0.3 0.2VCC V – VIH Input High Voltage (P0) 2.2 VCC + 0.3 V – VIH1 P1, P2, P3, P4, P5, P6, P7 0.7VCC VCC + 0.3 V – VIH2 RESET, P45 (INT0) 0.75VCC VCC + 0.3 V – VIH3 EA VCC - 0.3 VCC + 0.3 V – VIH4 X1 0.8VCC VCC + 0.3 V VOL Output Low Voltage – 0.45 V IOL = 1.6mA VOH VOH1 VOH2 Output High Voltage 2.4 0.75VCC 0.9VCC – V V V IOH = -400µA IOH = -100µA IOH = -20µA IDAR Darlington Drive Current (8 I/O pins) (Note) -1.0 -3.5 mA VEXT = 1.5V REXT = 1.1kΩ – ILI Input Leakage Current 0.02 (Typ) ±5 µA 0.0 ≤ Vin ≤ VCC ILO Output Leakage Current 0.05 (Typ) ± 10 µA 0.2 ≤ Vin ≤ VCC - 0.2 Operating Current (RUN) Idle 1 35 (Typ) 1.5 (Typ) 50 5 mA mA tosc = 16MHz STOP (TA = -20 ~ 70°C) STOP (TA = 0 ~ 50°C) 0.2 (Typ) 40 10 µA µA 0.2 ≤ Vin ≤ VCC - 0.2 VSTOP Power Down Voltage (@STOP) 2.0 6.0 V VIL2 = 0.2VCC, VIH2 = 0.8VCC RRST RESET Pull Up Register 50 150 KΩ CIO Pin Capacitance – 10 pF VTH Schmitt width RESET, P45) 0.4 1.0 (Typ) V ICC 10/20 – testfreq = 1MHz – TOSHIBA CORPORATION TMP90PH44 4.3 AC Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 80 1000 80 – 62.5 – ns 4x 4x 320 – 250 – ns 2x - 40 – 120 – 85 – ns tOSC Oscillation cycle ( = x) tCYC CLK Period tWH CLK High width tWL CLK Low width 2x - 40 – 120 – 85 – ns tAL A0 ~ 7 effective address→ALE fall 0.5x - 15 – 25 – 16 – ns tLA ALE fall →A0 ~ 7 hold 0.5x - 15 – 25 – 16 – ns tLL ALE Pulse width x - 40 – 40 – 23 – ns tLC ALE fall RD/WR fall 0.5x - 30 – 10 – 1 – ns tCL RD/WR →ALE rise 0.5x - 20 – 20 – 11 – ns tACL A0 ~ 7 effective address →RD/WR fall x - 25 – 55 – 38 – ns tACH Upper effective address →RD/WR fall 1.5x - 50 – 70 – 44 – ns 0.5x - 20 – 20 – 11 – ns – 3.0x - 35 – 205 – 153 ns tCA RD/WR fall →Upper address hold tADL A0 ~ 7 effective address →Effective data input tADH Upper effective address →Effective data input – 3.5x - 55 – 225 164 164 ns tRD RD fall →Effective data input – 2.0x - 50 – 110 – 75 ns tRR RD Pulse width 2.0x - 40 – 120 – 85 – ns 0 – 0 – 0 – ns x - 15 – 65 – 48 – ns tHR RD rise →Data hold tRAE RD rise→ Address enable tWW WR pulse width 2.0x - 40 – 120 – 85 – ns tDW Effective data→WR rise 2.0x - 50 – 110 – 75 – ns tWD WR rise→Effective data hold 0.5x - 10 – 30 – 21 – ns tACKH Upper address→CLK fall 2.5x - 50 – 150 – 106 – ns tACKL Lower address →CLK fall 2.0x - 50 – 110 – 75 – ns tCKHA CLK fall→Upper address hold 1.5x - 80 – 40 – 13 – ns tCCK RD/WR→CLK fall x - 25 – 55 – 37 – ns tCKHC CLK fall→RD/WR rise x - 60 – 20 – 2 – ns tDCK Valid data CLK fall x - 50 – 30 – 12 – ns tCWA RD/WR fall→Valid WAIT – x - 40 – 40 – 22 ns 4.4 A/D Conversion Characteristics VCC = 5V ± 10% TA = -020 ~ 70°C f = 1 ~ 16MHz Symbol Parameter Condition Min Max VREF Analog reference voltage Vcc - 1.5 Vcc Vcc AGND Analog reference voltage Vss Vss Vss VAIN Analog input voltage range Vss – Vcc IREF Supply current for analog reference voltage – 0.5 1.0 Total error (TA = 25°C, Vcc = VREF = 5.0V) – – 1.0 Total error – – 2.5 Error (Quantize error of ± 0.5 LSB not included) Unit V mA LSB TOSHIBA CORPORATION 11/20 TMP90PH44 4.5 Zero-Cross Characteristics VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Symbol Parameter VZX Zero-cross detection input AZX Zero-cross accuracy FZX Zero-cross detection input frequency Condition Min Max Unit AC coupling C = 0.1µF 1 1.8 VAC P - P 50/60Hz sine wave – 135 mV – 0.04 1 kHz 4.6 Timer/ Counter Input Clock (TI0, TI2, and TI4) VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max tVCK Clock cycle 8x + 100 – 740 – 600 – ns tVCKL Low clock pulse width 4x + 40 – 360 – 290 – ns tVCKH High clock pulse width 4x + 40 – 360 – 290 – ns 4.7 Interrupt Operation VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 4x – 320 – 250 – ns 4x – 320 – 250 – ns 8x + 100 – 740 – 600 – ns 8x + 100 – 740 – 600 – ns INT0 Low level pulse width tINTAL tINTAH INT0 High level pulse width INT1, INT2 Low level pulse width tINTBL INT1, INT2 High level pulse width tINTBH 4.8 Serial Channel Timing-I/O Interface Mode (1) SCLK Input Mode VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Variable Symbol 12.5MHz Clock 16MHz Clock Parameter tSCY SCLK cycle Unit Min Max Min Max Min Max 16x – 1.28 – 1 – µs ns tOSS Output Data →rising edge of SCLK tSCY /2 - 5x - 50 – 190 – 137 – tOHS SCLK rising edge→output data hold 5x -100 – 300 – 212 – ns tHSR SCLK rising edge→input data hold 0 – 0 – 0 – ns tSRD SCLK rising edge→ effective data input – tSCY - 5x - 50 – 780 – 587 ns 12/20 TOSHIBA CORPORATION TMP90PH44 (2) SCLK Output Mode Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max tSCY SCLK cycle (programmable) 16x 8192x 1.28 655.4 1 512 µs tOSS Output Data →rising edge of SCLK tSCY - 2x - 50 – 970 – 725 – ns tOHS SCLK rising edge→output data hold 2x - 80 – 80 – 45 – ns tHSR SCLK rising edge→input data hold 0 – 0 – 0 – ns tSRD SCLK rising edge→ effective data input – tSCY - 2x - 150 – 970 – 725 ns 4.9 Slave Bus Interface Timing: RD, WR Bus Mode VCC = 5V ± 10% TA = -20 ~ 70°C f = 1 ~ 16MHz Symbol Parameter Min Max Unit TSAR C/D setup →SRD fall 20 – ns THRA SRD rise→ C/D hold 5 – ns TSCR SCS setup →SRD fall 0 – ns THRC SRD rise →SCS hold TWRD SRD pulse width 0 – ns 120 – ns ns TARD SRD fall →effective data output – 80 TVRB SRD rise →effective data hold 10 85 ns TSAW C/D setup →SWR fall 20 – ns THWA SWR rise →C/D hold 5 – ns TSCW SCR setup →SWR fall 0 – ns ns THWC SWR rise →SCS hold 0 – TWWR SWR pulse width 120 – ns TSBW effective data input →SWR rise 80 – ns THWB SWR rise →effective data hold 10 – ns Min Max Unit ns Slave Bus Interface Timing: DS, R/W Bus Mode Symbol Parameter TSAD C/D setup →DS fall 20 – THDA DSrise→ C/D hold 5 – ns TSCD SCS setup →DS fall 0 – ns THDC DS rise →SCS hold 0 – ns TSAD SCS setup →DS fall 20 – ns THDA DS rise →R/W hold TWDS DS pulse width TADS DS fall →effective data output TVDB TSBD THDB 5 – ns 120 – ns – 80 ns DS rise →effective data hold 10 85 ns Effective data input → DS rise 80 – ns DS rise →effective data hold 10 – ns TOSHIBA CORPORATION 13/20 TMP90PH44 STA Change Timing X = 1/fosc Variable Symbol 16MHz Clock Parameter Unit Min Max Min Max tRPH STA fall after Output Buffer is read – 2x + 50 – 175 ns tWPH STA rise after Input Buffer is written – 2x + 50 – 175 ns 4.10 Read Operation (PROM Mode) DC Characteristic, AC Characteristic TA = -40 ~ 85°C Vcc = 5V ± 10% Symbol Parameter VPP VIH1 VIL1 VPP Read Voltage Input High Voltage (A0 ~ A15, CE, OE) Input Low Voltage (A0 ~ A15, CE, OE) tACC Address to Output Delay Condition Min Max Unit – – – 4.5 0.7 x VCC -0.3 5.5 Vcc + 0.3 0. 3 x VCC V V V CL = 50PF – 2.25TCYC + α ns TCYC = 400ns (10MHz Clock) α = 200ns 4.11 Programming Operation (PROM Mode) DC Characteristic, AC Characteristic TA = 25 ± 5°C Vcc = 6V ± 0.25V Symbol 14/20 Parameter VPP VIH VIL VIH1 VIL1 ICC IPP Programming Voltage Input High Voltage (D0 ~ D7) Input Low Voltage (D0 ~ D7) Input High Voltage (A0 ~ A15, CE, OE) Input Low Voltage (A0 ~ A15, CE, OE) VCC Supply Current VPP Supply Current tPW CE Programming Pulse Width Condition Min Typ Max Unit – – – – – fOSC = 10MHz VPP = 13.00V 12.25 0.2VCC + 1.1 -0.3 0.7VCC -0.3 – – 12.50 12.75 VCC + 0.3 0.2VCC - 0.1 VCC + 0.3 0.3VCC 50 50 V V V V V mA mA CL = 50PF 0.95 1.00 1.05 ms TOSHIBA CORPORATION TMP90PH44 4.12 Timing Chart TOSHIBA CORPORATION 15/20 TMP90PH44 4.13 Timing Chart for I/O Interface Mode 16/20 TOSHIBA CORPORATION TMP90PH44 4.14 Timing Chart for Slave Bus Interface: RD, WR Bus Mode (1) Read Operation (2) Write Operation TOSHIBA CORPORATION 17/20 TMP90PH44 4.15 Timing Chart for Slave Bus Interface: DS, R/W Bus Mode (1) Read Operation (2) Write Operation 18/20 TOSHIBA CORPORATION TMP90PH44 4.16 Read Operation Timing Chart (PROM Mode) TOSHIBA CORPORATION 19/20 TMP90PH44 4.17 Programming Operation Timing Chart (PROM Mode) 20/20 TOSHIBA CORPORATION