ETC TMP90CH45N

TOSHIBA
TLCS-90 Series
TMP90CH45
CMOS 8–Bit Microcontrollers
TMP90CH45N/TMP90CH45F
1. Outline and Characteristics
The TMP90CH45 is a high-speed, high performance 8-bit
microcontroller developed for application in the control of
various devices.
The TMP90CH45 CMOS 8-bit microcontroller integrates an 8bit CPU, RAM, A/D converter, multi-function timer/event counter,
general-purpose serial interface and programmable chip selector
features in a single chip. In addition, it can expand to 4M byte
external program memory as well as 8M byte external data
memory.
The TMP90CH45N is a device with a 64-pin shrink DIP.
The TMP90CH45F is a device with a 64-pin flat package.
The following are the features of TMP90CH45:
(1)
Highly efficient instructions: 163 types of basic
instructions, including Multiplication, division, 16-bit
arithmetic operations, bit manipulation instructions
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Minimum instruction executing time: 250ns (at 16MHz
oscillation frequency)
Built-in RAM: 512 bytes
Memory expansion
External program memory: 4M bytes
External data memory:
8M bytes
Highly accurate 8-bit A/D converter (4 channels)
General-purpose serial interface (1 channel)
With asynchronous mode and I/O interface mode
Multi-function 16-bit timer/event counter (1 channel)
8-bit timer (4 channels)
Stepping motor control and pattern generation ports
(2 channels)
Input/Output ports: 36 pins
Programmable chip select function
Interrupt function: 10 internal, 3 external
Micro Direct Memory Access (DMA) function (11 channels)
Watchdog timer function
Standby function (3 HALT modes)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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TMP90CH45
Figure 1. TMP90CH45 Block Diagram
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TMP90CH45
2. Pin Assignment and Functions
The assignment of input/output pins for TMP90CH45, their
names and functions are described below.
2.1 Pin Assignment
Figure 2.1 (1) shows pin assignment of the TMP90CH45N.
Figure 2.1 (1). Pin Assignment (Shrink DIP)
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TMP90CH45
Figure 2.1 (2) shows the pin assignment of TMP90C45F.
Figure 2.1 (2). Pin Assignment (Flat Package)
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TMP90CH45
2.2 Pin Names and Functions
The names of input/output pins and their functions are summarized in Table 2.2.
Table 2.2 Pin Names and Functions (1/2)
Pin Name
No. of pins
AD0 ~ AD7
A8 ~ A15
P20 ~ P26
/A16 ~ A20
/A21 ~ A22
/ROMCS,
RAMCS
IOCS
P27
8
7
(5)
(2)
I/O or tristate
Function
Tristate
Address/data bus: 8-bit time sharing bus which transmits address (lower 8 bits) and data
Output
Address bus: The upper 8 bits address bus
Output
Port 20 ~ 26: 7-bit output port
/Output
Addresses 16 ~ 20: Address bus which is used to expand the program and data areas.
Addresses 21 and 22: Address bus which is used to extend the program and data area (inverted output)
/Output
(3)
/Output
8
Input
Port 27: 1-bit input port
Input
Wait: Input pin for connecting a memory or peripheral LSI with delayed access time.
/WAIT
Programmable chip select
P30 ~ P37/
8
I/O
/RxD
(1)
Input
Receiver of serial data
/SCLK
(1)
/I/O
Serial clock
/TxD
(1)
/Output
P40 ~ P47
8
I/O
/TO1, 3, 4, 5
(4)
/Output
Port 3: 8-bit I/O port which allows I/O selection on bit basis (with programmable pull-up resistor).
Transmitter of serial data
Port 4: 8-bit I/O port which allows I/O selection on bit basis (with programmable pull-up resistor).
Timer outputs 1, 3, 4, and 5: Output ports for timer 0, or timer 1, timer 2, timer 3 and timer 4 (2 lines).
/TI0, 2, 4, 5
(4)
/Input
Timer inputs 0, 2, 4, and 5: Input ports for timer 0, or timer 1, timer 2 and timer 4 (2 lines).
/INT0
(1)
/Input
Interrupt request terminal 0: Interrupt request pin 0: Level/rise edge programmable interrupt request pin.
/INT1
(1)
/Input
Interrupt request terminal 1: Interrupt request pin 1: Rise/fall edge programmable interrupt request pin
/INT2
(1)
/Input
Interrupt request terminal 2: Interrupt request pin 2: Rise edge interrupt request pin.
Port 5: 4-bit output ports.
P50 ~ P53
/AN0 ~ AN3
4
Input
P60 ~ P63
/M00 ~ M03
4
I/O
/Output
Port 6: 4 bit I/O port which allows I/O selection on bit basis.
Analog input: 4 analog inputs to A/D converter.
Stepping motor control port 0 or pattern generation port 0
P70 ~ P73
/M10 ~ M13
4
I/O
Output
Port 7: 4 bit I/O port which allows I/O selection on bit basis.
Stepping motor control port 0 or pattern generation port 1
RD
1
Output
Read: Strobe signal output for reading external memory
WR
1
Output
Write: Strobe signal output for writing an external memory
ALE
1
Output
Address latch enable
Output
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation.
It is pulled up internally during resetting.
CLK
1
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TMP90CH45
Table 2.2 (2/2)
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Pin Name
No. of pins
I/O or tristate
Function
EA
1
Input
External access: Connects with VCC pin in the TMP90C845 built ROM is used.
RESET
1
Input
Reset: Initializes the TMP90C845.
(pull-up resistance is built-in).
X1, X2
2
I/O
Crystal oscillator connection pin
Input of reference voltage to A/D converter
VREF
1
–
AGND
1
–
GND pin for A/D converter
VCC
1
–
Power supply (+5V +/- 10%)
GND
1
–
GND pin (0V)
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TMP90CH45
3. Operation
(1)
This section explains the functions and basic operations of the
TMP90CH45 in blocks.
The TMP90CH45 contains a 512-byte RAM which is allocated to the addresses FDC0H ~ FFBFH. The CPU can
also access some portions of the RAM (192 byte area
FF00H ~ FFBFH) using short instruction codes in the
direct addressing mode.
Addresses of FF18H ~ FF68H this RAM area can be
used as the parameter area for micro DMA processing.
(This area can freely be used when the micro DMA
function is not used.)
3.1 CPU
The TMP90CH845 has a built-in, high performance 8-bit CPU.
For the operation of the CPU, see the book TLCS 90
Series CPU Core Architecture.
This section explains the CPU functions unique to the The
TM90CH45 that are not explained in that book.
3.2 Memory Map
The TMP90CH45 can provide a maximum 4M byte program
and maximum 8M byte data memory.
The program memory may be allocated to the addresses
000000H ~ 3FFFFFH, while the data memory may be allocated to any address 000000H ~ 7FFFFFH.
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Built-in RAM
(2)
Built-in I/O
The TMP90CH45 uses 56 bytes of the address space as
a built-in I/O area. The area is allocated to the addresses
FFC0H ~ FFF7H. The CPU can access the built-in I/O
using short instruction codes in the direct addressing
mode.
Figure 3.2 shows the memory map and the access
ranges of the CPU for each addressing mode.
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TMP90CH45
Figure 3.2. Memory Map
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TMP90CH45
4. Electrical Characteristics
TMP90CH45N/TMP90CH45F
4.1 Absolute Maximum Ratings
Symbol
Parameter
VCC
Power supply voltage
VIN
Input voltage
PD
Power dissipation (Ta = 85°C)
TSOLDER
Rating
Unit
-0.5 ~ + 7
V
-0.5 ~ VCC + 0.5
V
F 500
mW
N 600
Soldering temperature (10s)
260
°C
TSTG
Storage temperature
-65 ~ 150
°C
TOPR
Operating temperature
-40 ~ 85
°C
4.2 DC Characteristics
VCC = 5V ± 10% TA = -20 ~ 70°C (1 ~ 16MHz)
Typical values are for TA = 25°C and Vcc = 5V.
Symbol
Parameter
Min
Max
Unit
Test Conditions
-0.3
0.8
V
–
VIL
Input Low Voltage (AD0 ~ AD7)
VIL1
P2, P3, P4, P5, P6, P7
-0.3
0.3VCC
V
–
VIL2
RESET, P45 (INT0)
-0.3
0.25VCC
V
–
VIL3
EA
-0.3
0.3
V
–
VIL4
X1
-0.3
0.2VCC
V
–
VIH
Input High Voltage (AD0 ~ AD7)
2.2
VCC + 0.3
V
–
VIH1
P2, P3, P4, P5, P6, P7
0.7VCC
VCC + 0.3
V
–
VIH2
RESET, P45 (INT0)
0.75VCC
VCC + 0.3
V
–
VIH3
EA
VCC -0 .3
VCC + 0.3
V
–
VIH4
X1
0.8VCC
VCC + 0.3
V
–
VOL
Output Low Voltage
–
0.45
V
IOL = 1.6mA
VOH
VOH1
VOH2
Output High Voltage
2.4
0.75VCC
0.9VCC
–
V
V
V
IOH = -400µA
IOH = -100µA
IOH = -20µA
IDAR
Darlington Drive Current
(8 I/O pins) (Note)
-1.0
-3.5
mA
VEXT = 1.5V
REXT = 1.1kΩ
Input Leakage Current
0.02 (Typ)
±5
µA
0.0 ≤ Vin ≤ VCC
Output Leakage Current
0.05 (Typ)
± 10
µA
0.2 ≤ Vin ≤ VCC - 0.2
Operating Current (RUN)
Idle 1
35 (Typ)
1.5 (Typ)
50
5
mA
mA
tosc = 16MHz
STOP (TA = -20 ~ 70°C)
STOP (TA = 0 ~ 50°C)
0.2 (Typ)
40
10
µA
µA
0.2 ≤ Vin ≤ VCC - 0.2
Power Down Voltage (@STOP)
(RAM back Up)
2.0
6.0
V
VIL2 = 0.2VCC,
VIH2 = 0.8VCC
RRST
RESET Pull Up Register
50
150
KΩ
CIO
Pin Capacitance
–
10
pF
VTH
Schmitt width RESET, P45)
0.4
1.0 (Typ)
V
ILI
ILO
ICC
VSTOP
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–
testfreq = 1MHz
–
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TMP90CH45
4.3 AC Characteristics
VCC = 5V ± 10% TA = -20 ~ 70°C (1 ~ 16MHz)
Variable
Symbol
12.5MHz Clock
16MHz Clock
Parameter
tOSC
Oscillation cycle ( = x)
tCYC
CLK Period
tWH
CLK High width
Unit
Min
Max
Min
Max
Min
62.5
1000
4x
4x
2x - 40
–
120
Max
80
–
62.5
–
ns
320
–
250
–
ns
–
85
–
ns
tWL
CLK Low width
2x - 40
–
120
–
85
–
ns
tAL
A0 ~ 7 effective address→ALE fall
0.5x - 15
–
25
–
16
–
ns
tLA
ALE fall →A0 ~ 7 hold
0.5x - 15
–
25
–
16
–
ns
tLL
ALE Pulse width
x - 40
–
40
–
23
–
ns
ns
tLC
ALE fall→ RD/WR fall
0.5x - 30
–
10
–
1
–
tCL
RD/WR →ALE rise
0.5x - 20
–
20
–
11
–
ns
tACL
A0 ~ 7 effective address →RD/WR fall
x - 25
–
55
–
38
–
ns
tACH
Upper effective address →RD/WR fall
1.5x - 50
–
70
–
44
–
ns
tCA
RD/WR fall →Upper address hold
0.5x - 20
–
20
–
11
–
ns
tADL
A0 ~ 7 effective address →Effective data input
–
3.0x - 35
–
205
–
153
ns
tADH
Upper effective address →Effective data input
–
3.5x - 55
–
225
164
164
ns
tRD
RD fall →Effective data input
tRR
RD Pulse width
tHR
RD rise →Data hold
tRAE
RD rise→ Address enable
tWW
WR pulse width
tDW
Effective data→WR rise
tWD
WR rise→Effective data hold
tACKH
tACKL
–
2.0x - 50
–
110
–
75
ns
2.0x - 40
–
120
–
85
–
ns
0
–
0
–
0
–
ns
x - 15
–
65
–
48
–
ns
2.0x - 40
–
120
–
85
–
ns
2.0x - 50
–
110
–
75
–
ns
0.5x - 10
–
30
–
21
–
ns
Upper address→CLK fall
2.5x - 50
–
150
–
106
–
ns
Lower address →CLK fall
2.0x - 50
–
110
–
75
–
ns
tCKHA
CLK fall→Upper address hold
1.5x - 80
–
40
–
13
–
ns
tCCK
RD/WR→CLK fall
x - 25
–
55
–
37
–
ns
tCKHC
CLK fall→RD/WR rise
x - 60
–
20
–
2
–
ns
tDCK
Valid data CLK fall
x - 50
–
30
–
12
–
ns
tCWA
RD/WR fall→Valid WAIT
–
x - 40
–
40
-
22
ns
tAWAL
Lower address →Valid WAIT
–
2.0x - 70
–
90
-
55
ns
tWAH
CLK fall →Valid WAIT hold
0
–
0
–
0
–
ns
tAWAH
Upper address →Valid WAIT
–
2.5x - 70
-
130
–
86
ns
tCPW
CLK fall →Port Data Output
–
x + 200
-
280
–
262
ns
tPRC
Port Data Input →CLK fall
200
–
200
200
–
ns
tCPR
CLK fall →Port Data hold
100
–
100
100
–
ns
AC Measuring Conditions
• Output level: High 2.2V/Low 0.8V, CL = 50pF
(However, CL = 100pF for AD0 ~ 7, A8 ~ 15, ALE, RD, WR)
• Input level: High 2.4V/Low 0.45V (AD0 ~ AD7)
High 0.8VCC/Low 0.2VCC (excluding AD0 ~ AD7)
High 0.8VCC/Low 0.2VCC (excluding AD0 ~ AD7)
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TMP90CH45
4.4 A/D Conversion Characteristics
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Symbol
Parameter
Condition
Min
Max
VREF
Analog reference voltage
Vcc - 1.5
Vcc
Vcc
AGND
Analog reference voltage
Vss
Vss
Vss
VAIN
Analog input voltage range
Vss
–
Vcc
IREF
Supply current for analog reference voltage
–
0.5
1.0
Total error
(TA = 25°C, Vcc = VREF = 5.0V)
–
–
1.0
Total error
–
–
2.5
Error
(Quantize
error of ± 0.5
LSB not
included)
Unit
V
mA
LSB
4.5 Zero-Cross Characteristics
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Symbol
Parameter
VZX
Zero-cross detection input
AZX
Zero-cross accuracy
FZX
Zero-cross detection input frequency
Condition
Min
Max
Unit
VAC P - P
AC coupling C = 0.1µF
1
1.8
50/60Hz sine wave
–
135
mV
–
0.04
1
kHz
4.6 Timer/ Counter Input Clock (TI0, TI2, and TI4)
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Variable
Symbol
12.5MHz Clock
16MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
tVCK
Clock cycle
8x + 100
–
740
–
600
–
ns
tVCKL
Low clock pulse width
4x + 40
–
360
–
290
–
ns
tVCKH
High clock pulse width
4x + 40
–
360
–
290
–
ns
4.7 Interrupt Operation
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Variable
Symbol
12.5MHz Clock
16MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
4x
–
320
–
250
–
ns
4x
–
320
–
250
–
ns
8x + 100
–
740
–
600
–
ns
8x + 100
–
740
–
600
–
ns
INT0 Low level pulse width
tINTAL
tINTAH
INT0 High level pulse width
INT1, INT2 Low level pulse width
tINTBL
INT1, INT2 High level pulse width
tINTBH
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TMP90CH45
4.8 Serial Channel Timing-I/O Interface Mode
(1) SCLK Input Mode
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Variable
Symbol
12.5MHz Clock
16MHz Clock
Parameter
tSCY
SCLK cycle
Unit
Min
Max
Min
Max
Min
Max
16x
–
1.28
–
1
–
µs
tSCY/2 - 5x - 50
–
190
–
137
–
ns
5x - 100
–
300
–
212
–
ns
tOSS
Output data →rising edge of SCLK
tOHS
SCLK rising edge→Output data hold
tHSR
SCLK rising edge→Input data hold
0
–
0
–
0
–
ns
tSRD
SCLK rising edge→ Effective data input
–
tSCY - 5x - 50
–
780
–
587
ns
(2) SCLK Output Mode
Variable
Symbol
12.5MHz Clock
16MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
tSCY
SCLK cycle (programmable)
16x
8192x
1.28
655.4
1
512
µs
tOSS
Output data setup→SCLK rising edge
tSCY - 2x - 50
–
970
–
725
–
ns
tOHS
SCLK rising edge→Output data hold
2x - 80
–
80
–
45
–
ns
tHSR
SCLK rising edge→Input data hold
0
–
0
–
0
–
ns
tSRD
SCLK rising edge→ Effective data input
–
tSCY - 2x - 150
–
970
–
725
ns
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TMP90CH45
4.9 Timing Chart
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TMP90CH45
4.10 Timing Chart for I/O Interface Mode
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