TOSHIBA TLCS-90 Series TMP90CH02/H03 CMOS 8–Bit Microcontrollers (2) TMP90CH02P/TMP90CH02M (3) TMP90CH03P/TMP90CH03M 1. Outline and Characteristics The TMP90CH02 is a high-speed advanced 8-bit microcontroller applicable to a variety of equipment. With its 8-bit CPU, ROM, RAM, timer/event counter and general-purpose serial interface integrated into a single CMOS chip, the TMP90CH02 allows the expansion of external memories for programs (up to 48K byte). The TMP90CH03 is the same as the TMP90CH02 bit without the ROM. The TMP90CH02P/H03P is in a DIP ppackage. The TMP90CH02M/H03M is in a SOP (Small Outline Package). The characteristics of the TMP90CH02 include: (1) Powerful instructions: 163 basic instructions, including Multiplication, division, 16-bit arithmetic operations, bit (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) manipulation instructions Minimum instruction executing time: 250ns (at 16MHz oscillation frequency) Internal ROM: 16K byte (the TMP90CH03 does not have a built in ROM) Internal RAM: 512 byte Memory expansion External memory: 48K byte General-purpose serial interface (1 channel) Asynchronous mode, I/O interface mode 8-bit timers (4 channels): (1 external clock input) Port with zero cross detection circuit (1 input) Input/Output ports (90CH02: 32 pins, 90CH03: 6 pins) Interrupt function: 8 internal interrupts and 3 external interrupts Micro Direct Memory Access (DMA) function (4 channels) Watchdog timer Standby function (4 HALT modes) The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA. TOSHIBA CORPORATION 1/12 TMP90CH02/H03 Figure 1. TMP90CH02 Block Diagram 2/12 TOSHIBA CORPORATION TMP90CH02/H03 2. Pin Assignment and Functions The assignment of input/output pins, their names and functions are described below. 2.1 Pin Assignment Figure 2.1 (1) shows pin assignment of the TMP90CH02/ CH03. Figure 2.1 (1). Pin Assignment (Shrink Dual Inline Package) TOSHIBA CORPORATION 3/12 TMP90CH02/H03 2.2 Pin Names and Functions The names of input/output pins and their functions are summarized in Table 2.2. Table 2.2 Pin Names and Functions (1/1) Pin Name No. of Pins I/O 3 states P00 ~ P07 /D0 ~ D7 8 3 states P10 ~ P17 /A0 ~ A7 8 Output P20 ~ P27 /A8 ~ A 15 8 Output P31 /RxD 1 Input P32 /TxD /RTS /SCLK 1 Output P33 /TxD 1 Output P35 /RD 1 Output P36 /WR 1 Output P37 /WAIT 1 Input I/O I/O I/O Function Port 0: 8-bit I/O port that allows selection of input/output on byte basis Data Bus: Also functions as 8-bit bidirectional data bus for external memory (For CH03, fixed to databus) Port 1: 8-bit I/O port that allows selection on byte basis Addrress Bus: The lower 8 bits address bus for external memory (For CH03, fixed to address bus) Port 2: 8-bit I/O port that allows selection on byte basis Addrress Bus: The uppper 8 bits address bus for external memory (For CH03, fixed to address bus) Port 31: 1-bit input port Receives serial data Port 32: 1-bit output port Serial clock output Port 33: 1-bit output port Transmits serial data Port 35: 1-bit output port Read: Generates strobe signal for reading external memory Port 36: 1-bit output port Writes: Generates strobe signal for writing external memory Port 37: 1-bit input port Wait: Input pin for connecting slow speed memory or peripheral LSI Port 80: 1-bit input port P80 /INTO 1 Input Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable) Port 81: 1-bit input port P81 /INT1 /TI4 Interrupt request pin 1: Interrupt request pin (Rising/falling edge is programmable) 1 Input Timer input 4: Counter/capture trigger signal for Timer 4 Non-maskable interrupt request pin: Falling edge interrupt request pin 4/12 NMI 1 Input CLK 1 Output Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is Pulled up internally during resetting. EA 1 Input External access: Connects with GND pin in the TMP90C802A using internal ROM, and with GND pin in the TMP90C803A with no internal ROM. RESET 1 Input Reset: Initializes the TMP 90CH02/CH03. (Built-in pull-up resistor) X1/X2 2 Input/ Output Pin for quartz crystal or ceramic resonator (1 ~ 16MHz) VCC 1 – Power supply (+5V) VSS (GND) 1 – Ground (0V) TOSHIBA CORPORATION TMP90CH02/H03 3. Operation The following explains the TMP90CH02 functions and basic operations. The CPU functions and internal I/O functions of the TMP90CH02 are the same as the TMP90C840A. Refer to the “TMP90C840A” section concerning functions which are not explained the following. The TMP90CH03 does not have a built-in ROM; therefore, the address space 0000H ~ 3 FFFH is used as external memory space. (2) The TMP90CH02 also contains a 512-byte RAM, which is allocated to the address space FDC0H ~ FFBFH. The CPU allows the access to whole RAM area (FF00H ~ FFBFH, 192 bytes) by a short operation code (opcode) in the “direct addressing mode”. The addresses from FF30H ~ FF7FH in this RAM area can be used as parameter area for micro DMA processing (and for any other purposes when the micro DMA function is not used). 3.1 CPU The TMP90CH02 has an internal high-performance 8-bit CPU. Refer to the book TLCS Series CPU Core Architecture concerning CPU operation. 3.2 Memory Map The TMP90CH02 supports a program memory of up to 64K bytes. The program memory may be assigned to the address space from 00000H to 0FFFFH, while the data memory can be allocated to any address from 0000H to FFFFH. (1) Internal ROM The TMP90CH02 internally contains a 16K byte ROM. The address space from 0000H to 3FFFH is provided to the ROM. The CPU starts executing a program from 0000H by resetting. The addresses from 0010H to 007FH in this internal ROM area are used for the entry area for the interrupt processing. TOSHIBA CORPORATION Internal RAM (3) Internal I/O The TMP90CH02 provides a 48-byte address space as an internal I/O area, whose addressess range from FFC0H to FFEFH. This I/O area can be accessed by the CPU using a short opcode in the “direct addressing mode”. Figure 3.2 is a memory map indicating the areas accessible by the CPU in the respective addressing mode. 5/12 TMP90CH02/H03 Figure 3.2. Memory Map 6/12 TOSHIBA CORPORATION TMP90CH02/H03 4. Electrical Characteristics TMP90CH02N/TMP90CH02F 4.1 Absolute Maximum Ratings Symbol Parameter VCC Supply voltage VIN Input voltage Unit -0.5 ~ + 6.5 V -0.5 ~ VCC + 0.5 V F 500 Power dissipation (Ta = 70°C) PD Rating mW N 600 260 °C TSTG Storage temperature -65 ~ 150 °C TOPR Operating temperature -20 ~ 70 °C TSOLDER Soldering temperature (10s) 4.2 DC Characteristics VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) TA = -20 ~ 70°C (1 ~ 16MHz) Symbol Parameter Min Max Unit Test Conditions VIL Input Low Voltage (P0) -0.3 0.8 V – VIL1 P1, P2, P3, P8 -0.3 0.3VCC V – VIL2 RESET, INT0, NMI -0.3 0.25VCC V – VIL3 EA -0.3 0.3 V – VIL4 X1 -0.3 0.2VCC V – VIH Input Low Voltage (D0 ~ D7) 2.2 VCC + 0.3 V – VIH1 P3, P5, P6, P7, P8 0.7VCC VCC + 0.3 V – VIH2 RESET, INT0, NMI 0.75VCC VCC + 0.3 V – VIH4 X1 0.8VCC VCC + 0.3 V – VOL Output Low Voltage – 0.45 V IOL = 1.6mA VOH VOH1 VOH2 Output High Voltage 2.4 0.75VCC 0.9VCC – V V V IOH = -400µA IOH = -100µA IOH = -20µA IDAR Darlington Drive Current (8 I/O pins) -1.0 -3.5 mA VEXT = 1.5V REXT = 1.1kΩ ILI Input Leakage Current 0.02 (Typ) ±5 µA 0.0 ≤ Vin ≤ VCC ILO Output Leakage Current 0.05 (Typ) ± 10 µA 0.2 ≤ Vin ≤ VCC - 0.2 ICC Operating Current (RUN) Idle 1 Idle 2 17 (Typ) 1.5 (Typ) 6 (Typ) 30 5 15 mA mA mA tosc = 10MHz (60% Up @ 16MHz) STOP (TA = -20 ~ 70°C) STOP (TA = 0 ~ 50°C) 0.2 (Typ) 50 10 µA µA 0.2 ≤ Vin ≤ VCC - 0.2 VSTOP Power Down Voltage (@STOP) 2 RAM BACK UP 150 KΩ VIL2 = 0.2VCC, VIH2 = 0.8VCC RRST RESET Pull Up Register 50 150 KΩ – 10 pF 0.4 1.0 (Typ) V CIO Pin Capacitance VTH Schmitt width RESET, NMI, INT0 – testfreq = 1MHz – Note: IDAR is guaranteed for a total of up to 8 optional ports. TOSHIBA CORPORATION 7/12 TMP90CH02/H03 4.3 AC Characteristics VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 62.5 1000 80 – 62.5 – ns tOSC OSC. Period = x tCYC CLK Period 4x 4x 320 – 250 – ns tWL CLK Low width 2x - 40 – 120 – 85 – ns tWH CLK High width 2x - 40 – 120 – 85 – ns tAC Address Setup to RD, WR x - 45 – 35 – 18 – ns tRR RD Low width 2.5x - 40 – 160 – 117 – ns tCA Address Hold Time After RD, WR 0.5x - 20 – 20 – 12 – ns tAD Address to Valid Data In – 3.5x - 95 – 185 – 123 ns tRD RD to Valid Data In – 2.5x - 80 – 120 – 76 ns tHR Input Data Hold After RD 0 – 0 – 0 – ns tWW WR Low width tDW Data Setup to WR 2.5x - 40 – 160 – 117 – ns 2x - 50 – 110 – 75 – ns tWD Data Hold After WR tCWA RD, WR to Valid WAIT 20 70 20 70 20 70 ns – 1.5x - 100 – 20 – 13 ns tAWA Address to Valid WAIT – 2.5x - 130 – 70 – 26 ns tWAS WAIT Setup to CLK 50 – 50 – 50 – ns tWAH WAIT Hold After CLK 0 – 0 – 0 – ns tRV RD/WR Recovery Time 1.5x - 35 – 85 – 59 – ns tCPW CLK to Port Data Output – x + 200 – 280 – 262 ns tPRC Port Data Setup to CLK 200 – 200 – 200 – ns tCPR Port Data Hold After CLK 100 – 100 – 100 – ns tCHCL RD/WR Hold After CLK x - 40 – 40 – 23 – ns tCLC RD/WR Setup to CLK 1.5x - 25 – 95 – 69 – ns tCLHA Address Hold After CLK 1.5x - 80 – 40 – 14 – ns tACL Address Setup to CLK 2.5x - 80 – 120 – 77 – ns tCLD Data Setup to CLK x - 50 – 30 – 13 – ns • AC output level High 2.2V/Low 0.8V • AC input level High 2.4V/Low 0.45V (D0 ~ D7) High 0.8VCC/Low 0.2VCC (excluding D0 ~ D7) 8/12 TOSHIBA CORPORATION TMP90CH02/H03 4.4 Pin Names and Functions The names of input/output pins and their functions are summarized in Table 2.2. Table 2.2 Pin Names and Functions (1/1) Pin Name No. of Pins P00 ~ P07 /D0 ~ D7 8 P10 ~ P17 /A0 ~ A7 8 P20 ~ P27 /A8 ~ A 15 8 P31 /RxD 1 I/O 3 states I/O 3 states I/O Output I/O Output Input Function Port 0: 8-bit I/O port that allows selection of input/output on byte basis Data Bus: Also functions as 8-bit bidirectional data bus for external memory Port 1: 8-bit I/O port that allows selection on byte basis Addrress Bus: The lower 8 bits address bus for external memory Port 2: 8-bit I/O port that allows selection on byte basis Addrress Bus: The uppper 8 bits address bus for external memory Port 31: 1-bit input port Receives Serial Data Port 32: 1-bit output port P32 /TxD /RTS /SCLK 1 Output P33 /TxD 1 Output P35 /RD 1 Output P36 /WR 1 Output Serial clock output Port 33: 1-bit output port Transmits Serial Data Port 35: 1-bit output port Read: Generates strobe signal for reading external memory Port 36: 1-bit output port Writes: Generates strobe signal for writing external memory Port 37: 1-bit input port P37 /WAIT TO1 Input Wait: Input pin for connecting slow speed memory or peripheral LSI Output Timer output 1: Output of Timer 0 or 1 1 Port 80: 1-bit input port P80 /INTO 1 Input Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable) Port 81: 1-bit input port P81 /INT1 /TI2 Interrupt request pin 1: Interrupt request pin (Rising/falling edge is programmable) 1 Input Timer input 2: Counter/capture trigger signal for Timer 2 Non-maskable interrupt request pin: Falling edge interrupt request pin NMI 1 Input CLK 1 Output Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is pulled up internally during resetting. EA 1 Input External access: Connects with GND pin in the TMP90CH02 using internal ROM, and with GND pin in the TMP90CH03 with no internal ROM. RESET 1 Input Reset: Initializes the TMP 90CH02/CH03. (Built-in pull-up resistor) X1/X2 2 Input/ Output Pin for quartz crystal or ceramic resonator (1 ~ 16MHz) VCC 1 – Power supply (+5V) VSS (GND) 1 – Ground (0V) TOSHIBA CORPORATION 9/12 TMP90CH02/H03 4.5 Zero-Cross Characteristics VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) TA = -20 ~ 70°C (1 ~ 16MHz) Symbol Parameter VZX Zero-cross detection input AZX Zero-cross accuracy FZX Zero-cross detection input frequency Condition Min Max Unit VAC p - p AC coupling C = 0.1µF 1 1.8 50/60Hz sine wave – 135 mV – 0.04 1 kHz 4.6 Serial Channel Timing-I/O Interface Mode VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max tSCY Serial Port Clock Cycle Time 8x – 640 – 500 – ns tOSS Output Data Setup SCLK Rising Edge 6x - 150 – 320 – 225 – ns tOHS Output Data Hold After SCLK Rising Edge 2x - 120 – 120 – 45 – ns tHSR Input Data Hold After SCLK Rising Edge 0 – 0 – 0 – ns tSRD SCLK Rising Edge to Input DATA Valid – 6x - 150 – 450 – 225 ns 4.7 8-bit Event Counter VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 8x + 100 – 740 – 600 – tVCK TI2 clock cycle ns tVCKL TI2 Low clock pulse width 4x + 40 – 360 – 290 – ns tVCKH TI2 High clock pulse width 4x + 40 – 360 – 290 – ns 4.8 Interrupt Operation VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 12.5MHz Clock 12.5MHz Clock Parameter Unit Min Max Min Max Min Max 4x – 320 – 250 – ns 4x – 320 – 250 – ns 8x + 100 – 740 – 600 – ns 8x + 100 – 740 – 600 – ns NMI, INT0 Low level pulse width tINTAL NMI, INT0 High level pulse width tINTAH INT1, INT2 Low level pulse width tINTBL INT1, INT2 High level pulse width tINTBH 10/12 TOSHIBA CORPORATION TMP90CH02/H03 4.9 I/O Interface Mode Timing Chart TOSHIBA CORPORATION 11/12 TMP90CH02/H03 4.10 Timing Chart 12/12 TOSHIBA CORPORATION