19-1900; Rev 0; 5/01 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference ♦ 67dB SNR at fIN = 5MHz ♦ 66dB SNR at fIN = 15MHz ♦ Internal, +2.048V Precision Bandgap Reference ♦ Differential, Wideband Input T/H Amplifier ♦ Power-Down Modes 180mW (Reference Shutdown Mode) 10µW (Shutdown Mode) ♦ Space-Saving 48-Pin TQFP Package Ordering Information PART TEMP. RANGE 0°C to +70°C 48 TQFP MAX1421ECM -40°C to +85°C 48 TQFP Pin Configuration 37 38 39 AGND PD OE D11 D10 40 41 42 43 44 45 46 AGND AVDD CML REFN REFP REFIN AVDD 47 34 4 33 5 32 INN AGND AGND 7 AVDD AVDD AGND 11 26 12 25 6 31 MAX1421 30 D6 DVDD DVDD DGND DGND D5 D4 D3 D2 24 27 23 28 22 9 10 21 29 18 8 D9 D8 D7 AGND AVDD AVDD AGND CLK CLK AGND AVDD DVDD DGND D0 D1 IF and Baseband Digitization 3 AGND AGND INP 17 Radar 35 16 Data Acquisition 36 2 15 CCD Pixel Processing 1 14 Medical Ultrasound Imaging AGND AVDD AVDD 13 ________________________Applications 48 The MAX1421 provides parallel, offset binary, CMOScompatible three-state outputs. The MAX1421 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified over the commercial (0°C to +70°C) and the extended industrial (-40°C to +85°C) temperature ranges. Pin-compatible higher- and lower-speed versions of the MAX1421 are also available. Please refer to the MAX1420 data sheet for a frequency of 60Msps and the MAX1422 data sheet for a frequency of 20Msps. PIN-PACKAGE MAX1421CCM 20 In addition to low operating power, the MAX1421 features two power-down modes, a reference power-down and a shutdown mode. In reference power-down, the internal bandgap reference is deactivated, resulting in a typical 2mA supply current reduction. For idle periods, a full shutdown mode is available to maximize power savings. ♦ Single +3.3V Power Supply 19 The MAX1421 is a +3.3V, 12-bit analog-to-digital converter (ADC), featuring a fully-differential input, pipelined, 12-stage ADC architecture with wideband track-and-hold (T/H) and digital error correction incorporating a fully-differential signal path. The MAX1421 is optimized for low-power, high-dynamic performance applications in imaging and digital communications. The converter operates from a single +3.3V supply, consuming only 188mW while delivering a typical signal-to-noise ratio (SNR) of 66dB at an input frequency of 15MHz and a sampling frequency of 40Msps. The fully-differential input stage has a small signal -3dB bandwidth of 400MHz and may be operated with single-ended inputs. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure accommodates an internal or externally applied buffered or unbuffered reference for applications requiring increased accuracy or a different input voltage range. Features Functional Diagram appears at end of data sheet. 48-TQFP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1421 General Description MAX1421 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference ABSOLUTE MAXIMUM RATINGS AVDD, DVDD to AGND..............................................-0.3V to +4V DVDD, AVDD to DGND..............................................-0.3V to +4V DGND to AGND.....................................................-0.3V to +0.3V INP, INN, REFP, REFN, REFIN, CML, CLK, CLK,....................(AGND - 0.3V) to (AVDD + 0.3V) D0–D11, OE, PD .......................(DGND - 0.3V) to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW Maximum Junction Temperature .....................................+150°C Operating Temperature Ranges MAX1421CCM ...................................................0°C to +70°C MAX1421ECM ................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V AVDD = V DVDD = +3.3V, AGND = DGND = 0, V IN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL ≈ 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity Mid-scale Offset Mid-scale Offset Temperature Coefficient Gain Error RES DNL INL 12 TA = +25°C, no missing codes TA = TMIN to TMAX ±2 -3 GETC ±.75 %FSR %/°C Internal reference (Note 1) -5 0.1 5 External reference applied to REFIN (Note 2) -5 ±3 5 -1.5 ±0.5 1.5 External reference applied to REFP, CML, and REFN, (Note 3) LSB LSB 3 3 ✕ 10-4 MSOTC GE Bits 1 ±0.5 TA = TMIN to TMAX MSO External reference applied to REFP, CML, and REFN (Note 3) Gain Error Temperature Coefficient -1 15 ✕ 10-6 %FSR %/°C DYNAMIC PERFORMANCE (fCLK = 40MHz, 4096-point FFT) 2 Signal-to-Noise Ratio SNR Spurious-Free Dynamic Range SFDR Total Harmonic Distortion THD Signal-To-Noise Plus Distortion SINAD Effective Number of Bits ENOB Two-Tone Intermodulation Distortion IMDTT fIN = 5MHz fIN = 15MHz, TA = +25°C 67 62 66 64 70 fIN = 5MHz fIN = 15MHz, TA = +25°C 73 fIN = 5MHz -74 fIN = 15MHz, TA = +25°C -69 fIN = 5MHz fIN = 15MHz, TA = +25°C 66 60 fIN = 5MHz fIN = 15MHz, TA = +25°C fIN1 = 11.569MHz, fIN2 = 13.445MHz (Note 4) dB 63.5 10.7 60 10.3 -80 _______________________________________________________________________________________ dBc -62 dBc dB Bits dBc 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference (V AVDD = V DVDD = +3.3V, AGND = DGND = 0, V IN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL ≈ 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Gain DG ±1 % Differential Phase DP ±0.25 degrees ANALOG INPUTS (INP, INN, CML) Input Resistance RIN Either input to ground 32.5 kΩ Input Capacitance CIN Either input to ground 4 pF VCML VAVDD × 0.5 V VCMVR VCML ±5% V Common-Mode Input Level, (Note 5) Common-Mode Input Voltage Range, (Note 5) Differential Input Range VIN ±VDIFF V Small-Signal Bandwidth BW-3dB (Note 7) 400 MHz Large-Signal Bandwidth FPBW-3dB (Note 7) 150 MHz Over-Voltage Recovery OVR 1 Clock Cycle VINP - VINN (Note 6) 1.5 ✕ FS input INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF) Common-Mode Reference Input Voltage VCML At CML VAVDD ✕ 0.5 V Positive Reference Voltage Range VREFP At REFP VCML + 0.512 V Negative Reference Voltage Range VREFN At REFN VCML - 0.512 V Differential Reference Voltage Range VDIFF VDIFF = VREFP - VREFN 1.024 ±5% V ±100 ppm/°C Differential Reference Temperature Coefficient REFTC EXTERNAL REFERENCE REFIN Input Resistance RIN REFIN Input Capacitance CIN 10 pF VREFIN 2.048 ±10% V 0.95 ✕ 1.05 ✕ VREFIN/2 VREFIN/2 VREFIN/2 V REFIN Reference Input Voltage Differential Reference Voltage VDIFF (Note 8) VDIFF = (VREFP - VREFN) 5 kΩ EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN and CML) REFP, REFN, CML Input Current IIN REFP, REFN, CML Input Capacitance CIN -200 200 15 µA pF _______________________________________________________________________________________ 3 MAX1421 ELECTRICAL CHARACTERISTICS (continued) MAX1421 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (V AVDD = V DVDD = +3.3V, AGND = DGND = 0, V IN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL ≈ 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Differential Reference Voltage Range VDIFF CML Input Voltage Range CONDITIONS MIN TYP MAX UNITS 1.024 ±10% V VCML 1.65 ±10% V REFP Input Voltage Range VREFP VCML + VDIFF/2 V REFN Input Voltage Range VREFN VCML VDIFF/2 V VDIFF = VREFP - VREFN DIGITAL INPUTS (CLK, CLK, OE, PD) Input Logic High VIH Input Logic Low VIL 0.7 ✕ VDVDD 0.3 ✕ VDVDD V µA ±330 CLK, CLK Input Current V PD -20 20 OE -20 20 Input Capacitance 10 pF DIGITAL OUTPUTS (D0–D11) Output Logic High VOH IOH = 200µA Output Logic Low VOL IOL = -200µA Three-State Leakage VDVDD - 0.5 VDVDD 0 0.5 V -10 10 µA Three-State Capacitance 2 V pF POWER REQUIREMENTS Analog Supply Voltage VAVDD 3.135 3.3 3.465 V Digital Supply Voltage VDVDD 2.7 3.3 3.6 V Analog Supply Current IAVDD 52 65 mA 50 63 mA Analog Supply Current with Internal Reference in Shutdown REFIN = AGND Analog Shutdown Current Digital Supply Current PD = DVDD 20 IDVDD Digital Shutdown Current 5.5 PD = DVDD µA mA 20 214 µA Power Dissipation PDISS Analog power 188 Power-Supply Rejection Ratio PSRR (Note 9) ±1 mW Clock Frequency fCLK Figure 5 Clock High tCH Figure 5, clock period 25ns 12.5 ns Clock Low tCL Figure 5, clock period 25ns 12.5 ns mV/V TIMING CHARACTERISTICS 4 0.1 40 _______________________________________________________________________________________ MHz 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference (V AVDD = V DVDD = +3.3V, AGND = DGND = 0, V IN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL ≈ 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Pipeline Delay (Latency) CONDITIONS MIN TYP Figure 5 7 MAX UNITS fCLK cycles Aperture Delay tAD Figure 9 2 ns Aperture Jitter tAJ Figure 9 2 ps Data Output Delay tOD Figure 5 Bus Enable Time tBE Figure 4 5 ns Bus Disable Time tBD Figure 4 5 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: 5 10 14 ns Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor. External +2.048V reference applied to REFIN. Internal reference disabled. VREFIN = 0, VREFP = +2.162V, VCML = +1.65V, and VREFN = +1.138V. IMD is measured with respect to either of the fundamental tones. Specifies the common-mode range of the differential input signal supplied to the MAX1421. VDIFF = VREFP - VREFN Input bandwidth is measured at a 3dB level. VREFIN is internally biased to +2.048V through a 10kΩ resistor. Measured as the ratio of the change in mid-scale offset voltage for a ± 5% change in VAVDD using the internal reference. Typical Operating Characteristics (VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) AMPLITUDE (dB) -40 -60 HD3 HD2 -80 -100 -40 HD2 HD3 -60 -80 -100 -120 5 10 15 ANALOG INPUT FREQUENCY (MHz) 20 fIN = 38.5440183MHz AIN = -0.49dB FS -20 -40 HD2 -60 HD3 -80 -100 -120 0 0 MAX1421 toc02 fIN = 19.9047628MHz AIN = -0.50dB FS -20 AMPLITUDE (dB) fIN = 7.5439934MHz AIN = -0.45dB FS -20 0 MAX1421 toc01 0 FFT PLOT, 4096-POINT RECORD, DIFFERENTIAL INPUT MAX1421 toc03 FFT PLOT, 4096-POINT RECORD, DIFFERENTIAL INPUT AMPLITUDE (dB) FFT PLOT, 4096-POINT RECORD, DIFFERENTIAL INPUT -120 0 5 10 15 ANALOG INPUT FREQUENCY (MHz) 20 0 5 10 15 20 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX1421 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) TWO-TONE IMD, 8192-POINT RECORD, DIFFERENTIAL INPUT fIN2 fIN1 -60 IMD3 69 MAX1421 toc06 MAX1421 toc05 77 66 SNR (dB) -40 70 62 61 58 53 54 IMD2 -80 -100 -120 50 45 2 4 6 8 10 12 14 16 18 20 1 10 1 100 10 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 15MHz) 70 MAX1421 toc07 -50 -56 80 66 MAX1421 toc09 0 MAX1421 toc08 AMPLITUDE (dB) -20 85 SFDR (dBc) fIN1 = 11.5104229MHz fIN2 = 13.5126603MHz TWO-TONE ENVELOPE: -0.49dB FS AIN1 = AIN2 = -6.5dB FS SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY MAX1421 toc04 0 70 -62 -68 SFDR (dBc) SINAD (dB) THD (dBc) 60 62 58 50 40 54 -74 30 20 50 -80 1 10 1 100 10 -60 100 -50 -40 -30 -20 -10 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) INPUT POWER (dB FS) SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 15MHZ) TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 15MHz) SIGNAL-TO-NOISE PLUS DISTORTION vs. INPUT POWER (fIN = 15MHz) -40 0 MAX1421 toc12 70 80 MAX1421 toc11 -30 MAX1421 toc10 80 60 THD (dBc) 50 40 30 20 SINAD (dB) 60 SNR (dB) MAX1421 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference -50 -60 -70 40 20 0 10 -80 0 -60 -50 -40 -30 -20 INPUT POWER (dB FS) 6 -10 0 -20 -60 -50 -40 -30 -20 INPUT POWER (dB FS) -10 0 -60 -50 -40 -30 -20 INPUT POWER (dB FS) _______________________________________________________________________________________ -10 0 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference fIN = 5.51502MHz 68 64 -76 68 62 -78 -80 60 35 60 85 -40 -15 TEMPERATURE (°C) 10 35 60 -40 85 INL (LSB) INL (LSB) 1 66 0 INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE vs. DIGITAL OUTPUT CODE 2 -2 -15 10 35 60 0 -1 -20 85 0 1024 2048 3072 1024 2048 3072 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE -0.50 4096 4096 0 CL ≈ 10pF IAVDD (mA) IAVDD (mA) 50 -40 -15 10 35 TEMPERATURE (°C) 60 85 8 6 4 30 -0.50 4096 10 40 -0.25 3072 12 60 0.25 2048 DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX1421 toc20 MAX1421 toc19 70 1024 DIGITAL OUTPUT CODE ANALOG SUPPLY CURRENT vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V) 0 0 -0.25 TEMPERATURE (°C) 0.50 85 0.25 62 60 60 0.50 1 64 -1 35 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE DNL (LSB) fIN = 5.51502MHz 68 MAX1421 toc16 70 2 10 TEMPERATURE (°C) MAX1421 toc17 SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE -40 -15 TEMPERATURE (°C) MAX1421 toc18 10 MAX1421 toc21 -15 MAX1421 toc17 -40 GAIN ERROR (%FSR) -74 72 64 SINAD (dB) fIN = 5.51502MHz -72 THD (dB) 66 SNR (dB) SFDR (dBc) 76 -70 MAX1421 toc14 fIN = 5.51502MHz 80 70 MAX1421 toc13 84 TOTAL HARMONIC DISTORTION vs. TEMPERATURE SIGNAL-TO-NOISE RATIO vs. TEMPERATURE MAX1421 toc15 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) ________________________________________________________________________________________ 7 MAX1421 Typical Operating Characteristics (continued) (VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Typical Operating Characteristics (continued) (VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE SFDR, SNR, THD, SINAD vs. CLOCK FREQUENCY 80 2.0625 SFDR THD 70 60 SINAD MAX1421 toc23 2.0750 VREF (V) SNR 2.0500 2.0375 2.0250 50 10 18 26 3.1 34 3.2 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.08 3.4 3.5 OUTPUT NOISE HISTOGRAM (DC-INPUT) 50,000 MAX1421 toc24 2.10 3.3 VDD (V) CLOCK FREQUENCY (MHz) MAX1421 toc25 SFDR, SNR, THD, SINAD (dB) fIN = 5MHz MAX1421 toc22 90 43707 45,000 40,000 COUNTS 35,000 VREF (V) MAX1421 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference 2.06 30,000 25,000 20,000 2.04 15,000 5000 0 2.00 -40 -15 10 35 TEMPERATURE (°C) 8 10824 10709 10,000 2.02 60 85 1 N-3 179 N-2 N-1 N N+1 116 0 N+2 N+3 DIGITAL OUTPUT NOISE _______________________________________________________________________________________ 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference PIN NAME FUNCTION 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 AGND Analog Ground. Connect all return paths for analog signals to AGND. 2, 3, 10, 11, 14, 15, 20, 42, 47 AVDD Analog Supply Voltage. For optimum performance bypass to the closest AGND with a parallel combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between AVDD and AGND. 6 INP Positive Analog Signal Input 7 INN Negative Analog Signal Input 17 CLK Clock Frequency Input. Clock frequency input ranges from 100kHz to 40MHz. 18 CLK Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is driven with a single-ended clock, bypass CLK with a 0.1µF capacitor to AGND. 21, 31, 32, DVDD Digital Supply Voltage. For optimum performance bypass, to the closest DGND with a parallel combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between DVDD and DGND. 22, 29, 30 DGND Digital Ground 23–28 D0–D5 Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB. 33–38 D6–D11 Digital Data Outputs. D6 through D11, where D11 represents the MSB. 39 OE Output Enable Input. A logic “1” on OE places the outputs D0–D11 into a high-impedance state. A logic “0” allows for the data bits to be read from the outputs. 40 PD Shutdown Input. A logic “1” on PD places the ADC into shutdown mode. 43 REFIN External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND. 44 REFP Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFP should be biased to VCML + VDIFF / 2. 45 REFN Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFN should be biased to VCML - VDIFF / 2. 46 CML Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF. With the internal reference disabled (REFIN = AGND). _______________________________________________________________________________________ 9 MAX1421 Pin Description MAX1421 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference Detailed Description The MAX1421 uses a 12-stage, fully-differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Each sample moves through a pipeline stage every halfclock-cycle. Including the delay through the output latch, the latency is seven clock cycles. A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digital-toanalog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage. This process is repeated until the signal has been processed by all 12 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Input Track-and-Hold Circuit Figure 2 displays a simplified functional diagram of the input T/H circuit in both track-and-hold modes. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit passes the input signal to the two capacitors (C2a and C2b) throughswitches (S4a and S4b). Switches S2a and S2b set the common mode for the transconductance amplifier (OTA) input, and open simultaneously with S1, sampling the input waveform. The resulting differential voltage is held on capacitors C2a and C2b. Switches S4a and S4b are then opened before switches S3a and S3b, connecting capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The OTA is used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first-stage quantizer and isolates the pipeline from the fast-changing input. The wide-input bandwidth, T/H amplifier allows the MAX1421 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs INP and INN can be driven either differentially or single-ended. Match the impedance of INP and INN and set the common-mode voltage to midsupply (AVDD / 2) for optimum performance. Analog Input and Reference Configuration The full-scale range of the MAX1421 is determined by the internally generated voltage difference between REFP (AVDD / 2 + VREFIN / 4) and REFN (AVDD / 2 V REFIN / 4). The MAX1421’s full-scale range is adjustable through REFIN, which provides a high input impedance for this purpose. REFP, CML (AVDD / 2), and REFN are internally buffered low impedance outputs. MDAC VIN INTERNAL BIAS Σ T/H x2 S5a S2a C1a TO NEXT STAGE FLASH ADC CML VOUT S3a DAC S4a 2 BITS OUT C2a S4c VIN STAGE 1 STAGE 2 STAGE 12 S1 OTA OUT S4b C2b C1b S3b DIGITAL CORRECTION LOGIC Figure 1. Pipelined Architecture 10 12 S2b D11–D0 INTERNAL BIAS Figure 2. Internal Track-and-Hold Circuit ______________________________________________________________________________________ S5b CML 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421 AVDD 50Ω (AV2DD) CML R 0.22µF 1nF AVDD 2 50Ω R REFP MAX4284 R R AVDD 2 0.22µF (AV2DD + 1V) 1nF MAX1421 AVDD 4 R 50Ω R ( ) REFN AVDD + 1V 2 MAX4284 0.22µF 1nF R AVDD 4 REFIN R AGND +1V Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled The MAX1421 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the on-chip +2.048V bandgap reference is active and REFIN, REFP, CML, and REFN are left floating. For stability purposes, bypass REFIN, REFP, REFN, and CML with a capacitor network of 0.22µF, in parallel with a 1nF capacitor to AGND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In unbuffered external reference mode, REFIN is connected to AGND, which deactivates the on-chip buffers of REFP, CML, and REFN. With their buffers shut down, these nodes become high impedance and can be driven by external reference sources, as shown in Figure 3. Clock Inputs (CLK, CLK) The MAX1421’s CLK and CLK inputs accept both single-ended and differential input operation, and accept CMOS-compatible clock signals. If CLK is driven with a single-ended clock signal, bypass CLK with a 0.1µF capacitor to AGND. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible jitter. Any significant aperture jitter limits the SNR performance of the ADC according to the following relationship: 1 SNRdB = 20 × log10 2π × ƒIN × t AJ where fIN represents the analog input frequency and tAJ is the aperture jitter. Clock jitter is especially critical for high input frequency applications. The clock input should always be considered as an analog input and routed away from any analog or digital signal lines. The MAX1421 clock input operates with a voltage threshold set to AVDD / 2. Clock inputs must meet the specifications for high and low periods, as stated in the Electrical Characteristics. ______________________________________________________________________________________ 11 MAX1421 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference OE INP D11–D0 ADC INN tBD tBE AVDD OUTPUT DATA D11–D0 10kΩ HIGH-Z VALID DATA 10kΩ Figure 5. Output Enable Timing CLK 10kΩ 10kΩ CLK MAX1421 AGND Figure 4. Simplified Clock Input Circuit Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10kΩ resistors to bias the common-mode level of each input. This circuit may be used to AC-couple the system clock signal to the MAX1421 clock input. Output Enable (OE), Power-Down (PD), and Output Data (D0–D11) With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power-down. All data outputs, D0 (LSB) through D11 (MSB), are TTL/CMOS-logic compatible. There is a seven clock- Table 1. MAX1421 Output Code for Differential Inputs DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT OFFSET BINARY VREF × 2047/2048 +FULL SCALE 1LSB 1111 1111 1111 VREF × 2046/2048 +FULL SCALE 2LSB 1111 1111 1110 VREF × 1/2048 + 1 LSB 1000 0000 0001 0 Bipolar Zero 1000 0000 0000 -VREF × 1/2048 - 1 LSB 0111 1111 1111 -VREF × 2046/2048 -FULL SCALE + 1 LSB 0000 0000 0001 -VREF × 2047/2048 -FULL SCALE 0000 0000 0000 cycle latency between any particular sample and its valid output data. The output coding is in offset binary format (Table 1). The capacitive load on the digital outputs D0 through D11 should be kept as low as possible (≤10pF), to avoid large digital currents that could feed back into the analog portion of the MAX1421, thereby degrading its dynamic performance. The use of digital buffers (e.g., 74LVCH16244) on the digital outputs of the ADC can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1421, add small-series resistors of 100Ω to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output. System Timing Requirements Figure 6 depicts the relationship between the clock input, analog input, and data output. The MAX1421 samples at the rising edge of CLK (falling edge of CLK) and output data is valid seven clock cycles (latency) later. Figure 6 also displays the relationship between the input clock parameters and the valid output data. Applications Information Figure 7 depicts a typical application circuit containing a single-ended to differential converter. The internal reference provides an AVDD / 2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter at the input suppresses some of the wideband noise associated with high-speed op amps. Select the RISO and CIN values to optimize the filter performance and to suit a particular application. For the application in Figure 7, a RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. Connecting CIN from INN to INP may further improve dynamic performance. * VREF = VREFP - VREFN 12 HIGH-Z ______________________________________________________________________________________ 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421 7 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT CLK tDO tCH tCL CLK DATA OUTPUT N-7 N-6 N-5 N-4 N-3 N-2 N-1 N Figure 6. System and Output Timing Diagram Using Transformer Coupling An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1421 for optimum performance. Connecting the center tap of the transformer to CML provides an AVDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements. In general, the MAX1421 provides better SFDR and THD with fully differential input signals over singleended input signals, especially for very high input frequencies. In differential input mode, even-order harmonics are suppressed and each of the inputs requires only half the signal swing compared to singleended mode. Single-Ended AC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal. Grounding, Bypassing, and Board Layout The MAX1421 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass REFP, REFN, REFIN, and CML with a parallel network of 0.22µF capacitors and 1nF to AGND. AVDD should be bypassed with a similar network of a 10µF bipolar capacitor in parallel with two ceramic capacitors of 1nF and 0.1µF. Follow the same rules to bypass the digital supply DV DD to DGND. Multilayer boards with separate ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arrangement to match the physical location of the analog ground (AGND) and the digital output driver ground (DGND) on the ADCs package. The two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer, DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces and remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and free of 90 degree turns. Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straightline can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1421 are measured using the best straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL ______________________________________________________________________________________ 13 MAX1421 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference +5V 0.1µF LOWPASS FILTER INP MAX4108 RISO 50Ω 0.1µF 300Ω CIN* 22pF 0.1µF -5V MAX1421 600Ω 0.1µF 44pF* 600Ω 300Ω CML 0.1µF 0.22µF +5V 1nF +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INN MAX4108 RISO 50Ω 300Ω -5V CIN* 22pF 0.1µF 300Ω 300Ω 300Ω *TWO CIN (22pF) CAPS MAY BE REPLACED BY ONE 44pF CAP, TO IMPROVE PERFORMANCE. Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion error specification of less than 1LSB guarantees no missing codes. Dynamic Parameter Definitions Aperture Jitter Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of 14 the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-bits): SNR(MAX) = (6.02 ✕ N + 1.76)dB In reality, there are other noise sources besides quantization noise e.g., thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. ______________________________________________________________________________________ 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421 25Ω INP 22pF * 0.1µF 1 VIN T1 2 N.C. 3 MAX1421 44pF * 6 5 4 CML 0.22µF 1nF MINICIRCUITS T1–1T–KK81 25Ω INN 22pF * *REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROVE DYNAMIC PERFORMANCE. Figure 8. Using a Transformer for AC-Coupling VIN RISO 50Ω 0.1µF MAX4108 100Ω 1kΩ INP CIN 22pF MAX1421 CML 0.22µF 1nF RISO 50Ω INN 100Ω CIN 22pF Figure 9. Single-Ended AC-Coupled Input Signal Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. CLK CLK ANALOG INPUT Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from: tAD tAJ SAMPLED DATA (T/H) ENOB = T/H TRACK HOLD SINADdB - 1.76dB 6.02dB TRACK Figure 10. Track-and-Hold Aperture Timing ______________________________________________________________________________________ 15 MAX1421 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 × log10 (V 2 2 2 2 + V3 + V4 + V5 V1 2 ) where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Functional Diagram CLK CLK AGND INTERFACE INP T/H PIPELINE ADC INN PD BANDGAP REFERENCE OUTPUT DRIVERS REFIN REFP CML REFN ______________________________________________________________________________________ D11–D0 DVDD REF SYSTEM + BIAS Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale. 16 AVDD MAX1421 DGND OE 12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference 32L/48L,TQFP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1421 Package Information