CY7C1041D 4-Mbit (256K x 16) Static RAM Functional Description[1] Features • Pin-and function-compatible with CY7C1041B The CY7C1041D is a high-performance CMOS static RAM organized as 256K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). • High speed — tAA = 10 ns • Low active power — ICC = 90 mA @ 10 ns (Industrial) • Low CMOS standby power — ISB2 = 10 mA • 2.0 V Data Retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features • Available in lead-free 44-Lead (400-Mil) Molded SOJ and 44-Pin TSOP II packages Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041D is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Pin Configurations Logic Block Diagram SOJ / TSOPII Top View 256K x 16 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 I/O0–I/O7 I/O8–I/O15 A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 COLUMN DECODER BHE WE CE OE BLE 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Note: 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05472 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 31, 2006 [+] Feedback CY7C1041D Selection Guide -10 (Industrial) -12 (Automotive)[2] Unit Maximum Access Time 10 12 ns Maximum Operating Current 90 95 mA Maximum CMOS Standby Current 10 15 mA Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (Above which the useful life may be impaired. For user guidelines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Ambient Temperature VCC Speed Industrial –40°C to +85°C 5V ± 0.5 10 ns Automotive –40°C to +125°C 5V ± 0.5 12 ns Supply Voltage on VCC to Relative GND[3] .... –0.5V to +6.0V Range DC Voltage Applied to Outputs in High Z State[3] .....................................–0.5V to VCC +0.5V DC Input Voltage[3] ..................................–0.5V to VCC +0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage -10 (Industrial) -12 (Automotive) Min. Min. Max. 2.4 VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Unit V 0.4 Voltage[3] Max. 2.4 0.4 V V 2.0 VCC + 0.5 2.0 VCC + 0.5 VIL Input LOW –0.5 0.8 –0.5 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current –1 +1 –1 +1 µA ICC VCC Operating Supply VCC = Max., Current f = fMAX = 1/tRC GND < VOUT < VCC, Output Disabled 100 MHz 90 - mA 83 MHz 80 95 mA 66 MHz 70 85 mA 40 MHz 60 75 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 20 25 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 10 15 mA Capacitance[4] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 5.0V 8 pF 8 pF Notes: 2. Automotive product information is Preliminary. 3. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05472 Rev. *C Page 2 of 9 [+] Feedback CY7C1041D Thermal Resistance[4] Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient)[4] ΘJC Thermal Resistance (Junction to Case)[4] SOJ Package TSOP II Package Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board Unit 57.91 50.66 °C/W 36.73 17.17 °C/W AC Test Loads and Waveforms[5] 10 ns device Z = 50Ω OUTPUT ALL INPUT PULSES 3.0V 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 90% 30 pF* GND 1.5V 90% 10% 10% ≤ 3 ns ≤ 3 ns (b) (a) High-Z Characteristics: R1 481Ω 5V OUTPUT THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: R2 255Ω 5 pF INCLUDING JIG AND SCOPE (c) Switching Characteristics[6] Over the Operating Range -10 (Industrial) Parameter Description Min. Max. -12 (Automotive) Min. Max. Unit Read Cycle tpower VCC(typical) to the First Access[7] 100 100 µs tRC Read Cycle Time 10 12 ns tAA Address to Data Valid 10 3 12 ns tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 3 12 ns tDOE OE LOW to Data Valid 5 6 ns tLZOE OE LOW to Low Z 0 [8, 9] tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z[9] 0 5 3 [8, 9] ns ns 6 3 5 ns ns tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 10 12 ns tDBE Byte Enable to Data Valid 5 6 ns tLZBE Byte Enable to Low Z tHZBE Byte Disable to High Z 0 6 0 0 ns 0 5 ns ns 6 ns Notes: 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c) 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device. Document #: 38-05472 Rev. *C Page 3 of 9 [+] Feedback CY7C1041D Switching Characteristics[6] Over the Operating Range(continued) -10 (Industrial) Parameter Write Cycle Description Min. Max. -12 (Automotive) Min. Max. Unit [10, 11] tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 7 10 ns tAW Address Set-Up to Write End 7 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 10 ns tSD Data Set-Up to Write End 6 7 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z[9] 3 3 ns Z[8, 9] tHZWE WE LOW to High 5 tBW Byte Enable to End of Write 6 7 ns 10 ns Data Retention Characteristics Over the Operating Range Parameter Conditions[13] Description VDR VCC for Data Retention ICCDR Data Retention Current ICCDR Data Retention Current tCDR[4] Chip Deselect to Data Retention Time tR[12] Operation Recovery Time Min. Max. 2.0 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Unit V Ind’l 10 mA Auto 15 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC VDR > 2V 4.5V tR tCDR CE Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes: 10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs 13. No input may exceed VCC + 0.5V 14. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. Document #: 38-05472 Rev. *C Page 4 of 9 [+] Feedback CY7C1041D Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled) [15,16] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT Write Cycle No. 1 (CE HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Controlled)[17, 18] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Notes: 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW 17. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05472 Rev. *C Page 5 of 9 [+] Feedback CY7C1041D Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE BHE, BLE t SD DATA I/O NOTE 19 tHD DATAIN VALID t HZOE Note: 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05472 Rev. *C Page 6 of 9 [+] Feedback CY7C1041D Switching Waveforms (continued) Write Cycle No. 4 (WE Controlled, OE LOW) tWC BHE, BLE ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD NOTE 19 DATA I/O tLZWE Truth Table CE H OE X WE X BLE X BHE X L L H L L L H L L L X L I/O0–I/O7 I/O8–I/O15 Mode Power High Z High Z Power Down Standby (ISB) L Data Out Data Out Read All bits Active (ICC) L H Data Out High Z Read Lower bits only Active (ICC) H H L High Z Data Out Read Upper bits only Active (ICC) L L L Data In Data In Write All bits Active (ICC) X L L H Data In High Z Write Lower bits only Active (ICC) L X L H L High Z Data In Write Upper bits only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 12 Ordering Code Package Diagram CY7C1041D-10VXI 51-85082 44-Lead (400-Mil) Molded SOJ (Pb-Free) CY7C1041D-10ZSXI 51-85087 44-Lead TSOP Type II (Pb-Free) CY7C1041D-12VXE 51-85082 44-Lead (400-Mil) Molded SOJ (Pb-Free) CY7C1041D-12ZSXE 51-85087 44-Lead TSOP Type II (Pb-Free) Package Type Operating Range Industrial Automotive Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05472 Rev. *C Page 7 of 9 [+] Feedback CY7C1041D Package Diagrams 44-Lead (400-Mil) Molded SOJ (51-85082) 51-85082-*B 44-Pin TSOP II (51-85087) 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05472 Rev. *C Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1041D Document History Page Document Title: CY7C1041D 4-Mbit (256K x 16) Static RAM Document Number: 38-05472 REV. ECN NO. Orig. of Issue Date Change Description of Change ** 201560 See ECN SWI Advance Datasheet for C9 IPP *A 233729 See ECN RKF 1.AC, DC parameters are modified as per EROS (Spec #01-2165) 2.Pb-free offering in the ‘ordering information’ *B 351117 See ECN PCI Changed from Advance to Preliminary Removed 17 and 20 ns Speed bin Added footnote # 4 Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 67 and 54 mA to 75 and 70 mA for 12 and 15 ns speed bins respectively ICC (Ind’l): Changed from 80, 67 and 54 mA to 90, 85 and 80 mA for 10, 12 and 15 ns speed bins respectively Changed footnote # 10 on tR Changed tSCE from 8 to 7 ns for 10 ns speed bin Added Static Discharge Voltage and latch-up current spec Added VIH(max) spec in footnote # 2 Changed reference voltage level for measurement of Hi-Z parameters from ±500 mV to ±200 mV Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram Changed part names from Z to ZS in the Ordering Information Table Removed L-Version Added 10 ns parts in the Ordering Information Table Added Lead-Free Ordering Information Shaded Ordering Information Table *C 446328 See ECN NXR Converted Preliminary to Final Removed -15 speed bin Removed Commercial Operating Range product information Added Automotive Operating Range product information Changed Maximum Rating for supply voltage from 7V to 6V Updated Thermal Resistance table Changed tHZWE from 6 ns to 5 ns Updated footnote #8 on High-Z parameter measurement Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table Document #: 38-05472 Rev. *C Page 9 of 9 [+] Feedback