www.fairchildsemi.com FMS7950 Clock Multiplier Features • • • • • • • • • Feedback select (FBsel) pin allows for wider range of input frequencies. When connected low, the lower input frequency range is selected. This provides output frequencies of up to eight times the input (see table 3). The higher input range is allowed when FBsel is connected high. Crystal reference input Up to 175 MHz of output frequency Nine configurable outputs Output enable pin 250 pS of output to output skew 300 pS of Cycle to Cycle Jitter VDD Range of 3.3V ±0.2V Commercial temperature range Available in 32 pin LQFP There are four banks of outputs where each bank has a dedicated divide select (DIV_SEL). Depending on the divide selection, the outputs are one half, one quarter, or one eighth of the VCO speed (see table 2 for details). Description FMS7950 is a high speed clock synthesizer designed for clock multiplication applications. It uses phase locked loop technology to generate frequencies up to 175 MHz. It has four banks of configurable outputs. REF_SEL allows selection between crystal input or a clock driven input. Connecting PLL_EN LOW and REF_SEL HIGH will disable the Phase locked loop when the crystal oscillator is not used. In this mode, FMS7950 will be in clock buffer mode where any clock applied to TCLK will be divided down to the four output banks per Table 2. This is ideal for system diagnostic test. FMS7950 operates at 3.3 Volts and is available in 32 pin LQFP. Block Diagram REF_SEL PLL_EN OE TCLK QA MUX QB MUX PLL X1 X2 XTAL OSC QC0 QC1 FBsel QD0 QD1 DIV_SEL A QD2 DIV_SEL B DIV_SEL C Control Logic QD3 DIV_SEL D QD4 REV. 1.0.0 1/9/01 PRODUCT SPECIFICATION FMS7950 VDDCOR FBsel 1 2 DIV_SEL A 3 4 DIV_SEL B GNDOUT QB GNDOUT QA VDDOUT TCLK PLL_EN REF_SEL Pin Assignments 32 31 30 29 28 27 26 25 24 23 QC0 22 QC1 21 GNDOUT QD0 32-PIN LQFP DIV_SEL C DIV_SEL D 5 6 20 19 GNDCOR X1 7 8 18 17 VDDOUT VDDOUT QD1 GNDOUT QD2 QD3 VDDOUT GNDOUT QD4 VDDOUT X2 OE 9 10 11 12 13 14 15 16 Pin Description Pin Name Pin # Pin Type VDDCOR 1 PWR FBsel 2 IN Feedback Select. When high, the feedback divide is 8, and when low, it is 16. It allows for a wider range of input frequencies. 3, 4, 5, 6 IN Divider Select: It divides the clock to a desirable value. See table 2. GNDCOR 7 PWR X1 8 IN Crystal Connection. An input connection for an external crystal or oscillator. 18 pF internal cap. It can be used as an external crystal connection or as an external reference frequency input. X2 9 OUT Crystal Connection or External Reference Frequency. This pin has dual functions. OE 10 IN Output Enable. When high, all outputs are in high impedance. Normal operation when asserted low. 11, 15, 19, 23, 27 PWR Power Connection. Power supply for all the output buffers. Connect to 3.3 Volts nominal. QA; QB; QC(0:1); 12, 14, 16, 18, 20, QD(0:4) 22, 24, 26, 28 OUT Clock Outputs. These outputs are multiple of the input. GNDOUT 13, 17, 21, 25, 29 PWR Ground Connection. Ground for all the outputs. Connect to common system ground plane. TCLK 30 IN Test Clock. When REF_SEL is high, all outputs are buffer copy of TCLK. When REF_SEL is low, TCLK is disabled. PLL_EN 31 IN PLL Enable. When low, PLL is bypassed. REF_SEL 32 IN Reference Select. When low, crystal is used for input. When high, TCLK is used for input. DIV_SEL(A:D) VDDOUT 2 Description Power Connection. Power supply for core logic and PLL circuitry. Connect to 3.3 Volts nominal. Ground Connection. Ground for core logic and PLL circuitry. Connect to the common system ground plane. REV. 1.0.0 1/9/01 FMS7950 PRODUCT SPECIFICATION Table 1. Functionality REF_SEL PLL_EN OE PLL All Outputs Input 0 0 1 By Pass Hi-Z XTAL 0 0 0 By Pass Running XTAL 0 1 0 Enabled Running XTAL 1 0 1 By Pass Hi-Z TCLK 1 0 0 By Pass Running TCLK 1 1 0 Enabled Running TCLK Table 2. Input Versus Output Frequency FBsel = 1 DIV_SEL A DIV_SEL B DIV_SEL C DIV_SEL D QA QB FBsel = 0 QC QD QA QB QC QD 0 0 0 0 4XRef 2XRef 2XRef 2XRef 8XRef 4XRef 4XRef 4XRef 0 0 0 1 4XRef 2XRef 2XRef 0 0 1 0 4XRef 2XRef 0 0 1 1 4XRef 2XRef 0 1 0 0 4XRef Ref 2XRef 2XRef 8XRef 2XRef 4XRef 4XRef 0 1 0 1 4XRef Ref 2XRef 0 1 1 0 4XRef Ref Ref 0 1 1 1 4XRef Ref Ref 1 0 0 0 2XRef 2XRef 2XRef 2XRef 4XRef 4XRef 4XRef 4XRef 1 0 0 1 2XRef 2XRef 2XRef 1 0 1 0 2XRef 2XRef Ref 1 0 1 1 2XRef 2XRef Ref 1 1 0 0 2XRef Ref 2XRef 2XRef 4XRef 2XRef 4XRef 4XRef 1 1 0 1 2XRef Ref 2XRef 1 1 1 0 2XRef Ref Ref 1 1 1 1 2XRef Ref Ref Ref Ref 8XRef 4XRef 4XRef 2XRef 2XRef 8XRef 4XRef 2XRef 4XRef Ref Ref Ref 8XRef 4XRef 2XRef 2XRef 8XRef 2XRef 4XRef 2XRef 2XRef 8XRef 2XRef 2XRef 4XRef Ref Ref 8XRef 2XRef 2XRef 2XRef 4XRef 4XRef 4XRef 2XRef 2XRef 4XRef 4XRef 2XRef 4XRef Ref Ref 4XRef 4XRef 2XRef 2XRef 4XRef 2XRef 4XRef 2XRef 2XRef 4XRef 2XRef 2XRef 4XRef Ref 4XRef 2XRef 2XRef 2XRef Note: 1. Reference input could be either crystal input or TCLK input. Table 3. Divide Select Functionality DIV_SEL A DIV_SEL B DIV_SEL D DIV_SEL D QA QB QC QD 0 0 0 0 ÷2 ÷4 ÷4 ÷4 1 1 1 1 ÷4 ÷8 ÷8 ÷8 REV. 1.0.0 1/9/01 3 PRODUCT SPECIFICATION FMS7950 Absolute Maximum Ratings Symbol Parameter Ratings Units VDD, VIN Voltage on any pin with respect to ground -0.5 to 7.0 V TSTG Storage Temperature -65 to 150 °C TB Ambient Temperature -55 to 125 °C TA Operating Temperature 0 to 70 °C Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability. DC Electrical Characteristics TA = 0 to 70°C; Supply Voltage 3.3 V ±0.2V (unless otherwise stated) Parameter Symbol Conditions Min. Typ. Max. Units 0.8 V Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL VIN= 0 -10 10 µA Input High Current IIH VIN= VDD -30 30 µA 0.5 V 2.0 Output Low Voltage VOL IOL= 40 mA Output High Voltage VOH IOH= –40mA Capacitance(1) CIN Input Supply Current Clock Stabilization(1) IDD TSTAB V 2.2 V 7.0 pF Outputs loaded 200 mA From VDD = 3.3V to 1% Target 10 mS Note: 1. Guaranteed by design, not subject to 100% production testing. AC Electrical Characteristics TA = 0 to 70°C; Supply Voltage VDD = 3.3V ±0.2V, CL = 10 pF (unless otherwise stated) Parameter Input Frequency Range Output Frequency Range Output to Output Skew Symbol FINPUT FOUT TSK1 Conditions Min. Typ. Max. Units FBsel = 1 25 43 MHz FBsel = 0 12 22 MHz QA; DIV_SEL A = 0V 175 MHz QB, QC & QD; DIV_SEL B, C, D = 0V 88 MHz 400 750 pS 100 300 VTH = VDD/2; DIV_SEL A = 0 VTH = VDD/2; DIV_SEL A = 1 -300 TR 0.8 to 2.0V 0.10 1.0 nS TF 2.0 to 0.8V 0.10 1.0 nS Cycle(1) DT VTH = VDD/2 45 55 % Jitter (Cycle-Cycle) TJIT QA: DIV_SEL A = 0 450 pS QA: DIV_SEL A = 1 200 QB Output 200 QC(0:1) Outputs 300 QD(0:4) Outputs 375 Rise Time(1) Fall Time(1) Duty Note: 1. Guaranteed by design, not subject to 100% production testing. 4 REV. 1.0.0 1/9/01 FMS7950 PRODUCT SPECIFICATION Parameter Measurement Information Duty Cycle (DT) T1 T2 DT = 1.5V 1.5V 1.5V T2 x 100 T1 Rise/Fall Time (TR/TF) 2.0V 2.0V 0.8V Output 3.3V 0.8V 0V TR TF Output to Output Skew (TSK1) 1.5V Q0 1.5V Any Output TSK1 REV. 1.0.0 1/9/01 5 PRODUCT SPECIFICATION FMS7950 Application FMS7950 is one of the simplest form of frequency synthesizer. It uses phase locked loop technology with a divide of “N” in its feedback path. Its purpose is to generate a large number of different output frequencies, all related to a single, highly stable reference source. To achieve this, a crystal is connected at X1 and X2. No external components are required since the capacitors and oscillator are integrated. Figure 1 depicts the block diagram for FMS7950. X1 Phase Detected Loop Filter VCO P QA Q QB R QC(0:1) S QD(0:4) Osc. X2 Figure 1. In general, phase locked loops are governed by the equation: F OUT = N • F REF Equation 1 Equation 1 states that any output can be generated if “N” is varied. In FMS7950, the available dividers are eight or sixteen. These values are selected by connecting FBsel to ground or VDD. To determine the allowable range of input frequencies for each different FBsel setting, the following equation must be used: F REF = F VCO ÷ N Equation 2 If divided by eight is selected, the minimum input range will be: F REF_MIN = 200 ÷ 8 = 25 MHZ The maximum input range: F REF_MAX = 360 ÷ 8 = 43.75 MHZ If divide by sixteen is selected, a lower range of input frequency is allowed (12.5–22MHZ). This analysis reveals that if lower input frequency is available, FBsel must be connected to GND. On the other hand, higher input frequencies require FBsel to be connected to VDD. In practical applications, it is always the output frequency that is known and one must work backwards to determine the input and VCO frequencies. The best approach to explain is by an example. Assume an application requires the following output frequencies: QA = 133.33 MHZ QB = 66.66 MHZ QC & QD = 33.33 MHZ 6 REV. 1.0.0 1/9/01 FMS7950 PRODUCT SPECIFICATION The following connection is used: DIV_SEL A = 0;P=2 DIV_SEL B = 0;Q=4 DIV_SEL C & D = 1 ; R = S = 8 To calculate the VCO frequency, we find the output that requires the highest frequency and used the following equation. In this case, it will be QA output. F VCO = P • QA = 2 • 133.33 MHZ = 266.66 MHZ To determine the input frequency, we will use Equation 2, and set “N” to 16: F REF = 266.66 MHZ ÷ 16 = 16.66 MHZ Note, divide by eight could also have been used. The only difference is that it would require an input clock of 33.33MHZ rather than 16.66MHZ. REV. 1.0.0 1/9/01 7 PRODUCT SPECIFICATION FMS7950 Mechanical Dimensions 32-Pin LQFP Inches Symbol A A1 A2 B C D/E D1/E1 e L N ND α ccc Millimeters Min. Max. Min. Max. – 0.063 0.006 0.057 – 1.60 0.15 0.002 0.053 0.012 0.018 – 0.004 0.354 BSC 0.276 BSC 0.032 BSC 0.018 0.030 32 8 0° 7° – 0.004 0.05 1.35 1.45 0.30 0.45 – 0.10 9.00 BSC 7.00 BSC 0.800 BSC 0.45 0.75 32 8 0° 7° – 0.10 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. 3. Pin 1 identifier is optional. 4. Dimension N: number of terminals. 5. Dimension ND: Number of terminals per package edge. 7 6. "L" is the length of terminal for soldering to a substrate. 7. "B" includes lead finish thickness. 2 6 4 5 D D1 e PIN 1 E E1 IDENTIFIER C L α .039" Ref (1.00mm) See Lead Detail A Base Plane A2 B A1 Seating Plane -CLEAD COPLANARITY ccc 8 C REV. 1.0.0 1/9/01 PRODUCT SPECIFICATION FMS7950 Ordering Information Product Number FMS7950KWC FMS7950KWCX Package Description Package Marking LQFP-32 7950KWC LQFP-32 w/T+R 7950KWC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 1/9/01 0.0m 005 Stock#DS3007950 2000 Fairchild Semiconductor Corporation