EMIF02-SPK01C2 IPAD™ 2 line EMI filter and ESD protection Main product characteristics Where EMI filtering in ESD sensitive equipment is required: ■ Mobile phones and communication systems ■ Computers and printers and MCU Boards Description The EMIF02-SPK01C2 is a highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The Flip-Chip packaging means the package size is equal to the die size. This filter includes ESD protection circuitry, which prevents damage to the application when it is subjected to ESD surges up to 15 kV. Coated Flip-Chip package (about 20 times real size) Pin configuration (Bump side) Benefits ■ EMI symmetrical (I/O) low-pass filter ■ High efficiency EMI filter (-33 dB @ 900 MHz) ■ Very low PCB space consumption: 1.07 mm x 1.47 mm ■ Very thin package: 0.695 mm ■ Coating resin on back side and lead free package ■ High efficiency in ESD suppression ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging. 3 2 1 I2 I1 B GND O2 A O1 C Complies with following standards: IEC 61000-4-2 level 4 input pins level 1 output pins 15 kV (air discharge) 8 kV (contact discharge 2 kV (air discharge) 2 kV (contact discharge MIL STD 883G - Method 3015-7 Class 3 January 2007 Rev 1 1/7 www.st.com Characteristics 1 EMIF02-SPK01C2 Characteristics Figure 1. Basic cell configuration Low-pass Filter Input Output Ri/o = 10 Ω Cline = 200 pF GND Table 1. GND GND Absolute ratings (limiting values) Symbol Parameter Value Unit Tj Maximum junction temperature 125 °C Top Operating temperature range -40 to +85 °C Tstg Storage temperature range -55 to +150 °C Table 2. Electrical characteristics (Tamb = 25° C) Symbol Parameters I VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between input and output Cline Input capacitance per line IPP Symbol 2/7 Test conditions IR IRM VCL VBR VRM IRM IR V VRM VBR VCL IPP Min Typ 6 8 Max Unit VBR IR = 1 mA IRM VRM = 3 V per line RI/O Tolerance ±20% 10 Ω Cline VR = 0 V 200 pF V 500 nA EMIF02-SPK01C2 Figure 2. 0.00 Characteristics S21 (dB) attenuation measurement Figure 3. Analog crosstalk measurement dB dB 0.00 --5.00 --10.00 --10.00 --20.00 --15.00 --20.00 --30.00 --25.00 --40.00 --30.00 --50.00 -35.00 F (Hz) -40.00 100.0k 1.0M 10.0M 100.0M F (Hz) --60.00 100.0k 1.0G Figure 4. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input Vin and one output Vout Figure 6. Line capacitance versus applied voltage Figure 5. 1.0M 10.0M 100.0M 1.0G ESD response to IEC 61000-4-2 (- 15 kV air discharge) on one input Vin and one output Vout C(pF) 250 F=1MHz Vosc=30mVRMS Tj=25°C 200 150 100 50 VR(V) 0 0 1 2 3 4 5 3/7 Characteristics EMIF02-SPK01C2 Figure 7. IN1 Aplac model Rspk Rbump Lbump Lspk Lbump Rbump GND OUT1 Lsub model = D1 model = D2 Rsub Rbump GND model = D3 Lbump model = D1 model = D2 Lgnd Cgnd IN2 Rspk Lspk Lbump Rbump Ground return EMIF02-SPK01C2 model Figure 8. Rgnd OUT2 Rbump Lbump Aplac parameters Model D1 Model D3 Model D2 aplacvar Ls 1nH CJO=Cdiode1 CJO=Cdiode3 CJO=Cdiode2 aplacvar Rs 150m BV=7 BV=7 BV=7 aplacvar Rspk 10 IBV=1u IBV=1u IBV=1u aplacvar Lspk 10p IKF=1000 IKF=1000 IKF=1000 aplacvar Cdiode1 234pF IS=10f IS=10f IS=10f aplacvar Cdiode2 3.5ppF ISR=100p ISR=100p ISR=100p aplacvar Cdiode3 1nF N=1 N=1 N=1 aplacvar Lbump 50pH M=0.3333 M=0.3333 M=0.3333 aplacvar Rbump 10m RS=0.7 RS=0.12 RS=0.3 aplacvar Rsub 0.5m VJ=0.6 VJ=0.6 VJ=0.6 aplacvar Lsub 10pH TT=50n TT=50n TT=50n aplacvar Rgnd 1m aplacvar Lgnd 50pH aplacvar Cgnd 0.15pF 4/7 EMIF02-SPK01C2 2 Ordering information scheme Ordering information scheme EMIF yy - xxx zz Cx EMI Filter Number of lines Information 3 letters = application 2 digits = version Package C = Coated Flip-Chip x = 2: Leadfree Pitch = 500 µm, Bump = 315 µm Package information Figure 9. Flip-Chip Dimensions 500 µm ± 10 315 µm ± 50 695 µm ± 50 µm ± 15 1.47 mm ± 50 µm 250 µm ± 10 50 0 3 1.07 mm ± 50 µm Figure 10. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) Figure 11. Footprint recommendation Copper pad Diameter: 250µm recommended, 300 µm max E x x z y ww Solder stencil opening: 330 µm Solder mask opening recommendation: 340 µm min for 315 µm copper pad diameter 5/7 Ordering information EMIF02-SPK01C2 Figure 12. Flip-Chip tape and reel specification Dot identifying Pin A1 location Ø 1.5 ± 0.1 1.75 ± 0.1 ST E ST E ST E xxz yww xxz yww xxz yww 0.73 ± 0.05 3.5 ± 0.1 8 ± 0.3 4 ± 0.1 4 ± 0.1 User direction of unreeling All dimensions in mm In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 4 5 6/7 Ordering information Ordering code Marking Package Weight Base qty Delivery mode EMIF02-SPK01C2 FX Flip-Chip 2.3 mg 5000 7” Tape and reel Revision history Date Revision 26-Jan-2006 1 Changes Initial release. EMIF02-SPK01C2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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