SLD-2083CZ Product Description Pb RoHS Compliant & Green Package 12 Watt Discrete LDMOS FET in Ceramic Package Sirenza Microdevices’ SLD-2083CZ is a robust 12 Watt high performance LDMOS transistor designed for operation to 2700MHz. It is an excellent solution for applications requiring high linearity and efficiency at a low cost. The SLD-2083CZ is typically used in the design of driver stages for power amplifiers, repeaters, and RFID applications. The power transistor is fabricated using Sirenza’s high performance XeMOS IITM process. Functional Schematic Diagram Product Features • • • • • • ESD Protection 12 Watt Output P1dB Single Polarity Supply Voltage High Gain: 18 dB at 915 MHz High Efficiency: 47% at 10W CW XeMOS II LDMOS Integrated ESD Protection, Class 1B Applications • • • • • Case Flange = Ground RF Specifications Symbol Frequency Gain Efficiency IRL Linearity RTH Base Station PA driver Repeaters RFID Military Communication GSM/CDMA Parameter Unit Min Typ Max Frequency of Operation MHz 10 - 2700 - 10 Watt CW, 902 - 928MHz dB 17 18 Drain Efficiency at 10 Watt CW, 915MHz % 40 47 - Input Return Loss, 10 Watt Output Power, 915MHz dB - -15 -10 - 3rd Order IMD at 10 Watt PEP (Two Tone), 915MHz dBc -28 -26 1dB Compression (P1dB), 915MHz Watt 12 - IS-95, 9 Ch Fwd, Offset=750KHz, ACPR Integrated Bandwidth, ACPR=-55dB Watt 1.6 - IS-95, 9 Ch Fwd, Offset=750KHz, ACPR Integrated Bandwidth, ACPR=-45dB Watt 3.6 - Thermal Resistance (Junction-to-Case) ºC/W 4 Test Conditions VDS = 28.0V, IDQ = 125mA, TFlange = 25ºC T DC Specifications Symbol Parameter Unit Typical 590 IDS=3mA Volt 3.8 1mA IDS current Volt 65 Ciss Input Capacitance (Gate to Source) VGS=0V, VDS=28V pF 27.5 Crss Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V pF 0.81 Coss Output Capacitance (Drain to Source) VGS=0V, VDS=28V pF 14.65 Drain to Source Resistance, VGS=10V, VDS=250mV Ω 0.6 VGSThreshold VDS Breakdown RDSon Forward Transconductance @ 125mA IDS Min mA / V gm Max The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET Quality Specifications Parameter Description Unit ESD Rating Human Body Model Volts 750 85oC Leadframe, 200oC Channel Hours 1.2 X 106 MTTF Typical Pin Description Pin # Function Description 1 Gate Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the recommended maximum input power or voltage. . 2 Drain Transistor RF output and drain bias voltage. Typical voltage is 28V. Flange Source, Gnd Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions for recommendation. Pin Diagram Note 1: Gate voltage must be applied to VGS lead concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the transistor unless it is properly terminated on both input and output. ESD Protection Pin 2 Pin 1 Note 2: The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in threshold voltage withLDMOS transistors. Note 3: The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Case Flange = Ground Absolute Maximum Ratings Parameters Drain Voltage (VDS ) Value Unit 35 V Gate Voltage (VGS) 20 V RF Input Power +33 dBm Load Impedance for Continuous Operation Without Damage 10:1 VSWR Output Device Channel Temperature +200 ºC Lead Temperature During Solder Reflow +270 ºC Operating Temperature Range -20 to +90 ºC Storage Temperature Range -40 to +100 ºC Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET Typical Performance Curves in 900 MHz Application Circuit 60 55 23 50 22 45 21 40 20 35 19 30 18 25 Gain Efficiency 17 20 16 -4 Gain Efficiency 40 IRL 30 -12 20 -16 10 -20 0 900 10 2 4 6 8 10 12 14 16 905 910 Pout (W) Efficiency IM5 IRL 0 -20 30 -30 20 -40 10 -50 Gain (dB), Efficiency (%) -10 40 0 905 910 915 920 -25 40 -30 35 -35 30 -40 25 -45 20 -50 15 -55 10 -60 Gain IM3 IM7 5 900 -24 925 2 Tone Gain, Efficiency, Linearity vs Pout Vdd=28V, Idq=125mA, Freq=915 MHz, Delta F=1 MHz 45 IMD(dBc), IRL (dB) 50 920 Frequency (MHz) 2 Tone Gain, Efficiency, Linearity and IRL vs Frequency Vdd=28V, Idq=125mA, Pout=10W PEP, Delta F=1 MHz Gain IM3 IM7 915 -60 925 Frequency (MHz) IMD (dBc) 0 Gain (dB), Efficiency (%) -8 15 15 60 0 50 Gain (dB), Efficiency (%) 24 60 Efficiency (%) Gain (dB) 25 CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=125mA, Pout=10W Input Return Loss (dB) CW Gain, Efficiency vs Pout Vdd=28V, Idq=125mA, Freq=915 MHz Efficiency IM5 -65 0 -70 1 3 5 7 9 11 13 Pout (W PEP) To receive Gerber files, DXF drawings, and assembly recommendations for the test board with fixture, contact applications support at [email protected]. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET 900 MHz Application Circuit Bill of Materials - 900 MHz Application Circuit Reference Designation C1, C2 Description Mfg Mfg part # CAP 68PF250V 5% 0603 ATC 600S680JT250XT L1 IND, 5.1 Nh 5% 0603 coilcraft 0603CS-5N1XJB L2 IND, 2.7 nH +/- 0.3 nH 0603 Toko LL1608-F2N7S L3 IND, 4.7 nH 10% 0603 Toko LL1608-F4N7K CAP 0.1 UF 16V 10% 0603 AVX 0603YG104ZA2A 06035C102KAT2A C10 C11,C20 CAP 1000 PF 50V 10% 603 AVX C12, C21 CAP 68PF 250V 5% 603 LF ATC 600S680JT250XT Kemet T494D106M035AS Panasonic ECJ2YB1H104K Johnson 142-0751-821 C18 C19, C22 J1, J2 CAP 10 UF 35V 20% TAN T ELECT CAP 0.1 UF 50V 10% 805 Connector SMA END 0.037 J3 Connector MTA SMD R/A 2 PIN Amp R1 640455-2 RES 324 1/16W 1% 603 Panasonic ERJ-3EKF3240V R2 RES 49.9 1/10W 1% 805 Panasonic ERJ-6ENF49R9V R3 POT TRIM 500 OHM 2MM Panasonic EVM-2WSX80B52 R30 RES 49.9 1/16W 1% 603 Panasonic ERJ-EKF49R9V R5 RES 130 1/16W 1% 603 Panasonic ERJ-3EKF1300V R7 RES 210 1/16W 1% 603 Phillips 9C06031A2100FKHFT R9 RES 0 1/16W 5% 603 Panasonic ERJ-3GSY0R00V R90 RES 1.0K 1/16W 1% 603 Panasonic ERJ-3EKF1001V RT1 THERMISTOR 100K 5% 603 Panasonic ERT-J1VV104J LM3480IM3-5.0 U1 IC VOLT REG 100 MA 5 V SOT-23 National 6 Screws SCREW #2-56 PHILIPS PAN HEAD various - WASHER #2 FLAT SS various - PCB, 30 mils thick Dk=3.48 Rogers 4350 machined alumininum various - 6 Washers PCB Heatsink 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET Impedance data Device under test Input Matching Network Z source Output Matching Network Z load Zsource and Zload are the optimal impedances presented to the SLD-2083CZ when operating at 28V, Idq=125mA, Pout=10 W PEP Impedance Data Frequency (MHz) Zsource Zload 870 0.50 + j 2.0 4.3+ j 1.9 880 0.55 + j 1.9 4.3 + j 2.0 900 0.60 + j 1.8 4.4+ j 2.0 930 0.65 + j 1.7 4.5 + j 2.0 960 0.80 + j 1.4 4.7 + j 2.0 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 5 http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET Package Outline Drawing Chamferred Lead is FET Drain 0.290 Lead Coplanarity Lead foot to backside 0.000 ± 0.002 0.160 0.000±0.002 R0.015 DETAIL A TOP VIEW 0.200 0.160 0.100 0.090 0.140 0.050 0.008 0.160 SIDE VIEW DETAIL A END VIEW Recommended Landing Pads for the RF083 Package All Dimensions are in inches Part Number Ordering Information 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 6 Part Number Devices Per Reel Reel Size SLD-2083CZ 500 7’’ http://www.sirenza.com EDS-103754 Rev E