Si8410/20/21 S I N G L E & D U A L - C H A N N E L D I G I TA L I S O L A T O R S Features High-speed operation Pin Assignments 2500 VRMS isolation DC – 150 Mbps Narrow Body SOIC Transient Immunity Low propagation delay >25 kV/µs <10 ns DC correct No start-up initialization required <10 µs Startup Time High temperature operation Wide Operating Supply Voltage: 2.375–5.5 V Low power I1 + I2 < 12 mA/channel at 100 Mbps 125 °C at 100 Mbps 100 °C at 150 Mbps Precise timing Si841x VDD1 A1 VDD1 GND1 Narrow body SOIC-8 package 2 ns pulse width distortion 1 ns channel-channel matching 2 ns pulse width skew 8 7 6 5 1 2 3 4 VDD2 GND2 B1 GND2 Top View Si842x VDD1 Applications A1 Isolated switch mode supplies Isolated ADC, DAC Motor control Power factor correction systems Safety Regulatory Approvals A2 GND1 8 7 6 5 1 2 3 4 VDD2 B1 B2 GND2 Top View UL recognition:2500 Vrms for 1 Minute per UL1577 CSA component acceptance notice IEC certification conformity IEC 60747-5-2 (VDE0884 Part 2) Description The Silicon Laboratories family of digital isolators are CMOS devices that employ an RF coupler to transmit digital information across an isolation barrier. Very high speed operation at low power levels is achieved. These parts are available in an 8-pin narrow-body SOIC package. Three speed grade options (1, 10, and 150 Mbps) are available and achieve typical propagation delays of less than 10 ns. Block Diagram Si8410 A1 Si8420 B1 Preliminary Rev. 0.1 5/07 A1 A2 Si8421 B1 A1 B1 B2 A2 B2 Copyright © 2007 by Silicon Laboratories Si8410/20/21 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si8410/20/21 2 Preliminary Rev. 0.1 Si8410/20/21 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 22 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7. Package Outline: 8-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Preliminary Rev. 0.1 3 Si8410/20/21 1. Electrical Specifications Table 1. Electrical Characteristics (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL DC Supply Current (All inputs 0 V or at Supply) Si8410-A,-B,-C, VDD1 All inputs 0 DC — 7 10 mA Si8410-A,-B,-C, VDD2 All inputs 0 DC — 3 5 mA Si8410-A,-B,-C, VDD1 All inputs 1 DC — 9 14 mA Si8410-A,-B,-C, VDD2 All inputs 1 DC — 3 5 mA Si8420-A,-B,-C, VDD1 All inputs 0 DC — 7 10 mA Si8420-A,-B,-C, VDD2 All inputs 0 DC — 4 7 mA Si8420-A,-B,-C, VDD1 All inputs 1 DC — 11 15 mA Si8420-A,-B,-C, VDD2 All inputs 1 DC — 4 6 mA Si8421-A,-B,-C, VDD1 All inputs 0 DC — 9 12 mA Si8421-A,-B,-C, VDD2 All inputs 0 DC — 9 12 mA Si8421-A,-B,-C, VDD1 All inputs 1 DC — 10 14 mA Si8421-A,-B,-C, VDD2 All inputs 1 DC — 10 14 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8410-B,-C, VDD1 — 8 12 mA Si8410-B,-C, VDD2 — 5 7 mA Si8420-B,-C, VDD1 — 9 13 mA Si8420-B,-C, VDD2 — 9 12 mA Si8421-B,-C, VDD1 — 12 16 mA Si8421-B,-C, VDD2 — 12 16 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8410-C, VDD1 — 8 12 mA Si8410-C, VDD2 — 15 22 mA Si8420-C, VDD1 — 9 13 mA Si8420-C, VDD2 — 30 39 mA Si8421-C, VDD1 — 21 27 mA Si8421-C, VDD2 — 21 27 mA 4 Preliminary Rev. 0.1 Si8410/20/21 Table 1. Electrical Characteristics (Continued) (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 1 Mbps Minimum Pulse Width — — 1000 ns Timing Characteristics Si841x/2x-A Propagation Delay tPHL, tPLH See Figure 1 25 40 75 ns PWD See Figure 1 — — 30 ns tPSK(P-P) — — 50 ns tPSK — — 40 ns Maximum Data Rate 0 — 10 Mbps Minimum Pulse Width — — 100 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si841x/2x-B Propagation Delay tPHL, tPLH See Figure 1 10 20 35 ns PWD See Figure 1 — — 7.5 ns tPSK(P-P) — — 25 ns tPSK — — 5 ns Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.6 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si841x/2x-C Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew tPHL, tPLH See Figure 1 4 6.5 9.5 ns PWD See Figure 1 — — 3.5 ns tPSK(P-P) — — 5.5 ns tPSK — — 3 ns Preliminary Rev. 0.1 5 Si8410/20/21 Table 1. Electrical Characteristics (Continued) (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit For All Models Output Rise Time tr CL = 15 pF — 2 — ns Output Fall Time tf CL = 15 pF — 2 — ns CTMI VI = VDD or 0 V 25 30 — kV/µs — 3 — µs Common Mode Transient Immunity Start-up Time2 tSU Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output. 50% Typical Input tPLH tPHL 90% 90% 10% 10% 50% Typical Output tr tf Figure 1. Propagation Delay Timing 6 Preliminary Rev. 0.1 Si8410/20/21 Table 2. Electrical Characteristics (VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL DC Supply Current (All inputs 0 V or at supply) Si8410-A,-B,-C, VDD1 All inputs 0 DC — 6 9 mA Si8410-A,-B,-C, VDD2 All inputs 0 DC — 2 4 mA Si8410-A,-B,-C, VDD1 All inputs 1 DC — 8 13 mA Si8410-A,-B,-C, VDD2 All inputs 1 DC — 2 4 mA Si8420-A,-B,-C, VDD1 All inputs 0 DC — 7 9 mA Si8420-A,-B,-C, VDD2 All inputs 0 DC — 4 6 mA Si8420-A,-B,-C, VDD1 All inputs 1 DC — 10 14 mA Si8420-A,-B,-C, VDD2 All inputs 1 DC — 4 6 mA Si8421-A,-B,-C, VDD1 All inputs 0 DC — 8 11 mA Si8421-A,-B,-C, VDD2 All inputs 0 DC — 8 11 mA Si8421-A,-B,-C, VDD1 All inputs 1 DC — 9 13 mA Si8421-A,-B,-C, VDD2 All inputs 1 DC — 9 13 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8410-B,-C, VDD1 — 7 11 mA Si8410-B,-C, VDD2 — 4 6 mA Si8420-B,-C, VDD1 — 8 12 mA Si8420-B,-C, VDD2 — 8 12 mA Si8421-B,-C, VDD1 — 10 14 mA Si8421-B,-C, VDD2 — 10 14 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8410-C, VDD1 — 7 11 mA Si8410-C, VDD2 — 10 16 mA Si8420-C, VDD1 — 8 12 mA Si8420-C, VDD2 — 20 26 mA Si8421-C, VDD1 — 17 21 mA Si8421-C, VDD2 — 17 21 mA Preliminary Rev. 0.1 7 Si8410/20/21 Table 2. Electrical Characteristics (Continued) (VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 1 Mbps Minimum Pulse Width — — 1000 ns Timing Characteristics Si841x/2x-A Propagation Delay tPHL, tPLH See Figure 1 25 40 75 ns PWD See Figure 1 — — 30 ns tPSK(P-P) — — 50 ns tPSK — — 40 ns Maximum Data Rate 0 — 10 Mbps Minimum Pulse Width — — 100 ns Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew1 Channel-Channel Skew Si841x/2x-B Propagation Delay tPHL, tPLH See Figure 1 10 20 35 ns PWD See Figure 1 — — 7.5 ns tPSK(P-P) — — 25 ns tPSK — — 5 ns Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.6 ns Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew1 Channel-Channel Skew Si841x/2x-C Propagation Delay Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew1 Channel-Channel Skew 8 tPHL, tPLH See Figure 1 4 7.5 10 ns PWD See Figure 1 — — 3.5 ns tPSK(P-P) — — 5.5 ns tPSK — — 3 ns Preliminary Rev. 0.1 Si8410/20/21 Table 2. Electrical Characteristics (Continued) (VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit For All Models Output Rise Time tr CL = 15 pF — 2 — ns Output Fall Time tf CL = 15 pF — 2 — ns CTMI VI = VDD or 0 V 25 30 — kV/µs — 3 — µs Common Mode Transient Immunity Start-up Time2 tSU Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output. Preliminary Rev. 0.1 9 Si8410/20/21 Table 3. Electrical Characteristics (VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 °C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 2.3 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL DC Supply Current (All inputs 0 V or at supply) Si8410-A,-B,-C, VDD1 All inputs 0 DC — 5 7 mA Si8410-A,-B,-C, VDD2 All inputs 0 DC — 2 3 mA Si8410-A,-B,-C, VDD1 All inputs 1 DC — 7 9 mA Si8410-A,-B,-C, VDD2 All inputs 1 DC — 2 3 mA Si8420-A,-B,-C, VDD1 All inputs 0 DC — 6 7 mA Si8420-A,-B,-C, VDD2 All inputs 0 DC — 4 5 mA Si8420-A,-B,-C, VDD1 All inputs 1 DC — 9 11 mA Si8420-A,-B,-C, VDD2 All inputs 1 DC — 3 5 mA Si8421-A,-B,-C, VDD1 All inputs 0 DC — 7 9 mA Si8421-A,-B,-C, VDD2 All inputs 0 DC — 7 9 mA Si8421-A,-B,-C, VDD1 All inputs 1 DC — 8 10 mA Si8421-A,-B,-C, VDD2 All inputs 1 DC — 8 10 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8410-B,-C, VDD1 — 6 8 mA Si8410-B,-C, VDD2 — 3 5 mA Si8420-B,-C, VDD1 — 7 9 mA Si8420-B,-C, VDD2 — 6 8 mA Si8421-B,-C, VDD1 — 8 11 mA Si8421-B,-C, VDD2 — 8 11 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8410-C, VDD1 — 6 8 mA Si8410-C, VDD2 — 7 10 mA Si8420-C, VDD1 — 7 9 mA Si8420-C, VDD2 — 12 15 mA Si8421-C, VDD1 — 12 15 mA Si8421-C, VDD2 — 12 15 mA 10 Preliminary Rev. 0.1 Si8410/20/21 Table 3. Electrical Characteristics (Continued) (VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 °C) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 1 Mbps Minimum Pulse Width — — 1000 ns Timing Characteristics Si841x/2x-A Propagation Delay tPHL, tPLH See Figure 1 25 40 75 ns PWD See Figure 1 — — 30 ns tPSK(P-P) — — 50 ns tPSK — — 40 ns Maximum Data Rate 0 — 10 Mbps Minimum Pulse Width — — 100 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si841x/2x-B Propagation Delay tPHL, tPLH See Figure 1 10 20 35 ns PWD See Figure 1 — — 7.5 ns tPSK(P-P) — — 25 ns tPSK — — 5 ns Maximum Data Rate 0 — 100 Mbps Minimum Pulse Width — — 10 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si841x/2x-C Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew tPHL, tPLH See Figure 1 5 10 17 ns PWD See Figure 1 — — 7 ns tPSK(P-P) — — 12 ns tPSK — — 4 ns Preliminary Rev. 0.1 11 Si8410/20/21 Table 3. Electrical Characteristics (Continued) (VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 °C) Parameter Symbol Test Condition Min Typ Max Unit For All Models Output Rise Time tr CL = 15 pF — 2 — ns Output Fall Time tf CL = 15 pF — 2 — ns CTMI VI = VDD or 0 V 25 30 — kV/µs — 3 — µs Common Mode Transient Immunity Start-up Time2 tSU Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output. 12 Preliminary Rev. 0.1 Si8410/20/21 Table 4. Absolute Maximum Ratings Parameter Symbol Min Typ Max Unit TSTG –65 — 150 C° TA –40 — 125 C° VDD1, VDD2 –0.5 — 6 V Input Voltage VI –0.5 — VDD + 0.5 V Output Voltage VO –0.5 — VDD + 0.5 V Output Current Drive Channel LO — — 10 mA Lead Solder Temperature (10s) — — 260 C° Maximum Isolation Voltage — — 4000 VDC Storage Temperature Operating Temperature Supply Voltage Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Table 5. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Ambient Operating Temperature* TA 100 Mbps, 15 pF, 5 V –40 25 125 C° 150 Mbps, 15 pF, 5 V 0 25 100 C° VDD1 2.375 — 5.5 V VDD2 2.375 — 5.5 V Supply Voltage *Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating channels, and supply voltage. Preliminary Rev. 0.1 13 Si8410/20/21 Table 6. Regulatory Information CSA The Si84xx is certified under CSA Component Acceptance Notice. For more details, see File 232873. VDE The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL The Si84xx is certified under UL1577 component recognition program to provide basic insulation to 2500 VRMS (1 minute). It is production tested > 3000 VRMS for 1 second. For more details, see File E257455. Table 7. Insulation and Safety-related Specifications Parameter Symbol Test Condition Value Unit Minimum Air Gap (Clearance) L(IO1) 5.0 min mm Minimum External Tracking (Creepage) L(IO2) 4.60 mm 0.008 min mm >175 V 1012 Ω 1.4 pF 4.0 pF Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Resistance (Input-Output)1 RIO 1 Capacitance (Input-Output) Input Capacitance2 DIN IEC 60112/VDE 0303 Part 1 CIO CI f = 1 MHz Notes: 1. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–4 are shorted together to form the first terminal and pins 5–8 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 2. Measured from input pin to ground. 14 Preliminary Rev. 0.1 Si8410/20/21 Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings Parameter Basic isolation group Installation Classification Test Conditions Specification Material Group IIIa Rated Mains Voltages < 150 VRMS I-IV Rated Mains Voltages < 300 VRMS I-III Rated Mains Voltages < 400 VRMS I-II Table 9. IEC 60747-5-2 Insulation Characteristics* Parameter Maximum Working Insulation Voltage Input to Output Test Voltage Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Symbol Test Condition VIORM VPR Characteristic Unit 560 V peak Method a After Environmental Tests Subgroup 1 (VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC) 896 Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 1050 After Input and/or Safety Test Subgroup 2/3 (VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC) 672 4000 VTR Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V V peak V peak 2 >109 RS Ω *Note: The Si84xx is suitable for basic electrical isolation a climate classification of 40/125/21. Table 10. IEC Safety Limiting Values Parameter Symbol Case Temperature TS Safety input, output, or supply current IS Test Condition θJA = 210 °C/W, VI = 5.5 V, TJ = 150 °C, TA = 25 °C Min Typ Max Unit — — 150 °C — — 105 mA *Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2. Preliminary Rev. 0.1 15 Si8410/20/21 Table 11. Thermal Characteristics Parameter Symbol Test Condition Min Typ Max Unit IC Junction-to-Case Thermal Resistance θJC Thermocouple located at center of package — 100 — °C/W IC Junction-to-Air Thermal Resistance θJA — 210 — °C/W Device Power Dissipation* PD — — 250 mW 78 75 121 128 100 106 Safety-Limiting Current (mA) *Note: The Si8420-C-IS is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 °C, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. 2.75 V 5.5 V 50 3.6 V 25 0 0 50 100 150 Case Temperature (ºC) 200 Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 16 Preliminary Rev. 0.1 Si8410/20/21 2. Typical Performance Characteristics 10 20 5V 5V Current (mA) Current (mA) 9 8 3.3V 7 2.5V 6 5 0 10 20 30 40 50 60 70 80 90 15 3.3V 10 2.5V 5 0 100 0 10 20 30 Data Rate (Mbps) 40 50 60 70 80 90 100 Data Rate (Mbps) Figure 3. Si8410 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation Figure 6. Si8420 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) 12 5V 19 3.3V 8 6 2.5V 4 2 0 0 10 20 30 40 50 60 70 80 90 5V 17 Current (mA) Current (mA) 10 100 Data Rate (Mbps) 15 3.3V 13 11 2.5V 9 7 5 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) Figure 4. Si8410 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) Figure 7. Si8421 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) 15 Current (mA) 13 11 5V 9 3.3V 7 2.5V 5 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) Figure 5. Si8420 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation Preliminary Rev. 0.1 17 Si8410/20/21 10 Delay (ns) 9 8 Falling Edge 7 6 Rising Edge 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 8. Propagation Delay vs. Temperature 5 V Operation 10 Delay (ns) 9 Rising Edge 8 Falling Edge 7 6 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 9. Propagation Delay vs. Temperature 3.3 V Operation 15 Delay (ns) 13 Rising Edge 11 Falling Edge 9 7 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 10. Propagation Delay vs. Temperature 2.5 V Operation 18 Preliminary Rev. 0.1 Si8410/20/21 3. Application Information 3.1. Theory of Operation The operation of an Si841x or Si842x channel is analogous to that of an opto coupler, except that an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at startup. A simplified block diagram for a single Si8410 channel is shown in Figure 11. A channel consists of an RF transmitter and receiver separated by a transformer. Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying and applies the resulting waveform to the primary of the transformer. The receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. TRANSMITTER RF OSCILLATOR A RECEIVER MODULATOR DEMODULATOR B Figure 11. Simplified Channel Diagram 3.2. Eye Diagram Figure 12 illustrates an eye-diagram taken on an Si8410. The test used an Anritsu (MP1763C) Pulse Pattern Generator for the data source. The output of the generator's clock and data from an Si8410 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that very low pulse width distortion and very little jitter were exhibited. Figure 12. Eye Diagram Preliminary Rev. 0.1 19 Si8410/20/21 4. Layout Recommendations Dielectric isolation is a set of specifications produced by safety regulatory agencies from around the world, which describes the physical construction of electrical equipment that derives power from high-voltage power systems, such as 100–240 VAC systems or industrial power. The dielectric test (or HIPOT test) given in the safety specifications places a very high voltage between the input power pins of a product and the user circuits and the user-touchable surfaces of the product. For the IEC relating to products deriving their power from the 220–240 V power grids, the test voltage is 2500 VAC (or 3750 VDC, the peak equivalent voltage). There are two terms described in the safety specifications: Creepage—the distance along the insulating surface an arc may travel. Clearance—the shortest distance through air that an arc may travel. Figure 13 illustrates the accepted method of providing the proper creepage distance along the surface. For a 220–240 V application, this distance is 8 mm, and the wide-body SOIC package must be used. There must be no copper traces within this 8 mm exclusion area, and the surface should have a conformal coating, such as solder resist. The digital isolator chip must straddle this exclusion area. Figure 13. Creepage Distance 4.1. Supply Bypass The Si841x and Si842x families require a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package. 20 Preliminary Rev. 0.1 Si8410/20/21 4.2. Input and Output Characteristics The Si841x and Si842x inputs and outputs are standard CMOS drivers/receivers. Table 12 details powered and unpowered operation of the Si84xx. Table 12. Si84xx Operation Table Comments VI Input1,4 VDDI State1,2,3 VDDO State1,2,3 VO Output1,4 H P P H L P P L X UP P L Upon the transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. X P UP L Upon the transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. Normal operation. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. 2. Powered (P) state is defined as 2.375 V < VDD < 5.5 V. 3. Unpowered (UP) state is defined as VDD = 0 V. 4. X = not applicable; H = Logic High; L = Logic Low. 4.3. RF Radiated Emissions The Si841x and Si842x families use an RF carrier frequency of approximately 2.1 GHz. This will result in a small amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but, rather, is due to a small amount of RF energy driving the isolated ground planes, which can act as a dipole antenna. The unshielded Si8410 evaluation board passes FCC requirements. Table 13 shows measured emissions compared to FCC requirements. Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less efficient antenna. Table 13. Radiated Emissions Frequency Measured (GHz) (dBµV/m) FCC Spec (dBµV/m) Compared to Spec (dB) 2.094 70.0 74.0 –4.0 2.168 68.3 74.0 –5.7 4.210 61.9 74.0 –12.1 4.337 60.7 74.0 –13.3 6.315 58.3 74.0 –15.7 6.505 60.7 74.0 –13.3 8.672 45.6 74.0 –28.4 Preliminary Rev. 0.1 21 Si8410/20/21 4.4. RF Immunity and Common Mode Transient Immunity The Si841x and Si842x families have very high common mode transient immunity while transmitting data. This is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements show no failures up to 30 kV/µs. During a high surge event, the output may glitch low for up to 20–30 ns, but the output corrects immediately after the surge event. The Si841x and Si842x families pass the industrial requirements of CISPR24 for RF immunity of 3 V/m using an unshielded evaluation board. As shown in Figure 14, the isolated ground planes form a parasitic dipole antenna, while Figure 15 shows the RMS common mode voltage versus frequency above which the Si841x becomes susceptible to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage below the envelope specified in Figure 15. The PCB should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded. GND1 Isolator GND2 Dipole Antenna Figure 14. Dipole Antenna RMS Voltage (V) 5 4 3 2 1 0 500 1000 1500 Frequency (MHz) Figure 15. RMS Common Mode Voltage vs. Frequency 22 Preliminary Rev. 0.1 2000 Si8410/20/21 5. Pin Descriptions Si841x VDD1 A1 VDD1 GND1 Si842x 8 7 6 5 1 2 3 4 VDD2 VDD1 GND2 A1 B1 A2 GND2 GND1 Top View 8 7 6 5 1 2 3 4 VDD2 B1 B2 GND2 Top View Narrow Body SOIC Name SOIC-8 Pin# Si8410 SOIC-8 Pin# Si8420/21 Type VDD1 1,3 1 Supply Side 1 power supply. GND1 4 4 Ground Side 1 ground. A1 2 2 Digital I/O Side 1 digital input or output. A2 NA 3 Digital I/O Side 1 digital input or output. B1 6 7 Digital I/O Side 2 digital input or output. B2 NA 6 Digital I/O Side 2 digital input or output. VDD2 8 8 Supply Side 2 power supply. GND2 5,7 5 Ground Side 2 ground. Preliminary Rev. 0.1 Description 23 Si8410/20/21 6. Ordering Guide Ordering Part Number Number of Inputs Number of Inputs VDD1 Side VDD2 Side Maximum Data Rate Temperature Package Type Si8410-A-IS 1 0 1 –40 to 125 °C SOIC-8 Si8410-B-IS 1 0 10 –40 to 125 °C SOIC-8 Si8410-C-IS 1 0 150 –40 to 125 °C SOIC-8 Si8420-A-IS 2 0 1 –40 to 125 °C SOIC-8 Si8420-B-IS 2 0 10 –40 to 125 °C SOIC-8 Si8420-C-IS 2 0 150 –40 to 125 °C SOIC-8 Si8421-A-IS 1 1 1 –40 to 125 °C SOIC-8 Si8421-B-IS 1 1 10 –40 to 125 °C SOIC-8 Si8421-C-IS 1 1 150 –40 to 125 °C SOIC-8 Note: All packages are Pb-free and RoHS Compliant. Moisture sensitivity level is MSL2 with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature. 24 Preliminary Rev. 0.1 Si8410/20/21 7. Package Outline: 8-Pin SOIC Figure 16 illustrates the package details for the Si84xx. Table 14 lists the values for the dimensions shown in the illustration. α Figure 16. 8-pin Small Outline Integrated Circuit (SOIC) Package Table 14. Package Diagram Dimensions Symbol Millimeters Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.40 REF 1.55 REF B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 ∝ 0° 8° Preliminary Rev. 0.1 25 Si8410/20/21 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 26 Preliminary Rev. 0.1