Si8430/31/35 T R I P L E - C H A N N E L D I G I TA L I S O L A T O R Features Pin Assignments High-speed operation: DC – 150 Mbps Low propagation delay: <10 ns Wide Operating Supply Voltage: 2.375-5.5V Low power: I1 + I2 < 12 mA/channel at 100 Mbps Precise timing: 2 ns pulse width distortion 1 ns channel-channel matching 2 ns pulse width skew 2500 VRMS isolation Transient Immunity: >25 kV/µs Tri-state outputs with ENABLE control DC correct No start-up initialization required <10 µs Startup Time High temperature operation: 125 °C at 100 Mbps 100 °C at 150 Mbps Wide body SOIC-16 package Wide Body SOIC VDD1 GND1 A1 A2 A3 NC EN1/NC GND1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VDD2 GND2 B1 B2 B3 NC EN2/NC GND2 Top View Applications Isolated switch mode supplies Isolated ADC, DAC Motor control Power factor correction systems Safety Regulatory Approvals UL recognition:2500 VRMS for 1 Minute per UL1577 CSA component acceptance notice VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2) Description Silicon Lab's family of digital isolators are CMOS devices that employ an RF coupler to transmit digital information across an isolation barrier. Very high speed operation at low power levels is achieved. These parts are available in a 16-pin wide body SOIC package. Three speed grade options (1, 10, 150 Mbps) are available and achieve typical propagation delay of less than 10 ns. Block Diagram Si8430/35 Rev. 0.3 8/07 Si8431 A1 B1 A1 B1 A2 B2 A2 B2 A3 B3 A3 B3 NC EN2/NC EN1 EN2 Copyright © 2007 by Silicon Laboratories Si8430/31/35 Si8430/31/35 2 Rev. 0.3 Si8430/31/35 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3. Enable (EN1, EN2) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 24 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Rev. 0.3 3 Si8430/31/35 1. Electrical Specifications Table 1. Electrical Characteristics (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL Enable Input High Current IENH VENx = VIH — 4 — µA Enable Input Low Current IENL VENx = VIL — 20 — µA DC Supply Current (All inputs 0 V or at Supply) Si8430/35-A,-B,-C, VDD1 All inputs 0 DC — 7 10 mA Si8430/35-A,-B,-C, VDD2 All inputs 0 DC — 6 9 mA Si8430/35-A,-B,-C, VDD1 All inputs 1 DC — 14 18 mA Si8430/35-A,-B,-C, VDD2 All inputs 1 DC — 6 9 mA Si8431-A,-B,-C, VDD1 All inputs 0 DC — 8 12 mA Si8431-A,-B,-C, VDD2 All inputs 0 DC — 10 15 mA Si8431-A,-B,-C, VDD1 All inputs 1 DC — 13 19 mA Si8431-A,-B,-C, VDD2 All inputs 1 DC — 12 17 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8430/35-B,-C, VDD1 — 11 15 mA Si8430/35-B,-C, VDD2 — 13 17 mA Si8431-B,-C, VDD1 — 12 16 mA Si8431-B,-C, VDD2 — 13 17 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8430-C, VDD1 — 11 15 mA Si8430-C, VDD2 — 23 28 mA Si8431-C, VDD1 — 13 18 mA Si8431-C, VDD2 — 21 26 mA 4 Rev. 0.3 Si8430/31/35 Table 1. Electrical Characteristics (Continued) (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 1 Mbps Minimum Pulse Width — — 1000 ns Timing Characteristics Si843x-A Propagation Delay tPHL, tPLH See Figure 2 — — 75 ns PWD See Figure 2 — — 30 ns tPSK(P-P) — — 50 ns tPSK — — 40 ns Maximum Data Rate 0 — 10 Mbps Minimum Pulse Width — — 100 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-B Propagation Delay tPHL, tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 7.5 ns tPSK(P-P) — — 25 ns tPSK — — 5 ns Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.6 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-C Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew tPHL, tPLH See Figure 2 4 6.5 9.5 ns PWD See Figure 2 — — 3 ns tPSK(P-P) — — 5.5 ns tPSK — — 3 ns Rev. 0.3 5 Si8430/31/35 Table 1. Electrical Characteristics (Continued) (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Output Rise Time tr CL = 15 pF See Figure 2 — 2 — ns Output Fall Time tf CL = 15 pF See Figure 2 — 2 — ns CTMI VI = VDD or 0 V 25 30 — kV/µs Enable to Data Valid ten1 See Figure 1 — 5 — ns Enable to Data Tri-State ten2 See Figure 1 — 5 — ns Time2 tSU — 3 — µs For All Models Common Mode Transient Immunity Start-up Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output. ENABLE OUTPUTS ten1 ten2 Figure 1. ENABLE Timing Diagram 50% Typical Input tPLH tPHL 90% 90% 10% 10% 50% Typical Output tr tf Figure 2. Propagation Delay Timing 6 Rev. 0.3 Si8430/31/35 Table 2. Electrical Characteristics (VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL Enable Input High Current IENH VENx = VIH — 4 — µA Enable Input Low Current IENL VENx = VIL — 20 — µA DC Supply Current (All inputs 0 V or at supply) Si8430/35-A,-B,-C, VDD1 All inputs 0 DC — 7 10 mA Si8430/35-A,-B,-C, VDD2 All inputs 0 DC — 6 9 mA Si8430/35-A,-B,-C, VDD1 All inputs 1 DC — 13 17 mA Si8430/35-A,-B,-C, VDD2 All inputs 1 DC — 5 8 mA Si8431-A,-B,-C, VDD1 All inputs 0 DC — 7 11 mA Si8431-A,-B,-C, VDD2 All inputs 0 DC — 10 15 mA Si8431-A,-B,-C, VDD1 All inputs 1 DC — 12 18 mA Si8431-A,-B,-C, VDD2 All inputs 1 DC — 11 16 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8430/35-B,-C, VDD1 — 10 14 mA Si8430/35-B,-C, VDD2 — 11 16 mA Si8431-B,-C, VDD1 — 10 15 mA Si8431-B,-C, VDD2 — 13 18 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8430-C, VDD1 — 11 15 mA Si8430-C, VDD2 — 16 20 mA Si8431-C, VDD1 — 12 18 mA Si8431-C, VDD2 — 19 25 mA Rev. 0.3 7 Si8430/31/35 Table 2. Electrical Characteristics (Continued) (VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 1 Mbps Minimum Pulse Width — — 1000 ns Timing Characteristics Si843x-A Propagation Delay tPHL, tPLH See Figure 2 — — 75 ns PWD See Figure 2 — — 30 ns tPSK(P-P) — — 50 ns tPSK — — 40 ns Maximum Data Rate 0 — 10 Mbps Minimum Pulse Width — — 100 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-B Propagation Delay tPHL, tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 7.5 ns tPSK(P-P) — — 25 ns tPSK — — 5 ns Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.6 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-C Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew 8 tPHL, tPLH See Figure 2 4 6.5 9.5 ns PWD See Figure 2 — — 3 ns tPSK(P-P) — — 5.5 ns tPSK — — 3 ns Rev. 0.3 Si8430/31/35 Table 2. Electrical Characteristics (Continued) (VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Output Rise Time tr CL = 15 pF See Figure 2 — 2 — ns Output Fall Time tf CL = 15 pF See Figure 2 — 2 — ns CTMI VI = VDD or 0 V 25 30 — kV/µs Enable to Data Valid ten1 See Figure 1 — 5 — ns Enable to Data Tri-State ten2 See Figure 1 — 5 — ns — 3 — µs For All Models Common Mode Transient Immunity Start-up Time 2 tSU Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output. Rev. 0.3 9 Si8430/31/35 Table 3. Electrical Characteristics (VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 ºC) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 2.3 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL Enable Input High Current IENH VENx = VIH — 4 — µA Enable Input Low Current IENL VENx = VIL — 20 — µA DC Supply Current (All inputs 0 V or at supply) Si8430/35-A,-B,-C, VDD1 All inputs 0 DC — 6 8 mA Si8430/35-A,-B,-C, VDD2 All inputs 0 DC — 5 7 mA Si8430/35-A,-B,-C, VDD1 All inputs 1 DC — 11 13 mA Si8430/35-A,-B,-C, VDD2 All inputs 1 DC — 5 7 mA Si8431-A,-B,-C, VDD1 All inputs 0 DC — 7 10 mA Si8431-A,-B,-C, VDD2 All inputs 0 DC — 9 11 mA Si8431-A,-B,-C, VDD1 All inputs 1 DC — 11 13 mA Si8431-A,-B,-C, VDD2 All inputs 1 DC — 9 11 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8430/35-B,-C, VDD1 — 9 11 mA Si8430/35-B,-C, VDD2 — 8 10 mA Si8431-B,-C, VDD1 — 9 11 mA Si8431-B,-C, VDD2 — 10 13 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8430-C, VDD1 — 10 12 mA Si8430-C, VDD2 — 12 15 mA Si8431-C, VDD1 — 12 15 mA Si8431-C, VDD2 — 15 19 mA 10 Rev. 0.3 Si8430/31/35 Table 3. Electrical Characteristics (Continued) (VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 ºC) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 1 Mbps Minimum Pulse Width — — 1000 ns Timing Characteristics Si843x-A Propagation Delay tPHL, tPLH See Figure 2 — — 75 ns PWD See Figure 2 — — 30 ns tPSK(P-P) — — 50 ns tPSK — — 40 ns Maximum Data Rate 0 — 10 Mbps Minimum Pulse Width — — 100 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-B Propagation Delay tPHL, tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 7.5 ns tPSK(P-P) — — 25 ns tPSK — — 5 ns Maximum Data Rate 0 — 100 Mbps Minimum Pulse Width — — 10 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si843x-C Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew tPHL, tPLH See Figure 2 5 10 17 ns PWD See Figure 2 — — 7 ns tPSK(P-P) — — 12 ns tPSK — — 4 ns Rev. 0.3 11 Si8430/31/35 Table 3. Electrical Characteristics (Continued) (VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 ºC) Parameter Symbol Test Condition Min Typ Max Unit Output Rise Time tr CL = 15 pF See Figure 2 — 2 — ns Output Fall Time tf CL = 15 pF See Figure 2 — 2 — ns CTMI VI = VDD or 0 V 25 30 — kV/µs Enable to Data Valid ten1 See Figure 1 — 5 — ns Enable to Data Tri-State ten2 See Figure 1 — 5 — ns Start-up Time2 tSU — 3 — µs For All Models Common Mode Transient Immunity Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output. 12 Rev. 0.3 Si8430/31/35 Table 4. Absolute Maximum Ratings Parameter Symbol Min Typ Max Unit TSTG –65 — 150 ºC TA –40 — 125 ºC VDD1, VDD2 –0.5 — 6 V Input Voltage VI –0.5 — VDD + 0.5 V Output Voltage VO –0.5 — VDD + 0.5 V Output Current Drive Channel LO — — 10 mA Lead Solder Temperature (10s) — — 260 ºC Maximum Isolation Voltage — — 4000 VDC Storage Temperature Operating Temperature Supply Voltage Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Table 5. Recommended Operating Conditions Parameter Ambient Operating Temperature* Supply Voltage Symbol Test Condition Min Typ Max Unit TA 100 Mbps, 15 pF, 5 V –40 25 125 ºC 150 Mbps, 15 pF, 5 V 0 25 100 ºC VDD1 2.375 — 5.5 V VDD2 2.375 — 5.5 V *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Rev. 0.3 13 Si8430/31/35 Table 6. Regulatory Information CSA The Si84xx is certified under CSA Component Acceptance Notice. For more details, see File 232873. VDE The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL The Si84xx is certified under UL1577 component recognition program to provide basic insulation to 2500 VRMS (1 minute). It is production tested > 3000 VRMS for 1 second. For more details, see File E257455. Table 7. Insulation and Safety-related Specifications Parameter Symbol Test Condition Value Unit Minimum Air Gap (Clearance) L(IO1) 7.7 min mm Minimum External Tracking (Creepage) L(IO2) 8.1 mm 0.008 min mm >175 V 1012 Ω 1.4 pF 4.0 pF Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Resistance (Input-Output)1 RIO 1 Capacitance (Input-Output) Input Capacitance2 DIN IEC 60112/VDE 0303 Part 1 CIO f = 1 MHz CI Notes: 1. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 2. Measured from input pin to ground. 14 Rev. 0.3 Si8430/31/35 Table 8. IEC 60664-1 (VDE 0884 Part 2) Ratings Parameter Basic isolation group Installation Classification Test Conditions Specification Material Group IIIa Rated Mains Voltages < 150 VRMS I-IV Rated Mains Voltages < 300 VRMS I-III Rated Mains Voltages < 400 VRMS I-II Table 9. IEC 60747-5-2 Insulation Characteristics* Parameter Maximum Working Insulation Voltage Input to Output Test Voltage Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Symbol Test Condition VIORM VPR Characteristic Unit 560 V peak Method a After Environmental Tests Subgroup 1 (VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC) 896 Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 1050 After Input and/or Safety Test Subgroup 2/3 (VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC) 672 4000 VTR Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V V peak V peak 2 >109 RS Ω *Note: This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21. Table 10. IEC Safety Limiting Values Parameter Symbol Case Temperature TS Safety input, output, or supply current IS Test Condition θJA = 107 °C/W, VI = 5.5 V, TJ = 150 °C, TA = 25 °C Min Typ Max Unit — — 150 °C — — 210 mA *Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 3. Rev. 0.3 15 Si8430/31/35 Table 11. Thermal Characteristics Parameter Symbol Test Condition Min Typ Max Unit IC Junction-to-Case Thermal Resistance θJC Thermocouple located at center of package — 45 — ºC/W IC Junction-to-Air Thermal Resistance θJA — 107 — ºC/W Device Power Dissipation* PD — — 250 mW 200 175 162 110 125 130 Safety-Limiting Current (mA) *Note: The Si8430-C-IS is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. 150 2.75 V 125 5.5 V 100 3.6 V 75 50 25 0 0 50 100 150 200 Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 16 Rev. 0.3 Si8430/31/35 2. Typical Performance Characteristics 15 19 11 3.3V 9 2.5V 7 5V 17 5V Current (mA) Current (mA) 13 15 3.3V 13 11 2.5V 9 7 5 5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 Data Rate (Mbps) 50 60 70 80 90 100 Figure 6. Si8431 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation Figure 4. Si8430/35 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation 25 19 5V 20 5V 17 Current (mA) Current (mA) 40 Data Rate (Mbps) 3.3V 15 10 2.5V 5 3.3V 15 13 2.5V 11 9 7 0 5 0 10 20 30 40 50 60 70 80 90 100 0 Data Rate (Mbps) Figure 5. Si8430/35 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) Figure 7. Si8431 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) Rev. 0.3 17 Si8430/31/35 10 Delay (ns) 9 8 Falling Edge 7 6 Rising Edge 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 8. Propagation Delay vs. Temperature 5 V Operation 10 Delay (ns) 9 Rising Edge 8 Falling Edge 7 6 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 9. Propagation Delay vs. Temperature 3.3 V Operation 15 Delay (ns) 13 Rising Edge 11 Falling Edge 9 7 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 10. Propagation Delay vs. Temperature 2.5 V Operation 18 Rev. 0.3 Si8430/31/35 3. Application Information 3.1. Theory of Operation The operation of an Si8430 channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si8430 channel is shown in Figure 11. A channel consists of an RF transmitter and receiver separated by a transformer. Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying and applies the resulting waveform to the primary of the transformer. The receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. TRANSMITTER RF OSCILLATOR A RECEIVER MODULATOR DEMODULATOR B Figure 11. Simplified Channel Diagram 3.2. Eye Diagram Figure 12 illustrates an eye-diagram taken on an Si8430. The test used an Anritsu (MP1763C) Pulse Pattern Generator for the data source. The output of the generator's clock and data from an Si8430 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that very low pulse width distortion and very little jitter were exhibited. Figure 12. Eye Diagram Rev. 0.3 19 Si8430/31/35 4. Layout Recommendations Dielectric isolation is a set of specifications produced by the safety regulatory agencies from around the world that describes the physical construction of electrical equipment that derives power from a high-voltage power system such as 100–240 VAC systems or industrial power systems. The dielectric test (or HIPOT test) given in the safety specifications places a very high voltage between the input power pins of a product and the user circuits and the user touchable surfaces of the product. For the IEC relating to products deriving their power from the 220–240 V power grids, the test voltage is 2500 VAC (or 3750 VDC—the peak equivalent voltage). There are two terms described in the safety specifications: Creepage—the distance along the insulating surface an arc may travel. Clearance—the distance through the shortest path through air that an arc may travel. Figure 13 illustrates the accepted method of providing the proper creepage distance along the surface. For a 220–240 V application, this distance is 8 mm and the wide body SOIC package must be used. There must be no copper traces within this 8 mm exclusion area, and the surface should have a conformal coating such as solder resist. The digital isolator chip must straddle this exclusion area. Figure 13. Creepage Distance 4.1. Supply Bypass The Si843x requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package. 20 Rev. 0.3 Si8430/31/35 4.2. Input and Output Characteristics The Si843x inputs and outputs are standard CMOS drivers/receivers. The Si844x inputs and outputs are standard CMOS drivers/receivers. Table 12 details powered and unpowered operation of the Si84xx. Table 12. Si84xx Operation Table VI Input1,2 EN Input1,2,3,4 VDDI State1,5,6 VDDO State1,5,6 VO Output1,2 H H or NC P P H L H or NC P P L X L P P Hi-Z X H or NC UP P L X L UP P Hi-Z X X P UP L Comments Enabled, normal operation. Disabled Upon the transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. Disabled Upon the transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs, if EN is in either the H or NC state. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the enable control input located on the same output side. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si84xx is operating in noisy environments. 4. No Connect (NC) replaces EN1 on Si8430/35. No Connect replaces EN2 on the Si8435. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND. 5. "Powered" state (P) is defined as 2.375 V < VDD < 5.5 V. 6. "Unpowered" state (UP) is defined as VDD = 0 V. Rev. 0.3 21 Si8430/31/35 4.3. Enable (EN1, EN2) Inputs Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic operation is summarized for each isolator product in Table 13. These inputs are internally pulled-up to local VDD by a 9 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si84xx is operating in a noisy environment. Table 13. Enable Input Truth Table P/N EN1* EN2* Si8430 — H Outputs B1, B2, B3 are enabled. — L Outputs B1, B2, B3 are disabled and in high impedance state. H X Output A3 enabled. L X Output A3 disabled and in high impedance state. X H Outputs B1, B2 are enabled. X L Outputs B1, B2 are disabled and in high impedance state. — — Outputs B1, B2, B3 are enabled. Si8431 Si8435 Operation *Note: X = not applicable; H = Logic High; L = Logic Low. 22 Rev. 0.3 Si8430/31/35 4.4. RF Radiated Emissions The Si8430 family uses a RF carrier frequency of approximately 2.1 GHz. This will result in a small amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but due to a small amount of RF energy driving the isolated ground planes which can act as a dipole antenna. The unshielded Si8430 evaluation board passes FCC requirements. Table 14 shows measured emissions compared to FCC requirements. Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less efficient antenna. Table 14. Radiated Emissions Frequency (GHz) Measured (dBµV/m) FCC Spec (dBµV/m) Compared to Spec (dB) 2.094 70.0 74.0 –4.0 2.168 68.3 74.0 –5.7 4.210 61.9 74.0 –12.1 4.337 60.7 74.0 –13.3 6.315 58.3 74.0 –15.7 6.505 60.7 74.0 –13.3 8.672 45.6 74.0 –28.4 Rev. 0.3 23 Si8430/31/35 4.5. RF Immunity and Common Mode Transient Immunity The Si8430 family has very high common mode transient immunity while transmitting data. This is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements show no failures up to 30 kV/µs. During a high surge event the output may glitch low for up to 20–30 ns, but the output corrects immediately after the surge event. The Si843x family passes the industrial requirements of CISPR24 for RF immunity of 3 V/m using an unshielded evaluation board. As shown in Figure 14, the isolated ground planes form a parasitic dipole antenna, while Figure 15 shows the RMS common mode voltage versus frequency above which the Si843x becomes susceptible to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage below the envelope specified in Figure 15. The PCB should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded. GND1 Isolator GND2 Dipole Antenna Figure 14. Dipole Antenna RMS Voltage (V) 5 4 3 2 1 0 500 1000 1500 Frequency (MHz) Figure 15. RMS Common Mode Voltage vs. Frequency 24 Rev. 0.3 2000 Si8430/31/35 5. Pin Descriptions VDD1 GND1 A1 A2 A3 NC EN1/NC GND1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VDD2 GND2 B1 B2 B3 NC EN2/NC GND2 Top View Wide Body SOIC Name SOIC-16 Pin# Type Description VDD1 1 Supply Side 1 power supply. GND1 2 Ground Side 1 ground. A1 3 Digital Input Side 1 digital input. A2 4 Digital Input Side 1 digital input. A3 5 Digital I/O NC 6 NA EN1/NC* 7 Digital Input GND1 8 Ground Side 1 ground. GND2 9 Ground Side 2 ground. EN2/NC* 10 Digital Input NC 11 NA B3 12 Digital I/O B2 13 Digital Output Side 2 digital output. B1 14 Digital Output Side 2 digital output. GND2 15 Ground Side 2 ground. VDD2 16 Supply Side 2 power supply. Side 1 digital input or output. No Connect. Side 1 active high enable. NC on Si8430/35 Side 2 active high enable. NC on Si8435. No Connect. Side 2 digital input or output. *Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND. Rev. 0.3 25 Si8430/31/35 6. Ordering Guide Ordering Part Number Number of Inputs Number of Inputs VDD1 Side VDD2 Side Maximum Data Rate Temperature Package Type Si8430-A-IS 3 0 1 –40 to 125 °C SOIC-16 Si8430-B-IS 3 0 10 –40 to 125 °C SOIC-16 Si8430-C-IS 3 0 150 –40 to 125 °C SOIC-16 Si8431-A-IS 2 1 1 –40 to 125 °C SOIC-16 Si8431-B-IS 2 1 10 –40 to 125 °C SOIC-16 Si8431-C-IS 2 1 150 –40 to 125 °C SOIC-16 Si8435-B-IS 3 0 10 –40 to 125 °C SOIC-16 Note: All packages are Pb-free and RoHS Compliant. Moisture sensitivity level is MSL2 with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications, and peak solder temperature. 26 Rev. 0.3 Si8430/31/35 7. Package Outline: Wide Body SOIC Figure 16 illustrates the package details for the Quad-Channel Digital Isolator. Table 14 lists the values for the dimensions shown in the illustration. Figure 16. 16-Pin Wide Body SOIC Table 14. Package Diagram Dimensions Millimeters Symbol Min Max A — 2.65 A1 0.1 0.3 D 10.3 BSC E 10.3 BSC E1 7.5 BSC b 0.31 0.51 c 0.20 0.33 e 1.27 BSC h 0.25 0.75 L 0.4 1.27 θ 0° 7° Rev. 0.3 27 Si8430/31/35 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.11 Updated Table 7, “Regulatory Information,” on page 14. Minor typographical edits. Revision 0.11 to Revision 0.2 Updated Supply Current specifications in Table 1, “Electrical Characteristics,” on page 4, Table 2, “Electrical Characteristics,” on page 7, and Table 3, “Electrical Characteristics,” on page 10. Updated performance plots in Figures 4, 5, 6, and 7. Added NC note (Note 3) to Table 10, “Si84xx Truth Table (Positive Logic),” on page 16. Added NC note (*) to "5. Pin Descriptions" on page 25. Revision 0.2 to Revision 0.3 Updated Notes to Tables 1, 2, & 3. Updated Figure 2. Updated Tables 6–11 to clarify specifications, test limits, & device characteristics. 28 Rev. 0.3 Si8430/31/35 NOTES: Rev. 0.3 29 Si8430/31/35 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 30 Rev. 0.3