FDMS9620S tm Dual N-Channel PowerTrench® MOSFET Q1: 30V, 16A, 21.5mΩ Q2: 30V, 18A, 13mΩ Features Q1: N-Channel General Description Max rDS(on) = 21.5mΩ at VGS = 10V, ID = 7.5A This device includes two specialized MOSFETs in a unique dual Max rDS(on) = 29.5mΩ at VGS = 4.5V, ID = 6.5A Power 56 package. It is designed to provide an optimal Q2: N-Channel Synchronous Buck power stage in terms of efficiency and PCB Max rDS(on) = 13mΩ at VGS = 10V, ID = 10A utilization. Max rDS(on) = 17mΩ at VGS = 4.5V, ID = 8.5A complemented by a Low Conduction Loss "Low Side" SyncFET. Low Qg high side MOSFET Applications Low rDS(on) low side MOSFET Synchronous Buck Converter for: Thermally efficient dual Power 56 package Notebook System Power Pinout optimized for simple PCB design The low switching loss "High Side" MOSFET is General Purpose Point of Load RoHS Compliant G1 D1 D1 D1 D1 S2 5 4 D1 S2 6 3 D1 S2 7 2 D1 G2 8 1 G1 S1/D2 G2 S2 S2 S2 Power 56 MOSFET Maximum Ratings TA = 25°C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter Q1 30 Q2 30 Units V VGS Gate to Source Voltage ±20 ±20 V Drain Current 16 18 21 44 7.5 10 -Continuous (Package limited) TC = 25°C ID -Continuous (Silicon limited) TC = 25°C -Continuous TA = 25°C (Note 1a) TA = 25°C (Note 1a) 2.5 TA = 25°C (Note 1b) 1 -Pulsed 60 Power Dissipation for Single Operation PD TJ, TSTG Operating and Storage Junction Temperature Range A 60 W °C -55 to +150 Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient (Note 1a) 8.2 50 3.1 RθJA Thermal Resistance, Junction to Ambient (Note 1b) 120 °C/W Package Marking and Ordering Information Device Marking FDMS9620S Device FDMS9620S ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 Package Power 56 1 Reel Size 13” Tape Width 12mm Quantity 3000 units www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench® MOSFET July 2007 Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V ID = 1mA, VGS = 0V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250μA, referenced to 25°C ID = 1mA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24V, VGS = 0V Q1 Q2 1 500 μA IGSS Gate to Source Leakage Current VGS = ±20V, VDS= 0V Q1 Q2 ±100 ±100 nA 3 3 V V 23 23 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250μA VGS = VDS, ID = 1mA Q1 Q2 ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250μA, referenced to 25°C ID = 1mA, referenced to 25°C Q1 Q2 -4 -4 VGS = 10V, ID = 7.5A VGS = 4.5V, ID = 6.5A VGS = 10V, ID = 7.5A , TJ = 125°C Q1 18 23 25 21.5 29.5 32 VGS = 10V, ID = 10A VGS = 4.5V, ID = 8.5A VGS = 10V, ID = 10A , TJ = 125°C Q2 9 13 14 13 17 22 VDD = 10V, ID = 7.5A VDD = 10V, ID = 10A Q1 Q2 25 27 Q1 Q2 500 700 665 935 pF Q1 Q2 100 500 135 665 pF Q1 Q2 65 100 100 150 pF Q1 Q2 0.9 1.8 rDS(on) gFS Drain to Source On Resistance Forward Transconductance 1 1 1.6 1.6 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 15V, VGS = 0V, f = 1MHZ f = 1MHz Ω Switching Characteristics td(on) Turn-On Delay Time Q1 Q2 11 15 20 27 ns tr Rise Time Q1 Q2 7 13 14 24 ns Q1 Q2 23 27 37 44 ns Q1 Q2 2.3 7 10 14 ns Q1 Q2 10 18 14 25 nC Q1 Q2 1.7 2.8 nC Q1 Q2 2.0 3.6 nC td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 VDD = 15V, ID = 1A, VGS = 10V, RGEN = 6Ω Q1 VDD = 15V, VGS = 10V ,ID = 7.5A Q2 VDD = 15V, VGS = 10V ,ID = 10A 2 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25°C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units 2.1 3.5 A 1.2 1.0 V Drain-Source Diode Characteristics IS Maximum Continuous Drain-Source Diode Forward Current VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0V, IS = 2.1A VGS = 0V, IS = 3.5A Q1 IF = 7.5A, di/dt = 100A/μs Q2 IF = 10A, di/dt = 300A/μs Q1 Q2 (Note 2) (Note 2) Q1 Q2 0.7 0.5 Q1 Q2 13 14 ns Q1 Q2 4 9 nC Notes: 1: RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 120°C/W when mounted on a minimum pad of 2 oz copper a.50°C/W when mounted on a 1 in2 pad of 2 oz copper 2: Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%. ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 3 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25°C unless otherwise noted 60 VGS = 6V 50 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.8 VGS = 10V VGS = 4.5V 40 VGS = 4V 30 VGS = 3.5V 20 PULSE DURATION = 300μs DUTY CYCLE = 2.0%MAX 10 0 0 1 2 3 PULSE DURATION = 300μs DUTY CYCLE = 2.0%MAX 2.6 2.4 2.2 VGS =3.5V VGS = 4V 2.0 VGS = 6V 1.6 1.4 1.2 1.0 VGS = 10V 0.8 4 0 10 20 VDS, DRAIN TO SOURCE VOLTAGE (V) rDS(on), DRAIN TO 1.3 1.2 1.1 1.0 0.9 0.8 0 25 50 75 100 125 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.4 40 TJ = 125oC 30 20 TJ = 25oC 2 6 8 10 Figure 4. On-Resistance vs Gate to Source Voltage 60 IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 4 VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 300μs DUTY CYCLE = 2.0%MAX VDD = 5V 20 TJ =125oC TJ = 25oC TJ = -55oC 0 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) VGS = 0V 10 TJ = 125oC 1 TJ = 25oC 0.1 0.01 TJ = -55oC 1E-3 0.2 5 0.4 0.6 0.8 1.0 1.2 1.4 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 PULSE DURATION = 300μs DUTY CYCLE = 2.0%MAX 10 150 40 1 60 50 Figure 3. Normalized On Resistance vs Junction Temperature 10 ID = 3.8A 60 TJ, JUNCTION TEMPERATURE (oC) 30 50 70 ID = 7.5A VGS =10V -25 40 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 0.7 -50 30 ID, DRAIN CURRENT(A) Figure 1. On Region Characteristics 1.5 VGS = 4.5V 1.8 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted 1000 ID = 7.5A VDD =10V 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE(V) 10 VDD = 15V 6 VDD = 20V 4 Ciss Coss 100 2 f = 1MHz VGS = 0V 0 0 2 4 6 8 10 30 0.1 12 1 Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 100 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 100 10 0.1 1ms SINGLE PULSE TJ = MAX RATE 10ms RθJA = 120oC 100ms TA = 25oC 1s THIS AREA IS LIMITED BY rDS(ON) 0.01 0.1 10s DC 1 30 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) 1 Crss 10 100 VGS = 10V 10 SINGLE PULSE o RθJA = 120 C/W 1 o TA= 25 C 0.5 -3 10 -2 -1 10 10 0 1 10 10 2 10 3 10 t, PULSE WIDTH (s) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 9. Forward Bias Safe Operating Area Figure 10. Single Pulse Maximum Power Dissipation 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 120 C/W 0.01 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 t, RECTANGULAR PULSE DURATION (s) Figure 11. Transient Thermal Response Curve ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 5 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted 60 ID, DRAIN CURRENT (A) VGS = 4V VGS = 4.5V 50 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.8 VGS = 10V VGS = 6V 40 VGS = 3.5V 30 20 10 PULSE DURATION = 300μs DUTY CYCLE = 2.0%MAX 0 0.0 0.5 1.0 1.5 2.0 2.5 2.6 PULSE DURATION = 300μs DUTY CYCLE = 2.0%MAX VGS =3.5V 2.4 2.2 VGS = 4V 2.0 1.6 VGS = 6V 1.4 1.2 1.0 VGS = 10V 0.8 0 10 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 40 50 60 Figure 13. Normalized on-Resistance vs Drain Current and Gate Voltage 1.8 60 ID = 10A VGS =10V rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.6 -50 -25 0 25 50 75 100 125 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 30 ID, DRAIN CURRENT(A) Figure 12. On-Region Characteristics PULSE DURATION = 300μs DUTY CYCLE = 2.0%MAX ID = 5A 50 40 30 TJ = 125oC 20 10 TJ = 25oC 0 150 2 TJ, JUNCTION TEMPERATURE (oC) 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 15. On-Resistance vs Gate to Source Voltage Figure 14. Normalized On-Resistance vs Junction Temperature 10 60 PULSE DURATION = 300μs DUTY CYCLE = 2.0%MAX 50 IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = 4.5V 1.8 VDD = 5V 40 30 TJ =125oC 20 TJ = 25oC 10 TJ = -55oC 2 3 4 5 TJ = 125oC 0.1 TJ = 25oC 0.01 TJ = -55oC 0.2 0.4 0.6 0.8 VSD, BODY DIODE FORWARD VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) Figure 16. Transfer Characteristics ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 1 0.001 0.0 0 1 VGS = 0V Figure 17. Source to Drain Diode Forward Voltage vs Source Current 6 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q2 SyncFET) 2000 ID = 10A VDD =10V VDD = 15V 6 4 Ciss 1000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE(V) 10 VDD = 20V 2 Coss 100 50 0.1 0 0 4 8 12 16 20 Crss 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) Figure 19. Capacitance vs Drain to Source Voltage Figure 18. Gate Charge Characteristics ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 f = 1MHz VGS = 0V 7 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench® MOSFET Typical Characteristics FDMS9620S Dual N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 8 www.fairchildsemi.com TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I30