P4C1041L LOW POWER 256K x 16 (4 MEG) STATIC CMOS RAM FEATURES Fast Access Time - 55 ns Advanced CMOS Technology Low Power Operation Fast tOE Single 5V±10% Power Supply Automatic Power Down when deselected 2.0V Data Retention Packages Easy Memory Expansion Using CE and OE Inputs – 44-Pin 400 mil TSOP II Fully TTL Compatible Inputs and Outputs DESCRIPTION The P4C1041L is a 262,144 words by 16 bits high-speed CMOS static RAM. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5.0V ± 10% tolerance power supply. Access times of 55 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1041L device provides asynchronous operation with matching access and cycle times. Memory locations Functional Block Diagram are specified on address pins A0 to A17. Reading is accomplished by device selection (CE) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. The P4C1041L comes in a 44-Pin 400 mil TSOP II package. Pin Configuration TSOP II Document # SRAM142 REV OR Revised March 2011 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Maximum Ratings(1) Sym RECOMMENDED OPERATING CONDITIONS Parameter Value Unit VCC Power Supply Pin with Respect to GND -0.5 to +7.0 V VTERM Terminal Voltage with Respect to GND -0.5 to VCC + 0.5 V TA Operating Temperature -40 to +85 °C TBIAS Temperature Under Bias -40 to +85 °C TSTG Storage Temperature -65 to +150 °C IOUT DC Output Current 20 mA Grade(2) Commercial Industrial Ambient Temp GND VCC 0°C to 70°C 0V 5.0V ± 10% -40°C to +85°C 0V 5.0V ± 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Sym Parameter CIN Input Capacitance COUT Output Capacitance Conditions Typ Unit VIN=0V 6 pF VOUT=0V 8 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter Test Conditions Min Max Unit VIH Input High Voltage 2.4 VCC + 0.3 V VIL Input Low Voltage -0.2 0.6 V VOL Output Low Voltage (TTL Load) IOL = +2 mA, VCC = Min 0.4 V VOH Output High Voltage (TTL Load) IOH = -1 mA, VCC = Min 2.4 Input Leakage Current VCC = Max, VIN = GND to VCC -1 +1 µA -1 +1 µA — 50 µA 60 mA 10 mA ILI V VCC = Max, ILO Output Leakage Current CE = VIH, VOUT = GND to VCC CE ≥ VCC - 0.2V, ISB1 Standby Power Supply Current (CMOS Input Levels) VCC = Max, f = 0, Outputs Open, VIN ≥ VCC - 0.2V or VIN ≤ 0.2V Cycle Time = Min, ICC Dynamic Operating Current CE = VIL, II/O = 0 mA, Other pins at VIH or VIL Cycle Time = 1 µs, ICC1 Dynamic Operating Current (CMOS) CE ≤ 0.2V, II/O = 0 mA, Other pins at 0.2V or VCC - 0.2V Document # SRAM142 REV OR Page 2 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym Parameter -55 Min Max tRC Read Cycle Time tAA Address Access Time 55 ns tAC Chip Enable Access Time 55 ns tOE Output Enable Access Time 30 ns tLZ Chip Enable to Output in Low-Z 10 ns tOLZ Output Enable to Output in Low-Z 5 ns tHZ Chip Disable to Output in High-Z 20 ns tOHZ Output Disable to Output in High-Z 20 ns tOH Output Hold from Address Change tBE Byte Access Time 55 ns tHZBE Byte Disable to High-Z Output 25 ns tLZBE Byte Enable to Low-Z Output Document # SRAM142 REV OR 55 Unit ns 10 10 ns ns Page 3 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM TIMING WAVEFORM OF READ CYCLE NO. 1 TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)(5,6) Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3.Transient inputs with VIL and IIL not more negative than –2.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. Document # SRAM142 REV OR 4.This parameter is sampled and not 100% tested. 5.WE is HIGH for READ cycle. 6.CE is LOW and OE is LOW for READ cycle. 7.ADDRESS must be valid prior to, or coincident with CE transition LOW. 8.Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9.Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -55 Sym Parameter tWC Write Cycle Time 55 ns tAW Address Valid to End of Write 50 ns tCW Chip Enable to End of Write 50 ns tAS Address Setup Time 0 ns tWP Write Pulse Width 45 ns tWR Write Recovery Time 0 ns tDW Data to Write Time Overlap 25 ns tDH Data Hold from End of Write Time 0 ns tOW Output Active from End of Write 5 ns tWZ Write to Output in High-Z tBW Byte Enable to End of Write Min Max 20 45 Unit ns ns TIMING WAVEFORM OF WRITE Cycle No. 1 (CE Controlled) Document # SRAM142 REV OR Page 5 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Timing Waveform of Write Cycle No. 2 (BLE OR BHE Controlled) Timing Waveform of Write Cycle No. 3 (WE Controlled, OE LOW) Document # SRAM142 REV OR Page 6 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent Note: Because of the ultra-high speed of the P4C1041L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589Ω resistor must be used in series with DOUT to match 639Ω (Thevenin Resistance). * including scope and test fixture. TRUTH TABLE Mode CE OE WE BLE BHE I/O0 - I/O7 I/O8 - I/O15 Power Powerdown H X X X X High Z High Z Standby Read All Bits L L H L L DOUT DOUT Active Read Lower Bits Only L L H L H DOUT High Z Active Read Upper Bits Only L L H H L High Z DOUT Active Write All Bits L X L L L DIN DIN Active Write Lower Bits Only L X L L H DIN High Z Active Write Upper Bits Only L X L H L High Z DIN Active Selected, Outputs Disabled L H H X X High Z High Z Active Document # SRAM142 REV OR Page 7 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM DATA RETENTION Sym Parameter Test Conditions Min Max Unit 2.0 5.5 V 30 µA VDR VCC for Data Retention CE ≥ VCC - 0.2V, VIN ≥ VCC - 0.2V or VIN ≤ 0.2V ICCDR Data Retention Current VDR=2.0V tCDR Chip Deselect to Data Retention Time tR Operating Recovery Time See Retention Waveform 0 ns tRC ns LOW VCC DATA RETENTION WAVEFORM Document # SRAM142 REV OR Page 8 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM ORDERING INFORMATION Document # SRAM142 REV OR Page 9 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM TSOP II SMALL OUTLINE PACKAGE T2 Pkg # # Pins 44 Symbol Min Max A 0.039 0.047 A2 0.033 0.045 b 0.012 0.017 D 0.717 0.733 e 0.0315 BSC E 0.453 0.473 E1 0.392 0.408 Document # SRAM142 REV OR Page 10 P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM REVISIONS DOCUMENT NUMBER SRAM 142 DOCUMENT TITLE P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM REV ISSUE DATE ORIGINATOR OR Mar-2011 JDB Document # SRAM142 REV OR DESCRIPTION OF CHANGE New Data Sheet Page 11