TOSHIBA TMP91CW28

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91CW28
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
TMP91CW28
Low-Voltage, Low-Power
CMOS 16-Bit Microcontroller
TMP91CW28FG
1.
Outline
The TMP91CW28 is a high-speed, high-performance 16-bit microcontroller suitable for
low-voltage, low-power applications.
The TMP91CW28FG comes in a 100-pin mini flat package. Features of the TMP91CW28FG
include the following:
(1) High-speed 16-bit CPU (900/L1 CPU)
•
Instruction set is upwardly assembly code compatible with the TLCS-90
•
16-Mbyte linear address space
•
Architecture based on general-purpose registers and register banks
•
16-bit multiply/divide instructions and bit transfer/arithmetic instructions
•
4-channel micro DMA (1.6 μs/2 bytes at 10 MHz)
(2) Minimum instruction execution time: 400 ns (at 10 MHz)
(3) 8-Kbyte on-chip RAM
128-Kbyte on-chip ROM
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(4) External memory expansion
•
16-Mbyte off-chip address space for code and data
•
External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports
(5) 4-channel 8-bit timer
(6) 2-channel 16-bit timer
(7) 1-channel general-purpose serial interface
•
Both UART and synchronous transfer modes are supported
(8) 2-channel serial bus interface
Either I2C bus mode or clock-synchronous mode can be selected
(9) 8-channel 10-bit AD converter (with internal sample/hold)
(10) Watchdog timer
(11) Key wakeup interrupt with 8-bit inputs
(12) WAKE output pin
(13) BCD adder/subtracter
(14) Program patch logic
•
6 banks of registers
(15) 4-channel chip select/wait controller
(16) 48 interrupt sources
•
9 CPU interrupts: Triggered by software interrupt instruction or upon the execution of an
undefined instruction
•
21 internal interrupts: 7 priority levels
•
18 external interrupts: 7 priority levels (16 interrupts supporting selection of triggering
edge)
(17) 80-pin input/output ports
(18) Standby modes
•
Three HALT modes: Programmable IDLE2, IDLE1, STOP
(19) Clock control
•
Clock gear: Changes the frequency of high-frequency clock within the range from fc to
fc/16
(20) Operating voltage range: 1.8 to 2.6 V (fc max = 10 MHz)
(21) Package: P-LQFP100-1414-0.50F
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TMP91CW28
(P60) SCK0
(P64) SCOUT
(P65)
(P66)
(P70) TA0IN
8-bit timer
(TMRA0)
(P71) TA1OUT
8-bit timer
(TMRA1)
CPU (TLCS-900/L1)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
Clock gear
W A
B C
D E
H L
IX
IY
IZ
SP
32 bits
F
SR
PC
X1
X2
EMU0
EMU1
RESET
AM0
AM1
ALE
AD0 (P00)
AD1 (P01)
AD2 (P02)
Port 0
Port 6
(P62) SI0/SCL0
(P63) INT0
High-frequency
oscillator
2
I C/SIO
(Channel 0)
(P61) SO0/SDA0
AD3 (P03)
AD4 (P04)
Port 7
AD5 (P05)
(P72) TA3OUT
8-bit timer
(TMRA2)
8-bit timer
(TMRA3)
AD6 (P06)
Watchdog timer
(WDT)
AD7 (P07)
BCD
calculator
(BCDC)
AD8/A8 (P10)
AD9/A9 (P11)
(P73)
(P80) TB0IN0/INT5
16-bit timer
(TMRB0)
(P81) TB0IN1/INT6
(P84) TB1IN0/INT7
(P85) TB1IN1/INT8
AD15/A15 (P17)
A0/A16 (P20)
A1/A17 (P21)
A2/A18 (P22)
16-bit timer
(TMRB1)
(P86) TB1OUT0
AD12/A12 (P14)
AD14/A14 (P16)
Port 2
(P83) TB0OUT1
AD11/A11 (P13)
AD13/A13 (P15)
Port 8
(P82) TB0OUT0
8-Kbyte RAM
Program
patch logic
6 banks
Port 1
AD10/A10 (P12)
(P74)
(P75)
128-Kbyte ROM
A3/A19 (P23)
A4/A20 (P24)
A5/A21 (P25)
(P87) TB1OUT1
A6/A22 (P26)
(P90) SCK1
(P92) SI1/SCL1
SIO/UART
WAIT (P33)
BUSRQ (P34)
BUSAK (P35)
R/ W (P36)
Standby
controller
(KWI)
Interrupt
controller
(PA1) INT2
CS/WAIT
controller
Port A
(PA2) INT3
(P37)
CS0 (P40)
Port 4
(PA0) INT1
(PA4)
Port 3
HWR (P32)
(P96)
(PA3) INT4
RD (P30)
WR (P31)
Port 9
(P93) TXD
(P94) RXD
(P95) SCLK/ CTS
A7/A23 (P27)
2
I C/SIO
(Channel 1)
(P91) SO1/SDA1
CS1 (P41)
CS2 (P42)
CS3 (P43)
AN0/KWI0 (P50)
AN1/KWI1 (P51)
(PA6)
AN2/KWI2 (P52)
AN3/ ADTRG /KWI3 (P53)
(PA7)
NMI
10-bit 8-ch
AD
converter
WAKE
Port 5
(PA5)
AN4/KWI4 (P54)
AN5/KWI5 (P55)
AN6/KWI6 (P56)
AN7/KWI7 (P57)
DVCC [3]
DVSS [3]
AVCC
AVSS
VREFL
VREFH
( ): Initial pin function after reset
Figure 1.1 TMP91CW28 Block Diagram
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TMP91CW28
2.
Signal Descriptions
This section contains pin assignments for the TMP91CW28 as well as brief descriptions of the
TMP91CW28 input and output signals.
2.1
Pin Assignment
The following illustrates the TMP91CW28FG pin assignment.
88 P65
DVCC
89
87 P64/SCOUT
P66
90
86 P63/INT0
DVSS
91
85 P62/SI0/SCL0
P50/AN0/KWI0
92
84 P61/SO0/SDA0
P51/AN1/KWI1
93
83 P60/SCK0
P52/AN2/KWI2
94
82 P43/ CS3
P53/AN3/ ADTRG /KWI3
95
81 P42/ CS2
P54/AN4/KWI4
96
80 P41/ CS1
P55/AN5/KWI5
97
79 P40/ CS0
P56/AN6/KWI6
98
78 P37
P57/AN7/KWI7
99
77 P36/R/ W
VREFH
100
76 P35/ BUSAK
VREFL
1
75 P34/ BUSRQ
AVSS
2
74 P33/ WAIT
AVCC
3
73 P32/ HWR
P70/TA0IN
4
72 P31/ WR
P71/TA1OUT
5
71 P30/ RD
P72/TA3OUT
6
70 P27/A7/A23
P73
7
69 P26/A6/A22
P74
8
68 P25/A5/A21
P75
9
67 P24/A4/A20
P80/TB0IN0/INT5
10
66 P23/A3/A19
P81/TB0IN1/INT6
11
P82/TB0OUT0
12
P83/TB0OUT1
13
P84/TB1IN0/INT7
14
P85/TB1IN1/INT8
15
61 P21/A1/A17
P86/TB1OUT0
16
60 P20/A0/A16
P87/TB1OUT1
17
59 P17/AD15/A15
P90/SCK1
18
58 P16/AD14/A14
P91/SO1/SDA1
19
57 P15/AD13/A13
P92/SI1/SCL1
20
56 P14/AD12/A12
P93/TXD
21
55 P13/AD11/A11
P94/RXD
22
54 P12/AD10/A10
P95/SCLK/ CTS
23
53 P11/AD9/A9
AM0
24
52 P10/AD8/A8
DVCC
25
51 P07/AD7
X2
26
50 P06/AD6
DVSS
27
49 P05/AD5
X1
28
48 P04/AD4
AM1
29
47 P03/AD3
30
46 P02/AD2
31
45 P01/AD1
WAKE
32
44 P00/AD0
EMU0
33
43 ALE
EMU1
34
42 PA7
PA0/INT1
35
41 PA6
PA1/INT2
36
40 PA5
PA2/INT3
37
39 PA4
RESET
P96
TMP91CW28FG
Top view
LQFP100
65 P22/A2/A18
64 DVCC
63 NMI
62 DVSS
38 PA3/INT4
Figure 2.1.1 100-Pin LQFP Pin Assignment
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2.2
Pin Usage Information
Table 2.2.1 to 2.2.4 list the input and output pins of the TMP91CW28, including alternate pin
names and functions for multi-function pins.
Table 2.2.1 Pin Names and Functions (1/4)
Pin Name
P00 to P07
Number
of Pins
I/O
8
I/O
AD0 to AD7
P10 to P17
8
AD8 to AD15
A8 to A15
P20 to P27
Port 0: Individually programmable as input or output
I/O
Address/data (Lower): Bits 0 to 7 of the address/data bus
I/O
Port 1: Individually programmable as input or output
I/O
Address/data (Upper): Bits 8 to 15 of the address/data bus
Output
8
Functions
I/O
Address: Bits 8 to 15 of the address bus
Port 2: Individually programmable as input or output
A0 to A7
Output
A16 to A23
Output
Address: Bits 16 to 23 of the address bus
Output
Port 30: Output only
Output
Read strobe: Asserted during a read operation from an external memory
device
P30
1
RD
Address: Bits 0 to 7 of the address bus
Also asserted during a read from internal memory if P3.P30 = 0 and
P3FC.P30F = 1
P31
1
WR
P32
1
HWR
P33
1
1
1
I/O
Port 32: Programmable as input or output (with internal pull-up resistor)
Output
Higher write strobe: Asserted during a write operation on AD8 to AD15
I/O
Port 33: Programmable as input or output (with internal pull-up resistor)
I/O
I/O
Output
BUSAK
P36
Write strobe: Asserted during a write operation on AD0 to AD7
Input
BUSRQ
P35
Port 31: Output only
Output
Input
WAIT
P34
Output
1
I/O
Output
R/ W
Wait: Causes the CPU to suspend external bus activity ((1 + N) wait states)
Port 34: Programmable as input or output (with internal pull-up resistor)
Bus request: Asserted to request that the AD0 to AD15, A0 to A23, RD ,
WR , HWR , R/ W , and CS0 to CS3 pins be placed in high-impedance state
(for external DMAC)
Port 35: Programmable as input or output (with internal pull-up resistor)
Bus acknowledge: Indicates that the AD0 to AD15, A0 to A23, RD , WR ,
HWR , R/ W , and CS0 to CS3 pins have been placed in high-impedance
state in response to BUSRQ (for external DMAC)
Port 36: Programmable as input or output (with internal pull-up resistor)
Read/write: Indicates the direction of data transfer on the bus: 1 = Read or
dummy cycle, 0 = Write cycle
P37
1
I/O
Port 37: Programmable as input or output (with internal pull-up resistor)
P40
1
I/O
Port 40: Programmable as input or output (with internal pull-up resistor)
Output
Chip select 0: Asserted low to enable external devices at programmed
addresses
CS0
Note: An external DMA controller configured with the BUSRQ and BUSAK pins cannot access the
on-chip memory and peripheral functions of the TMP91CW28.
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TMP91CW28
Table 2.2.2 Pin Names and Functions (2/4)
Pin Name
P41
Number
of Pins
1
CS1
P42
1
CS2
P43
1
CS3
P50 to P57
Functions
I/O
Port 41: Programmable as input or output (with internal pull-up resistor)
Output
Chip select 1: Asserted low to enable external devices at programmed
addresses
I/O
Port 42: Programmable as input or output (with internal pull-up resistor)
Output
Chip select 2: Asserted low to enable external devices at programmed
addresses
I/O
Port 43: Programmable as input or output (with internal pull-up resistor)
Output
Chip select 3: Asserted low to enable external devices at programmed
addresses
Input
Port 5: Input only
AN0 to AN7
Input
Analog input: Input to the on-chip AD converter
ADTRG
Input
AD trigger: Starts an AD conversion (multiplexed with P53)
KWI0 to KWI7
Input
P60
8
I/O
I/O
Port 60: Programmable as input or output
I/O
Clock input/output pin when serial bus interface 0 is in SIO mode
1
I/O
Port 61: Programmable as input or output (with internal pull-up resistor)
SCK0
P61
Key wakeup input (multiplexed with P50 to P57)
1
SO0
Output
Data transmit pin when serial bus interface 0 is in SIO mode
2
SDA0
P62
1
SI0
1
INT0
P64
I/O
Port 62: Programmable as input or output (with internal pull-up resistor)
Input
SCL0
P63
I/O
Data transmit/receive pin when serial bus interface 0 is in I C mode;
programmable as an open-drain output
1
2
Clock input/output pin when serial bus interface 0 is in I C mode;
programmable as an open-drain output
I/O
Port 63: Programmable as input or output
Input
SCOUT
Data receive pin when serial bus interface 0 is in SIO mode
I/O
Interrupt request 0: Programmable to be high-level, low-level, rising-edge or
falling-edge sensitive
I/O
Port 64: Programmable as input or output
Output
System clock output: Drives out fFPH clock
Port 65: Programmable as input or output
P65
1
I/O
P66
1
I/O
Port 66: Programmable as input or output
P70
1
I/O
Port 70: Programmable as input or output (with internal pull-up resistor)
TA0IN
P71
Input
1
TA1OUT
P72
TA3OUT
I/O
Output
1
I/O
Output
8-bit timer 0 input: Input to timer 0
Port 71: Programmable as input or output (with internal pull-up resistor)
8-bit timer 1 output: Output from either timer 0 or timer 1
Port 72: Programmable as input or output (with internal pull-up resistor)
8-bit timer 3 output: Output from either timer 2 or timer 3
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Table 2.2.3 Pin Names and Functions (3/4)
Number
of Pins
I/O
P73
1
I/O
Port 73: Programmable as input or output (with internal pull-up resistor)
P74
1
I/O
Port 74: Programmable as input or output (with internal pull-up resistor)
P75
1
I/O
Port 75: Programmable as input or output (with internal pull-up resistor)
P80
1
I/O
Port 80: Programmable as input or output (with internal pull-up resistor)
Pin Name
Functions
TB0IN0
Input
16-bit timer 0 input 0: Count/capture trigger input to 16-bit timer 0
INT5
Input
Interrupt request 5: Programmable to be rising-edge or falling-edge sensitive
P81
1
I/O
Port 81: Programmable as input or output (with internal pull-up resistor)
TB0IN1
Input
16-bit timer 0 input 1: Count/capture trigger input to 16-bit timer 0
INT6
Input
Interrupt request 6: Rising-edge sensitive
P82
1
TB0OUT0
P83
1
TB0OUT1
P84
I/O
Output
I/O
Output
1
I/O
Port 82: Programmable as input or output (with internal pull-up resistor)
16-bit timer 0 output 0: Output from 16-bit timer 0
Port 83: Programmable as input or output (with internal pull-up resistor)
16-bit timer 0 output 1: Output from 16-bit timer 0
Port 84: Programmable as input or output (with internal pull-up resistor)
TB1IN0
Input
16-bit timer 1 input 0: Count/capture trigger input to 16-bit timer 1
INT7
Input
Interrupt request 7: Programmable to be rising-edge or falling-edge sensitive
P85
1
I/O
Port 85: Programmable as input or output (with internal pull-up resistor)
TB1IN1
Input
16-bit timer 1 input 1: Count/capture trigger input to 16-bit timer 1
INT8
Input
Interrupt request 8: Rising-edge sensitive
P86
1
TB1OUT0
P87
1
TB1OUT1
P90
Port 87: Programmable as input or output (with internal pull-up resistor)
16-bit timer 1 output 1: Output from 16-bit timer 1
Port 90: Programmable as input or output
I/O
Clock input/output pin when serial bus interface 1 is in SIO mode
1
I/O
Port 91: Programmable as input or output (with internal pull-up resistor)
Output
1
SI1
1
Data transmit pin when serial bus interface 1 is in SIO mode
2
I/O
Data transmit/receive pin when serial bus interface 1 is in I C mode;
programmable as an open-drain output
I/O
Port 92: Programmable as input or output (with internal pull-up resistor)
Input
SCL1
TXD
16-bit timer 1 output 0: Output from 16-bit timer 1
I/O
SDA1
P93
Port 86: Programmable as input or output (with internal pull-up resistor)
1
SO1
P92
I/O
Output
SCK1
P91
I/O
Output
Data receive pin when serial bus interface 1 is in SIO mode
2
I/O
Clock input/output pin when serial bus interface 1 is in I C mode;
programmable as an open-drain output
I/O
Port 93: Programmable as input or output
Output
Serial transmit data: Programmable as an open-drain output
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TMP91CW28
Table 2.2.4 Pin Names and Functions (4/4)
Pin Name
P94
Number
of Pins
1
RXD
P95
I/O
I/O
Input
1
SCLK
Port 94: Programmable as input or output
Serial receive data
I/O
Port 95: Programmable as input or output
I/O
Serial clock input/output
Input
CTS
Functions
Serial clear-to-send
P96
1
I/O
Port 96: Programmable as input or output
PA0 to PA3
4
I/O
Ports A0 to A3: Individually programmable as input or output (with internal
pull-up resistor)
INT1 to INT4
Input
PA4 to PA7
4
I/O
WAKE
1
Output
Interrupt request 1 to 4: Individually programmable to be rising-edge or
falling-edge sensitive
Ports A4 to A7: Individually programmable as input or output (with internal
pull-up resistor)
STOP mode monitor output
This pin drives low when the CPU is operating; the pin is in high-impedance
state during reset or in STOP mode.
ALE
1
Output
NMI
1
Input
Nonmaskable interrupt request: Causes an NMI interrupt on the falling edge;
programmable to be rising-edge sensitive
Address latch enable (This pin can be disabled in order to reduce noise.)
AM0 to AM1
2
Input
Both AM0 and AM1 should be held at logic 1.
EMU0
1
Output
EMU1
1
Output
RESET
1
Input
Reset (with internal pull-up resistor): Initializes the whole TMP91CW28.
VREFH
1
Input
Input pin for high reference voltage for the AD converter
VREFL
1
Input
AVCC
1
AVSS
1
X1/X2
2
DVCC
3
Power supply pins. The DVCC pins should be connected to power supply.
DVSS
3
Ground pins. The DVSS pins should be connected to ground.
Test pin. This pin should be left open.
Test pin. This pin should be left open.
Input pin for low reference voltage for the AD converter
Power supply pin for the AD converter
Ground pin for the AD converter
I/O
Connection pins for a crystal oscillator
Note: All pins that have built-in pull-up resistors (other than the RESET pin) can be disconnected from the
built-in pull-up resistor by software.
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TMP91CW28
3.
Operation
This section describes the functions and basic operation of each block constituting the
TMP91CW28.
See also section 7, “Points of Note and Restrictions” for an explanation of precautions and
restrictions for individual blocks.
3.1
CPU
The TMP91CW28 contains a high-performance 16-bit CPU called the 900/L1. For a detailed
description of the CPU, refer to “TLCS-900/L1 CPU” in the preceding chapter.
Functions unique to the TMP91CW28, which are not covered in “TLCS-900/L1 CPU”, are
described below.
3.1.1
Reset Operation
When resetting the TMP91CW28 microcontroller, ensure that the power supply voltage
is within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then set the RESET input to low level at least for 10 system clocks (32 μs at 10
MHz).
Thus, when turn on the switch, be set to the power supply voltage is within the operating
voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the
RESET input to low level at least for 10 system clocks.
Clock gear is initialized 1/16 mode by reset operation. It means that the system clock
mode fSYS is set to fc/32 (= fc/16 × 1/2).
The CPU performs the following operations as a result of a reset:
•
Set the program counter (PC) according to the reset vectors stored at addresses
FFFF00H to FFFF02H
PC [7:0] ← Value at FFFF00H
PC [15:8] ← Value at FFFF01H
PC [23:16] ← Value at FFFF02H
•
Set the stack pointer (XSP) to 100H.
•
Set the IFF2 to IFF0 bits of the status register (SR) to 111 (Setting the interrupt
level mask register to level 7).
•
Set the MAX bit of the status register (SR) to 1 (Selecting maximum mode).
•
Clear the RFP2 to RFP0 bits of the status register (SR) to 000 (Selecting register
bank0).
After a reset, the CPU starts executing instructions according to the set PC. CPU
internal registers other than the above are not modified.
The on-chip I/O peripherals, ports and other pins are initialized as follows upon a reset.
•
All on-chip I/O peripheral registers are initialized.
•
All port pins, including those multiplexed with on-chip peripheral functions, are
configured as either general-purpose inputs or general-purpose outputs.
•
The ALE pin is placed in high-impedance state.
Note: A reset operation does not affect the contents of the on-chip RAM or the CPU
registers other than PC, SR and XSP.
Figure 3.1.1 shows TMP91CW28 reset timings.
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(P00 to P07, P10 to P17: Input mode)
Figure 3.1.1 TMP91CW28 Reset Timings
P00 to P07, P10 to P17,
P20 to P27, P60,
P63 to P66, P90,
P93 to P96
P32 to P37, P40 to P43,
P61 to P62, P70 to P75,
P80 to P87, P91 to P92,
PA0 to PA7
P30 to P31
indicates that the pins are pulled up internally.
indicates high-impedance state.
(Input mode)
(Input mode)
(Output mode)
(P32: Input mode)
Address
(P30: Input mode)
(P00 to P07, P10 to P17: Input mode)
HWR
Data output
Address
(P36: Input mode)
(P40 to P43: Input mode)
(P20 to P27: Input mode)
Sampling
(P31: Input mode)
Address
Address
Sampling
WR
AD0 to AD15
RD
AD0 to AD15
ALE
R/W
CS0 to CS3
A16 to A23
RESET
fFPH
Write
Read
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3.2
Memory Map
Figure 3.2.1 shows memory assignment for the TMP91CW28.
000000H
On-chip peripherals
(4 Kbytes)
Direct area
(n)
000100H
001000H
64-Kbyte area
(nn)
On-chip RAM
(8 Kbytes)
003000H
010000H
External
memory
16-Mbyte area
(R)
(−R)
(R+)
(R + R8/16)
(R + d8/16)
(nnn)
FE0000H
On-chip ROM
(128 Kbytes)
FFFF00H
FFFFFFH
Vector table (256 bytes)
(
= Internal area)
Figure 3.2.1 Memory Map
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3.3
Standby Control and Noise Reduction
The TMP91CW28 incorporates clock gear, standby control and noise reduction circuits to
minimize power consumption as well as noise.
The TMP91CW28 only supports single-clock mode, in which it operates off of the clock
supplied from the X1 and X2 pins.
Figure 3.3.1 shows state transitions in single-clock mode.
Reset
(fOSCH/32)
Instruction
IDLE2 mode
(Peripherals active) Interrupt
IDLE1 mode (Only
oscillator active)
Instruction
Reset released
NORMAL mode
(fOSCH/gear value/2)
Instruction
Interrupt
STOP mode
(Whole chip halted)
Interrupt
State transitions in single-clock mode
Figure 3.3.1 State Transitions in Single-clock Mode
fOSCH:
fFPH:
fSYS:
1 state:
Clock frequency supplied via the X1 and X2 pins
Clock frequency selected by the GEAR[2:0] bit in the SYSCR1
System clock frequency, created by dividing fFPH by two
One period of fSYS
91CW28-12
2006-03-24
TMP91CW28
3.3.1
Clock Source Block Diagram
SYSCR2.WUPTM[1:0]
SYSCR2<WUPTM1:0>
SYSCR0.
SYSCR0<PRCK1:0>
PRCK[1:0]
Warm up (for high-speed oscillator)
φT
φT0
fc/16
fFPH
÷2 ÷4
fFPH
÷2
fc
fSYS
fc/2
fc/4
fc/8
fc/16
X1
High-speed
X2
oscillator
÷2 ÷4 ÷8 ÷16
fOSCH
SYSCR1.GEAR[2:0]
SYSCR1<GEAR2:0>
Clock gear
fSYS
CPU
TMRA01 to TMRA23
φT0
ROM
Prescaler
RAM
Interrupt
controller
TMRB0 to TMRB1
Prescaler
WDT
I/O ports
SIO
CS/WAIT
controller
Prescaler
SBI0 to SBI1
φT
Prescaler
SYSCR2.SCOSEL
P64
fFPH
Figure 3.3.2 Clock and Standby Block Diagram
91CW28-13
2006-03-24
TMP91CW28
3.3.2
SFR Descriptions
7
6
5
4
3
2
1
0
SYSCR0 Bit symbol
(00E0H) Read/Write
−
−
−
−
−
−
PRCK1
PRCK0
Reset value
1
0
0
0
0
Function
W
Must be
written as
“1”.
R/W
1
Must be
written as
“0”.
Must be
written as
“1”.
Must be
written as
“0”.
Must be
written as
“0”.
Must be
written as
“0”.
0
0
Prescaler clock select
00: fFPH
01: Reserved
10: fc/16
11: Reserved
−
SYSCR1 Bit symbol
(00E1H) Read/Write
GEAR2
GEAR1
W
Reset value
0
Function
Must be
written as
“0”.
GEAR0
R/W
1
0
0
High-speed clock gear select
000: High-speed clock
001: High-speed clock /2
010: High-speed clock /4
011: High-speed clock /8
100: High-speed clock /16
101: Reserved
110: Reserved
111: Reserved
SYSCR2
(00E2H)
Bit symbol
SCOSEL
WUPTM1
WUPTM0
HALTM1
HALTM0
DRVE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
1
0
1
1
Function
SCOUT
output
Oscillator warm-up time
0: Low
level
01: 2 /input frequency
1: fFPH
00: Reserved
HALT mode select
00: Reserved
8
01: STOP mode
14
10: IDLE1 mode
16
11: IDLE2 mode
10: 2 /input frequency
11: 2 /input frequency
0
1: Pins are
driven in
STOP
mode.
Note 1: Bits7 to 2 of the SYSCR0, bits7 to 4 of the SYSCR1 and bits7 and 1 of the SYSCR2 are read as undefined.
Note 2: When the on-chip SBI is used, the prescaler select register, SYSCR0.PRCK[1:0], must be set to 00 (fFPH).
Figure 3.3.3 Clock-related SFRs
91CW28-14
2006-03-24
TMP91CW28
7
6
5
4
3
2
1
EMCCR0
Bit symbol
PROTECT
−
−
−
ALEEN
EXTIN
−
−
(00E3H)
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
Reset value
Function
0
0
1
0
0
Protection
flag
Must be
set to “0”.
Must be
set to “1”.
Must be
set to “0”.
1: ALE
output
enabled
0: Disabled
1: Enabled
EMCCR1
Bit symbol
−
(00E4H)
Read/Write
W
1
Must be
set to “1”.
−
Reset value
Function
1: External Must be
clock
set to “1”.
used as
fc
0
On writes:
1FH: Protection disabled
Other than 1FH: Protection enabled
Figure 3.3.4 Noise-related SFRs
91CW28-15
2006-03-24
TMP91CW28
3.3.3
System Clock Control Section
The system clock control section generates system clock pulses (fSYS) that are supplied to
the CPU core and on-chip peripherals. It accepts the fc clock pulses, output from the
high-speed oscillator, and uses the SYSCR1.GEAR[2:0] bits to gear down the high-speed
clock frequency to fc, fc/2, fc/4, fc/8, or fc/16, thus enabling reduction in power consumption.
A system reset initializes the SYSCR1.GEAR[2:0] bits to 100, putting the TMP91CW28
in single-clock mode. The system clock frequency (fSYS) is geared down to fc/32 (= fc/16 ×
1/2). For example, if a 10 MHz crystal is connected between the X1 and X2 pins, the fSYS
clock operates at 0.3125 MHz.
(1) Changing the clock gear
The clock gear select register SYSCR1.GEAR[2:0] can be used to set fFPH to fc, fc/2,
fc/4, fc/8 or fc/16. Gearing down fFPH results in smaller power consumption.
The following shows an example of changing the clock gear:
Example:
Gearing down the high-speed clock frequency
SYSCR1
EQU
00E1H
LD
(SYSCR1), XXXX0000B
;
Changes system clock fSYS to fc/2.
X: Don’t care
There is one thing to remember when changing the clock gear value.
The clock gear can be changed by the programming of the GEAR[2:0] bits of the
SYSCR1, as shown in the above example. It takes a few clock cycles for a gear change
to take effect. Therefore, one or more instructions following the instruction that
changed the clock gear value may be executed using the old clock gear value. If
subsequent instructions need be executed with a new clock gear value, a dummy
instruction (one that executes a write cycle, as shown below) should be inserted after
the instruction that modifies the clock gear value.
Example:
SYSCR1
EQU
00E1H
LD
(SYSCR1), XXXX0001B
;
Changes fSYS to fc/4.
LD
(DUMMY), 00H
;
Dummy instruction.
Instructions that need be
executed with a new clock
gear value
91CW28-16
2006-03-24
TMP91CW28
(2) Internal clock output
The fFPH internal clock can be driven out from the P64/SCOUT pin.
The P64/SCOUT pin is configured as SCOUT (System clock output) by programming
the port 6 registers as follows: P6CR.P64C = 1 and P6FC.P64F = 1. The output clock is
selected through the SYSCR2.SCOSEL bit.
Table 3.3.1 shows the pin states in each clocking mode when the P64/SCOUT pin is
configured as SCOUT.
Table 3.3.1 SCOUT Output States
Mode
SCOUT Select
SCOSEL = 0
SCOSEL = 1
HALT Modes
NORMAL
IDLE2
IDLE1
STOP
A low level is driven out.
The fFPH clock is driven out.
91CW28-17
Held at either 1 or 0.
2006-03-24
TMP91CW28
3.3.4
Prescaler Clock Control Section
The on-chip peripherals (TMRA01 to TMRA23, TMRB0, TMRB1, SIO, SBI0 and SBI1)
have a clock prescaler.
The prescaler clock source (φT, φT0) can be selected from either fFPH or fc/16 through the
PRCK[1:0] bits of the SYSCR0. The selected clock frequency (fFPH or fc/16) is divided by
two or four before being supplied to the prescaler.
When the on-chip SBI is used, PRCK[1:0] must be cleared to 00.
3.3.5
Noise Cancellers
The TMP91CW28 incorporates circuits providing the following features in order to
reduce electromagnetic interference (EMI) and improve electromagnetic susceptibility
(EMS):
(1) Canceling double-drive operation of the high-speed oscillator
(2) Disabling output from the ALE pin
(3) Preventing software or system lockups
These features can be selected using the EMCCR0 and EMCCR1 registers.
(1) Canceling double-drive operation of the high-speed oscillator
Purpose:
To prevent malfunction due to noise coming through the X2 pin that is open
when an external oscillator is used, with double-drive operation not required.
Block diagram:
fOSCH
X1 pin
Oscillation enable (STOP + EMCCR0.EXTIN)
X2 pin
Description:
Setting the EXTIN bit of the EMCCR0 to 1 causes the high-speed oscillator to
stop oscillation and operate as a buffer, with the X2 pin driven high.
A system reset initializes the EXTIN bit to 0.
Note: Do not write EMCCR0<EXTIN> = “1” when using external resonator.
91CW28-18
2006-03-24
TMP91CW28
(2) Disabling output from the ALE pin
Purpose:
To prevent unwanted clock noise from being driven out when no external area is
accessed.
Block diagram:
EMCCR0.ALEEN
Internal ALE
ALE pin
Description:
Clearing the ALEEN bit of the EMCCR0 to 0 disables the output buffer of the
ALE pin, placing the pin into high-impedance state.
A system reset initializes the ALEEN bit to 0.
When accessing an external area, set ALEEN to 1 before attempting to access
the area.
91CW28-19
2006-03-24
TMP91CW28
(3) Preventing software or system lockups using a protection register
Purpose:
To prevent software or system lockups that may occur due to incoming noise.
Applying protection causes specified SFRs to be write-protected, thus
preventing the system recovery routine from becoming unfetchable, for example,
if the system clock stops or a memory control register (CS/WAIT controller) is
modified.
Applicable SFRs
1. CS/WAIT controller
B0CS, B1CS, B2CS, B3CS, BEXCS,
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3
2. Clock gear (Only EMCCR1 can be written.)
SYSCR0, SYSCR1, SYSCR2, EMCCR0
Block diagram:
Protection flag
EMCCR0.PROTECT
Write other than 1FH to EMCCR1
Write 1FH to EMCCR1
S
R
Q
SFR write signal
Write signal to specified SFRs
Write signal to other SFRs
Description:
Writing any code other than 1FH to the EMCCR1 register enables protection,
thus preventing specified SFRs from being written.
Writing 1FH to the EMCCR1 register cancels protection. The state of protection
can be determined by reading the PROTECT bit of the EMCCR0.
A system reset cancels protection.
91CW28-20
2006-03-24
TMP91CW28
3.3.6
Standby Control Section
(1) HALT mode
Executing the HALT instruction causes the TMP91CW28 to enter one of the HALT
modes − IDLE2, IDLE1 or STOP − as specified by the SYSCR2.HALTM[1:0] bits.
The characteristics of the IDLE2, IDLE1 and STOP modes are as follows.
a. IDLE2: The CPU stops.
On-chip peripherals can be selectively enabled and disabled
through use of a register bit in an SFR, as shown in Table 3.3.2.
Table 3.3.2 IDLE2 Mode Register Settings
Peripheral
SFR
TMRA01
TA01RUN.I2TA01
TMRA23
TA23RUN.I2TA23
TMRB0
TB0RUN.I2TB0
TMRB1
TB1RUN.I2TB1
SIO
SC0MOD1.I2S0
SBI0
SBI0BR0.I2SBI0
SBI1
SBI1BR0.I2SBI1
ADC
ADMOD1.I2AD
WDT
WDMOD.I2WDT
b. IDLE1: Only the on-chip oscillator is operational.
c. STOP: The whole TMP91CW28 stops.
Table 3.3.3 shows the operation of each circuit block in HALT modes.
Table 3.3.3 TMP91CW28 Circuit Blocks in HALT Modes
HALT Mode
IDLE2
IDLE1
STOP
SYSCR2.HALTM[1:0]
11
10
01
CPU
Circuit block
I/O ports
OFF
Holding the states when the HALT instruction was
executed
See Table 3.3.6
to Table 3.3.9
TMRA, TMRB
SIO, SBI
ADC
Selectable programmatically on
a block-by-block basis
OFF
WDT
Interrupt controller
ON
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2006-03-24
TMP91CW28
(2) Wakeup signaling
There are two ways to exit a HALT mode: An interrupt request or reset signal.
Availability of wakeup signaling depends on the settings of the interrupt mask level
bits, IFF[2:0], of the CPU status register (SR) and the current HALT mode (See Table
3.3.4).
•
Wakeup via interrupt signaling
The operation upon return from a HALT mode varies, depending on the
interrupt priority level programmed before executing the HALT instruction. If the
interrupt priority level is greater than or equal to the processor’s interrupt mask
level, execution resumes with the interrupt service routine. Upon completion of
the interrupt service routine, program execution resumes with the instruction
immediately following the HALT instruction. If the interrupt priority level is less
than the processor’s interrupt mask level, the HALT mode is not terminated.
(Nonmaskable interrupts are always serviced upon return from a HALT mode,
regardless of the current interrupt mask level.)
Only interrupts INT0 to INT4 can, however, terminate a HALT mode even if the
interrupt priority level is less than the processor’s interrupt mask level. In that
case, program execution resumes with the instruction immediately following the
HALT instruction, without executing the interrupt service routine. The interrupt
request flag remains set.
•
Wakeup via reset signaling
Reset signaling always brings the TMP91CW28 out of any HALT mode. A
wakeup from STOP mode must allow sufficient time for the oscillator to restart
and stabilize (See Table 3.3.5).
A reset does not affect the contents of the on-chip RAM, but initializes
everything else, whereas an interrupt preserves all internal states that were in
effect before the HALT mode was entered.
91CW28-22
2006-03-24
TMP91CW28
Table 3.3.4 Wakeup Signaling Sources and Wakeup Operations
Interrupt Masking
Interrupts
Wakeup signaling sources
HALT Mode
Unmasked Interrupt
Masked Interrupt
(Request_level ≥ mask_level)
(Request_level < mask_level)
IDLE1 STOP
Programmable IDLE2
♦
NMI
♦
INTWDT
♦
×
INT0 to 4 (Note 1)
♦
♦
INT5 to INT8
♦ (Note 2)
INTTA0 to INTTA3
♦
INTTB00 to 01, 10, 11, OF0, OF1
INTRX, INTTX
Programmable IDLE2
*1
♦
IDLE1 STOP
−
−
−
×
−
−
−
*1
○
○
○*1
×
×
×
×
×
×
×
×
×
×
♦
×
×
×
×
×
♦
×
×
×
×
×
INTSBI0 to 1
♦
×
×
×
×
×
INTAD
♦
×
×
×
×
×
INTBCD
♦
×
×
×
×
×
RESET
♦
Initializes the whole TMP91CW28
♦: Execution resumes with the interrupt service routine. (RESET initializes the whole TMP91CW28.)
○: Execution resumes with the instruction immediately following the HALT instruction. The interrupt is left
pending.
×: Cannot be used to exit a HALT mode.
−: These combinations are not possible because nonmaskable interrupts are assigned a highest priority
level (7).
*1: The TMP91CW28 exits the HALT mode after the warm-up period timer expires.
Note 1: If the interrupt request level is greater than the mask level, an INT0 interrupt signal which is
programmed as level-sensitive must be held high until interrupt processing begins. Otherwise, the
interrupt will not be serviced successfully.
Note 2: When external INT5 to INT8 interrupts are used in programmable IDLE2 mode, 16-bit timer run
register bits TB0RUN.I2TB0 and TB1RUN.I2TB1 must be set to 1.
Example of exiting a HALT mode:
When using an edge-sensitive INT0 interrupt to exit IDLE1 mode
Address
8200H
LD
(PAFC), 01H
;
Set PA0 to INT0.
8203H
LD
(IIMC), 00H
;
Set INT0 interrupt to rising-edge sensitive.
8206H
LD
(INTE0AD), 06H
;
Set INT0 interrupt priority level to 6.
8209H
EI
5
;
Set CPU interrupt priority level to 5.
820BH
LD
(SYSCR2), 28H
820EH
HALT
;
Select IDLE1 mode.
;
Stop CPU.
INT0
INT0 interrupt service routine
RETI
820FH
LD
XX, XX
91CW28-23
2006-03-24
TMP91CW28
(3) Operation in HALT modes
a.
IDLE2 mode
In IDLE2 mode, the CPU stops executing instructions and only the on-chip
peripherals enabled with the IDLE2 setting bits in respective SFRs are
operational.
Figure 3.3.5 shows example timings for exiting IDLE2 mode with an interrupt.
X1
A0 to A23
ALE
AD0 to AD15
Address
Data
Address
Address
Data
RD
WR
Wakeup interrupt
IDLE2
mode
Figure 3.3.5 Example Timings for Exiting a HALT Mode with an Interrupt (in IDLE2 mode)
b.
IDLE1 mode
In IDLE1 mode, the system clock stops while only the on-chip oscillator is active.
Interrupt requests are sampled asynchronously with the system clock in a halt
state but the HALT mode is exited in synchronization with the system clock.
Figure 3.3.6 shows example timings for exiting IDLE1 mode with an interrupt.
X1
A0 to A23
ALE
AD0 to AD15
Address
Data
Address
Data
RD
WR
Wakeup interrupt
IDLE1
mode
Figure 3.3.6 Example Timings for Exiting a HALT Mode with an Interrupt (in IDLE1 mode)
91CW28-24
2006-03-24
TMP91CW28
c.
STOP mode
In STOP mode, the whole TMP91CW28 stops, including the on-chip oscillator.
Pin states in STOP mode depend on the setting of the SYSCR2.DRVE bit, as
shown in Table 3.3.6 to Table 3.3.9.
Upon detection of wakeup signaling, the warm-up period timer should be
activated to allow sufficient time for the oscillator to restart and stabilize before
exiting STOP mode. After that, the system clock output can restart. The warm-up
period is chosen through the SYSCR2.WUPTM[1:0] bits, as shown in Table 3.3.5.
Figure 3.3.7 shows example timings for exiting STOP mode with an interrupt.
Warm-up
period
X1
A0 to A23
ALE
AD0 to AD15
Address
Data
Address
Data
RD
WR
Wakeup interrupt
STOP
mode
Figure 3.3.7 Example Timings for Exiting a HALT Mode with an Interrupt (in STOP mode)
Table 3.3.5 Example Warm-up Period Settings (when exiting STOP mode)
at fOSCH = 10 MHz
SYSCR2.WUPTM[1:0]
01 (28)
10 (214)
11 (216)
25.6 μs
1.6384 ms
6.5536 ms
91CW28-25
2006-03-24
TMP91CW28
3.3
Table 3.3.6 Input Buffer State Table (1/2)
Input Buffer State
Input Function
Port Name
Name
P00 to P07
P10 to P17
When the CPU is
Operating
During
Reset
In HALT Mode (STOP)
In HALT Mode
(IDLE2/IDLE1)
<DRVE> = 1
<DRVE> = 0
When
When
When
When
When
When
When
When
Used as
Used as
Used as
Used as
Used as
Used as
Used as
Used as
Function
Function
Function
Function
Input Port
Input Port
Input Port
Input Port
Pin
Pin
Pin
Pin
AD0 to AD7
AD8 to AD15
A8 to A15
A0 to A7
P20 to P27
OFF
ON
ON (*3)
OFF
OFF
OFF
OFF
OFF
A16 to A23
P32 (*1)
−
P33 (*1)
WAIT
P34 (*1)
BUSRQ
P35 (*1)
−
P36 (*1)
−
P37 (*1)
−
P40 to P43
(*1)
−
−
ON
ON
−
−
OFF
OFF
ON
ON
−
−
−
OFF
OFF
ON
−
−
AN0
P50 (*2)
KWI0
P51 (*2)
P52 (*2)
P53 (*2)
P54 (*2)
P55 (*2)
P56 (*2)
P57 (*2)
OFF
AN1
ON
KWI1
OFF
AN2
ON
KWI2
OFF
AN3
ON
ADTRG
OFF
KWI3
OFF
AN4
ON
KWI4
OFF
AN5
ON
KWI5
OFF
AN6
ON
KWI6
OFF
AN7
ON
KWI7
OFF
P60
SCK0
P61 (*1)
SDA0
ON (*3)
ON
ON
ON
ON
ON
OFF
OFF
ON
ON
ON
SI0
P62 (*1)
ON
SCL0
P63
INT0
P64
−
P65
−
P66
−
P70 (*1)
P71 to P75
(*1)
ON
ON
−
−
−
−
TA0IN
ON
ON
ON
OFF
−
−
−
−
−
OFF
ON: The buffer is always turned on. A current flows the input buffer if the input pin is not driven.
OFF: The buffer is always turned off.
−:
Not applicable.
*1:
Port having a pull-up/pull-down resistor.
*2:
AIN input does not cause a current to flow through the buffer.
*3:
The buffer is turned on if read port.
91CW28-26
2006-03-24
TMP91CW28
Table 3.3.7 Input Buffer State Table (2/2)
Input Buffer State
Input Function
Name
Port Name
When the CPU is
Operating
During
Reset
In HALT Mode (STOP)
In HALT Mode
(IDLE2/IDLE1)
<DRVE> = 1
<DRVE> = 0
When
When
When
When
When
When
When
When
Used as
Used as
Used as
Used as
Used as
Used as
Used as
Used as
Function
Function
Function
Function
Input Port
Input Port
Input Port
Input Port
Pin
Pin
Pin
Pin
TB0IN0
P80 (*1)
INT5
TB0IN1
P81 (*1)
ON
ON
ON
OFF
−
−
−
−
ON
ON
ON
OFF
INT6
P82 (*1)
−
P83 (*1)
−
TB1IN0
P84 (*1)
INT7
TB1IN1
P85 (*1)
INT8
P86 (*1)
−
P87 (*1)
−
P90
SCK1
P91 (*1)
SDA1
ON
SI1
P92 (*1)
ON
−
−
ON
−
ON
−
ON
ON
ON
OFF
−
−
−
−
ON
ON
ON
OFF
−
−
−
−
ON
ON
ON
ON
OFF
SCL1
−
P93
P94
RXD1
SCLK1
P95
CTS1
P96
−
PA0 (*1)
INT1
PA1 (*1)
INT2
PA2 (*1)
INT3
PA3 (*1)
INT4
PA4 (*1)
−
PA5 (*1)
−
PA6 (*1)
−
PA7 (*1)
−
NMI (*1)
−
RESET (*1)
−
AM0, AM1
−
X1
−
OFF
ON (*3)
−
ON
ON
OFF
−
ON
ON
OFF
−
ON
−
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON: The buffer is always turned on. A current flows the input buffer if the input pin is not driven.
OFF: The buffer is always turned off.
−:
Not applicable.
*1:
Port having a pull-up/pull-down resistor.
*2:
AIN input does not cause a current to flow through the buffer.
*3:
The buffer is turned on if read port.
91CW28-27
2006-03-24
TMP91CW28
Table 3.3.8 Output Buffer State Table (1/2)
Output Buffer State
Port Name
Output
Function
Name
P00 to P07
AD0 to AD7
P10 to P17
When the CPU is
Operating
During
Reset
When
Used as
Function
Pin
When
Used as
Output
Port
In HALT Mode
(IDLE2/IDLE1)
When
Used as
Function
Pin
When
Used as
Output
Port
In HALT Mode (STOP)
<DRVE> = 1
When
When
Used as Used as
Function
Output
Pin
Port
<DRVE> = 0
When
When
Used as Used as
Function
Output
Pin
Port
AD8 to AD15
A8 to A15
A0 to A7
P20 to P27
A16 to A21
P30
ON
ON
ON
OFF
−
−
−
−
ON
ON
ON
OFF
−
−
−
−
ON
ON
ON
OFF
RD
P31
WR
P32 (*1)
HWR
P33 (*1)
−
P34 (*1)
−
P35 (*1)
BUSAK
P36 (*1)
R/ W
−
P37 (*1)
CS0
CS1
P40 to P43
(*1)
CS2
P60
SCK0
CS3
SDA0
P61
SO0
OFF
ON
ON
ON
OFF
P62
SCL0
P63
−
−
−
−
−
P64
SCOUT
ON
ON
ON
OFF
P65
−
−
−
−
−
ON
ON
ON
OFF
−
−
−
−
ON
ON
ON
OFF
−
−
−
−
ON
ON
ON
OFF
P66
−
P70 (*1)
−
P71(*1)
TA1OUT
P72 (*1)
TA3OUT
P73 (*1)
−
P74(*1)
−
P75(*1)
−
P80 (*1)
−
P81 (*1)
−
P82 (*1)
TB0OUT0
P83 (*1)
TB0OUT1
P84 (*1)
−
P85 (*1)
−
P86 (*1)
TB1OUT0
P87 (*1)
TB1OUT1
ON: The buffer is always turned on.
OFF: The buffer is always turned off.
−:
Not applicable.
*1:
Port having a pull-up/pull-down resistor.
*2:
AIN input does not cause a current to flow through the buffer.
91CW28-28
2006-03-24
TMP91CW28
Table 3.3.9 Output Buffer State Table (2/2)
Output Buffer State
Port Name
Output
Function
Name
P90
SCK1
When the CPU is
Operating
During
Reset
When
Used as
Function
Pin
When
Used as
Output
Port
In HALT Mode
(IDLE2/IDLE1)
When
Used as
Function
Pin
When
Used as
Output
Port
In HALT Mode (STOP)
<DRVE> = 1
When
When
Used as Used as
Function
Output
Pin
Port
<DRVE> = 0
When
When
Used as Used as
Function
Output
Pin
Port
SDA1
P91 (*1)
SO1
P92 (*1)
SCLK1
P93
TXD1
P94
−
P95
SCLK1
P96
−
PA0 to PA7
(*1)
−
WAKE
−
ALE
−
X2
−
OFF
ON
ON
ON
−
−
−
ON
ON
ON
−
−
ON
ON
ON
OFF
ON
−
ON
OFF
−
−
ON
OFF
OFF
OFF
OFF
ON
OFF
ON: The buffer is always turned on.
OFF: The buffer is always turned off.
−:
Not applicable.
*1:
Port having a pull-up/pull-down resistor.
*2:
AIN input does not cause a current to flow through the buffer.
91CW28-29
2006-03-24
TMP91CW28
3.4
Interrupts
Interrupt processing is coordinated between the CPU interrupt mask register SR.IFF[2:0]
and the on-chip interrupt controller.
The TMP91CW28 supports the following 48 interrupt sources:
•
9 CPU internal interrupts
(Software interrupts and interrupts triggered when an undefined instruction is
executed.)
•
18 external interrupt pins ( NMI , INT0 to INT8, KWI0 to KWI7)
•
21 on-chip peripheral interrupts
Each interrupt source has a unique interrupt vector number (Fixed). Each maskable
interrupt is assigned one of six priority levels (Variable) while nonmaskable interrupts have the
highest priority level of 7 (Fixed).
When an interrupt occurs, the interrupt controller sends the priority level of that interrupt
source to the CPU. If two or more interrupts occur simultaneously, it sends the highest of their
priority levels (7 if a nonmaskable interrupt occurs) to the CPU.
The CPU compares the sent priority level with the contents of the CPU interrupt mask
register IFF[2:0]. If the sent priority level is greater than or equal to the interrupt mask level,
the CPU accepts the interrupt. The contents of the IFF[2:0] bits can be modified using the EI
instruction in the format of EI num, where num is the value to be set in IFF[2:0]. For example,
EI 3 causes the CPU to accept maskable interrupts having a priority level of 3 or greater, as
specified with the interrupt controller, as well as all nonmaskable interrupts. The DI
instruction, which sets IFF[2:0] to 7, has the same effect as EI 7. It is used to prevent the CPU
from accepting maskable interrupts because maskable interrupts can have priority levels of
only up to 6. The EI instruction takes effect immediately after it is executed.
In addition to general interrupt servicing, as described above, the TMP91CW28 supports
micro DMA mode, where the CPU automatically transfers data (1 byte, 2 bytes or 4 bytes). This
mode enables faster data transfer to on-chip/external memory and on-chip peripherals.
A micro DMA request can be issued either using an interrupt source or programmatically
with the soft start feature.
Figure 3.4.1 shows the overall flow of interrupt servicing.
91CW28-30
2006-03-24
TMP91CW28
Interrupt servicing
Interrupt
Yes
Micro DMA soft
start request
specified with micro DMA
request vector?
No
Clear interrupt request
flip-flop
Micro DMA soft start request
Read interrupt vector V
clear interrupt request flag
General
interrupt
servicing
PUSH
PC
PUSH
SR
SR.IFF[2:0]←Accepted
interrupt
level + 1
INTNEST←INTNEST + 1
PC←(FFFF00H + V)
Transfer data using
micro DMA
Micro DMA
mode
COUNT←COUNT − 1
COUNT = 0
No
Yes
INTTC interrupt occurred
clear micro DMA request
vector register
Interrupt service routine
RETI instruction
POP
SR
POP
PC
INTNEST←INTNEST − 1
End
Figure 3.4.1 Overall Interrupt Servicing Flow
91CW28-31
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TMP91CW28
3.4.1
General Interrupt Servicing
The CPU performs the following operations once it accepts an interrupt. However, when
the CPU itself generates an interrupt, as triggered by a software interrupt instruction or
upon the execution of an undefined instruction, it only performs steps 2, 4 and 5. The
operations are the same as those performed by the TLCS-900/L and TLCS-900/H.
(1) Reads an interrupt vector from the interrupt controller.
If two or more interrupts having the same priority level occur simultaneously, the
interrupt controller generates an interrupt vector according to default priorities
(Fixed; higher priorities assigned to smaller vector values) and clears the interrupt
request.
(2) Pushes the contents of the program counter (PC) and status register (SR) to the stack
area, indicated by the XSP.
(3) Sets the interrupt mask register bits IFF[2:0] to one higher than the accepted
interrupt level. If the level is 7, however, it sets the bits to 7 without incrementing the
value.
(4) Increments the interrupt nesting counter INTNEST by one.
(5) Makes a branch to the address specified with the data stored at address (FFFF00H +
interrupt vector) and then starts the interrupt service routine.
The above procedure requires 18 states (3.6 μs at 10 MHz) in the best case (with 16-bit
data bus and 0-wait cycles).
Upon the completion of interrupt servicing, the RETI instruction is usually used to
return to the main routine. The RETI instruction restores the contents of the PC and SR
from the stack and decrements the INTNEST by one.
Nonmaskable interrupts cannot be disabled programmatically. Maskable interrupts can
be disabled or enabled programmatically and a priority level can be specified for each
interrupt source. The CPU accepts an interrupt if its priority level is greater than or equal
to the value stored in the CPU’s IFF[2:0] bits. The CPU then sets the IFF[2:0] bits to the
accepted priority level plus one. This enables the CPU to accept any higher-priority
interrupt that occurs while servicing the current interrupt, so that interrupts are nested.
If another interrupt request is issued while the CPU is performing the above steps, the
request is sampled immediately after the first instruction of the current interrupt service
routine is executed. The DI instruction can be used as the first instruction to prohibit
nesting of maskable interrupts.
Upon a system reset, the IFF[2:0] bits are initialized to 7 so that maskable interrupts are
disabled.
Addresses FFFF00H through FFFFFFH (256 bytes) are assigned to the interrupt vector
area. Table 3.4.1 shows the interrupt vector table.
91CW28-32
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TMP91CW28
Table 3.4.1 TMP91CW28 Interrupt Vector Table
Default
Priority
1
2
3
4
5
6
7
8
9
10
−
11
12
13
14
15
16
17
18
19
20
21
22
23
−
−
−
−
24
25
26
27
28
29
−
−
30
31
32
33
34
35
36
37
38
39
Type
Interrupt Source
Reset or SWI 0 instruction
SWI1 instruction
INTUNDEF: Execution of an undefined instruction; or SWI2 instruction
Nonmaskable
Maskable
SWI3 instruction
SWI4 instruction
SWI5 instruction
SWI6 instruction
SWI7 instruction
NMI pin
INTWD: Watchdog timer
(Micro DMA)
INT0 pin
INT1 pin
INT2 pin
INT3 pin
INT4 pin, KWI0 to KWI7 pins
INT5 pin
INT6 pin
INT7 pin
INT8 pin
INTTA0: 8-bit timer 0
INTTA1: 8-bit timer 1
INTTA2: 8-bit timer 2
INTTA3: 8-bit timer 3
−
−
−
−
INTTB00: 16-bit timer 0 (TB0RG0)
INTTB01: 16-bit timer 0 (TB0RG1)
INTTB10: 16-bit timer 1 (TB1RG0)
INTTB11: 16-bit timer 1 (TB1RG1)
INTTBOF0: 16-bit timer 0 (Overflow)
INTTBOF1: 16-bit timer 1 (Overflow)
−
−
INTRX: UART receive
INTTX: UART transmit
INTSBI0: Serial bus interface interrupt
INTSBI1: Serial bus interface interrupt
INTAD: AD conversion complete
INTTC0: Micro DMA complete (Channel 0)
INTTC1: Micro DMA complete (Channel 1)
INTTC2: Micro DMA complete (Channel 2)
INTTC3: Micro DMA complete (Channel 3)
INTBCD: BCD computation complete
(Reserved)
:
(Reserved)
Vector
Value
0000H
0004H
0008H
000CH
0010H
0014H
0018H
001CH
0020H
0024H
−
0028H
002CH
0030H
0034H
0038H
003CH
0040H
0044H
0048H
004CH
0050H
0054H
0058H
−
−
−
−
006CH
0070H
0074H
0078H
007CH
0080H
−
−
008CH
0090H
0094H
0098H
009CH
00A0H
00A4H
00A8H
00ACH
00B0H
00B4H
:
00FCH
Vector
Micro DMA
Reference
Request
Address
Vector
FFFF00H
FFFF04H
FFFF08H
FFFF0CH
FFFF10H
FFFF14H
FFFF18H
FFFF1CH
FFFF20H
FFFF24H
−
FFFF28H
FFFF2CH
FFFF30H
FFFF34H
FFFF38H
FFFF3CH
FFFF40H
FFFF44H
FFFF48H
FFFF4CH
FFFF50H
FFFF54H
FFFF58H
−
−
−
−
FFFF6CH
FFFF70H
FFFF74H
FFFF78H
FFFF7CH
FFFF80H
−
−
FFFF8CH
FFFF90H
FFFF94H
FFFF98H
FFFF9CH
FFFFA0H
FFFFA4H
FFFFA8H
FFFFACH
FFFFB0H
FFFFB4H
:
FFFFFCH
−
−
−
−
−
−
−
−
−
−
−
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
−
−
−
−
1BH
1CH
1DH
1EH
1FH
20H
−
−
23H
24H
25H
26H
27H
−
−
−
−
2CH
−
:
−
Note: Micro DMA default priority.
If an interrupt request is generated by a source specified by micro DMA, the interrupt has the
highest priority of the maskable interrupts (Irrespective of the default priority allocated to all
channels).
91CW28-33
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TMP91CW28
3.4.2
Micro DMA
In addition to general interrupt servicing, the TMP91CW28 supports a micro DMA
feature. Interrupt requests specified with the micro DMA are assigned highest priority
levels among maskable interrupts regardless of the priority levels actually set.
The micro DMA consists of four channels so that continuous transfer can be performed
using burst specification, described later.
Because the micro DMA feature is provided in combination with the CPU, micro DMA
requests are ignored and remain pending if the CPU executes the HALT instruction and
enters a standby state (STOP, IDLE1 or IDLE2). A DMA transfer is started upon the
release from the standby state.
(1) Micro DMA operation
If an interrupt specified with the micro DMA request vector register is requested, the
micro DMA transfers data to the CPU assuming the highest priority level for a
maskable interrupt regardless of the priority level assigned to the interrupt source.
Micro DMA requests are not, however, accepted when IFF[2:0] = 7.
The micro DMA has four channels so that it can be specified for up to four interrupt
sources simultaneously.
When the CPU accepts a micro DMA request, it clears the interrupt request flag
assigned to that channel, performs a single data transfer (1 byte, 2 bytes or 4 bytes)
from the source address to destination address, as specified with the control register,
and then decrements the transfer counter. If the decremented counter reaches zero, the
interrupt controller receives a request from the CPU and generates a micro DMA
transfer complete interrupt (INTTCn). Then the CPU clears the micro DMA request
vector register (DMAnV) to 0, thus disabling subsequent start of the micro DMA and
terminating micro DMA servicing. If the decremented counter does not reach zero, the
CPU terminates micro DMA servicing unless burst is specified. In that case, the
interrupt controller does not generate a micro DMA transfer complete interrupt
(INTTCn).
When using an interrupt source only to start the micro DMA, set the priority level
for that interrupt to 0. If another interrupt request with a priority level of 1 to 6 is
issued before the current interrupt is set for the micro DMA request vector, the CPU
performs general interrupt servicing for the new interrupt.
When using an interrupt source for both the micro DMA and general interrupt
servicing, set the priority level for that interrupt to a level less than those of all other
interrupt sources (Note). Note that only edge-triggered interrupts can be used in such
a way.
A micro DMA transfer complete interrupt is serviced according to its priority level
and default priorities, in the same way as other maskable interrupts.
If two or more micro DMA channels issue requests simultaneously, channels having
smaller numbers have higher priorities, regardless of the respective interrupt priority
levels.
The transfer source and destination addresses are specified using a 32-bit control
register. The micro DMA can, however, handle only 16-Mbyte space because there are
only 24 address output lines.
91CW28-34
2006-03-24
TMP91CW28
Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.
In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking
“Interrupt specified by micro DMA start vector” (in the Figure 3.4.1) and reading interrupt vector with
setting below. The vector shifts to that of INTyyy at the time.
This is because the priority level of INTyyy is higher than that of INTxxx.
In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished.
And INTyyy is generated regardless of transfer counter of micro DMA.
INTxxx: level 1 without micro DMA
INTyyy: level 6 with micro DMA
The micro DMA supports three transfer modes: 1 byte, 2 bytes or 4 bytes. For each
transfer mode, the transfer source and destination addresses can be incremented,
decremented or fixed after the transfer of a single unit of data. This ability to select
various modes facilitates data transfer from memory to memory, peripheral to memory,
memory to peripheral and peripheral to peripheral. For details of transfer modes, see
(4) “Transfer mode registers”.
The transfer counter consists of 16 bits, so that up to 65536 micro DMA transfers (if
the counter defaults to 0000H) can be performed for a single interrupt source.
The micro DMA supports 30 interrupt sources, for which micro DMA request vectors
are shown in Table 3.4.1, as well as a soft start.
Figure3.4.2 shows micro DMA cycles for 2-byte transfer with the transfer destination
address incremented, where all address areas are accessed with a 16-bit bus, no wait
cycles are inserted, and both the source and destination addresses are even numbers.
Cycles for other counter modes are also similar to the following.
1 state
DM1
Note 1
DM2
DM3
DM4
DM5
Note 2
DM6
DM7
DM8
X1
A0 to A23
Source
Destination
RD
WR / HWR
D0 to D15
Input
Output
Figure3.4.2 Micro DMA Cycles
1st to 3rd states:
Instruction fetch cycles (Prefetching next instruction code).
These cycles are dummy cycles if three or more bytes of instruction code
are stored in the instruction queue buffer.
4th and 5th states: Micro DMA read cycles.
6th states:
Dummy cycle (Address bus left in 5th state).
7th and 8th states: Micro DMA write cycles.
Note 1: Additional two states are involved if the source address area uses an 8-bit bus.
If the source address area uses a 16-bit bus but starts with an odd address, additional two
states are involved.
Note 2: Additional two states are involved if the destination address area uses an 8-bit bus.
If the destination address area uses a 16-bit bus but starts with an odd address, additional
two states are involved.
91CW28-35
2006-03-24
TMP91CW28
(2) Soft start
The micro DMA is usually started by an interrupt source but it also supports a soft
start feature that enables it to start upon the detection of a write cycle to the DMAR
register.
Writing 1 to a bit of the DMAR register can start the corresponding micro DMA
channel once (Writing 0 has no effect). Upon the completion of transfer, the DMAR
register bit for that channel is automatically cleared to 0. Only a single channel can be
started simultaneously (More than one bit cannot be set to 1 simultaneously) due to a
restriction imposed by the specification.
A DMAR register bit must be determined to be 0 before it can be set to 1 again. If the
bit is read as 1, a micro DMA transfer has not yet started.
If the DMAB register specifies burst, the started micro DMA channel transfers data
continuously until the micro DMA transfer counter reaches 0.
Any soft start attempted between interrupt-triggered micro DMA transfers does not
cause the micro DMA transfer counter to change. To prevent other bits from being
written unintentionally, no read-modify-write instruction should be used.
Symbol
Name
Address
DMAR
DMA
request
register
89H
(RMW
prohibited)
7
6
5
4
3
2
DMAR3
DMAR2
1
0
DMAR1
DMAR0
R/W
0
0
0
0
DMA request
(3) Transfer control registers
The following registers in the CPU are used to control the transfer source and
destination addresses. Use the “LDC cr, r” instruction to set data in these registers.
Channel 0
DMAS0
Transfer source address register 0
DMAD0
Transfer destination address register 0 … Only lower 24 bits are used.
DMAC0
DMAM0
Transfer counter register 0
… Only lower 24 bits are used.
… 1 to 65536
Transfer mode register 0
Channel 3
DMAS3
Transfer source address register 3
DMAD3
Transfer destination address register 3
DMAC3
DMAM3
Transfer counter register 3
Transfer mode register 3
8 bits
16 bits
32 bits
91CW28-36
2006-03-24
TMP91CW28
(4) Transfer mode registers: DMAM0 to DMAM3
(DMAM0 to DMAM3)
0
0
0
Mode
Note: The upper three bits of data written to
these registers must always be 0.
Execution time
ZZ: 0 = Byte transfer, 1 = Word transfer, 2 = 4-byte transfer, 3 = Reserved
0
0
0
Z
Z
Destination address increment mode ............. Peripheral to memory
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
0
0
1
Z
Z
Destination address decrement mode ............ Peripheral to memory
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
0
1
0
Z
Z
Source address increment mode.................... Memory to peripheral
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
0
1
1
Z
Z
Source address decrement mode................... Memory to peripheral
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
1
0
0
Z
Z
Fixed address mode ..................................... Peripheral to peripheral
(DMADn) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
1
0
1
0
0
Counter mode … Counting the number of interrupts that have occurred
8 states (1600 ns)
Byte/word transfer
12 states (2400 ns)
4-byte transfer
8 states (1600 ns)
Byte/word transfer
12 states (2400 ns)
4-byte transfer
8 states (1600 ns)
Byte/word transfer
12 states (2400 ns)
4-byte transfer
8 states (1600 ns)
Byte/word transfer
12 states (2400 ns)
4-byte transfer
8 states (1600 ns)
Byte/word transfer
12 states (2400 ns)
4-byte transfer
5 states
DMASn ← DMASn + 1
(1000 ns)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
Note 1 n: Corresponding micro DMA channel (0 to 3)
DMADn+/DMASn+: Post-increment (Incrementing the register value after transfer)
DMADn−/DMASn−: Post-decrement (Decrementing the register value after transfer)
In the table, “peripheral” means a fixed address while “memory” means an address that can be
incremented or decremented.
Note 2: Execution time: The time required to complete transferring a single unit of data when a 16-bit
bus is used for the source and destination address areas and no wait cycles
are inserted.
Clock settings: fc = 10 MHz, clock gear: 1 (fc)
Note 3: Any code other than those listed above must not be written to transfer mode registers.
91CW28-37
2006-03-24
TMP91CW28
3.4.3
Interrupt Controller
Figure3.4.3 shows a block diagram of the interrupt circuit. The left-hand side of the
diagram shows the interrupt controller while the right-hand side shows the CPU’s
interrupt request signal circuit and halt wakeup circuit.
The interrupt controller has an interrupt request flag, interrupt priority register and
micro DMA request vector. The interrupt request flag is used to latch an interrupt request
issued by peripherals.
This flag is cleared in the following cases:
•
The device is reset.
•
The CPU accepts the interrupt and reads the vector for the interrupt.
•
An instruction that clears the interrupt is executed (A DMA request vector is
written to the INTCLR register).
•
The CPU accepts a micro DMA request for the interrupt.
•
Micro DMA burst transfer for the interrupt completes.
Priority levels for individual interrupts can be specified using interrupt priority registers
(such as INTE0AD and INTE12) provided for each interrupt source. Six levels of priority (1
to 6) can be set. An interrupt request is disabled when its priority level is set to 0 or 7.
Nonmaskable interrupts ( NMI pin and watchdog timer) have a fixed level of 7. If two or
more interrupts having the same priority level occur simultaneously, the CPU accepts
interrupts according to default priorities. Reading bits 3 and 7 of the interrupt priority
register obtains the status of the interrupt request flag, indicating whether an interrupt
request is present for a channel.
The interrupt controller determines the interrupt, and sends its priority level and vector
address to the CPU. The CPU compares that priority level with the contents of the
interrupt mask register, that is, the IFF[2:0] bits of the status register (SR). The CPU
accepts the interrupt if its priority level is greater than the register value. It then sets the
SR.IFF[2:0] bits to the accepted interrupt level plus one, so that only interrupt requests
having a priority level greater than or equal to the register value can be accepted while the
current interrupt is handled. Upon the completion of interrupt servicing (with the
execution of the RETI instruction), the SR.IFF[2:0] bits restore the values existing before
the interrupt occurred from the stack.
The interrupt controller has registers for storing micro DMA request vectors for four
channels. Writing a request vector (See Table 3.4.1) to these registers enables the micro
DMA to start when the corresponding interrupt occurs. Note that the micro DMA
parameter registers (such as DMAS and DMAD) must be set beforehand.
91CW28-38
2006-03-24
91CW28-39
Micro DMA
counter 0
interrupt
INTAD
INTTC0
INTTC1
INTTC2
INTTC3
INT1
INT2
INT3
INT4, KWI0 to KWI7
INT5
INT6
INT7
INT8
INTTA0
INT0
INTWD
NMI
Dn + 2
Q
Reset
D5
D4
D3
D2
D1
D0
INTTC0
D Q
CLR
Dn + 3
6
V = 20H
V = 24H
6
34
Selector
S
DMA0V
DMA1V
DMA2V
DMA3V
Soft start
V = 9CH
V = A0H
V = A4H
V = A8H
V = ACH
V = 28H
V = 2CH
V = 30H
V = 34H
V = 38H
V = 3CH
V = 40H
V = 44H
V = 48H
V = 4CH
Interrupt request flip-flop read
C
B
A
Y1
Y2
Y3
Y4
Y5
Y6
Decoder
Interrupt accept
Micro DMA accept
S Q
R
Interrupt
request flag
D
Q
CLR
Micro DMA startup vector register
Reset
S
R
Priority setting register
Dn + 1
Dn
Reset
Interrupt
vector read
Interrupt request flag
Interrupt Controller
4
1
7
3
2
1
0
A
B
C
B
A
D2
D3
D4
D5
D6
D7
D0
D1
3 INTRQ2 to 0
2
Interrupt vector
read
Generate
interrupt vector
(7 is top priority)
Select
highest
priority
level
4-input OR
36
1
2
3
4
5
6
7
Micro DMA channel
priority encoder
6
1
request
Priority encoder Interrupt
priority level
Determine
Reset
Halt wakeup
STOP mode
IDLE1 mode
Interrupt request
signal
EI1 to 7
DI
2
if IFF = 7 then 0
NMI
Micro DMA channel
specification
Micro DMA request
INT0, INT1, INT2, INT3, INT4, KWI0 to KWI7
Reset
if INTRQ2-0 ≥ IFF
2 to 0 then 1.
3
3
IFF[2:0]
CPU interrupt
acceptance flag
CPU
TMP91CW28
Figure3.4.3 Interrupt Controller Block Diagram
2006-03-24
TMP91CW28
(1) Interrupt priority registers
Symbol
Name
INTE0AD
INT0 &
INTAD
enable
Address
7
6
IADC
IADM2
5
4
3
2
IADM1
IADM0
I0C
I0M2
INTAD
90H
R
0
INT1 &
INT2
enable
91H
I2C
R/W
0
0
I2M2
R
0
INT3 &
INT4
enable
92H
I4C
0
I2M0
R/W
0
0
I4M2
0
0
I1C
I1M2
R
0
I4M0
R/W
0
0
I6C
I6M2
INTE56
93H
R
0
0
I3C
I3M2
R
0
0
0
0
I6M1
I6M0
I5C
I5M2
I8C
I8M2
INTE78
94H
R
0
R
INTTA0 &
INTTA1
enable
95H
ITA1C
0
0
0
I8M1
I8M0
I7C
I7M2
0
0
ITA1M1
R
R
0
0
0
ITA1M0
0
ITA3C
ITA3M2
ITA0C
INTETA23
INTETB0
INTETB1
INTTB00
&
INTTB01
enable
INTTB10
&
INTTB11
enable
96H
ITA3M1
R
0
0
ITB01C
ITB01M2
99H
R
0
ITA3M0
ITA2C
ITA2M2
ITB11C
0
ITB11M2
ITB11M1
R
0
0
I5M1
I5M0
0
0
I7M1
I7M0
R
0
0
ITA0M1
ITA0M0
0
0
ITA2M1
ITA2M0
R/W
0
0
0
ITB01M0
ITB00C
ITB00M2
0
0
INTTB00 (TMRB0)
R
0
0
ITB00M1
ITB00M0
R/W
0
0
0
INTTB10 (TMRB1)
ITB11M0
R/W
0
0
INTTA2 (TMRA2)
INTTB11 (TMRB1)
9AH
0
R/W
0
R/W
0
ITA0M2
0
INTTB01 (TMRB0)
ITB01M1
0
R
R/W
0
I3M0
R/W
0
INTTA3 (TMRA3)
INTTA2 &
INTTA3
enable
I3M1
INTTA0 (TMRA0)
R/W
0
0
INT7
R/W
ITA1M2
0
R/W
0
INTTA1 (TMRA1)
INTETA01
I1M0
INT5
INT8
INT7 &
INT8
enable
I1M1
R/W
0
R/W
0
0
R/W
INT6
INT5 &
INT6
enable
0
INT3
I4M1
R
I0M0
R/W
INT4
INTE34
I0M1
INT1
I2M1
R
0
INT0
INT2
INTE12
1
ITB10C
ITB10M2
R
0
0
ITB10M1
ITB10M0
R/W
0
0
0
Interrupt request flag
lxxM2
lxxM1
lxxM0
0
0
0
0
0
1
Disable interrupt requests.
Set the priority level to 1.
Function (Write)
0
1
0
Set the priority level to 2.
0
1
1
Set the priority level to 3.
1
0
0
Set the priority level to 4.
1
0
1
Set the priority level to 5.
1
1
0
Set the priority level to 6.
1
1
1
Disable interrupt requests.
91CW28-40
2006-03-24
TMP91CW28
Symbol
INTETB01V
Name
INTTBOF0
&
INTTBOF1
enable
Address
7
6
5
4
3
INTTBOF1 (TMRB1 overflow)
9BH
ITF1C
ITF1M2
ITF1M1
R
ITF1M0
R/W
0
0
−
−
2
ITF0C
ITF0M2
INTEBCD
9CH
0
0
−
−
IBCDC
IBCD1M2
−
INTES1
9DH
INTSBI0 &
INTSBI1
enable
9EH
IS1C
ITX1M0
R/W
0
0
0
IRX1C
IRX1M2
R
0
IS1M2
0
INTTC0 &
INTTC1
enable
A0H
ITC1C
IS1M0
R/W
0
0
ITC1M2
0
0
IS0C
IS0M2
0
ITC3C
ITC3M2
INTETC23
A1H
ITC1M1
0
ITC1M0
ITC0C
ITC0M2
R
IS0M1
IS0M0
0
0
ITC0M1
ITC0M0
R/W
0
0
0
ITC3M1
ITC3M0
ITC2C
ITC2M2
0
0
ITC2M1
ITC2M0
INTTC2
R/W
0
0
R/W
0
R
0
0
INTTC3
INTTC2 &
INTTC3
enable
IRX1M0
INTTC0
R/W
0
IRX1M1
0
R
0
R
0
R/W
INTTC1
INTETC01
0
INTSBI0
IS1M1
R
0
IBCD1M0
R/W
INTSBI1
INTES2
IBCD1M1
INTRX
ITX1M1
R
0
0
R
INTTX
ITX1M2
0
INTBCD
−
ITX1C
ITF0M0
R/W
0
Must be written as “0”.
INTRX &
INTTX
enable
0
ITF0M1
R
0
−
INTBCD
enable
1
INTTBOF0 (TMRB0 overflow)
0
R
0
0
R/W
0
0
0
Interrupt request flag
lxxM2
lxxM1
lxxM0
Function (Write)
0
0
0
Disable interrupt requests.
0
0
1
Set the priority level to 1.
0
1
0
Set the priority level to 2.
0
1
1
Set the priority level to 3.
1
0
0
Set the priority level to 4.
1
0
1
Set the priority level to 5.
1
1
0
Set the priority level to 6.
1
1
1
Disable interrupt requests.
Note: Bits7 to 4 of the INTEBCD are read as undefined.
91CW28-41
2006-03-24
TMP91CW28
(2) Controlling external interrupts
Symbol
Name
Address
7
6
5
4
−
I4EDGE
I3EDGE
I2EDGE
3
2
1
0
I1EDGE
I0EDGE
I0LE
NMIREE
0
0
0
W
IIMC
8CH
Interrupt
input
mode
control
0
Must be
written as
(RMW
prohibited) “0”.
0
0
0
0
INT4 edge INT3 edge INT2 edge INT1 edge INT0 edge INT0
polarity
polarity
polarity
polarity
sensitivity
polarity
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
0: Edgetriggered
1: Also
triggered by
NMI rising
edge
1: Levelsensitive
INT0 level detection enable
0
Edge sensitive INT
1
Active high level-sensitive INT
NMI rising edge enable
0
INT request occurs at falling edge
1
INT request occurs at rising/falling edge
(3) Interrupt request flag clear register
An interrupt request flag can be cleared by writing a micro DMA request vector (See
Table 3.4.1) to the INTCLR register.
For example, the INT0 interrupt flag can be cleared by the following register
operation after executing the DI instruction.
INTCLR ← 0AH: Clear the INT0 interrupt request flag
Symbol
Name
Address
INTCLR
Interrupt
clear
control
88H
(RMW
prohibited)
7
6
5
4
3
CLRV5
CLRV4
CLRV3
2
1
0
CLRV2
CLRV1
CLRV0
0
0
0
W
0
0
0
Interrupt vector
(4) Micro DMA request vector registers
A micro DMA request vector register specifies which interrupt source is targeted for
a micro DMA request. The interrupt source having the micro DMA request vector
specified in the register is assigned as the micro DMA request source.
When the micro DMA transfer counter reaches 0, the interrupt controller receives a
request from the CPU and generates a micro DMA transfer complete interrupt for the
relevant channel. Then, the CPU clears the micro DMA request vector register, thus
clearing the micro DMA request source for the channel. If it is necessary to continue
micro DMA processing for the same interrupt source, the interrupt controller must
reload the micro DMA request vector into the register during the service routine for the
micro DMA transfer completion interrupt.
If the same vector is set in micro DMA request vector registers for two or more
channels simultaneously, the channel having the smallest number takes precedence.
When the same vector is set in micro DMA request vector registers for two channels
simultaneously, micro DMA transfer is first performed with the channel having the
smaller number. Once transfer completes, micro DMA transfer for the channel having
the larger number starts (Micro DMA chaining), unless the interrupt controller reloads
the micro DMA request vector for the first channel.
91CW28-42
2006-03-24
TMP91CW28
Symbol
Name
DMA0V
DMA0
request
vector
Address
7
6
5
4
3
DMA0V5
DMA0V4
DMA0V3
2
1
0
DMA0V2
DMA0V1
DMA0V0
0
0
DMA1V1
DMA1V0
0
0
DMA2V1
DMA2V0
0
0
DMA3V1
DMA3V0
0
0
R/W
80H
0
0
0
0
DMA0 request vector
DMA1V5
DMA1V
DMA1
request
vector
DMA1V4
DMA1V3
DMA1V2
R/W
81H
0
0
0
0
DMA1 request vector
DMA2V
DMA2
request
vector
DMA2V5
DMA2V4
DMA2V3
0
0
0
DMA2V2
R/W
82H
0
DMA2 request vector
DMA3V5
DMA3V
DMA3
request
vector
DMA3V4
DMA3V3
DMA3V2
R/W
83H
0
0
0
0
DMA3 request vector
(5) Micro DMA burst specification
The micro DMA supports burst specification, with which a single micro DMA startup
can cause transfer to continue until the transfer counter register reaches zero. Burst
transfer can be specified by setting the DMAB register bit corresponding to a micro
DMA channel to 1.
If another interrupt request (Maskable or nonmaskable) is issued during a burst
transfer, the CPU first completes the burst transfer before servicing the interrupt.
Symbol
Name
Address
89H
DMAR
DMA
software
request
register
DMAB
DMA
burst
register
7
6
5
(RMW
prohibited)
4
3
2
1
0
DMAR3
DMAR2
DMAR1
DMAR0
R/W
R/W
R/W
R/W
0
0
0
0
1: DMA soft request
DMAB3
DMAB2
0
0
DMAB1
DMAB0
R/W
8AH
0
0
1: DMA burst request
91CW28-43
2006-03-24
TMP91CW28
(6) Precautions
The CPU consists of a separate instruction execution unit and bus interface unit. It
may fetch an instruction that clears the interrupt request flag for an interrupt (Note)
immediately before that instruction is issued. Once the CPU accepts an interrupt, it
may execute such an instruction before reading the interrupt vector. In such a case, the
CPU reads 0008H (Interrupt vector cleared) and reads the interrupt vector from
address FFFF08H.
To prevent the above situation from arising, the DI instruction should be executed
before an instruction for clearing an interrupt request flag. After the clear instruction
is executed, at least one instruction should be executed before the EI instruction is
executed to re-enable interrupts. If the EI instruction immediately follows the clear
instruction, interrupts may be enabled before the interrupt flag is cleared.
When the POP SR instruction is used to modify the interrupt mask level
(SR.IFF[2:0]), the DI instruction must be executed to disable interrupts before
executing the POP SR instruction.
Also note the following two exceptional circuits:
INT0 level detection
mode
When INT0 is used as a level-sensitive interrupt pin, rather than
edge-triggered, the interrupt request flip-flop is disabled so that a
peripheral interrupt request directly passes through the S input of the
flip-flop to appear at the S output. Modifying the mode (Edge to level)
causes the previous interrupt request flag to be cleared automatically.
If INT0 is driven from low to high, causing the CPU to start an
interrupt response sequence, INT0 must be held high until the
interrupt response sequence is completed. When INT0 in
level-sensitive mode is used to exit a HALT mode, INT0 must also be
held high once it is driven from low to high. Ensure that it is not
temporarily driven low due to noise during that period.
When the INT0 detection mode is changed from level to edge, any
interrupt request flag accepted in level-sensitive mode is not cleared.
Use the following sequence to clear the interrupt request flag:
DI
LD (IIMC), 00H
; Change from level to edge.
LD (INTCLR), 0AH ; Clear INT0 interrupt request flag.
NOP
; Wait EI instruction.
EI
INTRXn
Clearing the interrupt request flip-flop requires a system reset or
reading the serial channel receive buffer. It cannot be cleared by
writing INTCLR register.
Note: The following instructions and pin state transition are also equivalent to this type of
instruction:
INT0:
Instruction that changes the pin mode to level detection after an interrupt
occurs in edge-triggered mode.
Change in the pin input (from high to low) after an interrupt occurs
level-sensitive mode.
INTRXn: Instruction that reads the receive buffer.
91CW28-44
2006-03-24
TMP91CW28
3.5
I/O Ports
The TMP91CW28 has 80 I/O port pins. All the port pins except a few share pins with
alternate functions. They can be individually programmed as general-purpose I/O or dedicated
I/O for the on-chip CPU or peripherals. Table 3.5.1 shows all the I/O port pins available on the
TMP91CW28 and their shared functions. Table 3.5.2 to Table 3.5.4 give a summary of register
settings used to control the port pins.
Table 3.5.1 Programmable I/O Ports
Port
Pin Name
Port 0
Port 1
Pull
Direction
Resistor Programmability
# of Pins
Direction
P00 to P07
8
Input/output
−
Bitwise
AD0 to AD7
P10 to P17
8
Input/output
−
Bitwise
AD8 to AD15/A8 to A15
Alternate Functions
Port 2
P20 to P27
8
Input/output
−
Bitwise
A16 to A23/A0 to A7
Port 3
P30
P31
1
1
Output
Output
−
−
(Fixed)
(Fixed)
RD
P32
1
Input/output
Pull up
Bitwise
HWR
P33
1
Input/output
Pull up
Bitwise
WAIT
P34
1
Input/output
Pull up
Bitwise
BUSRQ
Port 4
Port 5
WR
P35
1
Input/output
Pull up
Bitwise
BUSAK
P36
1
Input/output
Pull up
Bitwise
R/ W
P37
1
Input/output
Pull up
Bitwise
P40
1
Input/output
Pull up
Bitwise
CS0
P41
1
Input/output
Pull up
Bitwise
CS1
P42
1
Input/output
Pull up
Bitwise
CS2
P43
1
Input/output
Pull up
Bitwise
CS3
P50 to P57
8
Input
−
(Fixed)
AN0 to AN7, ADTRG (P53)
KWI0 to KWI7
Port 6
Port 7
Port 8
Port 9
Port A
P60
1
Input/output
−
Bitwise
SCK0
P61
1
Input/output
Pull up
Bitwise
SO0/SDA0
P62
1
Input/output
Pull up
Bitwise
SI0/SCL0
P63
1
Input/output
−
Bitwise
INT0
P64
1
Input/output
−
Bitwise
SCOUT
P65
1
Input/output
−
Bitwise
P66
1
Input/output
−
Bitwise
P70
P71
1
1
Input/output
Input/output
Pull up
Pull up
Bitwise
Bitwise
TA0IN
TA1OUT
P72
1
Input/output
Pull up
Bitwise
TA3OUT
P73
1
Input/output
Pull up
Bitwise
P74
1
Input/output
Pull up
Bitwise
P75
1
Input/output
Pull up
Bitwise
P80
1
Input/output
Pull up
Bitwise
TB0IN0/INT5
P81
1
Input/output
Pull up
Bitwise
TB0IN1/INT6
P82
1
Input/output
Pull up
Bitwise
TB0OUT0
P83
1
Input/output
Pull up
Bitwise
TB0OUT1
P84
1
Input/output
Pull up
Bitwise
TB1IN0/INT7
P85
1
Input/output
Pull up
Bitwise
TB1IN1/INT8
P86
1
Input/output
Pull up
Bitwise
TB1OUT0
P87
1
Input/output
Pull up
Bitwise
TB1OUT1
P90
P91
1
1
Input/output
Input/output
−
Pull up
Bitwise
Bitwise
SCK1
SO1/SDA1
P92
1
Input/output
Pull up
Bitwise
SI1/SCL1
P93
1
Input/output
−
Bitwise
TXD
P94
1
Input/output
−
Bitwise
RXD
P95
1
Input/output
−
Bitwise
SCLK/ CTS
P96
1
Input/output
−
Bitwise
PA0 to PA3
4
Input/output
Pull up
Bitwise
PA4 to PA7
4
Input/output
Pull up
Bitwise
91CW28-45
INT1 to INT4
2006-03-24
TMP91CW28
Table 3.5.2 I/O Port Programmability (1/3)
Port
Port 0
Port 1
Port 2
Port 3
Pin Name
P00 to P07
P10 to P17
P20 to P27
P30
P31
P32 to P37
Port 5
I/O Register Settings
Pn
PnCR
Input port
×
0
Output port
×
1
PnFC
PUPn
N/A
N/A
AD0 to AD7 bus lines
×
×
Input port
×
0
0
Output port
×
1
0
AD8 to AD15 bus lines
×
0
1
A8 to A15 outputs
×
1
1
Input port
×
0
0
Output port
×
1
0
A0 to A7 outputs
×
0
1
1
1
N/A
0
A16 to A23 outputs
×
Output port
×
RD output during external accesses
1
N/A
N/A
1
N/A
RD always output
0
Output port
×
1
WR output during external accesses
×
Input port (with pull-up disabled)
0
0
0
Input port (with pull-up enabled)
1
0
0
Output port
×
1
0
1
N/A
N/A
N/A
N/A
0
1
P32
HWR output
×
1
P33
WAIT input (with pull-up disabled)
0
0
WAIT input (with pull-up enabled)
1
0
BUSRQ input (with pull-up disabled)
0
0
1
BUSRQ input (with pull-up enabled)
1
0
1
P34
Port 4
Direction/Function
N/A
N/A
N/A
P35
BUSAK output
×
1
1
N/A
P36
R/ W output
×
1
1
N/A
P40 to P43
Input port (with pull-up disabled)
0
0
0
Input port (with pull-up enabled)
1
0
0
Output port
×
1
0
P40
CS0 output
×
1
1
N/A
P41
CS1 output
×
1
1
N/A
P42
CS2 output
×
1
1
N/A
P43
CS3 output
×
1
1
N/A
P50 to P57
Input port
×
AN[0:7] inputs
(Note 1)
×
KWI[0:7] inputs
P53
ADTRG input
×
(Note 2)
N/A
N/A
×
×: Don’t care
Note 1: When P50 to P57 are configured as analog channels of the ADC, the ADCH[2:0] field in the
ADMOD1 register is used to select a channel(s).
Note 2: When P53 is configured as ADTRG , the ADTRGE bit in the ADMOD1 register is used to
enable and disable the external trigger input to the ADC.
91CW28-46
2006-03-24
TMP91CW28
Table 3.5.3 I/O Port Programmability (2/3)
Port
Port 6
Pin Name
PnCR
PnFC
PUPn
Input port
×
0
0
P63 to P67
Output port
×
1
0
P61, P62
Input port (with pull-up disabled)
×
×
×
0
Input port (with pull-up disabled)
0
0
0
1
Input port (with pull-up enabled)
1
0
0
1
Output port
×
1
0
×
P61
P62
Port 8
I/O Register Settings
Pn
P60,
P60
Port 7
Direction/Function
SCK0 input
×
0
0
SCK0 output
×
1
1
N/A
N/A
SDA0 input (with pull-up disabled)
×
×
×
0
SDA0 input (with pull-up disabled)
0
0
0
1
SDA0 input (with pull-up enabled)
1
0
0
1
SDA0 output
×
1
1
×
SO0 output
×
1
1
×
SI0 input (with pull-up disabled)
×
×
×
0
SI0 input (with pull-up disabled)
0
0
0
1
SI0 input (with pull-up enabled)
1
0
0
1
SCL0 input (with pull-up disabled)
×
×
×
0
SCL0 input (with pull-up disabled)
0
0
0
1
SCL0 input (with pull-up enabled)
1
0
0
1
SCL0 output
×
1
1
×
×
0
1
N/A
N/A
(Note 3)
(Note 3)
P63
INT0 input
P64
SCOUT output
×
1
1
P70 to P75
Input port (with pull-up disabled)
0
0
0
Input port (with pull-up enabled)
1
0
0
Output port
×
1
0
P70
TA0IN input
×
0
P71
TA1OUT output
×
1
1
N/A
P72
TA3OUT output
×
1
1
N/A
P80 to P87
Input port (with pull-up disabled)
0
0
0
Input port (with pull-up enabled)
1
0
0
Output port
×
1
0
TB0IN0, INT5 input (with pull-up disabled)
0
0
1
TB0IN0, INT5 input (with pull-up enabled)
1
0
1
TB0IN1, INT6 input (with pull-up disabled)
0
0
1
TB0IN1, INT6 input (with pull-up enabled)
1
0
1
P82
TB0OUT0 output
×
1
1
N/A
P83
TB0OUT1 output
×
1
1
N/A
P84
TB1IN0, INT7 input (with pull-up disabled)
0
0
1
TB1IN0, INT7 input (with pull-up enabled)
1
0
1
TB1IN1, INT8 input (with pull-up disabled)
0
0
1
TB1IN1, INT8 input (with pull-up enabled)
1
0
1
P80
P81
P85
N/A
N/A
N/A
N/A
N/A
N/A
N/A
P86
TB1OUT0 output
×
1
1
N/A
P87
TB1OUT1 output
×
1
1
N/A
×: Don’t care
Note 3: When P61 and P62 are configured as SDA0 and SCL0 outputs for the SBI, the ODE6[2:1]
field in the ODE register can be used to configure them as either push-pull or open-drain
outputs. Upon reset, the default is push-pull.
91CW28-47
2006-03-24
TMP91CW28
Table 3.5.4 I/O Port Programmability (3/3)
Port
Port 9
Pin Name
Direction/Function
PnCR
PnFC
PUPn
P90,
Input port
×
0
0
P93 to P96
Output port
×
1
0
P91, P92
Input port (with pull-up disabled)
×
×
×
0
Input port (with pull-up disabled)
0
0
0
1
Input port (with pull-up enabled)
1
0
0
1
Output port
×
1
0
×
P90
P91
SCK1 input
×
0
0
×
1
1
SDA1 input (with pull-up disabled)
×
×
×
0
SDA1 input (with pull-up disabled)
0
0
0
1
SDA1 input (with pull-up enabled)
1
0
0
1
SDA1 output
P92
(Note 4)
×
1
1
×
1
1
×
SI1 input (with pull-up disabled)
×
×
×
0
SI1 input (with pull-up disabled)
0
0
0
1
SI1 input (with pull-up enabled)
1
0
0
1
SCL1 input (with pull-up disabled)
×
×
×
0
SCL1 input (with pull-up disabled)
0
0
0
1
SCL1 input (with pull-up enabled)
1
0
0
1
SCL1 output
×
1
1
×
1
N/A
(Note 4)
TXD output
×
1
P94
RXD input
×
0
P95
SCLK input
×
0
PA0
PA1
PA2
PA3
N/A
×
P93
PA0 to PA7
N/A
SCK1 output
SO1 output
Port A
I/O Register Settings
Pn
N/A
0
SCLK output
×
1
1
CTS input
×
0
0
Input port (with pull-up disabled)
0
0
0
Input port (with pull-up enabled)
1
0
0
Output port
×
1
0
INT1 input (with pull-up disabled)
0
0
1
INT1 input (with pull-up enabled)
1
0
1
INT2 input (with pull-up disabled)
0
0
1
INT2 input (with pull-up enabled)
1
0
1
INT3 input (with pull-up disabled)
0
0
1
INT3 input (with pull-up enabled)
1
0
1
INT4 input (with pull-up disabled)
0
0
1
INT4 input (with pull-up enabled)
1
0
1
N/A
N/A
N/A
N/A
N/A
N/A
×: Don’t care
Note 4: When P91 and P92 are configured as SDA1 and SCL1 outputs for the SBI, the ODE9[2:1]
field in the ODE register can be used to configure them as either push-pull or open-drain
outputs. Upon reset, the default is push-pull.
91CW28-48
2006-03-24
TMP91CW28
Upon reset, the port pins function as general-purpose input/output ports. Pins that can be
programmed for either input or output are input ports by default. Programming is necessary to
use port pins for alternate functions.
Notes on using the programmable pull-up function when the bus is relinquished
When the bus is relinquished ( BUSAK = 0), the output buffers for AD0 to AD15, A0 to A23 and
bus control signals ( RD , WR , HWR , R / W , CS0 to CS3 ) are disabled and placed in
high-impedance state. On-chip programmable pull-up resistors are, however, still active.
Whether these resistors are enabled can be selected only when the pin is used in input mode.
Table 3.5.5 shows the status of pins when the bus is relinquished.
Table 3.5.5 Pin Status when the Bus is Relinquished
Pin Name
P00 to P07
(AD0 to AD7)
Status
Port Mode
Function Mode
Not changed
(Not placed in high-impedance state)
Placed in high-impedance state
Not changed
(Not placed in high-impedance state)
Output buffer disabled (after the pin is driven high)
Not changed
(Not placed in high-impedance state)
Output buffer disabled (after the pin is driven high)
Not changed
(Not placed in high-impedance state)
Output buffer disabled. The on-chip pull-up resistor is
enabled regardless of the value contained in the
output latch.
Not changed
(Not placed in high-impedance state)
Output buffer disabled. The on-chip pull-up resistor is
enabled regardless of the value contained in the
output latch.
P10 to P17
(AD8 to AD15/
A8 to A15)
P20 to P27
(A16 to A23)
P30 ( RD )
P31 ( WR )
P32 ( HWR )
P37
P36 (R/ W )
P40 ( CS0 )
P41 ( CS1 )
P42 ( CS2 )
P43 ( CS3 )
91CW28-49
2006-03-24
TMP91CW28
Figure 3.5.1 shows an example external interface for the above signals when the bus
relinquish function is used.
When the bus is relinquished, the on-chip memory and peripherals cannot be accessed but
the on-chip peripherals continue operation, so that the watchdog timer (WDT) keeps counting.
The period for which the bus is relinquished must be taken into account to set the WDT
time-out period when using the bus relinquish function.
P30 ( RD )
P31 ( WR )
P32 ( HWR )
P36 (R/ W )
P40 ( CS0 )
P41 ( CS1 )
System control bus
P42 ( CS2 )
P43 ( CS3 )
P20 (A16)
Upper address bus (A23 to A16)
:
P27 (A23)
Figure 3.5.1 Example External Bus Interface when the Bus Relinquish Function is Used
A circuit as shown above is required when an external pull-up resistor is connected to fix a
signal level with the bus relinquished.
Upon reset, P30 ( RD ) and P31 ( WR ) are output pins while P40 to P43 ( CS0 to CS3 ), P32
( HWR ), P36 (R/ W ) and P35 ( BUSAK ) are input pins with pull-up resistors enabled.
91CW28-50
2006-03-24
TMP91CW28
Port 0 (P00 to P07)
Eight port 0 pins function as either discrete general-purpose I/O pins or the AD[0:7] bits
of the address/data bus. The P0CR register controls the direction of the port 0 pins. Upon
reset, the P0CR register bits are cleared, configuring all port 0 pins as inputs.
During external memory accesses, port 0 pins are automatically configured as AD[0:7],
with the P0CR register bits all cleared.
Reset
Direction control
(Bitwise)
P0CR write
Internal data bus
3.5.1
Port 0
Output latch
Output buffer
P00 to P07
(AD0 to AD7)
P0 write
P0 read
Figure3.5.2 Port 0
91CW28-51
2006-03-24
TMP91CW28
Port 1 (P10 to P17)
Eight port 1 pins can be individually programmed to function as discrete general-purpose
I/O pins, the AD[8:15] bits of the address/data bus or the A[8:15] bits of the address bus.
The P1CR and P1FC registers select the direction and function of the port 1 pins. Upon
reset, the output latch (P1) is cleared, and the P1CR and P1FC register bits are cleared to
all 0s, configuring all port 1 pins as input port pins.
Reset
Direction control
(Bitwise)
P1CR write
Function control
(Bitwise)
Internal data bus
3.5.2
P1FC write
Output latch
Output buffer
P1 write
Port 1
P10 to P17
(AD8 to AD15/A8 to A15)
P1 read
Figure3.5.3 Port 1
91CW28-52
2006-03-24
TMP91CW28
Port 0 Register
P0
(0000H)
Bit symbol
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
Read/Write
R/W
Reset value
Data from external port (Output latch register is undefined)
Port 0 Control Register
P0CR
(0002H)
Bit symbol
7
6
5
4
3
2
1
0
P07C
P06C
P05C
P04C
P03C
P02C
P01C
P00C
0
0
0
0
0
0
0
0
Read/Write
Reset value
Function
W
0: Input 1: Output (Functions as AD7 to AD0 during external memory accesses, with all bits cleared.)
Port 0 direction settings
0 Input port
1
Output port
Port 1 Register
P1
(0001H)
Bit symbol
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
Read/Write
R/W
Reset value
Data from external port (Output latch register is cleared to 0)
Port 1 Control Register
P1CR
(0004H)
Bit symbol
7
6
5
4
3
2
1
0
P17C
P16C
P15C
P14C
P13C
P12C
P11C
P10C
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
<<Refer to P1FC.>>
Port 1 Function Register
P1FC
(0005H)
Bit symbol
7
6
5
4
3
2
1
0
P17F
P16F
P15F
P14F
P13F
P12F
P11F
P10F
0
0
0
0
0
0
0
0
Read/Write
Reset value
Function
W
P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8
Note: P0CR, P1CR, and P1FC do
not support read-modify-write
operation.
Port 1 function settings
P1FC.P1XF
0
1
P1CR.P1XC
0
Input port
1
Output port
Address/Data bus
(AD15 to AD8)
Address bus
(A15 to A8)
Note: P1XF and P1XC mean bit X in the P1FC and P1CR
registers respectively.
Figure3.5.4 Port 0 and 1 Registers
91CW28-53
2006-03-24
TMP91CW28
Port 2 (P20 to P27)
A16 to A23
B
A0 to A7
A
Selector
Eight port 2 pins can be individually programmed to function as discrete general-purpose
I/O pins, the A[0:7] bits of the address bus or the A[16:23] bits of the address bus. The P2CR
and P2FC registers select the direction and function of the port 2 pins. Upon reset, the
output latch (P2) is cleared, and the P2CR and P2FC register bits are cleared to all 0s,
configuring all port 2 pins as input port pins.
Y
Reset
S
Direction control
(Bitwise)
P2CR write
Function control
(Bitwise)
P2FC write
S
B
Output latch
A
Selector
Internal data bus
3.5.3
Y
Output buffer
Port 2
P20 to P27
(A0 to A7/A16 to A23)
P2 write
P2 read
Figure3.5.5 Port 2
91CW28-54
2006-03-24
TMP91CW28
Port 2 Register
P2
(0006H)
Bit symbol
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Read/Write
R/W
Reset value
Data from external port (Output latch register is set to 1)
Port 2 Control Register
P2CR
(0008H)
Bit symbol
7
6
5
4
3
2
1
0
P27C
P26C
P25C
P24C
P23C
P22C
P21C
P20C
0
0
0
0
Read/Write
Reset value
W
0
0
0
0
Function
Refer to P2FC
Port 2 Function Register
P2FC
(0009H)
Bit symbol
7
6
5
4
3
2
1
0
P27F
P26F
P25F
P24F
P23F
P22F
P21F
P20F
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
P2FC/P2CR = 00: Input, 01: Output, 10: A7 to A0, 11: A23 to A16
Note: P2CR and P2FC do not support
read-modify-write operation.
Port 2 function settings
P2FC.P2XF
0
1
P2CR.P2XC
Note:
0
Input port
Address bus
(A7 to A0)
1
Output port
Address bus
(A23 to A16)
P2XF and P2XC mean bit X in the P2FC and P2CR
registers respectively.
When using the pin as address bus A23 to A16, set the
P2CR before setting the P2FC.
Figure3.5.6 Port 2 Registers
91CW28-55
2006-03-24
TMP91CW28
3.5.4
Port 3 (P30 to P37)
Eight port 3 pins can be individually programmed to function as either discrete
general-purpose I/O pins or CPU control/status pins. In either case, P30 and P31 are
output-only pins.
The P3CR and P3FC registers select the direction and function of the port 3 pins. Upon
reset, the P3CR and P3FC register bits are cleared, configuring P30 and P31 as output port
pins and P32 to P37 as input port pins with pull-up enabled. (Bits 0 and 1 in the P3CR and
bits 3 and 7 in the P3FC are unused.) Upon reset, the output latch (P3) is set to all 1s; so
logic 1 appears on P30 and P31.
When P30 is configured as RD (P3FC.P30F = 1), the read strobe signal is activated only
when external address space is accessed, if the P30 bit of the output latch is set to 1
(Default). Clearing P30 to 0 enables the read strobe signal to be also activated when on-chip
address space is accessed. This feature is provided for accessing pseudo static RAM.
91CW28-56
2006-03-24
TMP91CW28
Reset
Function control
P3FC write
S
S
Output latch
A
B
P30( RD )
Selector
Internal data bus
(Bitwise)
P31( WR )
Output buffer
P3 write
RD
,
WR
P3 read
Reset
Direction control
(Bitwise)
P3CR write
(Bitwise)
P-ch
P3FC write
Programmable
pull-up resistor
S
S
Output latch
A
B
Selector
Internal data bus
Function control
P32( HWR )
Output buffer
P3 write
P35( BUSAK )
P36(R/ W )
HWR , BUSAK , R/ W
P37
P3 read
Figure3.5.7 Port 3 (P30, P31, P32, P35, P36, P37)
91CW28-57
2006-03-24
TMP91CW28
Reset
Direction control
(Bitwise)
P-ch
Internal data bus
P3CR write
S
Output latch
Programmable
pull-up resistor
P33 ( WAIT )
Output buffer
P3 write
Internal
WAIT
P3 read
Reset
Direction control
(Bitwise)
P3CR write
Internal data bus
Function control
(Bitwise)
P3FC write
P-ch
S
Output latch
Programmable
pull-up resistor
P34 ( BUSRQ )
P3 write
Internal
BUSRQ
P3 read
Figure3.5.8 Port 3 (P33, P34)
91CW28-58
2006-03-24
TMP91CW28
Port 3 Register
P3
(0007H)
Bit symbol
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
Read/Write
R/W
Reset value
Data from external port (Output latch register is set to 1)
1
1
−
0 (Output latch register) : Pull-up resistor disabled
Function
1 (Output latch register) : Pull-up resistor enabled
Port 3 Control Register
P3CR
(000AH)
Bit symbol
7
6
5
4
3
2
P37C
P36C
P35C
P34C
P33C
P32C
0
0
0
0
0
0
Read/Write
Reset value
1
0
W
Function
0: Input
1: Output
Port 3 direction settings
0 Input port
1 Output port
Port 3 Function Register
P3FC
(000BH)
Bit symbol
7
6
5
4
2
1
0
−
P36F
P35F
P34F
P32F
P31F
P30F
0
0
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
1: R/ W
1: BUSAK
1: BUSRQ
1: HWR
1: WR
1: RD
Read/Write
Reset value
Function
3
W
Must be
written as
“0”.
W
P30 ( RD ) function settings
P30
0
1
P30F
BUSRQ settings
P3FC.P34F
1
P3CR.P34C
0
0
1
BUSAK settings
Output a “0”.
Output a “1”.
Always assert
Assert RD only
RD (for pseudo
P3FC.P35F
1
P3CR.P35C
1
R/ W settings
P3FC.P36F
1
P3CR.P36C
1
Note 1: P3CR and P3FC do not support read-modify-write operation.
Note 2: When a port 3 pin is used in input mode, the P3 register controls the
on-chip pull-up resistor. A read-modify-write instruction cannot be
executed if at least one pin of port 3 is placed in input mode. A
read-modify-write instruction may modify the on-chip pull-up setting for
an input pin depending on the current pin status.
Note 3: When the P33/ WAIT pin is used as the WAIT pin, the P3CR.P33C bit
must be cleared and the BnW[2:0] bits (Bits 3 to 1 of the chip
select/wait control register) must be set to 010.
during external
accesses.
SRAM).
P31 ( WR ) function settings
P31
0
1
P31F
0
1
Output a “0”. Output a “1”.
Assert WR only during
external accesses.
HWR settings
P3FC.P32F
1
P3CR.P32C
1
Figure3.5.9 Port 3 Registers
91CW28-59
2006-03-24
TMP91CW28
3.5
Port 4 (P40 to P43)
Four port 4 pins can be individually programmed to function as either discrete
general-purpose I/O pins or programmable chip select ( CS0 to CS3 ) pins. The P4CR and
P4FC registers select the direction and function of the port 4 pins. Upon reset, the output
latch (P4) is set to all 1s and the P4CR and P4FC register bits are cleared, configuring all
the port 4 pins as input port pins having internal pull-up resistors.
Reset
Direction control
(Bitwise)
P4CR write
Function control
(Bitwise)
P-ch
P4FC write
Programmable
pull-up resistor
S
S
Output latch
A
B
Selector
Internal data bus
3.5.5
Output buffer
P4 write
CS0 , CS1 , CS2 , CS3
P40 ( CS0 ),
P41 ( CS1 ),
P42 ( CS2 ),
P43 ( CS3 )
P4 read
Figure 3.5.10 Port 4
91CW28-60
2006-03-24
TMP91CW28
Port 4 Register
7
P4
(000CH)
6
5
4
Bit symbol
3
2
1
0
P43
P42
P41
P40
Read/Write
R/W
Reset value
Data from external port
(Output latch register is set to 1)
0 (Output latch register): Pull-up resistor disabled
1 (Output latch register): Pull-up resistor enabled
Function
Port 4 Control Register
7
P4CR
(000EH)
6
5
4
Bit symbol
3
2
1
0
P43C
P42C
P41C
P40C
0
0
0
0
Read/Write
W
Reset value
Function
0: Input
1: Output
Port 4 direction settings
0 Input port
1 Output port
Port 4 Function Register
7
P4FC
(000FH)
6
5
4
Bit symbol
3
2
1
0
P43F
P42F
P41F
P40F
0
0
0
0
Read/Write
W
Reset value
Function
0: Port
Note 1: P4CR and P4FC do not support read-modify-write
operation.
Note 2: When a port 4 pin is used in input mode, the P4 register
controls the on-chip pull-up resistor. A read-modify-write
instruction cannot be executed if at least one pin of port 4
is placed in input mode. A read-modify-write instruction
may modify the on-chip pull-up setting for an input pin
depending on the current pin status.
Note 3: To output chip select signals ( CS0 to CS3 ), first set the
corresponding bits in the function register (P4FC) to 1
and then set the corresponding bits in the control register
(P4CR) to 1.
1: CS
0 Port (P40)
1
CS0
0 Port (P41)
1
CS1
0 Port (P42)
1
CS2
0 Port (P43)
1
CS3
Figure 3.5.11 Port 4 Registers
91CW28-61
2006-03-24
TMP91CW28
3.5.6
Port 5 (P50 to P57)
Eight port 5 pins are input-only pins shared with the analog input pins of the AD
converter (ADC) as well as KWI input pins. P53 is also shared with the AD trigger input
pin.
Internal data bus
Port 5
Port 5 read
AD
conversion
AD read
result
register
AD
converter
Channel
selector
ADTRG
(Only P53)
KWI0 to KWI7
Figure 3.5.12 Port 5
Port 5 Register
P5
(000DH)
Bit symbol
7
6
5
4
3
2
1
0
P57
P56
P55
P54
P53
P52
P51
P50
Read/Write
R
Reset value
Data from external port
Figure 3.5.13 Port 5 Register
Note 1: The AD converter mode register (ADMOD1) is used to select an AD converter input channel(s) and
to enable the AD trigger input for P53.
Note 2: The KWI control register (KWIC) is used to select a KWI input channel(s) and to enable the KWI
input.
91CW28-62
2006-03-24
TMP91CW28
Port 6 (P60 to P66)
Seven port 6 pins can be individually programmed to function as either discrete
general-purpose I/O pins or serial bus interface (SBI) pins. Upon reset, the output latch
(P6) is set to all 1s and all port 6 pins are configured as input port pins.
Setting the P6FC register bits configures the corresponding port 6 pins for dedicated
functions.
A reset clears all the P6CR and P6FC register bits, configuring all port 6 pins as input
port pins; P61 and P62 have an internal pull-up resistor.
(1) P60 (SCK0)
P60 can be programmed to function as a general-purpose I/O pin or an SCK0 clock
input or output pin for the serial bus interface in SIO mode.
Reset
Direction control
(Bitwise)
P6CR write
Function control
Internal data bus
3.5.7
(Bitwise)
P6FC write
S
Output latch
A
S
Selector
SCK0 output
P60 (SCK0)
P6 write
B
S B
Selector
P6 read
A
SCK0 input
Figure 3.5.14 Port 6 (P60)
91CW28-63
2006-03-24
TMP91CW28
(2) P61 (SO0/SDA0)
P61 can be programmed to function as a general-purpose I/O pin, an SDA0 data
input pin for the serial bus interface in I2C bus mode, or an SO0 data output pin for the
serial bus interface in SIO mode. P61 is configurable as an open-drain output and has a
programmable pull-up resistor.
When P61 is used as an open-drain output and does not require a pull-up resistor,
the pull-up resistor can be disconnected by clearing the PUP.PUP61 register bit to 0.
Reset
Pull-up control
(Bitwise)
PUP write
Direction control
(Bitwise)
P6CR write
Function control
Internal data bus
(Bitwise)
P6FC write
S
Output latch
Programmable pull-up
P-ch resistor: PUP.PUP61
A
S
Selector
P61 (SO0/SDA0)
P6 write
SO0 output
Configurable as
B
open-drain output:
ODE.ODE61
S B
Selector
P6 read
A
SDA0 input
Figure 3.5.15 Port 6 (P61)
91CW28-64
2006-03-24
TMP91CW28
(3) P62 (SI0/SCL0)
P62 can be programmed to function as a general-purpose I/O pin, an SI0 data input
pin for the serial bus interface in SIO mode, or an SCL0 clock input or output pin for
the serial bus interface in I2C bus mode. P62 is configurable as an open-drain output
and has a programmable pull-up resistor.
When P62 is used as an open-drain output and does not require a pull-up resistor,
the pull-up resistor can be disabled by clearing the PUP.PUP62 register bit to 0.
Reset
Pull-up control
(Bitwise)
PUP write
Direction control
(Bitwise)
P6CR write
Function control
Internal data bus
(Bitwise)
P6FC write
P-ch
S
Output latch
A
S
Selector
P6 write
SCL0 output
Programmable pull-up
resistor: PUP.PUP62
P62 (SI0/SCL0)
Configurable as
open-drain output:
ODE.ODE62
B
S B
Selector
P6 read
A
SI0 input
SCL0 input
Figure 3.5.16 Port 6 (P62)
91CW28-65
2006-03-24
TMP91CW28
(4) P63 (INT0)
P63 can be programmed to function as a general-purpose I/O pin or an external
interrupt request pin (INT0).
Reset
Direction control
(Bitwise)
P6CR write
Internal data bus
Function control
(Bitwise)
P6FC write
S
Output latch
P63 (INT0)
P6 write
S B
Selector
P6 read
INT0
A
Level/edge sensitivity
&
positive/negative polarity
IIMC.I0LE, IIMC.I0EDGE
Figure 3.5.17 Port 6 (P63)
91CW28-66
2006-03-24
TMP91CW28
(5) P64 (SCOUT)
P64 can be programmed to function as a general-purpose I/O pin or a system clock
output (SCOUT) pin.
Reset
Direction control
(Bitwise)
P6CR write
Function control
Internal data bus
(Bitwise)
P6FC
S
Output latch
S
A
Y
Selector
B
P6 write
P64 (SCOUT)
S
B
Selector
Y
A
P6 read
A
fFPH clock
Y
Selector
B
S
SYSCR.SCOSEL
Figure 3.5.18 Port 6 (P64)
(6) P65 and P66
P65 and P66 function as general-purpose I/O pins.
Reset
Internal data bus
Direction
control
(Bitwise)
P6CR write
S
Output latch
P6 write
P65
P66
S
B
Selector
P6 read
A
Figure 3.5.19 Port 6 (P65, P66)
91CW28-67
2006-03-24
TMP91CW28
Port 6 Register
7
P6
(0012H)
Bit symbol
6
5
4
3
2
1
0
P66
P65
P64
P63
P62
P61
P60
Read/Write
R/W
Reset value
Data from external port (Output latch register is set to 1)
Function
0 (Output latch register)
:Pull-up resistor disabled
−
−
1 (Output latch register)
: Pull-up resistor enabled
Port 6 Control Register
7
P6CR
(0014H)
Bit symbol
6
5
4
3
2
1
0
P66C
P65C
P64C
P63C
P62C
P61C
P60C
0
0
0
0
0
0
Read/Write
W
Reset value
Function
0
0: Input
1: Output
Port 6 direction settings
0 Input port
1 Output port
Port 6 Function Register
7
P6FC
(0015H)
4
3
2
1
0
Bit symbol
P64F
P63F
P62F
P61F
P60F
Read/Write
W
W
W
W
W
Reset value
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
0: Port
1: SCOUT
output
1: INT0
input
1: SCL0
output
1: SDA0/SO0 1: SCK0
output
output
Function
Note 1:
Note 2:
6
5
P6CR and P6FC do not support read-modify-write
operation.
When a port 6 pin is used in input mode, the P6 register
controls the on-chip pull-up resistor. A read-modify-write
instruction cannot be executed if at least one pin of port 6
is placed in input mode. A read-modify-write instruction
may modify the on-chip pull-up setting for an input pin
depending on the current pin status.
SCK0 output settings for P60
P6FC.P60F
1
P6CR.P60C
1
SDA0/SO0 output settings for P61
P6FC.P61F
1
P6CR.P61C
1
SCL0 output settings for P62
P6FC.P62F
1
P6CR.KP62C
1
INT0 input settings for P63
P6FC.P63F
1
P6CR.P63C
0
SCOUT output settings for P64
P6FC.P64F
1
P6CR.P64C
1
Figure 3.5.20 Port 6 Registers
91CW28-68
2006-03-24
TMP91CW28
3.5
3.5.8
Port 7 (P70 to P75)
Six port 7 pins can be individually programmed to function as discrete general-purpose
or dedicated I/O pins. Upon reset, all port 7 pins are configured as input port pins.
Alternatively, P70 can be programmed as the clock input (TA0IN) to 8-bit timer 0. P71 and
P72 can each be programmed as the timer output (TA1OUT or TA3OUT) from an 8-bit
timer. Setting the P7FC register bits configures the corresponding port 7 pins as timer
output pins. A reset clears the P7CR and P7FC register bits, configuring all port 7 pins as
input port pins having internal pull-up resistors.
91CW28-69
2006-03-24
TMP91CW28
Reset
Direction
control
(Bitwise)
P-ch Programmable
pull-up resistor
P7CR write
S
P70 (TA0IN)
Output latch
S
P7 write
B
Selector
P7 read
TA0IN
A
Reset
Internal data bus
Direction
control
(Bitwise)
P7CR write
Function
control
(Bitwise)
P7FC write
S
Programmable
P-ch pull-up resistor
Output latch
A
P7 write
Timer flip-flop
S
Selector
P71 (TA1OUT)
P72 (TA3OUT)
B
TA1OUT: from TMRA1
OUT
TA3OUT: from TMRA3
B
Selector
P7 read
S
A
Reset
R
Direction
control
(Bitwise)
Programmable
P-ch pull-up resistor
P7CR write
Internal data bus
S
Output
latch
P73 to P75
P7 Write
S
B
Selector
Y
A
P7 read
Figure 3.5.21 Port 7
91CW28-70
2006-03-24
TMP91CW28
Port 7 Register
7
P7
(0013H)
6
Bit symbol
5
4
3
P75
P74
P73
2
1
0
P72
P71
P70
Read/Write
R/W
Reset value
Data from external port (Output latch register is set to 1)
0 (Output latch register) : Pull-up resistor disabled
Function
1 (Output latch register) : Pull-up resistor enabled
Port 7 Control Register
7
P7CR
(0016H)
6
Bit symbol
5
4
3
2
1
0
P75C
P74C
P73C
P72C
P71C
P70C
0
0
0
0
0
0
Read/Write
W
Reset value
Function
0: Input
1: Output
Port 7 direction settings
0 Input port
1 Output port
Port 7 Function Register
7
P7FC
(0017H)
6
5
4
3
Bit symbol
2
P72F
Read/Write
Function
Note 2:
Note 3:
0
P71F
W
Reset value
Note 1:
1
P7CR and P7FC do not support read-modify-write
operation.
When a port 7 pin is used in input mode, the P7 register
controls the on-chip pull-up resistor. A read-modify-write
instruction cannot be executed if at least one pin of port 7
is placed in input mode. A read-modify-write instruction
may modify the on-chip pull-up setting for an input pin
depending on the current pin status.
The P70/TA0IN pin does not have a register bit for
selecting the port or timer function. The input to the
P70/TA0IN pin is always directed to 8-bit timer 0 even
when the pin is used as a general-purpose input pin.
0
0
0: Port
0: Port
1: TA3OUT
1: TA1OUT
Timer output 1 setting for P71
P7FC.P71F
1
P7CR.P71C
1
Timer output 3 settings for P72
P7FC.P72F
1
P7CR.P72C
1
Figure 3.5.22 Port 7 Registers
91CW28-71
2006-03-24
TMP91CW28
3.5.9
Port 8 (P80 to P87)
Eight port 8 pins can be individually programmed to function as discrete general-purpose
or dedicated I/O pins. Upon reset, all port 8 pins are configured as input port pins, and the
output latch (P8) is set to all 1s. port 8 pins can be programmed as clock inputs to 16-bit
timers, timer flip-flop outputs from 16-bit timers, or external interrupt request pins (INT5
through INT8). Setting the P8FC register bits configures the corresponding port 8 pins for
dedicated functions. A reset clears the P8CR and P8FC register bits, configuring all port 8
pins as input port pins having internal pull-up resistors.
(1) P80 to P87
Reset
Direction
control
(Bitwise)
P8CR write
Function
control
(Bitwise)
P-ch
P8FC write
Programmable
pull-up resistor
S
P80 (TB0IN0/INT5)
P81 (TB0IN1/INT6)
P84 (TB1IN0/INT7)
P85 (TB1IN1/INT8)
Output latch
S
B
P8 write
Internal data bus
Selector
P8 read
TB0IN0, INT5
TB0IN1, INT6
TB1IN0, INT7
TB1IN1, INT8
A
Reset
Direction
control
(Bitwise)
P8CR write
Function
control
(Bitwise)
P8FC write
P-ch
S
Output
latch
Timer flip-flop
output
P8 write
A
Programmable
pull-up resistor
S
P82 (TB0OUT0)
P83 (TB0OUT1)
P86 (TB1OUT0)
P87 (TB1OUT1)
Selector
B
TB0OUT0: From TMRB0
TB0OUT1: From TMRB0
TB1OUT0: From TMRB1
TB1OUT1: From TMRB1
B
Selector
P8 read
S
A
Figure 3.5.23 Port 8 (P80 to P87)
91CW28-72
2006-03-24
TMP91CW28
Port 8 Register
Bit symbol
P8
(0018H) Read/Write
7
6
5
4
P87
P86
P85
P84
3
2
1
0
P83
P82
P81
P80
R/W
Reset value
Data from external port (Output latch register is set to 1)
0 (Output latch register) : Pull-up resistor disabled
Function
1 (Output latch register) : Pull-up resistor enabled
Port 8 Control Register
Bit symbol
P8CR
(001AH) Read/Write
Reset value
7
6
5
4
3
2
1
0
P87C
P86C
P85C
P84C
P83C
P82C
P81C
P80C
0
0
0
0
0
0
0
0
W
Function
0: Input
1: Output
Port 8 direction settings
0 Input port
1 Output port
Port 8 Function Register
Bit symbol
P8FC
(001BH) Read/Write
Reset value
Function
7
6
5
4
3
2
1
0
P87F
P86F
P85F
P84F
P83F
P82F
P81F
P80F
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
1: TB1OUT1
1: TB1OUT0
1: TB1IN1,
1: TB1IN1,
1: TB0OUT1
1: TB0OUT0
1: TB0IN1
1: TB0IN0
INT8 input
INT7 input
Note 1: P8CR and P8FC do not
support read-modify-write
operation.
Note 2: When a port 8 pin is used in
input mode, the P8 register
controls the on-chip pull-up
resistor. A read-modify-write
instruction cannot be
executed if at least one pin of
port 8 is placed in input
mode. A read-modify-write
instruction may modify the
on-chip pull-up setting for an
input pin depending on the
current pin status.
INT6 input
INT5 input
Timer output 4 settings for P82
P8FC.P82F
1
P8CR.P82C
1
Timer output 5 settings for P83
P8FC.P83F
1
P8CR.P83C
1
Timer output 6 settings for P86
P8FC.P86F
1
P8CR.P86C
1
Timer output 7 settings for P87
P8FC.P87F
1
P8CR.P87C
1
Figure 3.5.24 Port 8 Registers
91CW28-73
2006-03-24
TMP91CW28
Port 9 (P90 to P96)
Seven port 9 pins can be individually programmed to function as discrete
general-purpose or dedicated I/O pins. Upon reset, all port 9 pins are configured as input
port pins, and the output latch (P9) is set to all 1s. port 9 pins can be programmed as SIO
input or output pins.
Setting the P9FC register bits configures the corresponding port 9 pins for dedicated
functions.
A reset clears all the P9CR and P9FC register bits, configuring all port 9 pins as input
port pins; P91 and P92 have an internal pull-up resistor.
(1) P90 (SCK1)
P90 can be programmed to function as a general-purpose I/O pin or an SCK1 clock
input or output pin for the serial bus interface in SIO mode.
Reset
Direction
control
(Bitwise)
P9CR write
Function
control
(Bitwise)
Internal data bus
3.5.10
P9FC write
S
Output latch
A
S
Selector
SCK1
output
P9 write
P90 (SCK1)
B
S B
Selector
P9 read
A
SCK1 input
Figure 3.5.25 Port 9 (P90)
91CW28-74
2006-03-24
TMP91CW28
(2) P91 (SO1/SDA1)
P91 can be programmed to function as a general-purpose I/O pin, an SDA1 data
input pin for the serial bus interface in I2C bus mode, or an SO1 data output pin for the
serial bus interface in SIO mode. P91 is configurable as an open-drain output and has a
programmable pull-up resistor.
When P91 is used as an open-drain output and does not require a pull-up resistor,
the pull-up resistor can be disabled by clearing the PUP.PUP91 register bit to 0.
Reset
Pull-up
control
(Bitwise)
PUP write
Direction
control
(Bitwise)
Internal data bus
P9CR write
Function
control
(Bitwise)
P9FC write
P-ch
S
Output latch
P9 write
SO1
output
A
Programmable pull-up
resistor: PUP.PUP91
S
Selector
P91 (SO1/SDA1)
Configurable as
open-drain
output:
ODE.ODE91
B
S B
Selector
P9 read
A
SDA1 input
Figure 3.5.26 Port 9 (P91)
91CW28-75
2006-03-24
TMP91CW28
(3) P92 (SI1/SCL1)
P92 can be programmed to function as a general-purpose I/O pin, an SI1 data input
pin for the serial bus interface in SIO mode, or an SCL1 clock input or output pin for
the serial bus interface in I2C bus mode. P92 is configurable as an open-drain output
and has a programmable pull-up resistor.
When P92 is used as an open-drain output and does not require a pull-up resistor,
the pull-up resistor can be disabled by clearing the PUP.PUP92 register bit to 0.
Reset
Pull-up
control
(Bitwise)
PUP write
Internal data bus
Direction
control
(Bitwise)
P9CR write
Function
control
(Bitwise)
P9FC write
P-ch
S
Output latch
P9 write
SCL1
output
A
S
Programmable pull-up
resistor: PUP.PUP92
P92 (SI1/SCL1)
Selector
B
Configurable as
open-drain output:
ODE.ODE92
S B
Selector
P9 read
A
SI1 input
SCL1 input
Figure 3.5.27 Port 9 (P92)
91CW28-76
2006-03-24
TMP91CW28
(4) P93 (TXD)
P93 can be programmed to function as a general-purpose I/O pin or a TXD output pin
for the SIO channel. P93 is configurable as an open-drain output.
Reset
Direction
control
(Bitwise)
P9CR write
Internal data bus
Function
control
(Bitwise)
P9FC write
TXD
S
Output latch
A
P9 write
Selector
B
S
S
P9 read
B
P93 (TXD)
Configurable as
open-drain output:
ODE.ODE93
Selector
A
Figure 3.5.28 Port 9 (P93)
(5) P94 (RXD)
P94 can be programmed to function as a general-purpose I/O pin or an RXD input
pin for the SIO channel.
Reset
Direction
control
(Bitwise)
Internal data bus
P9CR write
S
Output latch
P9 write
P94 (RXD)
S
B
Selector
P9 read
A
RXD
Figure 3.5.29 Port 9 (P94)
91CW28-77
2006-03-24
TMP91CW28
(6) P95 ( CTS /SCLK)
P95 can be programmed to function as a general-purpose I/O pin, or an SCLK clock
input/output pin or CTS input pin for the SIO channel.
Reset
Direction
control
(Bitwise)
P9CR write
Internal data bus
Function
control
(Bitwise)
P9FC write
S
Output latch
S
P95 (SCLK/ CTS )
Selector
P9 write
SCLK
output
A
B
S B
Selector
A
P9 read
CTS
SCLK input
Figure 3.5.30 Port 9 (P95)
(7) P96
P96 functions as a general-purpose I/O pin.
Reset
Internal data bus
Direction
control
(Bitwise)
P9CR write
S
Output latch
P96
S
P9 write
B
Selector
P9 read
A
Figure 3.5.31 Port 9 (P96)
91CW28-78
2006-03-24
TMP91CW28
Port 9 Register
7
P9
(0019H)
Bit symbol
6
5
4
P96
P95
P94
3
2
1
0
P93
P92
P91
P90
Read/Write
R/W
Reset value
Data from external port (Output latch register is set to 1)
−
Function
−
0 (Output latch register)
: Pull-up resistor disabled
1 (Output latch register)
: Pull-up resistor enabled
Port 9 Control Register
7
P9CR
(001CH)
Bit symbol
6
5
4
3
2
1
0
P96C
P95C
P94C
P93C
P92C
P91C
P90C
0
0
0
0
0
0
Read/Write
W
Reset value
Function
0
0: Input
1: Output
Port 9 direction settings
0 Input port
1 Output port
Port 9 Function Register
7
P9FC
(001DH)
Note 2:
Note 3:
5
4
3
2
1
0
Bit symbol
P95F
P93F
P92F
P91F
P90F
Read/Write
W
W
W
W
W
Reset value
0
0
0
0
0
Function
Note 1:
6
0: Port
1: SCLK
output
0: Port
1: TXD
0: Port
1: SCL1
output
0: Port
0: Port
1: SDA1/SO1 1: SCK1
output
output
SCK1 output settings for P90
P9CR and P9FC do not support
read-modify-write operation.
When a port 9 pin is used in input mode,
the P9 register controls the on-chip pull-up
resistor. A read-modify-write instruction
cannot be executed if at least one pin of
port 9 is placed in input mode. A
read-modify-write instruction may modify
the on-chip pull-up setting for an input pin
depending on the current pin status.
To specify the TXD pin as an open-drain
output, write a 1 to bit1 (for the TXD pin) of
the ODE register. The P94/RXD pin does
not have a register bit for selecting the port
or timer function. The input to the
P94/RXD pin is always directed to the SIO
as serial receive data even when the pin is
used as a general-purpose input pin.
P9FC.P90F
1
P9CR.P90C
1
SDA1/SO1 output settings for P91
P9FC.P91F
1
P9CR.P91C
1
SCL1 output settings for P92
P9FC.P92F
1
P9CR.P92C
1
TXD output settings for P93
P9FC.P93F
1
P9CR.P93C
1
SCLK output settings for P95
P9FC.P95F
1
P9CR.P95C
1
Figure 3.5.32 Port 9 Registers
91CW28-79
2006-03-24
TMP91CW28
Port A (PA0 to PA7)
Eight port A pins can be individually programmed to function as discrete
general-purpose or dedicated I/O pins. A reset clears all the PACR register bits, configuring
all port A pins as input port pins. Alternatively, PA0 to PA3 can be programmed as external
interrupt request pins (INT1 to INT4). PA0 to PA3 have programmable pull-up resistors.
Reset
Direction
control
(Bitwise)
Internal data bus
PACR write
P-ch
S
Output latch
Programmable
pull-up resistor
PA0 to PA3
(INT1 to INT4)
PA write
S
B
Selector
Y
A
PA read
Positive/Negative
polarity
INT1
:
INT4
PAFC. PA0F,
PA1F,
PA2F,
PA3F
IIMC. I1EDGE,
I2EDGE,
I3EDGE,
I4EDGE
Figure 3.5.33 Port A (PA0 to PA3)
Reset
R
Direction
control
(Bitwise)
PACR write
Internal data bus
3.5.11
S
Output
latch
P-ch
Programmable
pull-up resistor
PA4 to PA7
PA write
S
B
Selector
Y
A
PA read
Figure 3.5.34 Port A (PA4 to PA7)
91CW28-80
2006-03-24
TMP91CW28
Port A Register
PA
(001EH)
Bit symbol
7
6
5
4
PA7
PA6
PA5
PA4
3
2
1
0
PA3
PA2
PA1
PA0
Read/Write
R/W
Reset value
Data from external port (Output latch register is set to 1)
0 (Output latch register) : Pull-up resistor disabled
1 (Output latch register) : Pull-up resistor enabled
Function
Port A Control Register
PACR
(0020H)
Bit symbol
7
6
5
4
3
2
1
0
PA7C
PA6C
PA5C
PA4C
PA3C
PA2C
PA1C
PA0C
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
0: Input
1: Output
Port A Function Register
7
PAFC
(0021H)
3
2
1
0
Bit symbol
6
5
4
PA3F
PA2F
PA2F
PA0F
Read/Write
W
W
W
W
Reset value
0
0
0
0
Function
0: Port
1: INT4
input
0: Port
1: INT3
input
0: Port
1: INT2
input
0: Port
1: INT1
input
INT1 input settings for PA0
Note 1:
Note 2:
PACR and PAFC do not support
PAFC.PA0F
1
PACR.PA0C
0
INT2 input settings for PA1
read-modify-write operation.
PAFC.PA1F
1
When a port A pin is used in input mode, the PA
PACR.PA1C
0
register controls the on-chip pull-up resistor. A
read-modify-write instruction cannot be
executed if at least one pin of port A is placed in
INT3 input settings for PA2
PAFC.PA2F
1
PACR.PA2C
0
input mode. A read-modify-write instruction may
modify the on-chip pull-up setting for an input
pin depending on the current pin status.
INT4 input settings for PA3
PAFC.PA3F
1
PACR.PA3C
0
Figure 3.5.35 Port A Registers
91CW28-81
2006-03-24
TMP91CW28
3.5.12
Input Pull-up Resistor and Open-drain Output Control
The SO0/SDA0 (P61) and SO1/SDA1 (P91) data transmit or data transmit/receive pins of
the serial bus interface and the SI0/SCL0 (P62) and SI1/SCL1 (P92) data receive or clock
input/output pins of the serial bus interface can be configured as inputs with pull-up
resistors enabled.
Pull-up Enable Register
7
6
Bit symbol
PUP
(002EH) Read/Write
5
4
3
2
PUP92
PUP91
PUP62
PUP61
1
1
1
1
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
1
0
R/W
Reset value
Function
The TXD (P93) output pin of the SIO, the SO0/SDA0 (P61) and SO1/SDA1 (P91) data
transmit or data transmit/receive pins of the serial bus interface, and the SI0/SCL0 (P62)
and SI1/SCL1 (P92) data receive or clock input/output pins of the serial bus interface can
be configured as open-drain outputs.
Serial Open-drain Enable Register
7
Bit symbol
ODE
(002FH) Read/Write
Reset value
Function
6
5
4
3
2
1
ODE92
ODE91
ODE62
ODE61
ODE93
0
0
0
0
0
1: P92ODE
1: P91ODE
1: P62ODE
1: P61ODE
1: P93ODE
0
R/W
91CW28-82
2006-03-24
TMP91CW28
3.6
Chip Select/Wait Controller
The TMP91CW28 provides four programmable chip select signals. Programmable features
include variable block sizes, data bus width, and wait state insertion.
CS0 to CS3 (Multiplexed with P40 to P43) are the chip select output pins for the CS0 to CS3
address ranges. These chip select signals are generated when the CPU issues an address within
the programmed ranges. The P40 to P43 pins must be configured as CS0 to CS3 by
programming the port 4 control (P4CR) register and the port 4 function (P4FC) register.
The TMP91CW28 supports direct connections to ROM and SRAM devices.
Chip select address ranges are defined in terms of a memory start address and an address
mask. There is a memory start address (MSAR0 to MSAR3) register and memory address mask
(MAMR0 to MAMR3) register for each of the four chip select signals.
There is also a set of chip select/wait control registers, B0CS to B3CS and BEXCS, each of
which consists of a master enable bit, a data bus width bit, and a wait state field.
External memory devices can also use the WAIT pin to insert wait states and consequently
prolong read and write bus cycles.
3.6.1
Programming Chip Select Ranges
Each of the four chip select address ranges is defined in the memory start address
(MSAR0 to MSAR3) register and memory address mask (MAMR0 to MAMR3) register. The
basic chip select model allows one of the chip select output signals ( CS0 to CS3 ) to assert
when an address on the address bus falls within a particular programmed range. The B0CS
to B3CS registers define specific operations for CS0 to CS3 , respectively (See section
3.6.2).
91CW28-83
2006-03-24
TMP91CW28
(1) Memory start address register
Figure 3.6.1 shows the organization of a memory start address register. The memory
start address register (MSAR0 to MSAR3) specifies the start address for a chip select.
The S[23:16] bits specify the upper 8 bits (A23 to A16) of the start address. The lower
16 bits (A15 to A0) are assumed to be 0. Thus, the start address is any multiple of 64
Kbytes starting at 000000H. Figure 3.6.2 shows the relationships between start
addresses and the contents of the memory start address register.
Memory Start Address Register (for CS0 to CS3)
7
6
5
4
S22
S21
S20
MSAR0
(00C8H)
MSAR1 Bit symbol
(00CAH) Read/Write
S23
MSAR2
(00CCH)
MSAR3 Reset value
(00CEH) Function
1
3
2
1
0
S19
S18
S17
S16
1
1
1
1
R/W
1
1
1
A23 to A16 of the start address
Start address settings for CS0 to CS3
address ranges
Figure 3.6.1 Memory Start Address Register
Start address
Address
000000H
Start address register value (MSAR0 to MSAR3)
000000H ...................... 00H
64 Kbytes
010000H ...................... 01H
020000H ...................... 02H
030000H ...................... 03H
040000H ...................... 04H
050000H ...................... 05H
060000H ...................... 06H
:......................................:
FF0000H ...................... FFH
FFFFFFH
Figure 3.6.2 Relationships between Start Addresses and Start Address Register Values
91CW28-84
2006-03-24
TMP91CW28
(2) Memory address mask register
Figure 3.6.3 shows the memory address mask register. The memory address mask
register (MAMR0 to MAMR3) controls the size of a chip select address range (CS0 to
CS3) by specifying a mask for each bit of the start address specified with the memory
start address register (MSAR0 to MSAR3). Any set bit masks the corresponding start
address bit. The address compare logic uses only the address bits that are not masked
(e.g., mask bit cleared to 0) to detect an address match.
Address bits that can be masked (e.g., supported block sizes) differ for the four chip
select spaces.
Memory Address Mask Register (for CS0)
MAMR0
(00C9H)
Bit symbol
7
6
5
4
3
2
1
0
V20
V19
V18
V17
V16
V15
V14 to V9
V8
1
1
1
1
Read/Write
Reset value
R/W
1
Function
1
1
1
CS0 block size 0: The address compare logic uses this address bit.
The CS0 block size can be set in the range from 256 bytes to 2 Mbytes.
Memory Address Mask Register (for CS1)
MAMR1
(00CBH)
Bit symbol
7
6
5
4
3
2
1
0
V21
V20
V19
V18
V17
V16
V15 to V9
V8
1
1
1
1
1
1
1
1
Read/Write
Reset value
R/W
Function
CS1 block size 0: The address compare logic uses this address bit.
The CS1 block size can be set in the range from 256 bytes to 4 Mbytes.
Memory Address Mask Register (for CS2, CS3)
MAMR2
(00CDH)
MAMR3
(00CFH)
Bit symbol
7
6
5
4
3
2
1
0
V22
V21
V20
V19
V18
V17
V16
V15
1
1
1
1
1
1
1
1
Read/Write
Reset value
Function
R/W
CS2/CS3 block size 0: The address compare logic uses this address bit.
The CS2 and CS3 block size can be set in the range from 32 Kbytes to 8 Mbytes.
Figure 3.6.3 Memory Address Mask Register
91CW28-85
2006-03-24
TMP91CW28
(3) Memory start address and address mask value calculations
Figure 3.6.4 shows example register settings, causing CS0 to be asserted in the
64 Kbytes of address space starting at 010000H.
The S[23:16] bits in the MSAR0 register specify the upper eight bits of the start
address, or 01H. Calculate the difference between the start address and the end
address (01FFFFH). Bits 20 to 8 of the result specify a mask value to be used when the
CS0 space is specified. Set this value in the V[20:8] bits in the memory address mask
register MAMR0 to specify the space size.
This example sets 07H in the MAMR0 to specify 64 Kbytes of address space.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
F
1
1
1
1
F
1
1
1
1
F
1
1
H
F
Memory
end
address
(64 Kbytes)
S23 S22 S21 S20 S19 S18 S17 S16
MSAR0
0
0
0
0
0
0
0
0
Memory
start
address
1
1
H
V20 V19 V18 V17 V16 V15
MSMR0
0
0
0
0
0
0
0
0
0
CS0 space
size
1
V14 to V9
1
1
1
1
V8
1
1
1
7
1
1
1
1
1
1
1
1
Memory address mask
register value
H
Setting 07H specifies 64 Kbytes of address space.
Figure 3.6.4 Example CS0 Space Settings
Upon reset, the MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to FFH while the
B0CS.B0E, B1CS.B1E and B3CS.B3E bits are cleared to 0, so that the CS0, CS1 and
CS3 spaces are disabled. The TMP91CW28, however, enables the CS2 space in the
address range of 003000H through FDFFFFH because B2CS.B2M is cleared to 0 and
B2CS.B2E is set to 1. The BEXCS register controls the bus width and wait insertion for
addresses other than those included in the CS0 to CS3 spaces. See section 3.6.2.
91CW28-86
2006-03-24
TMP91CW28
(4) Specifying an address space size
Table 3.6.1 shows the programmable block sizes for CS0 to CS3. “Δ” indicates a
combination which may not be possible depending on the memory start address and
address mask register values. When using a size marked “Δ”, specify start addresses
using desired increments from 000000H.
Even if the user has accidentally programmed more than one chip select line to the
same area, or if the CS2 space is specified to be 16 Mbytes, only one chip select line is
driven because of internal line priorities. CS0 has the highest priority, and CS3 the
lowest.
Example: Specifying 128 Kbytes of CS0 space.
a Possible start addresses
000000H
128 Kbytes
020000H
128 Kbytes
040000H
All of these start addresses can be set.
128 Kbytes
060000H
b.
Impossible start addresses
000000H
68 Kbytes
010000H
128 Kbytes
030000H
The size increment is wrong. Subsequent start
addresses cannot specify required space.
128 Kbytes
050000H
Table 3.6.1 Supported Block Sizes
Size (bytes)
CS Space
CS0
CS1
CS2
CS3
256
512
32 K
64 K
128 K
256 K
512 K
1M
2M
○
○
○
○
○
○
○
○
○
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
○
○
4M
8M
Note: “Δ” indicates a combination which may not be possible depending on the memory start address
and address mask register values.
91CW28-87
2006-03-24
TMP91CW28
3.6.2
Chip Select/Wait Control Registers
The organizations of the chip select/wait control registers are shown in Figure 3.6.5.
Each of these registers consists of a chip select type field, a master enable bit, a data bus
width bit, and a wait state field. The B0CS to B3CS registers define the CS0 to CS3 lines,
respectively. The BEXCS register defines the access characteristics for the rest of the
address locations.
91CW28-88
2006-03-24
TMP91CW28
7
B0CS
(00C0H)
Bit symbol
B0E
Read/Write
W
Reset value
Read-modifyFunction
write
operation is
not
supported.
B1CS
(00C1H)
B2CS
(00C2H)
W
Reset value
0
0
B1OM1
1
0
B0W2
B0W1
B0W0
0
0
0
0
Data bus
width
Number of wait-state cycles
0: 16 bits
000: 2 wait states
001: 1 wait state
010: (1 + N) wait states
011: No wait state
1: 8 bits
B1OM0
B1BUS
100
101 Setting
110 prohibited
111
B1W2
B1W1
B1W0
0
0
0
W
0
0
0: Disable
0
0
Chip select output
waveform
00: ROM/SRAM
01:
10: Don’t care
11:
1: Enable
B2E
B2M
B2OM1
Data bus
width
Number of wait-state cycles
0: 16 bits
000: 2 wait states
001: 1 wait state
010: (1 + N) wait states
011: No wait state
1: 8 bits
B2OM0
B2BUS
100
101 Setting
110 prohibited
111
B2W2
B2W1
B2W0
0
0
0
W
1
0
0: Disable
CS2 space
select
1: Enable
0: Whole
16-Mbyte
space
1: CS space
Bit symbol
B3E
Read/Write
W
0
0
Chip select output
waveform
00: ROM/SRAM
01:
10: Don’t care
11:
B3OM1
0
Data bus
width
Number of wait-state cycles
0: 16 bits
000: 2 wait states
001: 1 wait state
010: (1 + N) wait states
011: No wait state
1: 8 bits
B3OM0
B3BUS
0
0
Chip select output
waveform
00: ROM/SRAM
01:
10: Don’t care
11:
Bit symbol
B3W2
B3W1
B3W0
0
0
0
0
Data bus
width
Number of wait-state cycles
0: 16 bits
000: 2 wait states
001: 1 wait state
010: (1 + N) wait states
011: No wait state
1: 8 bits
BEXBUS
BEXW2
Read/Write
100
101 Setting
110 prohibited
111
BEXW1
BEXW0
0
0
W
Reset value
0
Read-modifyFunction
write
operation is
not
supported.
0
Data bus
width
Number of wait-state cycles
0: 16 bits
000: 2 wait states
001: 1 wait state
010: (1 + N) wait states
011: No wait state
1: 8 bits
Master enable bit
Chip select output waveform
0
CS space disabled
1
CS space enabled
CS2 space select
100
101 Setting
110 prohibited
111
W
0
Read-modify- Reset value
Function
0: Disable
write
operation is
1: Enable
not
supported.
BEXCS
(00C7H)
B0BUS
Chip select output
waveform
00: ROM/SRAM
01:
10: Don’t care
11:
Read/Write
Read-modifyFunction
write
operation is
not
supported.
B3CS
(00C3H)
B0OM0
2
W
1: Enable
B1E
Bit symbol
B0OM1
0
Read/Write
Reset value
Chip Select/Wait Control Registers
5
4
3
0: Disable
Bit symbol
Read-modifyFunction
write
operation is
not
supported.
6
00 ROM/SRAM
100
101 Setting
110 prohibited
111
Wait state settings
(See “Wait control” in section 3.6.2 (3).)
01
10 Don’t care
Data bus width settings
11
0
16-bit data bus
1
8-bit data bus
Figure 3.6.5 Chip Select/Wait Control Registers
91CW28-89
2006-03-24
TMP91CW28
(1) Master enable bit
Bit7 (B0E, B1E, B2E and B3E) in each chip select/wait control register is a master
enable bit, which enables or disables the settings in the register for the corresponding
address space. Writing a 1 to the bit enables the settings. A reset results in B0E, B1E
and B3E being cleared to 0 and B2E being set to 1, so that only the register settings for
the CS2 space are enabled.
(2) Data bus width
The TMP91CW28 supports dynamic bus sizing, or modifying the data bus width
according to the address space it accesses. Bit3 (B0BUS, B1BUS, B2BUS, B3BUS and
BEXBUS) in each chip select/wait control register specifies the data bus width. Writing
a 0 to the bit causes the TMP91CW28 to access the corresponding memory space using
a 16-bit data bus. Writing a 1 to the bit causes the TMP91CW28 to use an 8-bit data
bus. Table 3.6.2 shows details of dynamic bus sizing.
Table 3.6.2 Dynamic Bus Sizing
Data Bus
Width for
Operand
Operand Start
Address
8 bits
2n + 0
(Even number)
8 bits
2n + 0
xxxxx
b7 to b0
16 bits
2n + 0
xxxxx
b7 to b0
2n + 1
(Odd number)
8 bits
2n + 1
xxxxx
b7 to b0
16 bits
2n + 1
b7 to b0
xxxxx
16 bits
2n + 0
(Even number)
2n + 1
(Odd number)
32 bits
2n + 0
(Even number)
Data Bus
Width on
Memory
D15 to D8
D7 to D0
2n + 0
xxxxx
b7 to b0
2n + 1
xxxxx
b15 to b8
16 bits
2n + 0
b15 to b8
b7 to b0
8 bits
2n + 1
xxxxx
b7 to b0
2n + 2
xxxxx
b15 to b8
16 bits
2n + 1
b7 to b0
xxxxx
2n + 2
xxxxx
b15 to b8
8 bits
2n + 0
xxxxx
b7 to b0
2n + 1
xxxxx
b15 to b8
8 bits
16 bits
2n + 1
(Odd number)
CPU Data
CPU Address
8 bits
16 bits
2n + 2
xxxxx
b23 to b16
2n + 3
xxxxx
b31 to b24
2n + 0
b15 to b8
b7 to b0
2n + 2
b31 to b24
b23 to b16
2n + 1
xxxxx
b7 to b0
2n + 2
xxxxx
b15 to b8
2n + 3
xxxxx
b23 to b16
2n + 4
xxxxx
b31 to b24
2n + 1
b7 to b0
xxxxx
2n + 2
b23 to b16
b15 to b8
2n + 4
xxxxx
b31 to b24
xxxxx: For a read, input data on the bus is ignored. For a write, the bus is placed in the high-impedance
state and the write strobe for the bus remains inactive.
91CW28-90
2006-03-24
TMP91CW28
(3) Wait control
Bits 2 to 0 (B0W[2:0], B1W[2:0], B2W[2:0], B3W[2:0] and BEXW[2:0]) in each chip
select/wait control register specifies the number of wait states to be inserted. The
following table shows how wait states are inserted according to the combination of
these bits. Any combinations other than those listed in the table cannot be used.
Table 3.6.3 Wait Settings
<BxW2:0>
Number of
Waits
Operation
000
2
Two wait states are inserted regardless of the state of the WAIT pin.
001
1
One wait state is inserted regardless of the state of the WAIT pin.
010
(1 + N)
One wait state is inserted, after which the state of the WAIT pin is
sampled and, if it is low, another wait state is inserted so that the bus
cycle is elongated until the pin goes high.
011
0
The bus cycle is completed without wait states inserted, regardless of
the state of the WAIT pin.
A reset clears the bits to 000 (2 waits).
(4) Bus width and wait control for addresses outside the CS0 to CS3 spaces
The BEXCS register controls the data bus width and wait states when an address
that does not belong to any of the CS0 to CS3 blocks is accessed. The settings in this
register are always enabled.
(5) 16-Mbyte space selection
Clearing the B2M bit in the B2CS register to 0 results in 16 Mbytes of address space
(003000H to FDFFFFH) being assigned to CS2. Setting the bit to 1 results in the CS2
space being assigned in the same way as CS0, CS1 and CS3, according to the settings
in the MSAR2 and MAMR2 registers. A reset clears the bit to 0 so that 16-Mbyte space
is assigned.
91CW28-91
2006-03-24
TMP91CW28
(6) Procedure for setting the chip select/wait controller
When using the chip select/wait controller, set the following registers in the stated
order:
1.
Memory start address registers: MSAR0 to MSAR3
Set the start addresses of the CS0 to CS3 spaces.
2.
Memory address mask registers: MAMR0 to MAMR3
Set the sizes of the CS0 to CS3 spaces.
3.
Control registers: B0CS to B3CS
Set the chip select type, data bus width, number of wait states and master
enable/disable for the CS0 to CS3 spaces.
The CS0 to CS3 pins are shared with the P40 to P43 pins. To drive a chip select
signal from these pins, the appropriate bits in the port 4 control register (P4CR) and
port 4 function register (P4FC) must be set to 1.
If an address specified for any of the CS0 to CS3 spaces falls in the on-chip
peripheral, RAM or ROM area, the corresponding CS pin does not drive a chip select
signal and the CPU accesses the internal area.
Example:
When the CS0 space is assigned a 64-Kbyte space of 010000H through 01FFFFH with a
16-bit data bus and no wait states:
MSAR0 = 01H ............Start address 010000H
MAMR0 = 07H ...........64-Kbyte address space
B0CS = 83H ...............ROM/SRAM, 16-bit data bus, 0-wait states, CS0 settings
enabled
91CW28-92
2006-03-24
TMP91CW28
3.6.3
Application Example
Figure 3.6.6 shows an example usage of the TMP91CW28 programmable chip selects. In
this example, an external ROM chip is connected through a 16-bit data bus and external
RAM and peripheral chips are connected through an 8-bit data bus.
74AC573
TMP91CW28
D Q
Address bus
LE
CS0
CS1
CS2
ALE
CS
LE
CS
Upper byte
ROM
D Q
OE
CS
Lower byte
ROM
OE
CS
8-bit
RAM
OE WE
8-bit
I/O
OE WE
AD8
:
AD15
AD0
:
AD7
RD
WR
Figure 3.6.6 External Memory Connections (ROM width = 16 bits, RAM and peripheral width = 8 bits)
Both CS1 and CS2 are shared with port 4 pins. Upon reset, all port 4 pins are configured
as input port pins. To use them as chip select pins, set appropriate bits in the port 4
function (P4FC) register and the port 4 control (P4CR) register to 1, in this order.
91CW28-93
2006-03-24
TMP91CW28
3.7
8-Bit Timers (TMRA)
The TMP91CW28 has a four-channel 8-bit timer (TMRA0 to TMRA3), which is comprised of
two modules named TMRA01 and TMRA23. The TMRA01 contains the TMRA0 and the
TMRA1, and the TMRA23 contains the TMRA2 and TMRA3. Each timer module has the
following operating modes:
•
8-bit interval timer mode
•
16-bit interval timer mode
•
8-bit programmable pulse generation (PPG) mode (Variable frequency, variable duty cycle)
•
8-bit pulse width modulated (PWM) signal generation mode (Fixed frequency, variable duty
cycle)
Figure 3.7.1 and Figure 3.7.2 are block diagrams of the TMRA01 and TMRA23 respectively.
The main components of a timer channel are an 8-bit up counter, an 8-bit comparator and an
8-bit timer register. Two timer channels share a prescaler and a timer flip-flop.
A total of five special function registers (SFRs) provide control over the operating modes and
timer flip-flops for the TMRA01 and the TMRA23 each, which can be independently
programmed. The TMRA01 and the TMRA23 are functionally equivalent. In the following
sections, any references to the TMRA01 also apply to the TMRA23.
Table 3.7.1 gives the pins and registers for the two timer modules.
Table 3.7.1 Pins and Registers for the TMRA01 and the TMRA23
Module
Specifications
External clock
input
TA0IN
(Shared with P70)
External pins
(Addresses)
TMRA23
None
TA1OUT
TA3OUT
(Shared with P71)
(Shared with P72)
Timer run register
TA01RUN (0100H)
TA23RUN (0108H)
Timer registers
TA0REG (0102H)
TA1REG (0103H)
TA2REG (010AH)
TA3REG (010BH)
Timer mode register
TA01MOD (0104H)
TA23MOD (010CH)
Timer flip-flop
control register
TA1FFCR (0105H)
TA3FFCR (010DH)
Timer flip-flop output
Registers
TMRA01
91CW28-94
2006-03-24
input: TA0IN
External clock
φT4
8-bit
up counter
(UC0)
91CW28-95
TA0RDE
TA01RUN.
Internal data bus
Register buffer 0
8-bit timer
register TA0REG
8-bit
comparator
(CP0)
TMRA0
interrupt
output:
INTTA0
Match
detect
TA01MOD.
PWM[01:00]
TA1FFCR
Timer
flip-flop
TA1FF
TMRA1
interrupt
output:
INTTA1
detect
Match
Internal data bus
8-bit timer
register
TA1REG
8-bit
comparator
(CP1)
8-bit
up counter
(UC1)
TA01RUN.TA1RUN
TA01MOD.
TA1CLK[1:0]
TMRA0
match
output:
TA0TRG
TA01MOD.
TA01M[1:0]
φT1
φT16
φT256
Selector
TA01RUN.TA01PRUN
TA0TRG
Run/clear
2
overflow
n
φT256
TA01RUN.TA0RUN
φT16
8 16 32 64 128 256 512
TA01MOD.TA0CLK[1:0]
φT1
φT4
φT16
4
Selector
φT1
2
Prescaler
Timer flip-flop
output: TA1OUT
3.7.1
Prescaler clock
source: φT0
TMP91CW28
Block Diagrams
Figure 3.7.1 TMRA01 Block Diagram
2006-03-24
Prescaler clock
source: φT0
4
φT4
91CW28-96
TA23RUN.
TA2RDE
8-bit
comparator
(CP2)
Register buffer 2
Internal
data bus
n
overflow
2
TA3CLK[1:0]
TA23MOD.
TMRA2
match
output:
TA2TRG
TA23M[1:0]
TA23MOD.
TA2TRG
φT1
φT16
φT256
Selector
TA23RUN.TA23PRUN
TMRA2
interrupt output:
INTTA2
Match
detect
TA23MOD.
PWM[21:20]
8-bit
up counter
(UC2)
8-bit timer register
TA2REG
TA23MOD.
TA2CLK[1:0]
φT1
φT4
φT16
Run/clear
φT256
TA23RUN.TA2RUN
φT16
8 16 32 64 128 256 512
Selector
φT1
2
Prescaler
data bus
Internal
8-bit timer
register
TA3REG
8-bit
comparator
(CP3)
8-bit
up counter
(UC3)
TA3FFCR
TA3FF
TMRA3
interrupt output:
INTTA3
Match
detect
TA23RUN.TA3RUN
Timer
flip-flop
Timer flip-flop output:
TA3OUT
TMP91CW28
Figure 3.7.2 TMRA23 Block Diagram
2006-03-24
TMP91CW28
3.7.2
Timer Components
(1) Prescaler
The TMRA01 has a 9-bit prescaler that slows the rate of a clocking source to the
counters. The prescaler clock source (φT0) has one-fourth the frequency selected by
programming the PRCK [1:0] field of the SYSCR0 located within the clock gear.
The TA0PRUN bit in the TA01RUN register allows the enabling and disabling of the
prescaler for the TMRA01. A write of 1 to this bit starts the prescaler. A write of 0 to
this bit clears and halts the prescaler. Table 3.7.2 shows prescaler output clock
resolutions.
Table 3.7.2 Prescaler Output Clock Resolutions
at fc = 10 MHz
Prescaler Clock
Source
PRCK[1:0]
00
(fFPH)
10
(fc/16 clock)
Clock Gear
Value
GEAR[2:0]
Prescaler Output Clock Resolution
φT1
φT4
φT16
φT256
000 (fc)
2 /fc ( 0.8 μs)
2 /fc ( 3.2 μs) 2 /fc ( 12.8 μs) 2 /fc ( 204.8 μs)
001 (fc/2)
2 /fc ( 1.6 μs)
2 /fc ( 6.4 μs) 2 /fc ( 25.6 μs) 2 /fc ( 409.6 μs)
010 (fc/4)
2 /fc ( 3.2 μs)
2 /fc ( 12.8 μs) 2 /fc ( 51.2 μs) 2 /fc ( 819.2 μs)
011 (fc/8)
2 /fc ( 6.4 μs)
2 /fc ( 25.6 μs) 2 /fc (102.4 μs) 2 /fc ( 1638.4 μs)
100 (fc/16)
2 /fc ( 12.8 μs)
2 /fc ( 51.2 μs) 2 /fc (204.8 μs) 2 /fc ( 3276.8 μs)
XXX
2 /fc ( 12.8 μs)
2 /fc ( 51.2 μs) 2 /fc (204.8 μs) 2 /fc ( 3276.8 μs)
3
4
5
6
7
7
5
6
7
8
9
9
7
8
9
10
11
11
11
12
13
14
15
15
XXX: Don’t care
(2) Up counters (UC0 and UC1)
The timer module contains two 8-bit binary up counters, each of which is driven by a
clock independently selected by the TA01MOD register.
The clock input to the UC0 is either one of three prescaler outputs (φΤ1, φT4, φT16)
or the external clock applied to the TA0IN pin. Which clock is to use is programmed
into the TA0CLK [1:0] field in the TA01MOD register.
Possible clock sources for the UC1 depend on the selected operating mode. In 16-bit
interval timer mode, the clock input to the UC1 is always the UC0 overflow output. In
other operating modes, the clock input to the UC1 is either one of three prescaler
outputs (φΤ1, φT16, φT256) or the TMRA0 comparator match-detect output.
The TA0RUN and TA1RUN bits in the TA01RUN register are used to start counting
and to stop and clear the counter. Upon reset, the up counter is cleared to 00H and the
whole timer module is disabled.
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TMP91CW28
(3) Timer registers (TA0REG and TA1REG)
Each timer register is an 8-bit register containing a time constant. When the up
counter reaches the time constant value in the timer register, the comparator block
generates a match-detect signal. When the time constant is cleared to 00H, a match
occurs upon a counter overflow.
One of the two timer registers, TA0REG, is double buffered. The double-buffering
function can be enabled and disabled through the programming of the TA0RDE bit in
the TA01RUN: 0 = disable, 1 = enable.
If double-buffering is enabled, the TA0REG latches a new time constant value from
the register buffer. This takes place upon detection of a 2n overflow in PWM mode and
upon a match between the UC0 and the TA1REG in PPG mode. Double-buffering must
be disabled in interval timer modes.
A reset clears the TA01RUN.TA0RDE bit to 0, disabling the double-buffering
function. To use this function, the TA01RUN.TA0RDE bit must be cleared after loading
the TA0REG with a time constant. When TA01RUN.TA0RDE = 1, the next time
constant can be written to the register buffer.
Figure 3.7.3 illustrates the double-buffer structure for the TA0REG.
Timer register 0 (TA0REG)
Selector
B
TA1REG match in PPG mode
n
2 overflow in PWM mode
A
Shift trigger
Write to TA0REG
Register buffer 0
S
Write
Internal data bus
TA01RUN.TA0RDE
Figure 3.7.3 Timer Register 0 (TA0REG) Structure
Note: The timer register and the corresponding register buffer are mapped to the same address.
When TA01RUN.TA0RDE = 0, a time constant value is written to both of the timer register
and the register buffer; when TA01RUN.TA0RDE = 1, a time constant value is written only to
the register buffer.
The addresses of the timer registers are as follows:
TA0REG: 000102H
TA1REG: 000103H
TA2REG: 00010AH
TA3REG: 00010BH
The timer registers are write-only registers.
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(4) Comparators (CP0 and CP1)
The comparator compares the output of the 8-bit up counter with a time constant
value in the 8-bit timer register. When a match is detected, an interrupt
(INTTA0/INTTA1) is generated and the timer flip-flop is toggled, if so enabled.
(5) Timer flip-flop (TA1FF)
The timer flip-flop (TA1FF) is toggled, if so enabled, each time the comparator
match-detect output is asserted. The toggling of the timer flip-flop can be enabled and
disabled through the programming of the TA1FFIE bit in the TA1FFCR.
A reset clears the TAFF1IE bit, disabling the toggling of the TA1FF. The TA1FF can
be initialized to 1 or 0 by writing 01 or 10 to the TA1FFC [1:0] field in the TA1FFCR.
Additionally, a write of 00 by software causes the TA1FF to be toggled to the opposite
value.
The value of the TA1FF can be driven onto the TA1OUT pin. The port 7 registers
(P7CR and P7FC) must be programmed to configure the P71/TA1OUT pin as TA1OUT.
Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required
as explained below.
If new data is written to the register buffer immediately before an overflow occurs by a
match between the timer register value and the up-counter value, the timer flip-flop may
output an unexpected value.
For this reason, make sure that in PWM mode new data is written to the register buffer by
six cycles (fSYS × 6) before the next overflow occurs by using an overflow interrupt.
In the case of using PPG mode, make sure that new data is written to the register buffer by
six cycles before the next cycle compare match occurs by using a cycle compare match
interrupt.
Example when using PWM mode
Match between
TA0REG and up-counter
n
2 overflow interrupt
(INTTA0)
TA1OUT
tPWM
(PWM cycle)
Desired PWM cycle
change point
Write new data to the register buffer
before the next overflow occurs by
using an overflow interrupt
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3.7.3
SFR Description
TMRA01 Run Register
7
TA01RUN
(0100H)
6
Bit symbol
TA0RDE
Read/Write
R/W
Reset value
0
Function
5
4
3
2
1
0
I2TA01
TA01PRUN
TA1RUN
TA0RUN
0
0
R/W
0
0
Double
IDLE2
8-bit timer run/stop control
buffering
0: OFF
0: Stop and clear
0: Disable
1: ON
1: Run
1: Enable
TA0REG double buffering control
Counting
0
Disable
0
Stop and clear
1
Enable
1
Count up
I2TA01:
Timer ON/OFF in IDLE2 mode
TA01PRUN: Prescaler
TA1RUN:
TMRA1
TA0RUN:
TMRA0
Note: Bits4, 5, and 6 are read as undefined.
TMRA23 Run Register
7
TA23RUN
(0108H)
6
Bit symbol
TA2RDE
Read/Write
R/W
Reset value
Function
5
4
3
2
I2TA23
TA23PRUN
1
0
TA3RUN
TA2RUN
R/W
0
0
0
0
0
Double
IDLE2
8-bit timer run/stop control
buffering
0: OFF
0: Stop and clear
0: Disable
1: ON
1: Run
1: Enable
Counting
TA2REG double buffering control
0
Disable
0
Stop and clear
1
Enable
1
Count up
I2TA23:
Timer ON/OFF in IDLE2 mode
TA23PRUN: Prescaler
TA3RUN:
TMRA3
TA2RUN:
TMRA2
Note: Bits4, 5, and 6 are read as undefined.
Figure 3.7.4 TMRA Registers (1)
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TMRA01 Mode Register
TA01MOD Bit symbol
(0104H)
Read/Write
Reset value
Function
7
6
5
4
3
2
1
0
TA01M1
TA01M0
PWM01
PWM00
TA1CLK1
TA1CLK0
TA0CLK1
TA0CLK0
0
0
0
0
0
0
R/W
0
0
Operating mode
PWM period
TMRA1 source clock
TMRA0 source clock
00: 8-bit interval timer
00: Reserved
01: 16-bit interval timer 01: 2
00: TA0TRG
00: TA0IN input
6
01: φT1
01: φT1
7
10: φT16
10: φT4
8
11: φT256
11: φT16
10: 8-bit PPG
10: 2
11: 8-bit PWM
11: 2
TMRA0 clock source
00
External input (TA0IN)
01
φT1
(Prescaler)
10
φT4
(Prescaler)
11
φT16 (Prescaler)
TMRA1 clock source
TA01MOD.TA01M[1:0] ≠ 01
TA01MOD.TA01M[1:0] = 01
00
TMRA0 match output
TMRA0 overflow output
01
φT1
10
φT16
11
φT256
16-bit timer
mode
Period select in 8-bit PWM mode
00
Reserved
01
2 × source clock
10
2 × source clock
11
2 × source clock
6
7
8
TMRA01 operating mode
00
8-bit timer × 2ch
01
16-bit timer
10
8-bit PPG
11
8-bit PWM generation (TMRA0) and
8-bit timer (TMRA1)
Figure 3.7.5 TMRA Registers (2)
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TMRA23 Mode Register
TA23MOD
(010CH)
Bit symbol
7
6
5
4
3
2
1
0
TA23M1
TA23M0
PWM21
PWM20
TA3CLK1
TA3CLK0
TA2CLK1
TA2CLK0
0
0
0
0
0
0
0
Read/Write
Reset value
Function
R/W
Operating mode
PWM period
00: 8-bit interval timer
00: Reserved
01:16-bit interval timer
01: 2
10: 8-bit PPG
10: 2
11: 8-bit PWM
11: 2
0
TMRA3 source clock
00: TA2TRG
TMRA2 source clock
00: Reserved
6
01: φT1
01: φT1
7
10: φT16
10: φT4
8
11: φT256
11: φT16
TMRA2 clock source
00
Setting prohibited
01
φT1
(Prescaler)
10
φT4
(Prescaler)
11
φT16 (Prescaler)
TMRA3 clock source
TA23MOD.TA23M[1:0] ≠ 01
TA23MOD.TA23M[1:0] = 01
00
TMRA2 match output
01
φT1
10
φT16
TMRA2
overflow
output
11
φT256
16-bit timer
mode
Period select in 8-bit PWM mode
00
Reserved
01
2 × source clock
10
2 × source clock
11
2 × source clock
6
7
8
TMRA23 operating mode
00
8-bit timer × 2ch
01
16-bit timer
10
8-bit PPG
11
8-bit PWM generation (TMRA2) and
8-bit timer (TMRA3)
Figure 3.7.6 TMRA Registers (3)
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TMRA1 Flip-flop Control Register
7
TA1FFCR
(0105H)
6
5
4
Bit symbol
3
2
1
0
TA1FFC1
TA1FFC0
TA1FFIE
TA1FFIS
Read/Write
R/W
Reset value
R/W
1
Function
Readmodifywrite
operation
is not
supported.
1
0
00: Toggle
TA1FF
01: Set
toggle
10: Clear
enable
0: Disable
11: Don’t care
1: Enable
0
TA1FF
toggle
trigger
0: TMRA0
1: TMRA1
Selects a signal to toggle timer flip-flop 1
(TA1FF)
(Don’t care in other than 8-bit timer mode)
0
Toggled by TMRA0
1
Toggled by TMRA1
TA1FF toggle enable
0
Disable
1
Enable
TA1FF control
00
Toggles TA1FF (Software toggle).
01
Sets TA1FF to 1.
10
Clears TA1FF to 0.
11
Don’t care
Note: Bits 4 to 7 are read as undefined.
Figure 3.7.7 TMRA Registers (4)
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TMRA3 Flip-flop Control Register
7
TA3FFCR
(010DH)
6
5
4
Bit symbol
2
1
0
TA3FFC0
TA3FFIE
TA3FFIS
Read/Write
R/W
Reset value
Readmodifywrite
operation
is not
supported.
3
TA3FFC1
R/W
1
Function
1
00: Toggle
0
0
TA3FF
10: Clear
TA3FF
toggle
enable
11: Don’t care
0: Disable
0: TMRA2
1: Enable
1: TMRA3
01: Set
toggle
trigger
Selects a signal to toggle timer flip-flop 3
(TA3FF)
(Don’t care in other than 8-bit timer mode)
0
Toggled by TMRA2
1
Toggled by TMRA3
TA3FF toggle enable
0
Disable
1
Enable
TA3FF control
00
Toggles TA3FF (Software toggle).
01
Sets TA3FF to 1.
10
Clears TA3FF to 0.
11
Don’t care
Note: Bits 4 to 7 are read as undefined.
Figure 3.7.8 TMRA Registers (5)
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TMRA register
7
TA0REG
(0102H)
TA1REG
(0103H)
TA2REG
(010AH)
TA3REG
(010BH)
6
5
4
3
bit Symbol
–
Read/Write
W
After reset
Undefined
bit Symbol
–
Read/Write
W
After reset
Undefined
bit Symbol
–
Read/Write
W
After reset
Undefined
bit Symbol
–
Read/Write
W
After reset
Undefined
2
1
0
Note: The above registers are prohibited read-modify-write instruction.
Figure 3.7.9 TMRA Registers (6)
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3.7.4
Operating Modes
(1) 8-bit interval timer mode
The TMRA0 and the TMRA1 can be independently programmed as 8-bit interval
timers. Programming these timers should only be attempted when the timers are not
running.
a.
Generating periodic interrupts
In the following example, the TMRA1 is used to accomplish periodic interrupt
generation. First, stop the TMRA1 (if it is running). Then, set the operating mode,
clock source and interrupt interval in the TA01MOD and TA1REG registers. Then,
enable the INTTA1 interrupt and start the TMRA1.
Example: Generating the INTTA1 interrupt at a 20 μs interval (fc = 10 MHz)
High-speed clock gear: × 1 (fc)
Clocking conditions:
Prescaler clock:
MSB
fFPH
LSB
7
6
5
4
3
2
1
0
TA01RUN
←
−
X
X
X
−
0
0
−
Stops and clears the TMRA1.
TA01MOD
←
0
0
X
X
0
1
X
X
Selects 8-bit interval timer mode and φ T1 ((2 /fc)s) as the
clock source (at fc = 10 MHz).
TA1REG
←
0
0
0
1
1
0
0
1
Sets the time constant value in the TA1REG
3
(20 μs ÷ φ T1 ((2 /fc)s) = 25 (19H)).
INTETA01
←
X
1
0
1
X
TA01RUN
←
−
X
X
X
−
− − −
1
1
−
3
Enables INTTA1 and sets the interrupt level to 5.
Starts the TMRA1.
X: Don’t care, −: No change
Refer to Table 3.7.2 when selecting a timer clock source.
Note: The clock inputs to the TMRA0 and the TMRA1 can be one of the following:
TMRA0: TA0IN input, φT1, φT4, or φT16
TMRA1: Match-detect signal from the TMRA0, φT1, φT16, or φT256
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b.
Generating a square wave with a 50% duty cycle
The 8-bit interval timer mode can be used to generate square-wave output. This
is accomplished by toggling the timer flip-flop (TA1FF) periodically. The TA1FF
state can be driven out to the TA1OUT pin. Both the TMRA0 and the TMRA1 can
be used as square-wave generators. The following shows an example using the
TMRA1.
Example: Generating square-wave output with a 4.8 μs period on the TA1OUT pin
(fc = 10 MHz).
High-speed clock gear: × 1 (fc)
Clocking conditions:
Prescaler clock:
fFPH
7
6
5
4
3
2
1
TA01RUN
←
–
X
X
X
–
0
0
0
–
Stops and clears the TMRA1.
TA01MOD
←
0
0
X
X
0
1
X
X
Selects 8-bit interval timer mode and φT1 ((2 /fc)s) as the
clock source (at fc = 10 MHz).
TA1REG
←
0
0
0
0
0
0
1
1
Sets the time constant value in the TA1REG
3
(4.8 μs ÷ φT1 ((2 /fc)s) ÷ 2 = 03H).
TA1FFCR
←
X
X
X
X
1
0
1
1
Clears the TA1FF to 0 and selects the TMRA1
match-detect output as a toggle-trigger signal.
P7CR
←
X
X
–
–
–
–
1
–
P7FC
←
X
X
–
–
X
–
1
X
TA01RUN
←
–
X
X
X
–
1
1
–
3
Configures P71 as the TA1OUT output pin.
Starts the TMRA1.
X: Don’t care, −: No change
φT1
TA01RUN.
TA1RUN
Bit7 to 2
Up
counter
Bit1
Bit0
0
1
2
3
0
1
2
3
1
2
3
0
Comparator
timing
Comparator output
(Match detect)
INTTA1
Up counter clear
TA1FF
TA1OUT
2.4 μs at fc = 10 MHz
Figure 3.7.10 Square-wave Generation (50% duty cycle)
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c.
Using the TMRA0 match-detect output as a trigger for the TMRA1
Set the TMRA01 in 8-bit interval timer mode. Select the TMRA0 comparator
match-detect output as the clock source for the TMRA1.
TMRA0 comparator
match output
TMRA0 up counter
(when TA0REG = 5)
TMRA1 up counter
(when TA1REG = 2)
1
2
3
4
1
5
1
2
3
2
4
5
1
2
3
1
TMRA1 match output
Figure 3.7.11 Using the TMRA0 Match-detect Output as a Trigger for the TMRA1
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(2) 16-bit interval timer mode
The TMRA0 and the TMRA1 are cascadable to form a 16-bit interval timer. The
TMRA01 is put in 16-bit interval timer mode by programming the TA01M [1:0] field in
the TA01MOD register to 01.
In 16-bit interval timer mode, the TMRA1 is clocked by the counter overflow output
from the TMRA0. In this mode, the TA1CLK [1:0] bits in the TA01MOD register are
don’t cares. The clock input to the TMRA0 can be selected as shown in Table 3.7.2.
Write the lower eight bits of a time constant value to the TA0REG and the upper
eight bits to the TA1REG. Note that the TA0REG must first be programmed prior to
the TA1REG. Writing data to the TA0REG causes comparison to be disabled
temporarily, after which writing data to the TA1REG restarts comparison.
Example: Generating the INTTA1 interrupt at a 0.8 second interval (fc = 10 MHz).
High-speed clock gear: × 1 (fc)
Clocking conditions:
Prescaler clock:
fFPH
When φT16 (= (27/fc)s) at 10 MHz) is used as the TMRA0 clock source, the required
time constant value is calculated as follows:
0.8 s ÷ (27/fc)s = 62500 = F424H
Thus, the TA1REG is to be set to F4H and the TA0REG to 24H.
Every time the up counter UC0 reaches the value in the TA0REG, the TMRA0
comparator generates a match-detect output, but the UC0 continues counting up. A
match between the UC0 and the TA0REG does not cause an INTTA0 interrupt.
Every time the up counter UC1 reaches the value in the TA1REG, the TMRA1
comparator generates a match-detect output. When the TMRA0 and TMRA1
match-detect outputs are asserted simultaneously, both the up counters (UC0 and
UC1) are reset to 00H and an interrupt is generated on INTTA1. Also, if so enabled, the
timer flip-flop (TA1FF) is toggled.
Example: TA1REG = 04H and TA0REG = 80H
Value of up counter
(UC1, UC0)
0080H
0180H
0280H
0380H
0480H
0080H
TMRA0 comparator match
detect signal
TMRA0 comparator match
detect signal
INTTA0
INTTA1
TA1OUT
Inversion
Figure 3.7.12 Timer Output in 16-Bit Interval Timer Mode
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(3) 8-bit programmable pulse generation (PPG) mode
The 8-bit PPG mode can be used to generate a square wave with any frequency and
duty cycle, as shown below. The pulse can be high-going and low-going, as determined
by the initial setting of the timer flip-flop (TA1FF). This mode is supported by the
TMRA0, but not by the TMRA1. The square-wave output is driven to the TA1OUT pin.
tH
tL
When <TA1FFC1:0>=”10”
t
tL
tH
When <TA1FFC1:0>=”01”
t
Example when <TA1FFC1:0>=”01”
TA0REG and UC0 match
(Interrupt INTTA0)
TA1REG and UC0 match
(Interruput INTTA1)
TA1OUT
TA0REG
TA1REG
Figure 3.7.13 8-Bit PPG Output Waveform
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In this mode, a square wave is generated by toggling the timer flip-flop (TA1FF). The
TA1FF changes state every time a match is detected between the UC0 and the
TA0REG and between the UC0 and the TA1REG.
The TA0REG must be set to a value less than the TA1REG value.
In this mode, the TMRA1 up counter (UC1) cannot be independently used. However,
the TMRA1 must be put in a running state by setting the TA1RUN bit in the
TA01RUN register to 1.
Figure 3.7.14 shows a functional diagram of 8-bit PPG mode.
TA1OUT
TA0IN
φT1
φT4
φT16
TA01RUN.TA0RUN
Selector
8-bit up counter
(UC0)
TA1FF
Toggle
TA01MOD.TA0CLK[1:0]
INTTA0
Comparator
Selector
TA0REG-WR
TA1FFCR.TA1FFIE
Comparator
INTTA1
TA0REG
Shift trigger
Register buffer
TA1REG
TA01RUN.TA0RDE
Internal data bus
Figure 3.7.14 Functional Diagram of 8-Bit PPG Mode
In 8-bit PPG mode, if the double-buffering function is enabled, the TA0REG value
can be changed dynamically by writing a new value into the register buffer. Upon a
match between the TA1REG and the UC0, the TA0REG latches a new value from the
register buffer.
The TA0REG can be loaded with a new value upon every match, thus making it easy
to generate a square wave with virtually any (and variable) duty cycle.
Match between TA0REG
and up counter 0
Match between TA1REG
and up counter 0
TA0REG
(Compare value)
Register buffer
(Up counter = Q1)
(Up counter = Q2)
Shift trigger for register buffer
Q2
Q1
Q2
Q3
Write to TA0REG
(Register buffer)
Figure 3.7.15 Register Buffer Operation
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Example: Generating a 50 kHz square wave with a 25% duty cycle (fc = 10 MHz)
20 μs
High-speed clock gear: × 1 (fc)
* Clocking conditions:
Prescaler clock:
fFPH
The time constant values to be loaded into the TA0REG and TA1REG are
determined as follows:
A 50 kHz waveform has a period of 20 μs.
When φT1 = ((23/fc)s) at 10 MHz) is used as the timer clock source, the TA1REG
should be loaded with:
20 μs ÷ (23/fc)s = 25
With a 25% duty cycle, the high pulse width is calculated as 20 µs × 1/4 = 5 µs. Thus,
the TA0REG should be loaded with:
5 μs ÷ (23/fc)s ≈ 6 = 06H
7
6
5
4
3
2
1
TA01RUN
←
0
X
X
X
−
0
0
0
0
Stops and clears the TMRA0 and the TMRA1.
TA01MOD
←
1
0
X
X
X
X
0
1
Selects 8-bit PPG mode and φT1 as the clock source.
TA0REG
←
0
0
0
0
0
1
1
0
Writes 06H.
TA1REG
←
0
0
0
1
1
0
0
1
Writes 19H.
TA1FFCR
←
X
X
X
X
0
1
1
X
Sets the TA1FF to 1 and enables toggling.
If these bits are set to 10, a low-going pulse is generated.
P7CR
←
X
X
−
−
P7FC
←
X
X
TA01RUN
←
1
X
−
X
−
X
−
X
−
−
1
−
−
1
1
X
1
1
Configures P71 as the TA1OUT output pin.
Starts the TMRA0 and the TMRA1.
X: Don’t care, −: No change
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TMP91CW28
(4) 8-bit PWM generation mode
The TMRA0 can be used as a pulse-width modulated (PWM) signal generator with
up to 8 bits of resolution. This mode is supported by the TMRA0, but not by the TMRA1.
The PWM signal is driven out on the TA1OUT pin.
While the TMRA01 is in this mode, the TMRA1 is usable as an 8-bit interval timer.
The timer flip-flop toggles when the up counter (UC0) reaches the TA0REG value
and when a 2n counter overflow occurs, where n is programmable to 6, 7, or 8 through
the PWM[01:00] field in the TA01MOD register. The UC0 is reset to 00H upon a 2n
overflow.
In 8-bit PWM generation mode, the following must be satisfied:
(TA0REG value) < (2n counter overflow value)
(TA0REG value) ≠ 0
Match between
TA0REG and
up counter 0
n
2 overflow
(INTTA0 interrupt)
TA1OUT
tPWM
(PWM cycle)
Figure 3.7.16 8-Bit PWM Signal Generation
Figure 3.7.17 shows a functional diagram of 8-bit PWM generation mode.
TA01RUN.TA0RUN
TA0IN
φT1
φT4
φT16
8-bit up counter
(UC0)
Selector
Clear
TA1OUT
TA1FF
TA1FFCR.
TA1FFIE
2
overflow
control
TA01MOD.TA0CLK[1:0]
Toggle
n
TA01MOD.
PWM[01:00]
Overflow
Comparator
INTTA0
TA0REG
Selector
TA0REG-WR
Shift trigger
Register buffer
TA01RUN.TA0RDE
Internal bus
Figure 3.7.17 Functional Diagram of 8-Bit PWM Generation Mode
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TMP91CW28
In 8-bit PWM generation mode, if the double-buffering function is enabled, the
TA0REG value (e.g., the duty cycle) can be changed dynamically by writing a new
value into the register buffer. Upon a 2n counter overflow, the TA0REG latches a new
value from the register buffer.
The TA0REG can be loaded with a new value upon every counter overflow, thus
making it easy to generate a PWM signal with virtually any (and variable) duty cycle.
Match between TA0REG and
up counter 0
Up counter = Q1
Up counter = Q2
n
2 overflow
TA0REG
Shift into TA0REG
Q2
Q1
(Compare value)
Q3
Write to TA0REG
(Register buffer)
Q2
Register buffer
Figure 3.7.18 Register Buffer Operation
Example: Generating a PWM signal as shown below on the TA1OUT pin (fc = 10 MHz).
59.2 μs
102.4 μs
High-speed clock gear: × 1 (fc)
* Clocking conditions:
Prescaler clock:
fFPH
Under the above conditions, φT1 has a 0.8 μs period (at fc = 10 MHz).
102.4 μs ÷ (23/fc)s = 128 = 2n
which is equal to n = 7.
59.2 μs ÷ (23/fc)s = 74 = 4AH
Hence, the time constant value to be programmed into the TA0REG is 4AH.
MSB
LSB
7
6
5
4
3
2
1
0
TA01RUN
←
−
X
X
X
−
0
−
0
Stops and clears the TMRA0.
TA01MOD
←
1
1
1
0
X
X
0
1
Selects 8-bit PWM mode (period = 2 ) and φT1
TA0REG
←
0
1
0
0
1
0
1
0
Writes 4AH.
TA1FFCR
←
X
X
X
X
1
0
1
X
Clears the TA1FF to 0 and enables toggling.
P7CR
←
X
X
−
−
−
−
1
−
P7FC
←
X
X
−
−
X
−
1
X
TA01RUN
←
1
X
X
X
−
1
−
1
7
as the clock source.
Configures P71 as the TA1OUT output pin.
Starts the TMRA0.
X: Don’t care, −: No change
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TMP91CW28
Table 3.7.3 PWM Period
at fc = 10 MHz
Prescaler
Clock Source
Clock Gear
Value
PRCK[1:0]
GEAR[2:0]
φT1
000 (fc)
51.2 μs
204.8 μs
819.2 μs
102.4 μs
001 (fc/2)
102.4 μs
409.6 μs
1638.4 μs
010 (fc/4)
204.8 μs
819.2 μs
3276.8 μs
011 (fc/8)
409.6 μs
1638.4 μs
100 (fc/16)
819.2 μs
819.2 μs
3276.8 μs
00
(fFPH)
10
(fc/16 clock)
XXX
PWM Period
2
6
2
φT4
φT16
φT1
7
8
φT16
φT1
409.6 μs
1638.4 μs
204.8 μs
819.2 μs
204.8 μs
819.2 μs
3276.8 μs
409.6 μs
1638.4 μs
6553.6 μs
409.6 μs
1638.4 μs
6553.6 μs
819.2 μs
3276.8 μs
13107.2 μs
6553.6 μs
819.2 μs
3276.8 μs 13107.2 μs
1638.4 μs
6553.6 μs
26214.4 μs
3276.8 μs 13107.2 μs
1638.4 μs
6553.6 μs 26214.4 μs
3276.8 μs
13107.2 μs
52428.8 μs
1638.4 μs
6553.6 μs 26214.4 μs
3276.8 μs
13107.2 μs
52428.8 μs
13107.2 μs
φT4
2
φT4
φT16
3276.8 μs
XXX: Don’t care
(5) Operating mode summary
Table 3.7.4 shows the settings for the TMRA01 for each of the operating modes.
Table 3.7.4 Register Settings for Each Operating Mode
Register
TA01MOD
Field
TA01M[1:0]
Function
Interval Timer
Mode
TA1FFCR
PWM[01:00]
TA1CLK[1:0]
TA0CLK[1:0]
TA1FFIS
PWM Period
UC1 Clock
Source
UC0 Clock
Source
Timer Flip-flop
Toggle Trigger
Match output from
External clock,
UC0
φT1, φT4, φT16
φT1, φT16, φT256
(00, 01, 10, 11)
(00, 01, 10, 11)
8-bit timer × 2 ch
00
−
16-bit timer mode
01
−
−
8-bit PPG × 1 ch
10
−
−
8-bit PWM × 1 ch
11
2 ,2 ,2
(01, 10, 11)
−
8-bit PWM × 1 ch
11
−
φT1, φT16, φT256
(01, 10, 11)
0: UC0 output
1: UC1 output
External clock,
φT1, φT4, φT16
(00, 01, 10, 11)
−
External clock,
6
7
φT1, φT4, φT16
(00, 01, 10, 11)
−
External clock,
8
φT1, φT4, φT16
(00, 01, 10, 11)
−
−
Output disabled
−: Don’t care
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2006-03-24
TMP91CW28
3.8
16-Bit Timers/Event Counters (TMRB)
The TMP91CW28 has a 16-bit timer/event counter consisting of two identical channels
(TMRB0 and TMRB1). Each channel has the following three basic operating modes:
•
16-bit interval timer mode
•
16-bit event counter mode
•
16-bit programmable pulse generation (PPG) mode
Each channel has the capture capability used to latch the value of the counter. The capture
capability allows:
•
Frequency measurement
•
Pulse width measurement
•
Time difference measurement
Figure 3.8.1 and Figure 3.8.2 are block diagrams of the TMRB0 and the TMRB1.
The main components of a TMRBn block are a 16-bit up counter, two 16-bit timer registers
(One of which is double-buffered), two 16-bit capture registers, two comparators, capture
control logic, a timer flip-flop and its associated control logic.
A total of eleven special function registers (SFRs) provide control over the operating modes
and timer flip-flops for the TMRB0 and the TMRB1 each, which can be independently
programmed. The TMRB0 and the TMRB1 are functionally equivalent. In the following
sections, any references to the TMRB0 also apply to the TMRB1.
Table 3.8.1 gives the pins and registers for the two channels.
Table 3.8.1 Pins and Registers for the TMRB0 and the TMRB1
Channel
Specifications
External
pins
External clock/capture
trigger inputs
Timer flip-flop output
Registers
TMRB0
TMRB1
TB0IN0 (Shared with P80)
TB1IN0 (Shared with P84)
TB0IN1 (Shared with P81)
TB1IN1 (Shared with P85)
TB0OUT0 (Shared with P82)
TB1OUT0 (Shared with P86)
TB0OUT1 (Shared with P83)
TB1OUT1 (Shared with P87)
Timer run register
TB0RUN (0180H)
TB1RUN (0190H)
Timer mode register
TB0MOD (0182H)
TB1MOD (0192H)
Timer flip-flop control
register
TB0FFCR (0183H)
TB1FFCR (0193H)
TB0RG0L (0188H)
TB1RG0L (0198H)
Timer registers
(Addresses)
Capture registers
TB0RG0H (0189H)
TB1RG0H (0199H)
TB0RG1L (018AH)
TB1RG1L (019AH)
TB0RG1H (018BH)
TB1RG1H (019BH)
TB0CP0L (018CH)
TB1CP0L (019CH)
TB0CP0H (018DH)
TB1CP0H (019DH)
TB0CP1L (018EH)
TB1CP1L (019EH)
TB0CP1H (018FH)
TB1CP1H (019FH)
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TA1OUT
(from TMRA01)
TB0IN0
TB0IN1
INT5
INT6
Prescaler clock
source: φT0
External interrupt
4
φT4
91CW28-117
TB0RUN.
TB0RDE
TB0MOD.
TB0CPM[1:0]
Selector
Counter
clock
Internal data bus
Register buffer 0
16-bit timer
register
TB0RG0H/L
16-bit
comparator
(CP0)
Match
detect
Internal data bus
16-bit timer
register
TB0RG1H/L
TB0FF1
TB0FF0
Match detect
Timer
flip-flop
control
Timer
flip-flop
Interrupt output
Register 0 Register 1
INTTB00 INTTB01
16-bit
comparator
(CP1)
TB0RUN.TB0RUN
TB0MOD.TB0CLE
Capture register 1
TB0CP1H/L
16-bit up counter
(UC0)
Capture register 0
TB0CP0H/L
TB0MOD.TB0CLK[1:0]
φT1
φT4
φT16
TB0MOD.
TB0CP0
φT16
Capture and
external interrupt
control
φT1
2
Run/
clear TB0RUN.
8 16 32
TB0PRUN
Internal data bus
Overflow
interrupt
INTTBOF0
TB0OUT1
TB0OUT0
Timer flip-flop
output
3.8.1
Internal data bus
TMP91CW28
Block Diagrams
Figure 3.8.1 TMRB0 Block Diagram
2006-03-24
TA1OUT
(from TMRA01)
TB1IN0
TB1IN1
External interrupt
INT7
INT8
Prescaler clock
source: φT0
4
φT4
TB1MOD.
φT16
91CW28-118
TB1RUN.
TB1RDE
TB1MOD.
TB1CPM[1:0]
Internal data bus
Register buffer 0
16-bit timer
register
TBIRG0H/L
16-bit
comparator
(CP0)
TB1MOD.TB1CLK[1: 0]
Match
detect
Internal data bus
16-bit timer
register
TBIRG1H/L
16-bit
comparator
(CP1)
TB1RUN.TB1RUN
TB1MOD.TB1CLE
Capture register 1
TB1CP1H/L
Internal data bus
16-bit up counter
(UC0)
Capture register 0
TB1CP0H/L
Selector
Counter
φT1
clock
φT4
φT16
Capture &
TB1CP0
external interrupt
control
φT1
2
Run/
clear TB1RUN.
8 16 32
TB1PRUN
Internal data bus
Interrupt output
Match
detect
Timer
flip-flop
control
TB1FF1
TB1FF0
Timer
flip-flop
Register 0 Register 1
INTTB10 INTTB11
Overflow
interrupt
INTTBOF1
TB1OUT1
TB1OUT0
Timer flip-flop
output
TMP91CW28
Figure 3.8.2 TMRB1 Block Diagram
2006-03-24
TMP91CW28
3.8.2
Timer Components
(1) Prescaler
The TMRB0 has a 5-bit prescaler that slows the rate of a clocking source to the
counter. The prescaler clock source (φT0) has one-fourth the frequency selected by
programming the PRCK[1:0] field of the SYSCR0 located within the clock gear.
The TB0RUN bit in the TB0RUN register allows the enabling and disabling of the
prescaler for the TMRB0. A write of 1 to this bit starts the prescaler. A write of 0 to this
bit clears and halts the prescaler. Table 3.8.2 shows prescaler output clock resolutions.
Table 3.8.2 Prescaler Output Clock Resolutions
at fc = 10 MHz
Prescaler
Clock Source
Clock Gear
Value
PRCK[1:0]
GEAR[2:0]
00
(fFPH)
10
(fc/16 clock)
Prescaler Output Clock Resolution
φT1
φT4
φT16
000 (fc)
2 /fc ( 0.8 μs)
2 /fc ( 3.2 μs) 2 /fc ( 12.8 μs)
001 (fc/2)
2 /fc ( 1.6 μs)
2 /fc ( 6.4 μs) 2 /fc ( 25.6 μs)
010 (fc/4)
2 /fc ( 3.2 μs)
2 /fc ( 12.8 μs) 2 /fc ( 51.2 μs)
011 (fc/8)
2 /fc ( 6.4 μs)
2 /fc ( 25.6 μs) 2 /fc ( 102.4 μs)
100 (fc/16)
2 /fc ( 12.8 μs)
2 /fc ( 51.2 μs) 2 /fc ( 204.8 μs)
XXX
2 /fc ( 12.8 μs)
2 /fc ( 51.2 μs) 2 /fc ( 204.8 μs)
3
4
5
6
7
7
5
6
7
8
9
9
7
8
9
10
11
11
xxx: Don’t care
(2) Up counter (UC0)
The TMRB0 contains a 16-bit binary up counter, which is driven by a clock selected
by the TB0CLK[1:0] field in the TB0MOD register. The clock input to the UC0 is either
one of three prescaler outputs (φΤ1, φT4, φT16) or the external clock applied to the
TB0IN0 pin.
The TB0RUN bit in the TB0RUN register is used to start the UC0 and to stop and
clear the UC0. The UC0 is cleared to 0000H, if so enabled, when it reaches the value in
the TB0RG1H/L register. The TB0CLE bit in the TB0MOD register allows the user to
enable and disable this clearing. If it is disabled, the UC0 acts as a free-running
counter.
An overflow interrupt (INTTBOF0) is generated upon a counter overflow.
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TMP91CW28
(3) Timer registers (TB0RG0H/L and TB0RG1H/L)
Each timer channel has two 16-bit timer registers containing a time constant. When
the up counter reaches the time constant value in each timer register, the associated
comparator block generates a match-detect signal.
Setting data for both upper and lower timer registers TB0RG0 and TB0RG1 is
always needed. And each of the timer registers (TB0RG0H/L, TB0RG1H/L) can be
written with either a halfword-store instruction or a series of two byte-store
instructions. When byte-store instructions are used, the low-order byte must be stored
first, followed by the high-order byte. The 16-bit timer registers are often simply
referred to as TB0RG0 and TB0RG1 without the high and low suffix.
One of the two timer registers, TB0RG0, is double-buffered. The double-buffering
function can be enabled and disabled through the programming of the TB0RDE bit in
the TB0RUN: 0 = disable, 1 = enable.
If double-buffering is enabled, the TB0RG0 latches a new time constant value from
the register buffer. This takes place when a match is detected between the UC0 and the
TB0RG1.
Upon reset, the contents of the TB0RG0 and TB0RG1 are undefined; thus, they must
be loaded with valid values before the timer can be used. A reset clears the
TB0RUN.TB0RDE bit to 0, disabling the double-buffering function. To use this
function, the TB0RUN.TB0RDE bit must be set to 1 after loading the TB0RG0 and
TB0RG1 with time constants. When TB0RUN.TB0RDE = 1, the next time constant can
be written to the register buffer.
The TB0RG0 and the corresponding register buffer are mapped to the same address
(0188H and 0189H). When TB0RUN.TB0RDE = 0, a time constant value is written to
both the TB0RG0 and the register buffer; when TB0RUN.TB0RDE = 1, a time constant
value is written only to the register buffer. Therefore, the double-buffering function
should be disabled when writing an initial time constant to the timer register.
The following diagram shows the addresses of each timer register.
TMRB0
TB0RG0
TB0RG1
8 high-order bits
(TB0RG0H)
8 low-order bits
(TB0RG0L)
8 high-order bits
(TB0RG1H)
8 low-order bits
(TB0RG1L)
000189H
000188H
00018BH
00018AH
TMRB1
TB1RG0
TB1RG1
8 high-order bits
(TB1RG0H)
8 low-order bits
(TB1RG0L)
8 high-order bits
(TB1RG1H)
8 low-order bits
(TB1RG1L)
000199H
000198H
00019BH
00019AH
The timer registers are write only registers and cannot be read.
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2006-03-24
TMP91CW28
(4) Capture registers (TB0CP0H/L and TB0CP1H/L)
The capture registers are 16-bit registers used to latch the value of the up counter
(UC0).
Data in the capture registers should be read all 16 bits. And each of the capture
registers can be read with either a halfword-load instruction or a series of two
byte-load instructions. When byte-load instructions are used, the low-order byte must
be read first, followed by the high-order byte. The 16-bit capture registers are often
simply referred to as TBnCP and TBnCP1 without the high and low suffix.
The following diagram shows the addresses of each capture register.
TMRB0
TB0CP0
8 high-order bits
8 low-order bits
(TB0CP0H)
(TB0CP0L)
00018DH
TB0CP1
8 high-order bits
8 low-order bits
(TB0CP1H)
(TB0CP1L)
00018CH
00018FH
00018EH
TMRB1
TB1CP0
8 high-order bits
8 low-order bits
(TB1CP0H)
(TB1CP0L)
00019DH
TB1CP1
8 high-order bits
8 low-order bits
(TB1CP1H)
(TB1CP1L)
00019CH
00019FH
00019EH
The capture registers are read-only registers and cannot be written by software.
(5) Capture and external interrupt control logic
This circuit block controls the capture of an up counter (UC0) value into the capture
registers (TB0CP0 and TB0CP1). It also controls generation of external interrupts.
The TB0CPM[1:0] field in the TB0MOD register selects a capture trigger input to be
sensed by the control logic, as well as the edge that triggers an external interrupt.
Furthermore, a counter value can be captured under software control; a write of 0 to
the TB0MOD.TB0CP0I bit causes the current UC0 value to be latched into the
TB0CP0. To use the capture capability, the prescaler must be running (e.g.,
TB0RUN.TB0PRUN = 1).
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2006-03-24
TMP91CW28
(6) Comparators (CP0 and CP1)
The TMRB0 contains two 16-bit comparators. The CP0 block compares the output of
the up counter (UC0) with a time constant value in the TB0RG0. The CP1 block
compares the output of the UC0 with a time constant value in the TB0RG1. When a
match is detected, an interrupt (INTTB00/INTTB01) is generated.
(7) Timer flip-flops (TB0FF0 and TB0FF1)
The timer flip-flops (TB0FF0 and TB0FF1) are toggled, if so enabled, upon assertion
of match-detect signals from the comparators and latch signals from the capture
control logic. The toggling of the TB0FF0 and TB0FF1 can be enabled and disabled
through the programming of the TB0C1T1, TB0C0T1, TB0E1T1 and TB0E0T1 bits in
the TB0FFCR register.
Upon reset, the TB0FF0 and TB0FF1 assume an undefined state. They can be
initialized to 1 or 0 by writing 01 or 10 to the TB0FF0C[1:0] and TB0FF1C[1:0] fields in
the TB0FFCR. A write of 01 to one of these fields sets the corresponding timer flip-flop;
a write of 10 clears the timer flip-flop. Additionally, a write of 00 causes the timer
flip-flop to be toggled to the opposite value.
The values of the TB0FF0 and TB0FF1 can be driven onto the TB0OUT0 pin, which
is multiplexed with P82 and the TB0OUT1 pin, which is multiplexed with P83,
respectively. The port 8 registers (P8CR and P8FC) must be programmed to configure
the P82/TB0OUT0 pin as TB0OUT0 or the P83/TB0OUT1 pin as TB0OUT1.
91CW28-122
2006-03-24
TMP91CW28
3.8
3.8.3
SFR Description
TMRB0 Run Register
TB0RUN
(0180H)
7
6
3
2
Bit symbol
TB0RDE
−
I2TB0
TB0PRUN
TB0RUN
Read/Write
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
Function
Double
buffering
0: Disable
5
4
Must be
written as
“0”.
1
0
IDLE2
16-bit timer run/stop control
0: OFF
0: Stop and clear
1: ON
1: Run
1: Enable
Counting
I2TB0:
0
Stop and clear
1
Count up
Timer ON/OFF in IDLE2 mode
TB0PRUN: Prescaler
TB0RUN: TMRB0
Note: Bits1, 4, and 5 are read as undefined.
TMRB1 Run Register
7
TB1RUN
(0190H)
6
5
4
3
2
1
0
Bit symbol
TB1RDE
−
I2TB1
TB1PRUN
TB1RUN
Read/Write
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
Function
Double
buffering
0: Disable
Must be
written as
“0”.
IDLE2
16-bit timer run/stop control
0: OFF
0: Stop and clear
1: ON
1: Run
1: Enable
Counting
I2TB1:
0
Stop and clear
1
Count up
Timer ON/OFF in IDLE2 mode
TB1PRUN: Prescaler
TB1RUN: TMRB1
Note: Bits1, 4, and 5 are read as undefined.
Figure 3.8.3 TMRB Registers (1)
91CW28-123
2006-03-24
TMP91CW28
TMRB0 Mode Register
TB0MOD
(0182H)
Bit symbol
6
5
TB0ET1
TB0CPI
Read/Write
Reset value
Function
Readmodifywrite
operation
is not
supported.
7
TB0CT1
R/W
0
4
2
1
0
TB0CLE
TB0CLK1
TB0CLK0
0
0
W*
0
R/W
1
TB0FF1 toggle trigger
0
0: Trigger disabled
Software
capture
1: Trigger enabled
0: Capture
When UC0
value is
latched into
capture
register 1
3
TB0CPM1 TB0CPM0
When UC0
reaches
timer
register 1
value
0
Capture triggers
00: Disabled
INT5 rising edge
1: Undefined 01: TB0IN0 ↑, TB0IN1 ↑
INT5 rising edge
0
Up counter TMRB0 input clock
clear control 00: TB0IN0 input
0: Disable
01: φT1
1: Enable
10: TB0IN0 ↑, TB0IN0 ↓
INT5 falling edge
10: φT4
11: φT16
11: TA1OUT ↑
TA1OUT ↓
INT5 rising edge
Input clock
00
External input clock (TB0IN0 input)
01
φT1
10
φT4
11
φT16
Up counter (UC0) clear control
0
Disabled
1
Cleared upon a match with TB0RG1
Capture/interrupt triggers
Capture control
00
Capture disabled
Latches UC0 value into TB0CP0 at
01
rising edges of TB0IN0.
INT5 control
INT5 occurs at rising
edges of TB0IN0.
Latches UC0 value into TB0CP1 at
rising edges of TB0IN1.
10
Latches UC0 value into TB0CP0 at
INT5 occurs at falling
rising edges of TB0IN0.
edges of TB0IN0.
Latches UC0 value into TB0CP1 at
falling edges of TB0IN0.
11
Latches UC0 value into TB0CP0 at
INT5 occurs at rising
rising edges of TA1OUT.
edges of TB0IN0.
Latches UC0 value into TB0CP1 at
falling edges of TA1OUT.
Software capture
0
Latches UC0 value into TB0CP0.
1
Undefined
Figure 3.8.4 TMRB Registers (2)
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TMP91CW28
TMRB1 Mode Register
TB1MOD
(0192H)
Bit symbol
6
5
TB1ET1
TB1CPI
Read/Write
Reset value
Function
Readmodifywrite
operation
is not
supported.
7
TB1CT1
R/W
0
4
2
1
0
TB1CLE
TB1CLK1
TB1CLK0
0
0
W*
0
R/W
1
TB1FF1 toggle trigger
0
0: Trigger disabled
Software
capture
1: Trigger enabled
0: Capture
When UC0
value is
latched into
capture
register 1
3
TB1CPM1 TB1CPM0
When UC0
reaches
timer
register 1
value
0
Capture triggers
00: Disabled
INT7 rising edge
1: Undefined 01: TB1IN0↑, TB1IN1↑
INT7 rising edge
0
Up counter TMRB1 source clock
clear control 00: TB1IN0 input
0: Disable
01: φT1
1: Enable
10: φT4
11: φT16
10: TB1IN0↑, TB1IN0↓
INT7 falling edge
11: TA3OUT↑, TA3OUT↓
INT7 rising edge
Input clock
00
External input clock (TB1IN0 input)
01
φT1
10
φT4
11
φT16
Up counter (UC0) clear control
0
Disabled
1
Cleared upon a match with TB1RG1
Capture/interrupt triggers
Capture control
00
Capture disabled
Latches UC0 value into TB1CP0 at
01
INT7 control
INT7 occurs at rising
edges of TB1IN0.
rising edges of TB1IN0.
Latches UC0 value into TB1CP1 at
rising edges of TB1IN1.
Latches UC0 value into TB1CP0 at
10
rising edges of TB1IN0.
INT7 occurs at falling
edges of TB1IN0.
Latches UC0 value into TB1CP1 at
falling edges of TB1IN0.
Latches UC0 value into TB1CP0 at
11
rising edges of TA3OUT.
INT7 occurs at rising
edges of TB1IN0.
Latches UC0 value into TB1CP1 at
falling edges of TA3OUT.
Software capture
0
Latches UC0 value into TB1CP0
1
Undefined
Figure 3.8.5 TMRB Registers (3)
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TMRB0 Flip-flop Control Register
7
TB0FFCR Bit symbol
(0183H)
Read/Write
Reset value
Function
Readmodifywrite
operation
is not
supported.
TB0FF1C1
6
5
4
TB0FF1C0
TB0C1T1
TB0C0T1
W*
1
3
2
1
TB0E1T1
TB0E0T1
TB0FF0C1
R/W
1
0
0
0
TB0FF0C0
W*
0
0
1
TB0FF1 control
TB0FF0 toggle trigger
TB0FF0 control
00: Toggle
0: Trigger disabled
00: Toggle
01: Set
1: Trigger enabled
01: Set
10: Clear
11: Don’t care
1
10: Clear
UC0 →
This field is always TB0CP1
read as “11”.
UC0 →
TB0CP0
UC0 =
TB0RG1
UC0 =
TB0RG0
11: Don’t care
This field is always
read as “11”.
Timer flip-flop (TB0FF0) control
00
Toggles TB0FF0 (Software toggle)
01
Sets TB0FF0 to 1
10
Clears TB0FF0 to 0
11
Don’t care (Read as 11)
When UC0 reaches TB0RG0 value
0
Toggle trigger disabled
1
Toggle trigger enabled
When UC0 reaches TB0RG1 value
0
Toggle trigger disabled
1
Toggle trigger enabled
When UC0 value is latched into TB0CP0
0
Toggle trigger disabled
1
Toggle trigger enabled
When UC0 value is latched into TB0CP1
0
Toggle trigger disabled
1
Toggle trigger enabled
Figure 3.8.6 TMRB Registers (4)
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TMRB1 Flip-flop Control Register
TB1FFCR Bit symbol
(0193H)
Read/Write
Reset value
Function
Readmodifywrite
operation
is not
supported.
7
6
5
4
3
2
1
0
TB1FF1C1
TB1FF1C0
TB1C1T1
TB1C0T1
TB1E1T1
TB1E0T1
TB1FF0C1
TB1FF0C0
0
0
0
0
1
W*
1
R/W
1
W*
TB1FF1 control
TB1FF0 toggle trigger
TB1FF0 control
00: Toggle
0: Trigger disabled
00: Toggle
01: Set
1: Trigger enabled
01: Set
10: Clear
11: Don’t care
1
10: Clear
UC0 →
This field is always TB1CP1
read as “11”.
UC0 →
TB1CP0
UC0 =
TB1RG1
UC0 =
TB1RG0
11: Don’t care
This field is always
read as “11”.
Timer flip-flop (TB1FF0) control
00
Toggles TB1FF0 (Software toggle)
01
Sets TB1FF0 to 1
10
Clears TB1FF0 to 0
11
Don’t care (Read as 11)
When UC0 reaches TB1RG0 value
0
Toggle trigger disabled
1
Toggle trigger enabled
When UC0 reaches TB1RG1 value
0
Toggle trigger disabled
1
Toggle trigger enabled
When UC0 value is latched into TB1CP0
0
Toggle trigger disabled
1
Toggle trigger enabled
When UC0 value is latched into TB1CP1
0
Toggle trigger disabled
1
Toggle trigger enabled
Figure 3.8.7 TMRB Registers (5)
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TMRB Register
7
TB0RG0L
(0188H)
TB0RG0H
(0189H)
TB0RG1L
(018AH)
TB0RG1H
(018BH)
TB1RG0L
(0198H)
TB1RG0H
(0199H)
TB1RG1L
(019AH)
TB1RG1H
(019BH)
6
5
4
3
bit Symbol
–
Read/Write
W
Reset value
Undefined
bit Symbol
1
0
–
Read/Write
W
Reset value
Undefined
bit Symbol
–
Read/Write
W
Reset value
Undefined
bit Symbol
–
Read/Write
W
Reset value
Undefined
bit Symbol
–
Read/Write
W
Reset value
Undefined
bit Symbol
2
–
Read/Write
W
Reset value
Undefined
bit Symbol
–
Read/Write
W
Reset value
Undefined
bit Symbol
–
Read/Write
W
Reset value
Undefined
Note: Ther above registers are prohibited read-modify-write instruction.
Figure 3.8.8 TMRB Registers (6)
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3.8
3.8.4
Operating Modes
(1) 16-bit interval timer mode
In the following example, the TMRB0 is used to accomplish periodic interrupt
generation. The interval time is set in timer register 1 (TB0RG1), and the INTTB01
interrupt is enabled.
7
6
5
4
3
2
1
TB0RUN
←
−
0
X
X
−
0
X
0
0
Stops the TMRB0.
INTETB0
←
X
1
0
0
X
0
0
0
Enables INTTB01, sets its priority level to 4 and disables
TB0FFCR
←
1
1
0
0
0
0
1
1
Disables the timer flip-flop toggle trigger.
TB0MOD
←
0
0
1
0
0
1
*
*
Selects a prescaler output clock as the timer
INTTB00.
(** = 01, 10, 11)
TB0RG1
←
*
*
*
*
*
*
*
TB0RUN
←
−
0
X
X
−
1
*
*
*
*
*
clock source and disables the capture function.
*
Sets the interval time
*
*
(16 bits).
X
1
Starts the TMRB0.
*
X: Don’t care, −: No change
(2) 16-bit event counter mode
This mode is used to count events by interpreting the rising edges of the external
counter clock (TB0IN0) as events.
The up counter (UC0) counts up on each rising clock edge. The counter value is
latched into a capture register under software control. To determine the number of
events (e.g., cycles) counted, the value in the capture register must be read.
7
6
5
4
3
2
1
0
TB0RUN
←
−
0
X
X
−
0
X
0
Stops the TMRB0.
P8CR
←
Configures the P80 pin for input mode.
P8FC
←
− − − − − − −
− − − − − − −
0
INTETB0
←
X
1
0
0
X
0
0
0
Enables INTTB01 (Interrupt level = 4) and disables
TB0FFCR
←
1
1
0
0
0
0
1
1
Disables the timer flip-flop toggle trigger.
TB0MOD
←
0
0
1
0
0
1
0
0
Selects the TB0IN0 input as the timer clock source.
TB0RG1
←
*
*
*
*
*
*
*
*
Sets a count value
←
*
*
*
*
*
*
*
*
(16 bits).
←
−
0
X
X
−
1
X
1
Starts the TMRB0.
1
INTTB00.
TB0RUN
X: Don’t care, −: No change
Even when the timer is used for event counting, the prescaler must be programmed
to run (e.g., the TB0RUN.TB0PRUN bit must be set to 1).
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(3) 16-bit programmable pulse generation (PPG) mode
The 16-bit PPG mode can be used to generate a square wave with any frequency and
duty cycle. The pulse can be high going and low going, as determined by the initial
setting of the timer flip-flop (TB0FF).
A square wave is generated by toggling the timer flip-flop every time the up counter
UC0 reaches the values in each timer register (TB0RG0 and TB0RG1). The
square-wave output is driven to the TB0OUT0 pin. In this mode, the following
relationship must be satisfied:
(TB0RG0 value) < (TB0RG1 value)
TB0RG0 match
(INTTB00 interrupt)
TB0RG1 match
(INTTB01 interrupt)
TB0OUT0 pin
Figure 3.8.8 PPG Output Waveform
If the double-buffering function is enabled, the TB0RG0 value can be changed
dynamically by writing a new value into the register buffer. Upon a match between the
TB0RG1 and the UC0, the TB0RG0 latches a new value from the register buffer. The
TB0RG0 can be loaded with a new value upon every match, thus making it easy to
generate a square wave with virtually any duty cycle.
TB0RG0 match
Up counter = Q1
Up counter = Q2
TB0RG1 match
TB0RG0
(Compare value)
Register buffer
Shift into TB0RG1
Q1
Q2
Q2
Q3
Write to TB0RG0
Figure 3.8.9 Register Buffer Operation
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Figure 3.8.10 shows a functional diagram of 16-bit PPG mode.
TB0IN0
φT1
φT4
φT16
TB0RUN.TB0RUN
TB0OUT0 (PPG output)
Selector
16-bit up counter
Clear
UC0
F/F
(TB0FF0)
Match
16-bit comparator
Selector
16-bit comparator
TB0RG0
TB0RG0-WR
Register buffer 0
TB0RUN.TB0RDE
TB0RG1
Internal data bus
Figure 3.8.10 Functional Diagram of 16-Bit PPG Mode
The following is an example of running the timer in 16-bit PPG mode.
7
6
5
4
3
2
1
0
TB0RUN
←
0
0
X
X
−
0
X
0
Disables the TB0RG0 double buffering and stops the
TB0RG0
←
*
*
*
*
*
*
*
*
Defines the duty cycle.
←
*
*
*
*
*
*
*
*
(16 bits).
TB0RG1
←
*
*
*
*
*
*
*
*
Defines the cycle period.
TMRB0.
←
*
*
*
*
*
*
*
*
(16 bits).
TB0RUN
←
1
0
X
X
−
0
X
0
Enables the TB0RG0 double buffering. (The duty cycle
TB0FFCR
←
X
X
0
0
1
1
1
0
Toggles the TB0FF0 when a match is detected between
and cycle period are changed by the INTTB01 interrupt.)
UC0 and TB0RG0 and between UC0 and TB0RG1.
Initially clears the TB0FF0 to 0.
TB0MOD
←
0
0
1
0
0
1
*
*
(** = 01, 10, 11)
P8FC
← −
← −
TB0RUN
←
P8CR
1
−
−
0
−
−
−
−
−
1
X
1
−
−
−
−
−
X −
1
X
1
Selects a prescaler output clock as the timer clock source
and disables the capture function.
Configures the P82 pin as TB0OUT0.
Starts the TMRB0.
X: Don’t care, −: No change
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(4) Timing and measurement functions using the capture capability
The capture capability of the TMRBn provides versatile timing and measurement
functions, including the following:
a.
One-shot pulse generation using an external trigger pulse
b.
Frequency measurement
c.
Pulse width measurement
d.
Time difference measurement
a.
One-shot pulse generation using an external trigger pulse
The TMRBn can be used to produce a one-time pulse as follows.
The 16-bit up counter (UC0) is programmed to function as a free-running
counter, clocked by one of the prescaler outputs. The TB0IN0 pin is used as an
active-high external trigger pulse input for latching the counter value into capture
register 0 (TB0CP0).
An INT5 interrupt is generated upon detection of a rising edge on the
TB0IN0/INT5 pin. A one-shot pulse has a delay and width controlled by the values
stored in the timer registers (TB0RG0 and TB0RG1). Programming the TB0RG0
and TB0RG1 is the responsibility of the INT5 interrupt handler. The TB0RG0 is
loaded with the sum of the TB0CP0 value (c) plus the pulse delay (d) − e.g., (c) + (d).
The TB0RG1 is loaded with the sum of the TB0RG0 value plus the pulse width (p)
− e.g., (c) + (d) + (p).
Next, the TB0E1T1 and TB0E0T1 bits in the timer flip-flop control register
(TB0FFCR) are set to 11, so that the timer flip-flop (TB0FF0) will toggle when a
match is detected between the UC0 and the TB0RG0 and between the UC0 and
the TB0RG1. With the TB0FF0 toggled twice, a one-shot pulse is produced. Upon
a match between the UC0 and the TB0RG1, the TMRB0 generates the INTTB01
interrupt, which must disable the toggle trigger for the TB0FF0.
Figure 3.8.11 depicts one-shot pulse generation, with annotations showing (c),
(d), and (p).
The counter is free-running.
Counter clock
(Internal clock)
c+d+p
c+d
c
TB0IN0 input pin
(External trigger pulse)
The UC0 value is latched into TB0CP1.
INT5 is generated.
TB0RG0 match
Toggle is
enabled.
INTTB01 is
generated.
TB0RG1 match
TB0OUT0 (Timer output) pin
Toggle is disabled
for a capture into
TB0CP1.
Toggle is
enabled.
Delay
Pulse width
(d)
(p)
Figure 3.8.11 One-shot Pulse Generation (with a delay)
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Example: Generating a one-shot pulse with a width of 2 ms and a delay of 3 ms on
assertion of an external trigger pulse on the TB0IN0 pin
High-speed clock gear: × 1 (fc)
Clocking conditions:
Prescaler clock:
fFPH
Settings in the main routine
Places the counter in free-running mode.
Selects φT1 as the counter clock source.
TB0MOD
←
X
X
1
0
1
0
0
1
TB0FFCR
←
X
X
0
0
0
0
1
0
Latches UC0 value into TB0CP0 at rising edges of the
TB0IN0 input.
Clears TB0FF0 to 0.
Disables the toggle trigger for TB0FF0.
P8CR
←
–
–
–
–
–
1
–
–
P8FC
←
–
–
–
–
–
1
–
–
INTE56
←
X
–
–
–
X
1
0
0
INTETB0
←
X
0
0
0
X
0
0
0
TB0RUN
←
–
0
X
X
–
1
X
1
1
–
–
Configures the P82 pin as TB0OUT0.
Enables INT5 and disables INTTB00 and INTTB01.
Starts the TMRB0.
Settings in INT5
TB0RG0
← TB0CP0 + 3 ms/φT1
TB0RG1
← TB0RG0 + 2 ms/φT1
TB0FFCR
←
X
X
–
–
1
Enables the TB0FF0 toggle trigger for TB0RG0 and
TB0RG1 matches.
INTETB0
←
X
1
0
0
X
–
–
–
X
–
–
0
0
–
–
Enables INTTB01.
Settings in INTTB01
TB0FFCR
←
X
Disables the TB0FF0 toggle trigger for TB0RG0 and
TB0RG1 matches.
INTETB0
←
X
0
0
0
X
–
–
–
Disables INTTB01.
X: Don’t care, −: No change
If no delay is necessary, enable the TB0FF0 toggle trigger for a capture of the UC0
value into the TB0CP0. Use the INT5 interrupt to load the TB0RG1 with a sum of the
TB0CP0 value (c) plus the pulse width (p) and to enable the TB0FF0 toggle trigger for
a match between the UC0 and TB0RG1 values. A match generates the INTTB01
interrupt, which then is to disable the TB0FF0 toggle trigger.
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Counter clock
(Prescaler output clock)
c+p
c
TB0IN0 Input
(External trigger pulse)
The UC0 value is latched into TB0CP0.
INT5 is generated.
The UC0 value is latched into
TB0CP1.
INTTB01 is
generated.
TB0RG1 match
Toggle is enabled.
TB0OUT0 (Timer output) pin
Pulse width
(p)
Toggle is enabled for a capture
into TB0CP0.
Toggle is left disabled for a capture into
TB0CP1 so that it will not be toggled.
Figure 3.8.12 One-shot Pulse Generation (without a delay)
b.
Frequency measurement
The capture function can be used to measure the frequency of an external clock.
Frequency measurement requires a 16-bit TMRBn channel running in event
counter mode and the 8-bit TMRA01. The timer flip-flop (TA1FF) in the TMRA01
is used to define the duration during which a measurement is taken.
Select the TB0IN0 pin as the clock source for the TMRB0. Set the TB0CPM[1:0]
field in the TB0MOD to 11 to select the TA1FF output signal from the TMRA01 as
a capture trigger input. This causes the TMRB0 to latch the 16-bit up counter
(UC0) value into capture register 0 (TB0CP0) on the low-to-high transition of the
TA1FF and into capture register 1 (TB0CP1) on the next high-to-low transition of
the TA1FF.
Either the INTTA0 or INTTA1 interrupt generated by the 8-bit timer can be
used to make a frequency calculation.
Counter clock
(TB0IN0 input)
C2
C1
TA1FF
Capture into TB0CP0
Capture into TB0CP1
C1
C1
C2
C2
INTTA0/INTTA1
Figure 3.8.13 Frequency Measurement
For example, if the TA1FF of the 8-bit timer is programmed to be at logic 1 for a
period of 0.5 seconds and the difference between the values captured into the
TB0CP0 and TB0CP1 is 100, then the TB0IN0 frequency is calculated as 100 ÷
0.5 s = 200 Hz.
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c.
Pulse width measurement
The capture function can be used to measure the pulse width of an external
clock. The external clock is applied to the TB0IN0 pin. The up counter (UC0) is
programmed to operate as a free-running counter, clocked by one of the prescaler
outputs. The capture function is used to latch the UC0 value into capture register
0 (TB0CP0) at the clock rising edge and into capture register 1 (TB0CP1) at the
next clock falling edge. An INT5 interrupt is generated at the falling edge of the
TB0IN0 input.
Multiplying the counter clock period by the difference between the values
captured into the TB0CP0 and TB0CP1 gives the high pulse width of the TB0IN0
clock.
For example, if the prescalar output clock has a period of 0.8 µs and the
difference between the TB0CP0 and TB0CP1 is 100, the high pulse width is
calculated as 0.8 μs × 100 = 80 μs.
Measuring a pulse width exceeding the maximum counting time for the UC0,
which depends on the clock source, requires software programming.
Prescaler output clock
C2
C1
TB0IN0 input
(External clock)
Capture into TB0CP0
C1
C1
C2
C2
Capture into TB0CP1
INT5
Figure 3.8.14 Pulse Width Measurement
Note: To measure a pulse width, set the TB0CPM[1:0] field of the TB0MOD to 10, so
that an INT5 external interrupt is generated at the falling edge of the TB0IN0
input. Otherwise, an INT5 interrupt is generated at the rising edge of the TB0IN0
input.
The low pulse width can be measured by the second INT5 interrupt. This is
accomplished by multiplying the counter clock period by the difference between
the TB0CP0 value at the first C2 and the TB0CP1 value at the second C1.
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d.
Time difference measurement
The capture function can be used to measure the time difference between two
event occurrences. The 16-bit up counter (UC0) is programmed to operate as a
free-running counter. The UC0 value is latched into capture register 0 (TB0CP0)
on the rising edge of TB0IN0. An INT5 interrupt is generated at this time.
Then, the UC0 value is latched into capture register 1 (TB0CP1) on the rising
edge of TB0IN1. An INT6 interrupt is generated at this time.
The time difference between the two events that occurred on the TB0IN0 and
TB0IN1 pins is calculated by multiplying the counter clock period by the
difference between the TB0CP1 and TB0CP0 values.
Prescaler output clock
C2
C1
TB0IN0 input
TB0IN1 input
Capture into TB0CP0
Capture into TB0CP1
INT5
INT6
Time difference
Figure 3.8.15 Time Difference Measurement
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3.9
Serial I/O (SIO)
The TMP91CW28 contains a single serial I/O channel (SIO). The SIO provides universal
asynchronous receiver/transmitter (UART) mode and synchronous I/O interface mode.
Transmits/receives a serial clock (SCLK) as well as data
streams for a synchronous clock mode of operation.
Mode 1: 7 data bits
Mode 2: 8 data bits
Mode 3: 9 data bits
• I/O interface mode
• UART mode
In mode 1 and mode 2, each character can include a parity bit. In mode 3, the SIO channel
operates in a wakeup mode for multidrop applications in which a master station is connected to
several slave stations through a serial link.
Figure 3.9.2 is a block diagram of the SIO channel. The main components of the SIO channel
are a clock prescaler, a serial clock generator, a receive buffer, a receive controller, a transmit
buffer and a transmit controller.
•
Mode 0 (I/O interface mode)
Bit0
2
1
3
4
5
6
7
Goes out first
•
Mode 1 (7-bit UART mode)
Without parity Start
Bit0
1
2
3
4
5
6
Stop
Start
Bit0
1
2
3
4
5
6
Parity Stop
With parity
•
Mode 2 (8-bit UART mode)
Without parity Start
Bit0
1
2
3
4
5
6
7
Stop
Start
Bit0
1
2
3
4
5
6
7
Parity Stop
With parity
•
Mode 3 (9-bit UART mode)
Wakeup
Start
Bit0
1
2
3
4
5
6
7
8
Stop
Start
Bit0
1
2
3
4
5
6
7
Bit8
Stop
Bit8: Address/data bit flag
1:
Address character (Select code)
0:
Data character
Figure 3.9.1 Data Formats
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3.9.1
Block Diagrams
φT0
Prescaler
4 8 16 32 64
2
φT2
φT8 φT32
Serial clock generator
TA0TRG
(from TMRA0)
BR1CR.
BR1CK[1:0]
BR1CR.
BR1ADDE
Baud rate
generator
SC1MOD0.
SC[1:0]
Selector
fSYS
÷2
SCLK input
(Shared with
P95)
SCLK output
(Shared with
P95)
UART
mode
Selector
Selector
BR1ADD.
BR1K[3:0]
Divider
φT0
φT2
φT8
φT32
Selector
BR1CR.
BR1S[3:0]
SIOCLK
SC1MOD0.
SM[1:0]
I/O interface
mode
SC1CR.
IOC
I/O interface mode
INTRX interrupt
request
INTTX interrupt
Receive counter
(÷ 16 for UART)
RXDCLK
SC1MOD0.
RXE
SC1MOD0.
WU
Serial channel
interrupt
control
(÷ 16 for UART)
TXDCLK
Receive
control
Transmit
control
SC1CR.
PE
EVEN
CTS
SC1MOD0.
CTSE
Parity control
RXD
(Shared
with P94)
request
Transmit counter
(Shared with
P95)
Receive buffer 1 (Shift register)
RB8
Receive buffer 2 (SC1BUF)
Error flag
TB8
Transmit buffer (SC1BUF)
(Shared with
P93)
SC1CR.
OERR PERR FERR
Internal data bus
Internal data bus
TXD
Internal data bus
Figure 3.9.2 SIO Block Diagram
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3.9.2
SIO Components
(1) Prescaler
The SIO has a 6-bit prescaler that slows the rate of a clocking source to the serial
clock generator. The prescaler clock source (φT0) has one-fourth the frequency selected
by programming the PRCK[1:0] field of the SYSCR0 located within the clock gear.
The serial clock is selectable from several clocks, the prescaler is only enabled when
the baud rate generator output clock is selected as a serial clock. Table 3.9.1 shows
prescaler output clock resolutions.
Table 3.9.1 Prescaler Output Clock Resolutions
Prescaler Clock
Source
Clock Gear
Value
PRCK[1:0]
GEAR[2:0]
00
(fFPH)
10
(fc/16 clock)
Prescaler Output Clock
Resolution
φT0
2 /fc
3
2 /fc
4
2 /fc
5
2 /fc
2 /fc
6
2 /fc
−
2 /fc
2 /fc
001 (fc/2)
2 /fc
010 (fc/4)
2 /fc
011 (fc/8)
2 /fc
100 (fc/16)
XXX
φT2
2
000 (fc)
φT8
4
2 /fc
5
2 /fc
6
2 /fc
7
2 /fc
8
2 /fc
8
2 /fc
φT32
6
2 /fc
8
7
2 /fc
8
2 /fc
9
2 /fc
10
2 /fc
10
2 /fc
9
10
11
12
12
XXX: Don’t care, −: Setting prohibited
Prescaler output taps can be divide-by-1 (φT0), divide-by-4 (φT2), divide-by-16 (φT8),
and divide-by-64 (φT32).
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(2) Baud rate generator
The frequency used to transmit and receive data through the SIO is derived from the
baud rate generator. The clock source for the baud rate generator can be selected from
the 6-bit prescaler outputs (φT0, φT2, φT8, φT32) through the programming of the
BR0CK[1:0] field in the BR1CR.
The baud rate generator contains a clock divider that can divide the selected clock by
1, N + (16 − K)/16, or 16. The clock divisor is programmed into the BR1ADDE and
BR0S[3:0] bits in the BR1CR and the BR0K[3:0] bits in the BR1ADD.
•
UART mode
(1) When BR1CR.BR1ADDE = 0
When the BR1CR.BR1ADDE bit is cleared, the BR1ADD.BR0K[3:0] field has no
meaning or effect. In this case, the baud rate generator input clock is divided
down by a value of N (1 to 16) programmed in the BR1CR.BR0S[3:0] field.
(2) When BR1CR.BR1ADDE = 1
Setting the BR1CR.BR1ADDE bit enables the N + (16 − K)/16 clock division
function. The baud rate generator input clock is divided down according to the
value of N (2 to 15) programmed in the BR1CR.BR0S[3:0] field and the value of K
(1 to 15) programmed in the BR1ADD.BR0K[3:0] field.
Note:
•
Setting N to 1 or 16 disables the N + (16 − K)/16 clock division function.
When N = 1 or 16, the BR1CR.BR1ADDE bit must be cleared.
I/O interface mode
I/O Interface mode cannot utilize the N + (16 − K)/16 clock division function.
The BR1CR.BR1ADDE must be cleared, so the baud rate generator input clock is
divided down by a value of N (1 to 16) programmed in the BR1CR.BR0S[3:0] field.
When the baud rate generator is used, the baud rate is calculated as follows:
•
UART mode
Baud rate =
•
I/O interface mode
Baud rate generator input clock
Baud rate =
Baud rate generator divisor
Baud rate generator input clock
÷ 16
Baud rate generator divisor
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TMP91CW28
•
Integral clock division (divide-by-N)
fc = 9.8304 MHz
Input clock: φT2
Clock divisor N (BR1CR.BR0S[3:0]) = 5
BR1CR.BR1ADDE = 0
Clocking conditions:
High-speed clock gear: × 1 (fc)
Prescaler clock:
fFPH
The baud rate is determind as follows:
Baud rate =
fc/16
÷ 16
4
= 9.8304 × 106 ÷ 16 ÷ 4 ÷ 16 = 9600 (bps)
Note:
•
Clearing the BR1CR.BR1ADDE bit to 0 disables the N + (16 − K)/16 clock
division function. At this time, the BR1ADD.BR0K[3:0] field is ignored.
N + (16 − K)/16 clock division (UART mode only)
fc = 4.8 MHz
Input clock: φT0
N (BR1CR.BR0S[3:0]) = 7
K (BR1ADD.BR0K[3:0]) = 3
BR1CR.BR1ADDE = 1
Clocking conditions:
High-speed clock gear: × 1 (fc)
Prescaler clock:
fFPH
The baud rate is determind as follows:
fc/4
÷ 16
7 + (16 − 3)
16
13
= 4.8 × 106 ÷ 4 ÷ ( 7 + 16 ) ÷ 16 = 9600 (bps)
Baud rate =
Table 3.9.2 show the UART baud rates obtained with various combinations of
clock inputs and clock divisor values.
The SIO can use an external clock as a serial clock, bypassing the baud rate
generator. When an external clock is used, the baud rate is determined as shown
below.
•
UART mode
Baud rate = external clock input ÷ 16
The external clock period must be greater than or equal to 4/fc.
•
I/O interface mode
Baud rate = external clock input
The external clock period must be greater than or equal to 16/fc.
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Table 3.9.2 UART Baud Rate Selection
(when the baud rate generator is used and BR1CR.BR1ADDE = 0)
Unit: kbps
Baud Rate Generator
Input Clock
fc [MHz]
φT0
φT2
φT8
φT32
Divisor N
(Programmed in BR1CR.
BR0S[3:0])
9.830400
2
76.800
19.200
4.800
1.200
↑
4
38.400
9.600
2.400
0.600
↑
8
19.200
4.800
1.200
0.300
↑
0
9.600
2.400
0.600
0.150
Note 1: In I/O interface mode, the transfer rate is eight times the value shown in this table.
Note 2: This table assumes: clock gear = fc, prescaler clock source (φT0) = fFPH
Timer out clock (TA0TRG) can be used for source clock of UART mode only.
Calculation method the frequency of TA0TRG
Frequency of TA0TRG =
Baud rate × 16
Note : I/O interface mode cannot utilize the trigger output signal from the 8-bit timer TMRA0 as a
serial clock.
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(3) Serial clock generator
This block generates a basic clock (SIOCLK) that controls the transmit and receive
circuit.
•
I/O interface mode
When the SCLK pin is configured as an output by clearing the SC1CR.IOC bit to
0, the output clock from the baud rate generator is divided by two to generate the
SIOCLK clock. When the SCLK pin is configured as an input by setting the
SC1CR.IOC bit to 1, the external SCLK clock is used as the SIOCLK clock; the
SC1CR.SCLKS bit determines the active clock edge.
•
UART mode
The SIOCLK clock is selected from a clock produced by the baud rate generator,
the system clock (fSYS), the trigger output signal from the 8-bit timer TMRA0, and
the external SCLK clock, according to the setting of the SC1MOD0.SC[1:0] field.
(4) Receive counter
The receive counter is a 4-bit binary up counter used in UART mode. This counter is
clocked by SIOCLK. The receiver utilizes 16 clocks for each received bit, and
oversamples each bit three times around their center (with 7th to 9th clocks), unless
fSYS is used for the basic clock. The value of a bit is determined by voting logic which
takes the value of the majority of three samples. For example, if the three samples of a
bit are 1, 0 and 1, then that bit is interpreted as a 1; if the three samples of a bit are 0,
0 and 1, then that bit is interpreted as a 0.
(5) Receive controller
•
I/O interface mode
If the SCLK pin is configured as an output by clearing the SC1CR.IOC bit to 0,
the receive controller samples the RXD input at the rising or falling edge of the
shift clock driven out from the SCLK pin, as programmed in the SC1CR.SCLKS bit.
If the SCLK pin is configured as an input by setting the SC1CR.IOC bit to 1, the
receive controller samples the RXD input at either the rising or falling edge of the
SCLK clock, as programmed in the SC1CR.SCLKS bit.
•
UART mode
The receive controller contains the start bit detection logic. Once a valid start bit
is detected (at least two 0 are detected among three samples), the receive controller
begins sampling the incoming data streams. The start bit, each data bit and the
stop bit are sampled three times for 2-of-3 majority voting.
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(6) Receive buffer
The receive buffer is double-buffered to prevent overrun errors. Received data is
serially shifted bit by bit into receive buffer 1. When a whole character (e.g., 7 or 8 bits,
as programmed) is loaded into receive buffer 1, it is transferred to receive buffer 2
(SC1BUF), and a receive-done interrupt (INTRX) is generated.
The CPU reads a character from receive buffer 2 (SC1BUF). Receive buffer 1 can
accept a new character through the RXD pin before the CPU picks up the previous
character in receive buffer 2. However, the CPU must read receive buffer 2 before
receive buffer 1 is filled with a new character. Otherwise, an overrun error occurs,
causing the character previously in receive buffer 1 to be lost. Even in that case, the
contents of receive buffer 2 and the SC1CR.RB8 bit are preserved.
The SC1CR.RB8 bit holds the parity bit for an 8-bit UART character and the
most-significant (e.g., address/data flag) bit for a 9-bit UART character.
In 9-bit UART mode, the receiver wakeup feature allows the slave station in a
multidrop system to wakeup whenever an address character is received. Setting the
SC1MOD0.WU bit enables the wakeup feature. When the SC1CR.RB8 bit has received
an address/data flag bit set to 1, the receiver generates the INTRX interrupt.
(7) Transmit counter
The transmit counter is a 4-bit binary up counter used in UART mode. Like the
receive counter, the transmit counter is also clocked by SIOCLK. The transmitter
generates a transmit clock (TXDCLK) pulse every 16 SIOCLK pulses.
SIOCLK
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
TXDCLK
Figure 3.9.3 Transmit Clock Generation
(8) Transmit controller
•
I/O interface mode
If the SCLK pin is configured as an output by clearing the SC1CR.IOC bit to 0,
the transmit controller shifts out each bit in the transmit buffer to the TXD pin at
the rising or falling edge of the shift clock driven out on the SCLK pin, as
programmed in the SC1CR.SCLKS bit. If the SCLK pin is configured as an input
by setting the SC1CR.IOC bit to 1, the transmit controller shifts out each bit in the
transmit buffer to the TXD pin at either the rising or falling edge of the SCLK
input, as programmed in the SC1CR.SCLKS bit.
•
UART mode
Once the CPU loads a character into the transmit buffer, the transmit controller
begins transmission at the next rising edge of TXDCLK, producing a transmit shift
clock (TXDSFT).
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Handshaking
If the CTS operation is enabled, the CTS input must be low in order for the
character to be transmitted. This feature can be used for flow control to prevent
overrun in the receiver. The SC1MOD0.CTSE bit enables and disables the CTS
operation.
If the CTS pin goes high in the middle of a transmission, the transmit controller
stops transmission upon completion of the current character until CTS again goes low.
If so enabled, the transmit controller generates the INTTX interrupt to notify the CPU
that the transmit buffer is empty. After the CPU loads the next character into the
transmit buffer, the transmit controller remains in idle state until it detects CTS going
low.
Although the SIO does not have the RTS pin, any general-purpose port pins can
serve as the RTS pin. The receiving device uses the RTS output to control the CTS
input of the transmitting device. Once the receiving device has received a character,
RTS should be set to high in the receive-done interrupt handler to temporarily stop the
transmitting device from sending the next character. This way, the user can easily
implement a two-way handshake protocol.
TMP91CW28
TMP91CW28
TXD
RXD
CTS
RTS (Any port)
Transmitting device
Receiving device
Figure 3.9.4 Handshaking Signals
Write to the transmit buffer
CTS
No transmission takes
place during this
a
period.
13
b
14
15
16
1
2
3
14
15
16
1
2
3
SIOCLK
TXDCLK
Start bit
Bit0
TXD
Note: a. When CTS goes high in the middle of transmission, the transmitter stops transmission after the current
character has been sent.
b. The transmitter starts transmission at the first falling edge of the TXDCLK clock after the CTS signal goes
low.
Figure 3.9.5 Clear-to-send ( CTS ) Signal Timing
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2006-03-24
TMP91CW28
(9) Transmit buffer
Once the CPU loads a character into the transmit buffer (SC1BUF), it is shifted out
on the TXD output, with the least-significant bit first, clocked by the transmit shift
clock TXDSFT from the transmit controller. When the transmit buffer is empty and
ready to be loaded with the next character, the INTTX interrupt is generated to the
CPU.
(10) Parity controller
For transmit operations, setting the SC1CR.PE enables parity generation in 7- and
8-bit UART modes. The SC1CR.EVEN bit selects either even or odd parity.
If enabled, the parity controller automatically generates parity for the character in
the transmit buffer (SC1BUF). In 7-bit UART mode, the TB7 bit in the SC1BUF holds
the parity bit. In 8-bit UART mode, the TB8 bit in the SC1MOD holds the parity bit.
The parity bit is set after the character has been transmitted. The SC1CR.PE and
SC1CR.EVEN bits must be programmed prior to a write to the transmit buffer.
For receive operations, the parity controller automatically computes the expected
parity when a character in receive buffer 1 is transferred to receive buffer 2 (SC1BUF).
The received parity bit is compared to the SC1BUF.RB7 bit in 7-bit UART mode and to
the SC1CR.RB8 bit in 8-bit UART mode. If a character is received with incorrect parity,
the SC1CR.PERR bit is set.
(11) Error flags
The SC1CR has the following error flag bits that indicate the status of the received
character for improved data reception reliability.
1.
Overrun error (OERR)
An overrun error is reported if all bits of a new character are received into
receive buffer 1 when receive buffer 2 (SC1BUF) still contains a valid character.
The following shows an example processing flow when an overrun error occurs:
(Receive interrupt routine)
1) Read the receive buffer.
2) Read the error flags.
3) if OERR = 1
then
a) Disable reception: Write 0 to RXE.
b) Wait until the current frame is completed.
c) Read the receive buffer.
d) Read the error flags.
e) Enable reception: Write 1 to RXE.
f)
Request retransmission.
4) Other processing
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2.
Parity error (PERR)
A parity error is reported when the parity bit attached to a character received on
the RXD pin does not match the expected parity computed from the character
transferred to receive buffer 2 (SC1BUF).
3.
Framing error (FERR)
A framing error is reported when a 0 is detected where a stop bit was expected.
(The middle three of the 16 samples are used to determine the bit value.)
(12) Signal generation timing
a.
UART mode
Receive operation
Mode
8 Data Bits with
Parity
9 Data Bits
8 Data Bits with No Parity
7 Data Bits with Parity
7 Data Bits with No Parity
Interrupt
Middle of the last bit
(e.g., bit8)
Middle of the last bit
(e.g., parity bit)
Middle of the stop bit
Framing error
Middle of the stop bit
Middle of the stop bit
Middle of the stop bit
−
Middle of the last bit
(e.g., parity bit)
Middle of the stop bit
Middle of the last bit
(e.g., bit8)
Middle of the last bit
(e.g., parity bit)
Middle of the stop bit
Parity error
Overrun error
Note: In 9 data bits and 8 data bits with No Parity mode, interrupts coincide with the ninth
bit pulse.
Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow
the stop bit to be transferred) to allow checking for a framing error.
Transmit operation
Mode
Interrupt
b.
9 Data Bits
8 Data Bits with
Parity
8 Data Bits with No Parity
7 Data Bits with Parity
7 Data Bits with No Parity
Immediately before the
stop bit is shifted out
←
←
I/O interface mode
Transmit
interrupt
SCLK output mode
Immediately after last bit data (See
SCLK input mode
Immediately after the rising or falling edge of the last SCLK pulse,
as programmed (See Figure 3.9.14)
SCLK output mode
When a received character has been transferred to receive buffer 2
(SC1BUF) (e.g., immediately after the last SCLK pulse) (See
Figure 3.9.15)
SCLK input mode
When a received character has been transferred to receive buffer 2
(SC1BUF) (e.g., immediately after the last SCLK pulse) (See
Figure 3.9.16)
Figure 3.9.13)
Receive
interrupt
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3.9.3
SFR Description
7
SC1MOD0 Bit symbol
(020AH)
Read/Write
Reset value
Function
TB8
Serial Mode Control Register 0
6
5
4
3
CTSE
RXE
WU
2
1
0
SM1
SM0
SC1
SC0
0
0
0
0
R/W
0
Bit8 of a
transmitted
character
0
0
0
Handshake
Receive
control
control
0: Disables
0: Disables
receiver
CTS
operation
Wakeup
function
Serial transfer mode
00: I/O interface mode
0: Disabled 01: 7-bit UART mode
1: Enabled 10: 8-bit UART mode
1: Enables
11: 9-bit UART mode
receiver
1: Enables
Serial clock (for UART)
00: TA0TRG (Timer)
01: Baud rate generator
10: Internal fSYS clock
11: External clock
(SCLK input)
CTS
operation
Serial clock (for UART)
00 Trigger output signal from the TMRA0 timer
01 Baud rate generator
10 Internal fSYS clock
11 External clock (SCLK input)
Note: In I/O interface mode, the serial
control register (SC1CR) is used
to select the clock source.
Serial transfer mode
00
I/O interface mode
01
10
7-bit
UART mode
11
8-bit
9-bit
Wakeup function
9-Bit UART mode
0
Interrupt on every
received character
1
Interrupt only when
SC1CR.RB8 = 1
Other modes
Don’t care
Receive control
0
Disables receiver
1
Enables receiver
Handshake ( CTS ) control
0
Disable (Accepts data streams at all times)
1
Enable
Bit8 of a transmitted character
Figure 3.9.6 SIO Registers (1)
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SC1CR
(0209H)
Bit symbol
7
6
RB8
EVEN
Read/Write
R
Reset value
Undefined
Function
Bit8 of a
received
character
Serial Control Register 1
5
4
3
PE
OERR
0
0
R/W
0
PERR
2
1
0
FERR
SCLKS
IOC
R (Cleared when read)
0
R/W
0
Parity type Parity
0: Odd
0: Disabled
1: Even
1: Enabled
0
0
0: SCLK
0: Baud rate
generator
1: Error has occurred
1: SCLK
Overrun
Parity
Framing
1: SCLK
input
Input clock in I/O interface mode
0
Baud rate generator
1
SCLK input
Active edge for the SCLK input
0
Data is transmitted/received
on the SCLK rising edge.
1
Data is transmitted/received
on the SCLK falling edge.
Framing error flag
Parity error flag
Overrun error flag
These bits are
cleared to 0
when read.
Parity generation
0
Disabled
1
Enabled
Parity type
0
Odd parity
1
Even parity
Bit8 of a received character
Note: All error flags are cleared to 0 when read. These bits should not be tested using a bit test instruction.
Figure 3.9.7 SIO Registers (2)
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7
BR1CR
(020BH)
−
Bit symbol
Baud Rate Generator Control Register 1
6
5
4
3
2
BR1ADDE
BR1CK0
Function
0
BR1S3
BR1S2
BR1S1
BR1S0
0
0
0
0
R/W
Reset value
0
Must be
written as
“0”.
0
0
0
N + (16 − K)
/16 function
00: φT0
01: φT2
Setting of the divided frequency “N”
0: Disabled
10: φT8
(0 to F)
1: Enabled
11: φT32
N + (16 − K)/16 functions
Clock source for baud rate generator
0
Disabled
00
Internal clock φT0
1
Enabled
01
Internal clock φT2
10
Internal clock φT8
11
Internal clock φT32
7
BR1ADD
(020CH)
BR1CK1
Read/Write
1
Baud Rate Generator K Value Register 1
6
5
4
3
2
Bit symbol
BR1K3
BR1K2
0
0
Read/Write
1
0
BR1K1
BR1K0
0
0
R/W
Reset value
Function
Sets frequency divisor “K”
(Divided by N + (16 − K)/16)
Clock divisor value for baud rate generator
BR1CR.BR1ADDE = 1
BR1CR.BR1ADDE = 0
BR1CR.
0000 (N = 16)
0010 (N = 2)
BR1S[3:0]
or
:
0001 (N = 1)
1111 (N = 15)
Don’t use.
Don’t use.
BR1ADD.
0001(N = 1) (Only UART)
:
BR1K[3:0]
0000
1111(K = 15)
0000 (N = 16)
Divided by
0001(K = 1)
:
1111 (N = 15)
Don’t use.
N+
Divided by N
16 − K
16
Note1:Availability of +(16-K)/16 division function
N
UART mode
I/O mode
2 to 15
Allowed
Not allowed
1 , 16
Not allowed
Not allowed
The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in
I/O interface mode.
Note2:Set BR1CR.BR1ADDE to 1 after setting K (K = 1 to 15) to BR1ADD.BR1K[3:0] when +(16-K)/16 division
function is used. Writes to unused bits in the BR1ADD register do not affext operation, and undefined data is
read from these unused bits.
Figure 3.9.8 SIO Registers (3)
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7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
SC1BUF
(0208H)
(for transmit)
(for receive)
Note: The SC1BUF register does not support read-modify-write operation.
Figure 3.9.9 Serial Transmit/Receive Buffer Register (SC1BUF)
Serial Mode Control Register 1
SC1MOD1
(020DH)
7
6
Bit symbol
I2S1
FDPX1
Read/Write
R/W
R/W
Reset value
0
0
SIO
operation in
IDLE2 mode
Synchronous
Function
5
4
3
2
1
0
0: Half duplex
1: Full duplex
0: OFF
1: ON
Figure 3.9.10 SIO Registers (4)
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2006-03-24
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3.9.4
Operating Modes
(1) Mode 0 (I/O interface mode)
Mode 0 is used to increase the number of input/output pins. In this mode, the
TMP91CW28 transmits or receives data to and from an external device, such as a shift
register.
Mode 0 utilizes a synchronization clock (SCLK), which can be configured for either
output mode in which the SCLK clock is driven out from the TMP91CW28 or input
mode in which the SCLK clock is supplied externally.
Output expansion
TMP91CW28
TXD
Input expansion
Shift
register
A
SI
C
TMP91CW28
B
RXD
Shift
register
A
QH
C
B
D
SCLK
E
SCK
D
SCLK
CLOCK
E
S/ L
G
F
Port
G
RCK
F
Port
H
H
TC74HC165
TC74HC595
Figure 3.9.11 Example Connection in SCLK Output Mode
Output expansion
TMP91CW28
TXD
Input expansion
Shift
register
A
B
C
SI
SCLK
SCK
Port
RCK
D
E
F
G
H
TMP91CW28
RXD
SCLK
Port
TC74HC595
External clock
A
Shift
register
B
C
QH
D
E
F
CLOCK
S/ L
G
H
TC74HC165
External clock
Figure 3.9.12 Example Connection in SCLK Input Mode
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a.
Transmit operations
In SCLK output mode, each time the CPU writes a character to the transmit buffer,
the eight bits of the character is shifted out on the TXD pin, and the synchronization
clock is driven out from the SCLK pin. When all the bits have been shifted out, the
INTES1.ITX1C bit is set and the transmit-done interrupt (INTTX) is generated.
Timing to write
transmission data
SCLK1 output
(SCLKS=0
Rising edge mode)
(Internal clock
timing)
SCLK1 output
(SCLKS=1
Falling edge mode)
Bit1
Bit0
TXD1
Bit6
Bit7
ITX1C
(INTTX1
Interrupt request)
Figure 3.9.13 Transmit Operation in I/O Interface Mode (SCLK output mode)
In SCLK input mode, the CPU must write a character to the transmit buffer before
the SCLK input is activated. The 8 bits of a character in the transmit buffer are shifted
out on the TXD pin, synchronous to the programmed edge of the SCLK input. When all
the bits have been shifted out, the INTES1.ITX1C bit is set and the transmit-done
interrupt (INTTX) is generated.
SCLK1input
(SCLKS = 0
Rising edge mode)
SCLK1 input
(SCLKS = 1
Falling edge mode)
Bit0
TXD1
Bit1
Bit5
Bit6
Bit7
ITX1C
(INTTX1
Interrupt request)
Figure 3.9.14 Transmit Operation in I/O Interface Mode (SCLK input mode)
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b.
Receive operations
In SCLK output mode, each time the CPU picks up the character in receive buffer 2,
clearing the receive-done interrupt flag (INTES1.IRX1C), the synchronization clock is
driven out from the SCLK pin to shift the next character into receive buffer 1. When a
whole 8-bit character has been loaded into receive buffer 1, it is transferred to receive
buffer 2 (SC1BUF), and the INTES1.IRX1C flag is set to 1 again, generating the
INTRX interrupt.
The SCLK output is initiated by setting the SC1MOD0.RXE bit to 1.
IRX1C
(INTRX1
interrupt request)
SCLK1 output
(SCLKS = 0
Rising edge mode)
SCLK1 output
(SCLKS = 1
Fallingf edge mode)
RXD1
Bit1
Bit0
Bit6
Bit7
Figure 3.9.15 Receive Operation in I/O Interface Mode (SCLK output mode)
In SCLK input mode, the CPU must pick up the character in the receive buffer 2,
clearing the receive-done interrupt flag (INTES1.IRX1C), before the SCLK input is
activated to shift the next character into receive buffer 1. When a whole 8-bit character
has been loaded into receive buffer 1, it is transferred to receive buffer 2 (SC1BUF),
and the INTES1.IRX1C flag is set to 1 again, generating the INTRX interrupt.
SCLK1 input
(SCLKS = 0:
Rising edge mode)
SCLK1 input
(SCLKS = 1:
Falling edge mode)
Bit0
RXD1
Bit1
Bit5
Bit6
Bit7
IRX1C
(INTRX1 )
Figure 3.9.16 Receive Operation in I/O Interface Mode (SCLK input mode)
Note:
Regardless of whether SCLK is in input mode or output mode, the receiver must be
enabled by setting the SC1MOD0.RXE bit to 1 in order to perform receive
operations.
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c.
Full-duplex transmit/receive operations
To perform full-duplex transmit/receive operations, the receive interrupt priority
level must be set to 0, with the transmit interrupt priority level set to an appropriate
value (1 to 6).
In the transmit interrupt handling routine, receive operation must be performed
before loading the transmit buffer with a character, as shown below.
Example:
SCLK output mode
Transfer rate: 9600 bps
fc = 14.7456 MHz
High-speed clock gear: × 1 (fc)
Prescaler clock: fFPH
Settings in the main routine
7 6 5
4
3
2
1
0
INTES1
X
0
0
1
X
0
0
0
Sets a transmit interrupt priority level and disables receive
interrupts.
P9CR
−
−
−
0
1
−
−
−
Configures the P93 pin as TXD and the P94 pin as RXD.
P9FC
−
−
−
−
1
−
−
−
SC1MOD0
SC1MOD1
−
−
1
1
0
X
−
X
0
X
0
X
−
X
−
X
Selects I/O interface mode.
Selects full-duplex operation.
SC1CR
−
−
−
−
−
−
0
0
BR1CR
SC1MOD0
0
0
1
1
0
0
1
1
Selects SCLK output mode, receiving at the rising edge
and transmitting at the falling edge.
Sets the transfer rate to 9600 bps.
−
−
1
−
−
−
−
−
Enables receive operation.
SC1BUF
*
*
*
*
*
*
*
*
Loads the transmit buffer with a character.
Transmit interrupt handling routine
Acc SC1BUF
SC1BUF
* * * * *
*
*
*
Loads the transmit buffer with a character.
Reads received data.
X: Don’t care, −: No change
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(2) Mode 1 (7-bit UART mode)
Setting the SM[1:0] field in the SC1MOD0 to 01 puts the SIO in 7-bit UART mode. In
this mode of operation, the parity bit can be added to the transmitted character, and
the receiver can perform a parity check on incoming data. Parity can be enabled and
disabled through the programming of the PE bit in the SC1CR. When PE = 1, the
SC1CR.EVEN bit selects even or odd parity.
Example: Transmitting 7-bit UART characters with an even-parity bit
Start
Bit0
1
2
3
4
5
6
Even
parity
Stop
Goes out first (Transfer rate = 2400 bps at fc = 9.8304 MHz)
High-speed clock gear: × 1 (fc)
Clocking conditions:
Prescaler clock:
System clock
7 6 5 4 3 2 1 0
←− − − − 1 − − −
P9FC
←− − − − 1 − − −
SC1MOD0 ← − − − − 0 1 0 1
P9CR
SC1CR
BR1CR
INTES1
SC1BUF
Configures the P93 pin as TXD.
Selects 7-bit UART mode.
←X 1 1 X X X − −
←0 0 1 0 0 1 0 0
Selects even parity.
Sets the transfer rate to 2400 bps.
←X 1 0 0 − − − −
← * * * * * * * *
Enables the INTTX interrupt and sets its priority level to 4.
Loads the transmit buffer with a character.
X: Don’t care, −: No change
(3) Mode 2 (8-bit UART mode)
Setting the SM[1:0] field in the SC1MOD0 to 10 puts the SIO in 8-bit UART mode. In
this mode of operation, the parity bit can be added to the transmitted character, and
the receiver can perform a parity check on incoming data. Parity can be enabled and
disabled through the programming of the PE bit in the SC1CR. When PE = 1, the
SC1CR.EVEN bit selects even or odd parity.
Example: Transmitting 8-bit UART characters with an odd-parity bit
Start
Bit0
1
2
3
4
5
6
7
Odd
parity
Stop
Goes out first (Transfer rate = 9600 bps at fc = 9.8304 MHz)
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High-speed clock gear: × 1 (fc)
Prescaler clock:
fFPH
Clocking conditions:
Settings in the main routine
7 6 5 4 3 2 1 0
P9CR
← − − − 0 − − − −
Configures P94 (RXD) to be an input.
SC1MOD0
← − − 1 − 1 0 0 1
Selects 8-bit UART mode and enables the receiver.
SC1CR
← X 0 1 X X X − −
Selects odd parity.
BR1CR
← 0 0 0 1 0 1 0 0
Sets the transfer rate to 9600 bps.
INTES1
← X − − − X 1 0 0
Enables the INTRX interrupt and sets its priority level to 4.
Example of interrupt routine processing.
Acc ← SC1CR AND 00011100
if Acc ≠ 0 then ERROR
Checks for errors.
Acc ← SC1BUF
Reads received data.
X: Don’t care, −: No change
(4) Mode 3 (9-bit UART mode)
Setting the SM[1:0] field in the SC1MOD0 to 11 puts the SIO in 9-bit UART mode. In
this mode, a parity bit cannot be used.
For transmit operations, the most-significant bit (9th bit) is stored in the TB8 bit in
the SC1MOD0. For receive operations, the most-significant bit is stored in the RB8 bit
in the SC1CR. Reads and writes of the transmit/receive character must be done with
the most-significant bit first, followed by the SC1BUF.
Wakeup feature
In 9-bit UART mode, the receiver wakeup feature allows the slave station in a
multidrop system to wakeup whenever an address character is received. Setting the
SC1MOD0.WU bit enables the wakeup feature. When the SC1CR.RB8 bit has received
an address/data flag bit set to 1, the receiver generates the INTRX interrupt.
TXD
RXD
Master
TXD
RXD
Slave 1
TXD
RXD
Slave 2
TXD
RXD
Slave 3
Note: The slave controller’s TXD pin must be configured as an open-drain output by programming the ODE register.
Figure 3.9.17 Serial Link Using the Wakeup Function
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Protocol
1.
Put all the master and slave controllers in 9-bit UART mode.
2.
Enables the receiver in each slave controller by setting the SC1MOD0.WU bit to 1.
3.
The master controller transmits an address character (e.g., select code) that identifies
a slave controller. The address character has the most-significant bit (Bit8) set to 1.
Start
Bit0
1
2
3
4
5
6
7
Slave controller select code
8
Stop
1
4.
Each slave controller compares the received address to its station address and clears
the WU bit if they match.
5.
The master controller transmits data characters or block of data to the selected slave
controller (with SC1MOD0.WU bit cleared). Data characters have the most-significant
bit (Bit8) cleared to 0.
Start
Bit0
1
2
3
4
Data
6.
5
6
7
Bit8
Stop
0
Slave controllers not addressed continue to monitor the data stream, but discard any
characters with the most-significant bit (RB8) cleared, and thus does not generate
receive-done interrupts (INTRX). The addressed slave controller with its WU bit
cleared can transmit data to the master controller to notify that it has successfully
received the message.
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Example: Connecting a master station with two slave stations through a serial link
using the fSYS clock as a serial clock
TXD
RXD
TXD
Master
•
RXD
TXD
RXD
Slave 1
Slave 2
Select code
00000001
Select code
00001010
Master controller settings
Main routine
7 6 5 4 3 2 1 0
P9CR
← − − − 0 1 − − −
P9FC
← − − − X 1 − − −
Configures the P93 pin as TXD and the P94 pin as RXD.
INTES1
← X 1 0 0 X 1 0 1
Enables INTTX and sets its interrupt level to 4.
Enables INTRX and sets its interrupt level to 5.
SC1MOD0
← 1 0 1 0 1 1 1 0
Selects 9-bit UART mode and selects fSYS as a serial clock.
SC1BUF
← 0 0 0 0 0 0 0 1
Loads the select code for slave 1.
Interrupt routine (INTTX)
•
SC1MOD0
← 0 − − − − − − −
Clears the TB8 bit to 0.
SC1BUF
← * * * * * * * *
Loads the transmit data.
Slave controller settings
Main routine
7 6 5 4 3 2 1 0
P9CR
P9FC
ODE
← − − − 0 1 − − −
← − − − X 1 − − −
← X X X X X X 1 −
← X 1 0 1 X 1 1 0
INTES1
SC1MOD0 ← 0 0 1 1 1 1 1 0
Configures the P93 pin as TXD (Open-drain output) and the
P94 pin as RXD.
Enables INTTX and INTRX.
Selects 9-bit UART mode, selects fSYS as the serial clock and
sets the WU bit to 1.
Interrupt routine (INTRX)
Acc ← SC1BUF
if Acc = Select code
Then SC1MOD0 ← − − − 0 − − − − − WU = Clears the WU bit to 0.
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3.10 Serial Bus Interface (SBI)
The TMP91CW28 serial bus interface (SBI) contains two channels named SBI0 and SBI1.
Each channel has the following two operating modes:
•
I2C bus mode (with multi-master capability)
•
Clock-synchronous 8-bit SIO mode
In I2C bus mode, the SBI0 is connected to external devices via the P61 (SDA0) and P62
(SCL0) pins and the SBI1 via the P91 (SDA1) and P92 (SCL1) pins. In clock-synchronous 8-bit
SIO mode, the SBI0 is connected to external devices via the P60 (SCK0), P61 (SO0) and P62
(SI0) pins and the SBI1 via the P90 (SCK1), P91 (SO1) and P92 (SI1) pins.
Each SBI channel is independently programmable, and functionally equivalent. In the
following sections, any references to the SBI0 also apply to the SBI1.
The following table shows the programming required to put the SBI0 in each operating mode.
2
I C bus mode
Clock-synchronous
8-bit SIO mode
ODE.ODE62
P6CR.P62C
thru
thru
thru
ODE.ODE61
P6CR.P60C
P6FC.P60F
11
11X
11X
011
XX
010
P6FC.P62F
X11
The following table shows the programming required to put the SBI1 in each operating mode.
ODE.ODE92
P9CR.P92C
thru
thru
thru
ODE.ODE91
P9CR.P90C
P9FC.P90F
I C bus mode
11
11X
11X
Clock-synchronous
8-bit SIO mode
XX
2
011
010
P9FC.P92F
X11
X: Don’t care
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3.10.1
Block Diagram
INTSBI0 interrupt request
SCL
SCK
SIO
clock
control
φT
P60
(SCK0)
Input/
Output
control
Divider
Transfer
2
I C bus clock
SIO
SO
data control
SI
P61
(SO0/SDA0)
control logic
synchronization
Noise
canceller
P62
(SI0/SCL0)
/control
Shift register
SBI0CR2/
SBI0SR
SBI0 control register 2/
SBI0 status register
I2C0AR
I2C bus 0
address register
I2C bus
data control
Noise
canceller
SBI0DBR
SBI0CR1
SBI0BR0, 1
SBI0 data
buffer register
SBI0 control
register 1
SBI0 baud rate
registers 0 and 1
SDA
Figure 3.10.1 SBI0 Block Diagram
INTSBI1 interrupt request
SCL
SCK
SIO
clock
control
φT
P60
(SCK1)
Input/
Output
control
Divider
Transfer
I2C bus clock
Noise
canceller
SIO
SO
data control
SI
P61
(SO1/SDA1)
control logic
synchronization
P62
(SI1/SCL1)
/control
Shift register
SBI1CR2/
SBI1SR
SBI1 control register 2/
SBI1 status register
I2C1AR
2
I C bus 1
address register
I2C bus
data control
Noise
canceller
SBI1DBR
SBI1CR1
SBI1BR0, 1
SBI1 data
buffer register
SBI1 control
register 1
SBI1 baud rate
registers 0 and 1
SDA
Figure 3.10.2 SBI1 Block Diagram
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3.10.2
Registers
A listing of the registers used to control the SBI0 and SBI1 follows:
•
Serial bus interface control register 1 (SBI0CR1, SBI1CR1)
•
Serial bus interface control register 2 (SBI0CR2, SBI1CR2)
•
Serial bus interface data buffer register (SBI0DBR, SBI1DBR)
•
I2C bus address register (I2C0AR, I2C1AR)
•
Serial bus interface status register (SBI0SR, SBI1SR)
•
Serial bus interface baud rate register 0 (SBI0BR0, SBI1BR0)
•
Serial bus interface baud rate register 1 (SBI0BR1, SBI1BR1)
The functions of these registers vary, depending on the mode in which the SBI channel is
operating. For a detailed description of the registers, refer to section 3.10.4, “Description of
the Registers Used in I2C Bus Mode”, and section 3.10.7, “Description of Registers Used in
Clock-synchronous 8-Bit SIO Mode”.
3.10.3
I2C Bus Mode Data Formats
Figure 3.10.3 shows the serial bus interface data formats used in I2C bus mode.
(a) Addressing format
8 bits
S
Slave address
1
R A
/ C
WK
1 to 8 bits
1
Data
A
C
K
Once
1 to 8 bits
Data
1
A
C P
K
Repeated
(b) Addressing format (with repeated START condition)
8 bits
S
Slave address
1
R A
/ C
WK
Once
1 to 8 bits
Data
1
A
C S
K
Repeated
8 bits
Slave address
1
R A
/ C
WK
Once
1 to 8 bits
1
A
C P
K
Data
Repeated
(c) Free data format (Master transmitter to slave-receiver)
S
8 bits
1
1 to 8 bits
1
1 to 8 bits
Data
A
C
K
Data
A
C
K
Data
Once
S:
1
A
C P
K
Repeated
START condition
R/ W : Direction bit
ACK: Acknowledge bit
P:
STOP condition
Figure 3.10.3 I2C Bus Mode Data Formats
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3.10.4
Description of the Registers Used in I2C Bus Mode
This section provides a summary of the registers which control I2C bus operation and
provide I2C bus status information for bus access/monitoring.
Serial Bus Interface Control Register 1
7
SBI0CR1
(0240H)
Bit symbol
BC2
Read/Write
Read-modify- Reset value
write
Function
operation is
not
supported.
6
BC1
5
BC0
W
4
3
2
ACK
SCK2
R/W
1
0
SCK1
SCK0/
SWRMON
W
0
0
0
0
Number of bits per transfer (Note 1) ACK clock
pulse
0: No ACK
1: ACK
R/W
0
0
0/1 (Note 3)
Internal SCL output clock frequency
(Note 2)/Software reset monitor
On writes: SCK[2:0] = Internal SCL output clock frequency
n=5
000
001
n=6
010
n=7
011
100
n=8
− (Note4)
− (Note4)
Assumptions:
73.5 kHz
37.9 kHz
System clock: fc
Clock gear: fc/1
n = 9 19.2 kHz
n = 10 9.7 kHz
110 n = 11 4.9 kHz
111 (Reserved) (Reserved)
fc = 10 MHz (Output to the SCL pin)
Frequency =
101
fc
n
2 +8
[Hz]
On reads: SWRMON = Software reset monitor
0
Software reset operation is in progress.
1
Initial Data
Acknowledgement clock generation
0
No acknowledgement clock pulse is generated.
1
An acknowledgement clock pulse is generated.
Number of bits per transfer
ACK = 0
BC[2:0]
000
001
010
011
100
101
110
111
Number of
clock cycles
8
1
2
3
4
5
6
7
Data
length
8
1
2
3
4
5
6
7
ACK = 1
Number of
clock cycles
9
2
3
4
5
6
7
8
Data
length
8
1
2
3
4
5
6
7
Note 1:
Clear the BC[2:0] field to 000 before switching the operating mode to “Clock-synchronous” 8-bit SIO mode.
Note 2:
For details on the SCL bus clock frequency, refer to section 3.10.5 (3) “Serial clock”.
Note 3:
Initial data of SCK0 is 0, SWRMON is 1.
Note 4:
This I C bus circuit dose not support fast mode, it supports standard mode only. Although the I C bus circuit
2
2
2
itself allows the setting of a baud rate over 100 kbps, the compliance with the I C specification is not
guaranteed in that case.
Figure 3.10.4 I2C Bus Mode Registers (1) (SBI0CR1 for the SBI0)
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Serial Bus Interface Control Register 1
7
SBI1CR1
(0248H)
Bit symbol
Read/Write
Reset value
Readmodify-write
operation is
not
supported.
BC2
Function
6
BC1
5
BC0
W
4
3
2
ACK
SCK2
R/W
1
0
SCK1
SCK0/
SWRMON
W
0
0
0
0
Number of bits per transfer (Note 1) ACK clock
pulse
0: No ACK
1: ACK
R/W
0
0
0/1 (Note 3)
Internal SCL output clock
frequency (Note 2)/
Software reset monitor
On writes: SCK[2:0] = Internal SCL output clock frequency
n=5
000
001
n=6
010
n=7
011
100
101
110
111
− (Note4)
− (Note4)
Assumptions:
n=8
73.5 kHz
37.9 kHz
System clock: fc
Clock gear: fc/1
n=9
19.2 kHz
fc = 10 MHz (Output to the SCL pin)
n = 10
n = 11
9.7 kHz
4.9 kHz
(Reserved)
(Reserved)
Frequency =
fc
2 +8
n
[Hz]
On reads: SWRMON = Software reset monitor
0
Software reset operation is in progress.
1
Initial data
Acknowledgement clock generation
0
No acknowledgement clock pulse is generated.
1
An acknowledgement clock pulse is generated.
Number of bits per transfer
ACK = 0
BC[2:0]
000
001
010
011
100
101
110
111
Number of
clock cycles
8
1
2
3
4
5
6
7
Data
length
8
1
2
3
4
5
6
7
ACK = 1
Number of
clock cycles
9
2
3
4
5
6
7
8
Data
length
8
1
2
3
4
5
6
7
Note 1:
Clear the BC[2:0] field to 000 before switching the operating mode to “Clock-synchronous” 8-bit SIO mode.
Note 2:
For details on the SCL bus clock frequency, refer to section 3.10.5 (3) “Serial clock”.
Note 3:
Initial data of SCK0 is 0, SWRMON is 1.
Note 4:
This I C bus circuit dose not support fast mode, it supports standard mode only. Although the I C bus circuit
2
2
2
itself allows the setting of a baud rate over 100 kbps, the compliance with the I C specification is not
guaranteed in that case.
Figure 3.10.5 I2C Bus Mode Registers (2) (SBI1CR1 for the SBI1)
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Serial Bus Interface Control Register 2
SBI0CR2
(0243H)
Bit symbol
6
5
4
3
2
1
0
TRX
BB
PIN
SBIM1
SBIM0
SWRST1
SWRST0
0
0
0
1
0
Read/Write
Reset value
Readmodify-write
operation is
not
supported.
7
MST
Function
W
Master/
slave
Transmit/
receive
W (Note 1)
INTSBI0
START/
interrupt
STOP
condition
clear
generation
W (Note 1)
0
0
Operating mode
(Note 2)
0
Software reset
A write of 10 followed
by a write of “01”.
00: Port mode
01: SIO mode
2
10: I C bus mode
11: (Reserved)
Operating mode (Note 2)
00 Port mode (Serial bus interface output disabled)
01 Clock-synchronous 8-bit SIO mode
2
10 I C bus mode
11 (Reserved)
INTSBI0 interrupt clear
0
Don’t care
1
Interrupt clear
START/STOP condition generation
0
STOP condition
1
START condition
Transmit/receive
0
Receive
1
Transmit
Master/slave
0
Slave
1
Master
Note 1:
Reading this register causes it to function as a status register (SBI0SR).
Note 2:
Ensure that the bus is free before switching the operating mode to Port mode.
2
Ensure that the port is at logic high before switching from Port mode to I C bus or SIO mode.
Figure 3.10.6 I2C Bus Mode Registers (3) (SBI0CR2 for the SBI0)
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TMP91CW28
Serial Bus Interface Control Register 2
SBI1CR2
(024BH)
Bit symbol
6
5
4
3
2
1
0
TRX
BB
PIN
SBIM1
SBIM0
SWRST1
SWRST0
0
0
0
1
0
Read/Write
Reset value
Readmodify-write
operation is
not
supported.
7
MST
Function
W
Master/
slave
Transmit/
receive
W (Note 1)
INTSBI1
START/
interrupt
STOP
condition
clear
generation
W (Note 1)
0
0
Operating mode
(Note 2)
0
Software reset
A write of 10 followed
by a write of “01”.
00: Port mode
01: SIO mode
2
10: I C bus mode
11: (Reserved)
Operating mode (Note 2)
00 Port mode (Serial bus interface output disabled)
01 Clock-synchronous 8-bit SIO mode
2
10 I C bus mode
11 (Reserved)
INTSBI1 interrupt clear
0
Don’t care
1
Interrupt clear
START/STOP condition generation
0
STOP condition
1
START condition
Transmit/receive
0
Receive
1
Transmit
Master/slave
0
Slave
1
Master
Note 1:
Reading this register causes it to function as a status register (SBI0SR).
Note 2:
Ensure that the bus is free before switching the operating mode to Port mode.
2
Ensure that the port is at logic high before switching from Port mode to I C bus or SIO mode.
Figure 3.10.7 I2C Bus Mode Registers (4) (SBI1CR2 for the SBI1)
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Serial Bus Interface Status Register
SBI0SR
(0243H)
Bit symbol
6
5
4
3
2
1
0
TRX
BB
PIN
AL
AAS
AD0
LRB
Read/Write
Reset value
Read-modifywrite
operation is
not
supported.
7
MST
Function
R
0
Master/
slave
0
Transmit/
receive
0
2
I C bus
status
1
INTSBI0
interrupt
status
0
Arbitration
lost
0: −
1: Detected
0
Addressed
as slave
0
General
call
0
Last
received
0: Undetected 0: Undetected bit
0: 0
1: Detected
1: Detected
1: 1
Last received bit
0
The last bit received was “0”.
1
The last bit received was “1”.
General call
0
Undetected
1
The address on the bus matches the
general-call address
Addressed as slave
0
Undetected
1
The address on the bus matches the
slave address or general-call address
Arbitration lost
0
−
1
Arbitration was lost to another master.
INTSBI0 interrupt status
0
The interrupt is asserted.
1
The interrupt is not asserted.
2
I C bus status
0
Free
1
Busy
Transmit/receive
0
Receive
1
Transmit
Master/slave
0
Slave
1
Master
Note: Writing to this register causes it to function as a control register (SBI0CR2).
Figure 3.10.8 I2C Bus Mode Registers (5) (SBI0SR for the SBI0)
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Serial Bus Interface Status Register
SBI1SR
(024BH)
Bit symbol
6
5
4
3
2
1
0
TRX
BB
PIN
AL
AAS
AD0
LRB
Read/Write
Reset value
Read-modifywrite
operation is
not
supported.
7
MST
Function
R
0
Master/
slave
0
Transmit/
receive
0
2
I C bus
status
1
INTSBI1
interrupt
status
0
Arbitration
lost
0: −
1: Detected
0
Addressed
as slave
0
0
General call Last
0: Undetected received bit
0: Undetected 1: Detected 0: 0
1: 1
1: Detected
Last received bit
0
The last bit received was “0”.
1
The last bit received was “1”.
General call
0
Undetected
1
The address on the bus matches the
general-call address
Addressed as slave
0
Undetected
1
The address on the bus matches the
slave address or general-call address
Arbitration lost
0
−
1
Arbitration was lost to another master.
INTSBI1 interrupt status
0
The interrupt is asserted.
1
The interrupt is not asserted.
2
I C bus status
0
Free
1
Busy
Transmit/receive
0
Receive
1
Transmit
Master/slave
0
Slave
1
Master
Note: Writing to this register causes it to function as a control register (SBI0CR2).
Figure 3.10.9 I2C Bus Mode Registers (6) (SBI1SR for the SBI1)
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Serial Bus Interface Baud Rate Register 0
SBI0BR0
(0244H)
Read-modifywrite
operation is
not
supported.
7
6
Bit symbol
−
I2SBI0
Read/Write
W
R/W
Reset value
0
Must be
written as
“0”.
Function
5
4
3
2
1
0
0
IDLE2
0: OFF
1: ON
SBI ON/OFF in IDLE2 mode
0
OFF
1
ON
Serial Bus Interface Baud Rate Register 1
SBI0BR1
(0245H)
7
6
Bit symbol
P4EN
−
Read/Write
W
W
Reset value
Read-modifywrite
operation is
not
supported.
Function
0
Internal
clock
0: OFF
1: ON
5
4
3
2
1
0
0
Must be
written as
“0”.
Controls the internal baud rate generator
0
OFF
1
ON
Serial Bus Interface Data Buffer Register
7
6
5
4
3
2
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SBI0DBR
(0241H)
Bit symbol
Read/Write
R (receive)/W (transmit)
Read-modifywrite
operation is
not
supported.
Reset value
Undefined
Note 1: In transmitter mode, data must be written to this register, with bit7 being the most-significant bit (MSB).
Note 2: SBIDBR can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is prohibited.
Note 3: Written data in SBI0DBR is cleared by INTSBI0 signal.
I2C Bus Address Register
I2C0AR
(0242H)
Read-modifywrite
operation is
not
supported.
Bit symbol
7
6
5
4
3
2
1
0
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ALS
0
0
0
0
Read/Write
Reset value
Function
W
0
0
0
0
2
When the SBI0 is addressed as a slave, this field specifies a 7-bit I C bus address to Address
recognition
which the SBI0 responds.
mode
Address recognition mode
0
Recognizes the slave address.
1
Does not recognize the slave address.
Figure 3.10.10 I2C Bus Mode Registers (7) (SBI0BR0, SBI0BR1, SBI0DBR, and I2C0AR for the SBI0)
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Serial Bus Interface Baud Rate Register 0
SBI1BR0
(024CH)
Read-modifywrite
operation is
not
supported.
7
6
Bit symbol
−
I2SBI1
Read/Write
W
R/W
Reset value
0
Must be
written as
“0”.
Function
5
4
3
2
1
0
0
IDLE2
0: OFF
1: ON
SBI ON/OFF in IDLE2 mode
0
OFF
1
ON
Serial Bus Interface Baud Rate Register 1
SBI1BR1
(024DH)
7
6
Bit symbol
P4EN
−
Read/Write
W
W
Reset value
Read-modifywrite
operation is
not
supported.
Function
0
Internal
clock
0: OFF
1: ON
5
4
3
2
1
0
0
Must be
written as
“0”.
Controls the internal baud rate generator
0
OFF
1
ON
Serial Bus Interface Data Buffer Register
SBI1DBR
(0249H)
Read-modifywrite
operation is
not
supported.
Bit symbol
7
6
5
4
3
2
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read/Write
R (Receive)/W (Transmit)
Reset value
Undefined
Note 1: In transmitter mode, data must be written to this register, with bit7 being the most-significant bit (MSB).
Note 2: SBIDBR can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is prohibited.
Note 3: Written data in SBI1DBR is cleared by INTSBI1 signal.
I2C Bus Address Register
I2C1AR
(024AH)
Read-modifywrite
operation is
not
supported.
Bit symbol
7
6
5
4
3
2
1
0
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ALS
0
0
0
0
Read/Write
Reset value
Function
W
0
0
0
0
2
When the SBI1 is addressed as a slave, this field specifies a 7-bit I C bus address to Address
recognition
which the SBI1 responds.
mode
Address recognition mode
0
Recognizes the slave address.
1
Does not recognize the slave address.
Figure 3.10.11 I2C Bus Mode Registers (8) (SBI1BR0, SBI1BR1, SBI1DBR, and I2C1AR for the SBI1)
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3.10.5
I2C Bus Mode Configuration
(1) Acknowledge mode
Set the SBI0CR1.ACK to 1 for operation in the acknowledge mode. The TMP91CW28
generates an additional clock pulse for an acknowledge signal when operating in
master mode.
In the transmitter mode during the clock pulse cycle, the SDA pin is released in
order to receive the acknowledge signal from the receiver. In the receiver mode during
the clock pulse cycle, the SDA pin is set to the low in order to generate the acknowledge
signal.
Clear the SBI0CR1.ACK to 0 for operation in the non-acknowledge mode, the
TMP91CW28 does not generate a clock pulse for the acknowledge signal when
operating in the master mode.
(2) Number of bits per transfer
The SBI0CR1.BC[2:0] field specifies the number of bits of the next data item to be
transmitted or received. After a reset, this field is cleared to 000, causing a 7-bit slave
address and the data direction ( R / W ) bit to be transferred in a packet of 8 bits. At
other times, the SBI0CR1.BC[2:0] field keeps a previously programmed value. Set the
baud rate, which have been calculated according to the formula below to meet the
specifications of the I2C bus, such as the smallest pulse width of tLOW.
(3) Serial clock
a.
I2C bus clock source
The SBI0CR1.SCK[2:0] field controls the maximum frequency of the SCL0 clock
driven out on the SCL0 pin in master mode, as illustrated below. Set a
communication baud rate that meets the I2C bus specification, such as the
shortest pulse width of tLOW, based on the equations shown below.
tHIGH
tLOW
1/fscl
SBI0CR1.SCK[2:0]
n
000
001
010
011
100
101
110
5
6
7
8
9
10
11
n−1
tLOW = 2
/fSBI
n−1
tHIGH = 2
/fSBI +
8/fSBI
=
fSBI
2 +8
n
Note 1:
fSBI = fFPH
Note 2:
It’s prohibited to use fc/16 prescaler clock when using SBI block.
2
(I C bus and clock synchrounous)
Figure 3.10.12 I2C Bus Clock Source
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b.
Clock synchronization
Clock synchronization is performed using the wired-AND connection of all I2C
bus components to the bus. If two or more masters try to transfer messages on the
I2C bus, the first to pull its clock line low wins the arbitration, overriding other
masters producing a high on their clock lines.
Clock signals of two or more devices on the I2C bus are synchronized to ensure
correct data transfers. Figure 3.10.13 shows a depiction of the clock
synchronization mechanism for the I2C bus with two masters.
Wait state
Start counting high period
Internal SCL level (Master A)
Counter reset
Internal SCL level (Master B)
SCL bus line
a
b
c
Figure 3.10.13 Clock Synchronization Example
At point a, master A pulls its internal SCL0 level low, bringing the SCL bus line
low. The high-to-low transition on the SCL0 bus line causes master B to reset its
high-level counter and pull its internal SCL0 level low.
Master A completes its low period at point b. However, the low-to-high
transition on its internal SCL0 level does not change the state of the SCL0 bus
line if master B’s internal SCL0 level is still within its low period. Therefore,
master A enters a high wait state, where it does not start counting off its high
period.
When master B has counted off its low period at point c, its internal SCL0 level
goes high, releasing the SCL0 bus line (High). There will then be no difference
between the internal SCL0 levels and the state of the SCL0 bus line, and both
master A and master B start counting off their high periods.
This way, a synchronized SCL0 clock is generated with its high period
determined by the master with the shortest clock high period and its low period
determined by the one with the longest clock low period.
(4) Slave addressing and address recognition mode
When the SBI0 is configured to operate as a slave, the SA[6:0] field in the I2C0AR
must be loaded with the 7-bit I2C bus address to which the SBI0 is to respond. The ALS
bit must be cleared for the SBI0 to recognize the incoming slave address.
(5) Configuring the SBI0 as a master or a slave
Setting the SBI0CR2.MST bit configures the SBI as a master, and clearing it
configures the SBI0 as a slave. This bit is cleared by hardware when a STOP condition
has been detected and when arbitration for the I2C bus has been lost.
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(6) Configuring the SBI0 as a transmitter or a receiver
The SBI0CR2.TRX bit is set or cleared by hardware to configure the SBI0 as a
transmitter or a receiver. As a slave, the SBI0 is put in either slave-receiver or
slave-transmitter mode, depending on the value of the data direction ( R / W ) bit
transmitted by the master. When the SBI0 is addressed as a slave, the TRX bit reflects
the value of the R / W bit. The TRX bit is set or cleared on the following occasions:
•
when transferring data using addressing format
•
when the received slave address matches the value in the I2C0AR
•
when a general-call address is received; e.g., the eight bits following the
START condition are all zeros.
As a master, the SBI0 is put in either master-transmitter or a master-receiver mode
upon reception of an acknowledge from an addressed slave. The TRX bit changes to the
opposite value of the R / W bit sent by the SBI0. If the SBI0 does not receive an
acknowledge from a slave, the TRX bit retains the previous value.
The TRX bit is cleared by hardware when a STOP condition has been detected and
when arbitration for the I2C bus has been lost.
(7) Generating START and STOP conditions
When the SBI0SR.BB bit is cleared, the bus is free. At this time, writing 1s to the
MST, TRX, BB and PIN bits in the SBI0CR2 causes the SBI0 to generate a START
condition on the bus and shift out slave address and direction bit. Before generating a
START condition, the ACK bit must be set to 1.
SCL line
1
2
3
4
5
6
7
SDA line
A6
A5
A4
A3
A2
A1
A0
START condition
8
9
R/W
Slave address and direction bit
Acknowledge signal
Figure 3.10.14 Generating a START Condition and a Slave Address
When the SBI0SR.BB bit is set, the bus is busy. When SBI0SR.BB = 1, writing 1s to
the MST, TRX and PIN bits and a 0 to the BB bit causes the SBI0 to start a sequence
for generating a STOP condition on the bus to abort the transfer. The MST, TRX, BB
and PIN bits should not be altered until a STOP condition appears on the bus.
SCL line
SDA line
STOP condition
Figure 3.10.15 Generating a STOP Condition
The BB bit can be read to determine if the I2C bus is in use. The BB bit is set when a
START condition is detected and cleared when a STOP condition is detected.
Some restrictions are imposed on the generation of a STOP condition when the SBI0
is a master. See section 3.10.6 (4) “Generating a STOP condition”.
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(8) Asserting and deasserting interrupt requests
When an SBI0 interrupt (INTSBI0) is generated, the pending interrupt not (PIN) bit
in the SBI0CR2 is cleared to 0. While the PIN bit is 0, the SBI0 pulls the SCL0 line low.
After transmission or reception of one data word on the I2C bus, the PIN bit is
automatically cleared. In transmitter mode, the PIN bit is subsequently set to 1 each
time the SBI0DBR is written. In receiver mode, the PIN bit is set to 1 each time the
SBI0DBR is read.
It takes a period of tLOW for the SCL0 line to be released after the PIN bit is set.
In address recognition mode (ALS = 0), the PIN bit is cleared when the SBI0 is
addressed as a slave and the received slave address matches the value in the I2C0AR
or is all 0s (e.g., a general call). A write of 1 by software sets the PIN bit, but a write of 0
has no effect on this bit.
(9) SBI0 operating modes
The SBIM[1:0] field in the SBI0CR2 is used to select an operating mode of the SBI0.
To configure the SBI0 for I2C bus mode, set the SBIM[1:0] field to 10 after confirming
pin condition of serial bus interface to “H”.
A switch to port mode should only be attempted when the bus is free.
(10) Lost-arbitration detection monitor
The I2C bus is a multi-master bus and has an arbitration procedure to ensure correct
data transfers. A master may start a transfer only if the bus is free.
The I2C bus arbitration takes place on the SDA0 line.
Figure 3.10.16 shows the arbitration procedure for two masters. Up until point a, the
internal data levels of master A and master B are the same. At point a master B’s
internal data level makes a low-to-high transition while master A’s internal data level
remains at logic low. However, the SDA0 bus line is held low because it is the
wired-AND of the two data outputs. When the SCL0 bus clock goes high at point b, the
addressed slave device reads the data transmitted by master A (e.g., winning master).
Master B loses arbitration and switches off its data output stage, releasing its SDA0
line (High), so that it does not affect the data transfer initiated by the winning master.
In case two competing masters have transmitted exactly the same first data word, the
arbitration procedure continues with the second data word.
SCL bus line
Internal SDA level (Master A)
Master B loses arbitration and connects
a high output level to the bus.
Internal SDA level (Master B)
SDA bus line
a
b
Figure 3.10.16 Arbitration Procedure of Two Masters
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A master compares its internal data level to the actual level on the SDA0 line at the
rising edge of the SCL0 clock. The master loses arbitration if there is a difference
between these two values. The losing master sets the AL bit in the SBI0SR to 1, which
causes the MST and TRX bits in the same register to be cleared. That is, the losing
master switches to slave-receiver mode. Thus, clock output is stopped in data transfer
after setting AL bit to 1.
The AL bit is subsequently cleared when data is written to or read from the
SBI0DBR and when the SBI0CR2 is programmed with new parameters.
Internal SCL level
Master
A
Internal SDA level
1
D7A
2
3
4
5
6
7
8
D6A
D5A
D4A
D3A
D2A
D1A
D0A
9
1
2
3
4
D7A’ D6A’ D5A’ D4A’
Clock output stops here
Internal SCL level
Master
B
Internal SDA level
1
D7B
2
3
D6B
4
Internal SDA0 level is held high because
master B has lost arbitration.
AL
MST
TRX
Access to the SBI0DBR
or SBI0CR2
Figure 3.10.17 Master B Loses Arbitration (D7A = D7B, D6A = D6B)
(11) Slave address match monitor
When acting as a slave-receiver, the ALS bit in the I2C0AR determines whether the
SBI0 recognizes the incoming slave address or not. In address recognition mode (e.g.,
ALS = 0), the addressed-as-slave (AAS) bit in the SBI0SR is set when an incoming
address over the I2C bus matches the value in the I2C0AR or when the general-call
address has been received. When ALS = 1, the AAS bit is set when the first data word
has been received. The AAS bit is cleared each time the SBI0DBR is read or written.
(12) General-call detection monitor
When acting as a slave-receiver, the AD0 bit in the SBI0SR is set when a general-call
address has been received. The general-call address is detected when the eight bits
following a START condition are all 0s. The AD0 bit is cleared when a START or STOP
condition is detected on the bus.
(13) Last received bit monitor
The LRB bit in the SBI0SR holds the value of the last bit received over the SDA0 line
at the rising edge of the SCL0 clock. In acknowledge mode, reading this bit
immediately after generation of the INTSBI0 interrupt returns the value of the ACK
signal.
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(14) Software reset
The SBI0 provides a software reset, which permits recovery from system lockups
caused by external noise. A software reset is performed by a write of 10 followed by a
write of 01 to the SWRST[1:0] field in the SBI0CR2. After a software reset, all control
and status register bits (except SBI0CR2. SBIM[1:0]) are initialized to their reset
values. And SBI0CR1.SWRMON is automatically set to 1 after the SBI circuit has been
initialized.
(15) Serial bus interface data buffer register (SBI0DBR)
The SBI0DBR is a data buffer interfacing to the I2C bus. All read and write
operations to/from the I2C bus are done via this register.
When the SBI0 is acting as a master, loading this register with a slave address and a
data direction bit causes a START condition to be generated.
(16) I2C bus address register (I2C0AR)
When the SBI0 is configured as a slave, the SA[6:0] field in the I2C0AR must be
loaded with the 7-bit I2C bus address to which the SBI0 is to respond.
If the ALS bit in the I2C0AR is cleared, the SBI0 recognizes a slave address
transmitted by the master device, interpreting incoming frame structures as per
addressing format. If the ALS bit is set, the SBI0 does not recognize a slave address
and interprets all frame structures as per free data format.
(17) Baud rate register (SBI0BR1)
Before the I2C bus can be used, the P4EN bit in the SBI0BR1 must be set to enable
the SBI0 internal baud rate generation logic.
(18) IDLE2 setting register (SBI0BR0)
The I2SBI0 bit in the SBI0BR0 determines whether the SBI0 is shut down or not
when the TMP91CW28 is put in IDLE2 standby mode. This register must be
programmed before executing the HALT instruction.
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3.10.6
Programming Sequences in I2C Bus Mode
(1) SBI0 initialization
First, program the P4EN bit in the SBI0BR1, and the ACK and SCK[2:0] bits in the
SBI0CR1. Set the SBI0BR1.P4EN bit to 1 to enable the internal baud rate generation
logic. Write 0s to bits 7 to 5 and bit3 in the SBI0CR1.
Next, program the I2C0AR. The SA[6:0] field in the I2C0AR defines the chip’s slave
address, and the ALS bit (Bit0) selects an address recognition mode. (The ALS bit must
be cleared when using the addressing format.)
Next, program the SBI0CR2 to initially configure the SBI0 in slave-receiver mode;
e.g., clear the MST, TRX and BB bits to 0, set the PIN bit to 1 and set the SBIM[1:0]
field to 10. Write 00 to the SWRST[1:0] field.
(2) Generating a START condition and a slave address
a.
Master mode
In master mode, the following steps are required to generate a START condition
and a slave address on the I2C bus.
First, ensure that the bus is free (e.g., SBI0CR2.BB = 0).
Next, set the ACK bit in the SBI0CR1 to enable generation of acknowledge clock
pulses. Then, load the SBI0DBR with a slave address and a data direction bit to be
transmitted via the I2C bus.
When BB = 0, writing 1s to the MST, TRX, BB and PIN bits in the SBI0CR2
causes a START condition to be generated on the bus. Following a START
condition, the SBI0 generates SCL0 clock pulses nine times: the SBI0 shifts out
the contents of the SBI0DBR with the first eight SCL0 clocks, and releases the
SDA0 line during the last (e.g., 9th) SCL0 clock to receive an acknowledgement
signal from the addressed slave.
The INTSBI0 interrupt request is generated on the falling edge of the ninth
SCL0 clock pulse, and the PIN bit in the SBI0CR2 is cleared to 0. In master mode,
the SBI0 holds the SCL0 line low while the PIN bit is 0. Upon interrupt, the TRX
bit either remains set or is cleared according to the value of the transmitted
direction bit, provided an acknowledgement signal has been returned from the
slave.
b.
Slave mode
In slave mode, the following steps are required to receive a START condition
and a slave address via the I2C bus.
Upon detection of a START condition, the SBI0 clocks in a 7-bit slave address
and a data direction bit transmitted by the master during the first eight SCL0
clock pulses. If the received slave address matches its own address in the I2C0AR
or is equal to the general-call address (00H), the SBI0 pulls the SDA0 line low
during the last (e.g., 9th) SCL0 clock for acknowledgement.
The INTSBI0 interrupt request is generated on the falling edge of the 9th SCL0
clock pulse, and the PIN bit in the SBI0CR2 is cleared to 0. In slave mode, the
SBI0 holds the SCL0 line low while the PIN bit is 0.
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SCL line
1
2
3
4
5
6
7
8
9
SDA line
A6
A5
A4
A3
A2
A1
A0
R/ W
ACK
START condition
Acknowledgement
from slave
Slave address + Direction bit
PIN
INTSBI0
interrupt
request
Master to slave
Slave to master
Figure 3.10.18 Generation of a START Condition and a Slave Address
(3) Transferring a data word
Each time a data word has been transmitted or received, the INTSBI0 interrupt is
generated. It is the responsibility of the INTSBI0 interrupt service routine to test the
MST bit in the SBI0CR2 to determine whether the SBI is in master or slave mode.
a.
Master mode (SBI0CR2.MST = 1)
If the MST bit in the SBI0CR2 is set, then test the TRX bit in the same register
to determine whether the SBI0 is in master-transmitter or master-receiver mode.
Master-transmitter mode (SBI0CR2.TRX = 1)
Test the LRB bit in the SBI0SR. If the LRB bit is set, that means the slave-receiver
requires no further data to be sent from the master-transmitter. The
master-transmitter must then generate a STOP condition as described later to stop
transmission.
If the LRB bit is cleared, that means the slave-receiver requires further data. If the
number of bits per transfer is 8, then write the transmit data into the SBI0DBR. When
using other data length, program the BC[2:0] and ACK bits in the SBI0CR1, and then
write the transmit data into the SBI0DBR. When the SBI0DBR is loaded, the PIN bit
in the SBI0SR is set to 1, and the transmit data is shifted out from the SDA0 pin,
clocked by the SCL0 clock. Once the transfer is complete, the INTSBI0 interrupt is
generated, the PIN bit is cleared, and the SCL0 line is pulled low. To transmit further
data, test the LRB bit again and repeat the above procedure.
SCL0 pin
Write to SBI0DBR
SDA0 pin
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Acknowledgement
signal from receiver
PIN
INTSBI0
interrupt request
Master to slave
Slave to master
Figure 3.10.19 SBI0CR1.BC[2:0] = 000 and SBI0CR1.ACK = 1 (Master-transmitter mode)
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Master-receiver mode (SBI0CR2.TRX = 0)
When using other than 8 bits data length, program the BC[2:0] and ACK bits in the
SBI0CR1, and then read the SBI0DBR. (The first read of the SBI0DBR is a dummy
read because data has not yet been received. A dummy read returns an undefined
value.) Upon this read, the SCL0 line is released, the PIN bit in the SBI0SR is set.
Serial clock pulse for transferring new 1 word of data is defined SCL and outputs “L”
level from SDA pin with acknowledge timing.
Once the transfer is complete, the INTSBI0 interrupt is generated, the PIN bit is
cleared, and the SCL0 line is pulled low. Each subsequent read from the SBI0DBR is
accompanied by an SCL0 clock pulse for a data word and an acknowledgement signal.
Read of the received data
SCL0 pin
1
2
3
4
5
6
7
8
9
SDA0 pin
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Next D7
Acknowledgement
signal to transmitter
PIN
INTSBI0
interrupt request
Master to slave
Slave to master
Figure 3.10.20 SBI0CR1.BC[2:0] = 000 and SBI0CR1.ACK = 1 (Master-receiver mode)
To prepare to terminate the data transfer, the master-receiver must clear the ACK
bit in the SBI0CR1 immediately before the read of the second to last data word. This
causes an acknowledge clock pulse not to be generated on the last data word.
When the transfer is complete, the INTSBI0 interrupt is generated. After interrupt
processing, the INTSBI0 interrupt handler must set the BC[2:0] field in the SBI0CR1
to 001 and read the SBI0DBR, so that a clock is generated on the SCL0 line once. With
the ACK bit cleared, the master-receiver holds the SDA0 line high, which signals the
end of transfer to the slave-transmitter.
Then, the SBI0 generates the INTSBI0 interrupt again, whereupon the INTSBI0
interrupt service routine must generate a STOP condition to stop communication via
the I2C bus.
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SCL line 9
SDA line
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
1
Negative acknowledge
(High) to transmitter
PIN
INTSBI0
interrupt request
Read out the received data after clearing the SBI0CR1.ACK bit.
Read out the received
data after setting the
SBI0CR1.BC[2:0]
field to 001.
Master to slave
Slave to master
Figure 3.10.21 Terminating Data Transmission in Master Receiver Mode
b.
Slave mode (SBI0CR2.MST = 0)
Processing to be done in slave mode varies, depending on whether or not the
SBI0 has switched over to slave mode as a result of lost arbitration.
If the MST bit in the SBI0CR2 is cleared, the SBI0 is in slave mode. In slave
mode, the SBI0 generates the INTSBI0 interrupt on four occasions: 1) when the
SBI0 has received any slave address; 2) when the SBI0 has received a general-call
address; 3) when the received slave address matches its own address in the
I2C0AR; and 4) when a data transfer has been completed in response to a
general-call.
Also, if the SBI0, as a master, loses arbitration for the I2C bus, it switches to
slave mode. If arbitration is lost during a data transfer, SCL0 continues to be
generated until the data word is complete, then the INTSBI0 interrupt is
generated.
When the INTSBI0 interrupt occurs, the PIN bit in the SBI0SR is cleared, and
the SCL0 line is pulled low. When the SBI0DBR is read or written or when the
PIN bit is set back to 1, the SCL0 line is released after a period of tLOW.
Test the AL, TRX, AAS and AD0 bits in the SBI0SR to determine the processing
required, as summarized in Table 3.10.1.
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Table 3.10.1 Processing in Slave Mode
TRX
AL
AAS
AD0
State
Processing
1
1
1
0
Arbitration was lost while the slave
address was being transmitted, and
the SBI0 received a slave address with
the direction bit set transmitted by
another master.
Set the SBI0CR1.BC[2:0] field to the
number of bits in a data word and write
the transmit data into the SBI0DBR.
0
1
0
In slave-receiver mode, the SBI0
received a slave address with the
direction bit set transmitted by the
master.
0
0
In slave-transmitter mode, the SBI0
has completed a transmission of one
data word.
Test the SBI0SR.LRB bit. If the LRB bit
is set, that means the master-receiver
does not require further data. Set the
SBI0CR2.PIN bit to 1 and clear the
TRX bit to 0 to release the bus.
If the LRB bit is cleared, that means
the master-receiver requires further
data. Set the SBI0CR1.BC[2:0] field to
the number of bits in the data word and
write the transmit data to the
SBI0DBR.
0
1
0
1
1/0
Arbitration was lost while a slave
address was being transmitted, and
received either a slave address with
the direction bit cleared or a
general-call address transmitted by
another master.
0
0
1
1/0
In slave-receiver mode, the SBI0
received either a slave address with
the direction bit cleared or a
general-call address transmitted by the
master.
0
1/0
In slave-receiver mode, the SBI0 has
completed a reception of a data word.
Read the SBI0DBR (a dummy read) to
set the SBI0CR2.PIN bit to 1, or write a
1 to this bit.
Arbitration was lost while a slave
address or a data word was being
transmitted, and the transfer
terminated.
91CW28-181
Set the SBI0CR1.BC[2:0] field to the
number of bits in the data word and
read the received data from the
SBI0DBR.
2006-03-24
TMP91CW28
(4) Generating a STOP condition
When the SBI0SR.BB bit is set, setting the MST, TRX and PIN bits in the SBI0CR2
to 1 and clearing the BB bit in the same register causes the SBI0 to start a sequence for
generating a STOP condition on the I2C bus. Do not alter the contents of these bits
until the STOP condition is present on the bus.
If another device is holding down the SCL0 bus line, the SBI0 waits until the SCL0
line is released (High) again; when SCL0 is high, the SBI0 drives the SDA0 pin high to
generate a STOP condition.
1 → MST
1 → TRX
0 → BB
1 → PIN
Generate a STOP condition
Internal SCL
SDA0 pin
PIN
BB bit (Read)
Figure 3.10.22 Generating a STOP Condition (Single master)
1 → MST
1 → TRX
0 → BB
1 → PIN
Generate a STOP condition
Internal SCL
SCL0 pin
If held low
by another master
SDA0 pin
PIN
BB bit (Read)
Figure 3.10.23 Generating a STOP Condition (Multi master)
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(5) Repeated START condition
A data transfer is always terminated by a STOP condition. However, if a master still
wishes to communicate on the bus, it can generate a repeated START condition and
address another slave or change the data direction without first generating a STOP
condition. The following describes the steps required to generate a repeated START
condition.
First, clear the MST, TRX and BB bits in the SBI0CR2 and set the PIN bit in the
same register to release the bus. This causes the SDA0 pin to be held high and the
SCL0 pin to be released. Because no STOP condition is generated on the bus, other
devices think that the bus is busy.
Then, poll the SBI0SR.BB bit until it is cleared to ensure that the SCL0 pin is
released. Next, poll the LRB bit until it is set to ensure that no other device is pulling
the SCL0 bus line low. Once the bus is determined to be free this way, use the steps
described in (2), above, to generate a START condition.
To satisfy the minimum setup time of the START condition, at least 4.7 μs wait
period must be created by software after the bus becomes free.
0 → MST
0 → TRX
0 → BB
1 → PIN
1 → MST
1 → TRX
1 → BB
1 → PIN
4.7 μs (Min)
START condition
SCL bus
SCL0 pin
9
SDA0 pin
LRB
BB
PIN
Figure 3.10.24 Repeated START Condition
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3.10.7
Description of Registers Used in Clock-synchronous 8-Bit SIO Mode
This section provides a summary of the registers which control clock-synchronous 8-bit
SIO operation and provides its status information for monitoring.
Serial Bus Interface Control Register 1
SBI0CR1
(0240H)
Bit symbol
6
5
4
SIOINH
SIOM1
SIOM0
Read/Write
Reset value
Readmodify-write
operation is
not
supported.
7
SIOS
2
1
0
SCK2
SCK1
SCK0
W
0
Start
transfer
0: Stop
1: Start
Function
3
0
Abort
transfer
0: Continue
1: Abort
W
0
Transfer mode
0
0
00: Transmit mode
01: (Reserved)
10: Transmit/Receive
mode
11: Receive mode
W
0
0
Serial clock frequency/
software reset monitor
On writes: SCK[2:0] = Serial clock frequency
000 n = 4 600.0 kHz
001 n = 5 312.5 kHz
010 n = 6 156.3 kHz
011 n = 7 78.1 kHz
100 n = 8 39.1 kHz
101 n = 9 19.5 kHz
110 n = 10
111
−
Assumptions
System clock: fc
Clock gear: fc/1
fc = 10 MHz (Output to the SCK pin)
Frequency =
fc
n
[ Hz ]
2
9.8 kHz
External clock (Input from the SCK pin)
Transfer mode
00
8-bit transmit mode
01
(Reserved)
10
8-bit transmit/receive mode
11
8-bit receive mode
Abort transfer
0
Continue
1
Abort (This bit is automatically cleared after transfer is aborted.)
Start transfer
0
Stop
1
Start
Note: Clear the SIOS bit and set the SIOINH bit before programming the transfer mode and serial clock frequency
bits.
Serial Bus Interface Data Buffer Register
SBI0DBR
(0241H)
Readmodify-write
operation is
not
supported.
Bit symbol
7
6
5
4
3
2
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read/Write
R (Receive)/W (Transmit)
Reset value
Undefined
Figure 3.10.25 SIO Mode Registers (1) (SBI0CR1 and SBI0DBR for the SBI0)
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Serial Bus Interface Control Register 1
SBI1CR1
(0248H)
Bit symbol
6
5
4
SIOINH
SIOM1
SIOM0
Read/Write
Reset value
Readmodify-write
operation is
not
supported.
7
SIOS
2
1
0
SCK2
SCK1
SCK0
W
0
Start
transfer
0: Stop
1: Start
Function
3
0
Abort
transfer
0: Continue
1: Abort
W
0
0
Transfer mode
00: Transmit mode
01: (Reserved)
10: Transmit/Receive
mode
11: Receive mode
0
W
0
0
Serial clock frequency/
software reset monitor
On writes: SCK[2:0] = Serial clock frequency
000 n = 4 600.0 kHz
001 n = 5 312.5 kHz
010 n = 6 156.3 kHz
011 n = 7 78.1 kHz
100 n = 8 39.1 kHz
101 n = 9
110 n = 10
111
19.5 kHz
−
Assumptions
System clock: fc
Clock gear: fc/1
fc = 10 MHz (Output to the SCK pin)
Frequency =
fc
n
[ Hz ]
2
9.8 kHz
External clock (Input from the SCK pin)
Transfer mode
00
8-bit transmit mode
01
(Reserved)
10
8-bit transmit/receive mode
11
8-bit receive mode
Abort transfer
0
Continue
1
Abort (This bit is automatically cleared after transfer is aborted.)
Start transfer
0
Stop
1
Start
Note: Clear the SIOS bit and set the SIOINH bit before programming the transfer mode and serial clock frequency
bits.
Serial Bus Interface Data Buffer Register
7
6
5
4
3
2
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SBI0DBR
(0249H)
Bit symbol
Read/Write
R (Receive)/W (Transmit)
Readmodify-write
operation is
not
supported.
Reset value
Undefined
Figure 3.10.26 SIO Mode Registers (2) (SBI1CR1 and SBI1DBR for the SBI1)
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Serial Bus Interface Control Register 2
7
SBI0CR2
(0243H)
Readmodify-write
operation is
not
supported.
6
5
4
Bit symbol
3
2
1
SBIM1
SBIM0
−
−
W
W
Read/Write
W
Reset value
0
Function
0
Operating mode
0
0
0
(Note 2)
(Note 2)
00: Port mode
01: SIO mode
2
10: I C bus mode
11: (Reserved)
Operating mode
Note 1: The BC[2:0] bits in the SBI0CR1 register must
be cleared to 000 before selecting
00 Port mode (Serial bus interface output disabled)
clock-synchronous 8-bit SIO mode.
01 Clock-synchronous 8-bit SIO mode
2
10 I C bus mode
Note 2: Please always write SBI0CR2[1:0] to 00.
11 (Reserved)
Serial Bus Interface Register
7
SBI0SR
(0243H)
6
5
4
Bit symbol
3
2
SIOF
SEF
Read/Write
1
0
R
Reset value
0
Function
0
Shift
operation
status
Serial
transfer
status
Serial transfer status monitor
Shift operation status monitor
0
Terminated
0
Terminated
1
In progress
1
In progress
Serial Bus Interface Baud Rate Register 0
7
6
SBI0BR0
(0244H)
Bit symbol
−
I2SBI0
Read/Write
W
R/W
Readmodify-write
operation is
not
supported.
Reset value
0
Must be
written as
“0”.
Function
5
4
3
2
1
0
0
IDLE2
0: OFF
1: ON
Operation in IDLE2 mode
0
OFF
1
ON
Serial Bus Interface Baud Rate Register 1
SBI0BR1
(0245H)
7
6
Bit symbol
P4EN
−
Read/Write
W
W
Reset value
Readmodify-write
operation is
not
supported.
Function
0
Internal
clock
0: OFF
1: ON
5
4
3
2
1
0
0
Must be
written as
“0”.
Internal baud rate generator
0
OFF
1
ON
Figure 3.10.27 SIO Mode Registers (3) (SBI0CR2, SBI0SR, SBI0BR0, and SBI0BR1 for the SBI0)
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Serial Bus Interface Control Register 2
7
SBI1CR2
(024BH)
Readmodify-write
operation is
not
supported.
6
5
4
Bit symbol
3
2
1
SBIM1
SBIM0
−
−
W
W
Read/Write
W
Reset value
0
Function
0
Operating mode
0
0
0
(Note 2)
(Note 2)
00: Port mode
01: SIO mode
2
10: I C bus mode
11: (Reserved)
Operating mode
Note 1: The BC[2:0] bits in the SBI1CR1 register must
be cleared to 000 before selecting
00 Port mode (Serial bus interface output disabled)
clock-synchronous 8-bit SIO mode.
01 Clock-synchronous 8-bit SIO mode
2
10 I C bus mode
Note 2: Please always write SBI1CR2[1:0] to 00.
11 (Reserved)
Serial Bus Interface Register
7
SBI1SR
(024BH)
6
5
4
Bit symbol
3
2
SIOF
SEF
Read/Write
1
0
R
Reset value
0
Function
0
Shift
operation
status
Serial
transfer
status
Serial transfer status monitor
Shift operation status monitor
0
Terminated
0
Terminated
1
In progress
1
In progress
Serial Bus Interface Baud Rate Register 0
7
6
SBI1BR0
(024CH)
Bit symbol
−
I2SBI0
Read/Write
W
R/W
Readmodify-write
operation is
not
supported.
Reset value
0
Must be
written as
“0”.
Function
5
4
3
2
1
0
0
IDLE2
0: OFF
1: ON
Operation in IDLE2 mode
0
OFF
1
ON
Serial Bus Interface Baud Rate Register 1
SBI1BR1
(024DH)
7
6
Bit symbol
P4EN
−
Read/Write
W
W
Reset value
Readmodify-write
operation is
not
supported.
Function
0
Internal
clock
0: OFF
1: ON
5
4
3
2
1
0
0
Must be
written as
“0”.
Internal baud rate generator
0
OFF
1
ON
Figure 3.10.28 SIO Mode Registers (4) (SBI1CR2, SBI1SR, SBI1BR0, and SBI1BR1 for the SBI1)
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(1) Serial clock
a.
Clock source
The clock source for SIO mode can be selected from internal and external clocks
through the programming of the SCK[2:0] field in the SBI0CR1.
Internal clocks
One of the seven internal clocks can be used as a serial clock, which is driven onto
the SCK0 pin.
If software is slow and the reading of the received data or the writing of the transmit
data cannot keep up with the serial clock rate, the SBI0 automatically inserts a wait
period, as shown below. During this period, the serial clock is temporarily stopped to
suspend a shift operation.
Automatically inserted wait period
1
2
3
7
8
1
a0
a1
a2 a5
a6
a7
b0
SCK0 output
SO0 output
Writes of the
transmit data
a
b
2
b1
b4
6
7
8
1
2
3
b5
b6
b7
c0
c1
c2
c
Figure 3.10.29 Automatic Wait Insertion
External clock (SBI0CR1.SCK[2:0] = 111)
If the SCK[2:0] field in the SBI0CR1 contains 111, the SBI0 uses an external clock
supplied from the SCK0 pin as a serial clock. For proper shift operations, the clock high
width and the clock low width must satisfy the following relationship, so that the
maximum transfer frequency is 0.6 MHz (when fc = 10 MHz).
SCK0 pin
tSCKL tSCKH
TSCKL, tSCKH > 8/fc
Figure 3.10.30 Maximum External Clock Frequency
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b.
Shift edge types
In transmit mode, leading-edge shift is used. In receive mode, trailing-edge shift
is used.
Leading-edge shift
Every bit of SIO data is shifted by the leading edge of the serial clock (Falling edge of
SCK0).
Trailing-edge shift
Every bit of SIO data is shifted by the trailing edge of the serial clock (Rising edge of
SCK0).
SCK0 pin
SO0 pin
Shift register
Bit0
Bit1
Bit2
76543210 *7654321 **765432
Bit3
Bit4
Bit5
Bit6
Bit7
***76543
****7654
*****765
******76
******7
Bit4
Bit5
Bit6
Bit7
(a) Leading-edge shift
SCK0 pin
SI0 pin
Shift register
Bit0
********
Bit1
0*******
Bit2
10******
Bit3
210*****
3210****
43210***
543210** 6543210* 76543210
(b) Trailing-edge shift
*: Don’t care
Figure 3.10.31 Shift Edge Types
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(2) Transfer modes
The SBI0 supports three SIO transfer modes: Receive mode, transmit mode and
transmit/receive mode. The SIOM[1:0] field in the SBI0CR1 is used to select a transfer
mode.
a.
8-bit transmit mode
Configure the SIO interface in transmit mode and write the transmit data into
the SBI0DBR. Then setting the SIOS bit in the SBI0CR1 initiates a transmission.
The contents of the SBI0DBR are moved to an internal shift register and then
shifted out on the SO0 pin, with the least-significant bit (LSB) first, synchronous
to the serial clock. Once the transmit data is transferred to the shift register, the
SBI0DBR becomes empty, and the buffer-empty interrupt (INTSBI0) is generated.
In internal clock mode, the SIO interface will be in wait state (SCK will stop)
until the INTSBI0 interrupt service routine provides the next transmit data to the
SBI0DBR. Once the SBI0DBR is loaded, the SIO interface will automatically get
out of the wait state.
In external clock mode, the INTSBI0 interrupt service routine must provide the
next transmit data to the SBI0DBR before the previous transmit data has been
shifted out. Therefore, the data rate is a function of the maximum latency between
when the INTSBI0 interrupt is generated and when the SBI0DBR is loaded by the
interrupt service routine.
At the beginning of a transmission, the value of the last bit of the previously
transmitted byte appears on the SO0 pin between when the SBI0SR.SIOF bit is
set and when SCK subsequently goes low.
Transmission can be terminated by the INTSBI0 interrupt service routine
clearing the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared,
the remaining bits in the SBI0DBR continue to be shifted out before transmission
ends. In this case, software can check the SBI0SR.SIOF bit to determine whether
transmission has come to an end (0 = end-of-transmission). If the SIOINH bit is
set, the ongoing transmission is aborted immediately, and the SIOF bit is cleared
at that point.
In external clock mode, the SIOS bit must be cleared before the SIO interface
begins shifting out the next transmit data. Otherwise, the SIO will stop after
sending out dummy data.
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The SIOS bit is cleared
SIOS
SIOF
SEF
SCK0 output
SO0 pin
a0
*
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
b6
b7
INTSBI0
interrupt request
SBI0DBR
b
a
Writes of the transmit data
(a) Internal clock mode
The SIOS bit is cleared
SIOS
SIOF
SEF
SCK0 input
SO0 pin
*
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
INTSBI0
interrupt request
SBI0DBR
a
b
Writes of the transmit data
(b) External clock mode
Figure 3.10.32 Transmit Mode
Example: Terminating transmission by SIOS (External clock mode)
STEST1: BIT
JR
STEST2: BIT
JR
LD
2, (SBI0SR)
NZ, STEST1
0, (P6)
Z, STEST2
(SBI0CR1), 00000111B
91CW28-191
; If SEF = 1 then loop.
; If SCK = 0 then loop.
; SIOS ← 0.
2006-03-24
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SCK0 pin
SIOF
SO0 pin
Bit6
Bit7
tSODH = Min 3.5/fFPH [s]
Figure 3.10.33 Retention Time of the Last Transmitted Bit
b.
8-bit receive mode
Configure the SIO interface in receive mode. Then setting the SIOS bit in the
SBI0CR1 enables reception. The receive data is clocked into the internal shift
register via the SI0 pin, with the least-significant bit (LSB) first, synchronous to
the serial clock. Once the shift register is fully loaded, the received byte is
transferred to the SBI0DBR, and the buffer-full interrupt (INTSBI0) is generated.
The INTSBI0 interrupt service routine must then pick up the received data from
the SBI0DBR.
In internal clock mode, the SIO interface will be in wait state (SCK will stop)
until the INTSBI0 interrupt service routine reads the data from the SBI0DBR.
In external clock mode, shift operations continue, synchronous to the external
clock. The INTSBI0 interrupt service routine must read the data from the
SBI0DBR before the next serial clock pulse is applied. Otherwise, subsequently
received data will be canceled. In this mode, the maximum data rate is a function
of the maximum latency between when the INTSBI0 interrupt is generated and
when the SBI0DBR is read by the interrupt service routine.
Reception can be terminated by the INTSBI0 interrupt service routine clearing
the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared,
reception continues until the shift register is fully loaded and transferred to the
SBI0DBR. In this case, software can check the SBI0SR.SIOF bit to determine
whether reception has come to an end (0 = end-of-reception). If the SIOINH bit is
set, the ongoing reception is aborted immediately, and the SIOF bit is cleared at
that point. (The received data becomes invalid, there is no need to read it out.)
Note:
The contents of the SBI0DBR are not preserved after changing the transfer
mode. Before changing the transfer mode, clear the SIOS bit to complete the
ongoing reception and have the INTSBI0 interrupt service routine pick up the
last received data.
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The SIOS bit is cleared
SIOS
SIOF
SEF
SCK0 output
a0
SI0 pin
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSBI0
interrupt request
a
SBI0DBR
Read of the received data
b
Read of the received data
Figure 3.10.34 Receive Mode (Internal clock mode)
c.
8-bit transmit/receive mode
Configure the SIO interface in transmit/receive mode and write the transmit
data into the SBI0DBR. Then setting the SIOS bit in the SBI0CR1 initiates
transmission and reception. The transmit data is shifted out through the SO0 pin,
with the least-significant bit (LSB) first, with the falling edge of the serial clock,
while at the same time the receive data is shifted in through the SI0 pin with the
rising edge of the serial clock. Once the shift register is fully loaded with eight bits
of the received data, it is transferred to the SBI0DBR, and the INTSBI0 interrupt
is generated. The INTSBI0 interrupt service routine must then pick up the
received data from the SBI0DBR and writes the next transmit data into the
SBI0DBR. Because the SBI0DBR is shared between transmit and receive
operations, the received data must be read before the next transmit data is
written.
In internal clock mode, the SIO interface will be in wait state (SCK will stop)
after a read of the received data until a write of the transmit data.
In external clock mode, shift operations continue, synchronous to the external
clock. Therefore, software must read the received data and write the transmit
data before the next shift operation begins. In this mode, the maximum data rate
is a function of the maximum latency between when the INTSBI0 interrupt is
generated and when the interrupt service routine reads the received data and
writes the transmit data.
At the beginning of a transmission, the value of the last bit of the previously
transmitted byte appears on the SO0 pin between when the SBI0SR.SIOF bit is
set and when SCK subsequently goes low.
Transmission/reception can be terminated by the INTSBI0 interrupt service
routine clearing the SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is
cleared, reception continues until the shift register is fully loaded and transferred
to the SBI0DBR. In this case, software can check the SBI0SR.SIOF bit to
determine whether transmission/reception has come to an end (0 =
end-of-reception/transmission). If the SIOINH bit is set, the ongoing
transmission/reception is aborted immediately, and the SIOF bit is cleared at that
point.
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Note:
The contents of the SBI0DBR are not preserved after changing the transfer
mode. Before changing the transfer mode, clear the SIOS bit to complete the
ongoing transmission/reception and have the INTSBI0 interrupt service
routine pick up the last received data.
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The SIOS bit is cleared
SIOS
SIOF
SEF
SCK0 output
SO0 pin
*
SI0 pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
c0
c1
c2
c3
c4
c5
c6
c7
d0
d1
d2
d3
d4
d5
d6
d7
INTSBI0
interrupt request
SBI0DBR
a
c
Write of the transmit data (a)
b
Read of the
Write of the
received data (c) transmit data (b)
d
Read of the
received data (d)
Figure 3.10.35 Receive/Transmit Mode (Internal clock mode)
SCK0 output
SIOF
SO0 pin
Bit6
Bit7 of the last byte transmitted
tSODH = Min 4/fFPH [s]
Figure 3.10.36 Retention Time of the Transmit Data in Receive/Transmit Mode
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3.11 Analog-to-Digital Converter (ADC)
The TMP91CW28 has a 8-channel, multiplexed-input, 10-bit successive-approximation
analog-to-digital converter (ADC).
Figure 3.11.1 shows a block diagram of the ADC. The eight analog input channels (AN0 to
AN7) can be used as general-purpose digital inputs (Port 5) if not needed as analog channels.
Note:
Ensure that the ADC has halted before executing the HALT instruction to place the
TMP91CW28 in IDLE2, IDLE1 or STOP mode to reduce power supply current. Otherwise,
the TMP91CW28 might go into a standby mode while the internal analog comparator is still
active.
Internal data bus
AD mode control register 1
(ADMOD1)
ADTRGE
ADCH[2:0]
VREFON
Internal data bus
Internal data bus
AD mode control register 0 (ADMOD0)
EOCF
ADBF
ITM0
REPEAT SCAN
ADS
Scan
Channel
Repeat
selection control
Interrupt
circuit
ADTRG
Busy
End
Start
Interrupt request
AD converter
(INTAD)
control circuit
AN7 (P57)
AN5 (P55)
AN4 (P54)
AN3/ ADTRG (P53)
Multiplexer
AN6 (P56)
AD conversion
Sampleand-hold
+
result registers
(ADREG04L to 37L)
AN2 (P52)
−
(ADREG04H to 37H)
AN1 (P51)
AN0 (P50)
VREFH
Comparator
DA converter
VREFL
Figure 3.11.1 ADC Block Diagram
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3.11.1
Register Description
The ADC has two mode control registers (ADMOD0 and ADMOD1) and four conversion
result high/low register pairs (ADREG04H/L, ADREG15H/L, ADREG26H/L and
ADREG37H/L). The conversion result registers contain the digital values of completed
conversions.
Figure 3.11.2 to Figure 3.11.5 show the registers available in the ADC.
AD Mode Control Register 0
ADMOD0
(02B0H)
Bit symbol
7
6
5
4
3
2
1
0
EOCF
ADBF
−
−
ITM0
REPEAT
SCAN
ADS
0
0
0
0
0
0
0
Must be
written as “0”.
Interrupt in
fixedchannel
continuous
conversion
mode
0: Generated
after each
conversion
1: Generated
after every
four
conversions
Continuous
conversion
mode
0: Single
1: Continuous
Channel scan
mode
0: Fixedchannel
1: Channel
scan
AD conversion
start
0: Don’t care
1: Start
Read/Write
Reset value
Function
R
0
End-ofconversion
flag
0: During
conversion
1: Completed
R/W
AD conversion Must be
busy flag
written as “0”.
0: Idle
1: During
conversion
This bit is
always read
as “0”.
AD conversion start
0
Don’t care
1
Starts AD conversion.
Note: This bit is always read as 0.
Channel scan mode
0
Fixed-channel mode
1
Channel scan mode
Continuous conversion mode
0
Single conversion mode
1
Continuous conversion mode
Interrupt in fixed-channel continuous conversion
mode
Fixed-channel continuous conversion mode
SCAN = 0, REPEAT = 1
0
Generates INTAD interrupt when a single
conversion has been completed.
1
Generates INTAD interrupt when a sequence
of four conversions has been completed.
AD conversion busy flag
0
Idle
1
During conversion
End-of-conversion flag
0
Before or during conversion
1
Completed
Figure 3.11.2 AD Conversion Registers (1)
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AD Mode Control Register 1
ADMOD1
(02B1H)
7
6
Bit symbol
VREFON
I2AD
Read/Write
R/W
R/W
Reset value
0
0
Function
VREF control
0: OFF
1: ON
5
4
3
2
1
0
ADTRGE
ADCH2
ADCH1
ADCH0
0
0
0
0
R/W
ADC
operation in
IDLE2 mode
0: OFF
1: ON
External
conversion
trigger
0: Disable
1: Enable
Analog input channel select
Analog input channel select
SCAN
0
1
Fixed-channel
Channel Scan
ADCH[2:0]
000
Mode
AN0
AN0
Mode
001
AN1
AN0→AN1
AN0→AN1→AN2
010
AN2
011 (Note)
AN3
AN0→AN1→AN2→AN3
100
AN4
AN4
101
AN5
AN4→AN5
110
AN6
AN4→AN5→AN6
111
AN7
AN4→AN5→AN6→AN7
AD external conversion trigger ( ADTRG )
0
Disable
1
Enable
ADC operation in IDLE2 mode
0
OFF
1
ON
Reference voltage for the ADC
0
OFF
1
ON
Set the VREFON bit to 1 before setting the
ADS bit in the ADMOD0 to start a conversion.
Note: The AN3 pin is shared with the ADTRG pin. Therefore, when the external conversion trigger input ( ADTRG ) is
enabled (e.g., when ADMOD1.ADTRGE = 1), the ADCH[2:0] field must not be programmed to 011.
Figure 3.11.3 AD Conversion Registers (2)
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AD Conversion Result Low Register 0/4
ADREG04L
(02A0H)
Bit symbol
7
6
ADR01
ADR00
5
4
3
2
1
0
ADR0RF
Read/Write
R
R
Reset value
Undefined
0
Function
Lower 2 bits of an AD
Conversion
conversion result
result store
flag
1: Stored
AD Conversion Result High Register 0/4
ADREG04H
(02A1H)
Bit symbol
7
6
5
4
3
2
1
0
ADR09
ADR08
ADR07
ADR06
ADR05
ADR04
ADR03
ADR02
Read/Write
R
Reset value
Undefined
Function
Upper 8 bits of an AD conversion result
AD Conversion Result Low Register 1/5
ADREG15L
(02A2H)
Bit symbol
7
6
ADR11
ADR10
5
4
3
2
1
0
ADR1RF
Read/Write
R
R
Reset value
Undefined
0
Function
Lower 2 bits of an AD
conversion result
Conversion
result store
flag
1: Stored
Lower 2 bits of an AD conversion result
ADREG15H
(02A3H)
Bit symbol
7
6
5
4
3
2
1
0
ADR19
ADR18
ADR17
ADR16
ADR15
ADR14
ADR13
ADR12
Read/Write
R
Reset value
Undefined
Function
Upper 8 bits of an AD conversion result
9
8
7
6
ADREGxH
7 6 5
4
5
4
3
2
1
0
Channel x conversion
result bits
3
2
1
•
•
0
7
6
5
4
3
2
ADREGxL
1 0
Bits 5 to 1 are always read as 1s.
Bit0 (ADRxRF), when set, indicates that the conversion
result has been stored in the ADREGxH/L register pair.
This bit is cleared when either the ADREGxH or the
ADREGxL is read.
Figure 3.11.4 AD Conversion Registers (3)
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AD Conversion Result Low Register 2/6
ADREG26L
(02A4H)
Bit symbol
7
6
ADR21
ADR20
5
4
3
2
1
0
ADR2RF
Read/Write
R
R
Reset value
Undefined
0
Function
Lower 2 bits of an AD
Conversion
conversion result
result store
flag
1: Stored
AD Conversion Result High Register 2/6
ADREG26H
(02A5H)
Bit symbol
7
6
5
4
3
2
1
0
ADR29
ADR28
ADR27
ADR26
ADR25
ADR24
ADR23
ADR22
Read/Write
R
Reset value
Undefined
Function
Upper 8 bits of an AD conversion result
AD Conversion Result Low Register 3/7
ADREG37L
(02A6H)
Bit symbol
7
6
ADR31
ADR30
5
4
3
2
1
0
ADR3RF
Read/Write
R
R
Reset value
Undefined
0
Function
Lower 2 bits of an AD
conversion result
Conversion
result store
flag
1: Stored
AD Conversion Result High Register 3/7
ADREG37H
(02A7H)
Bit symbol
7
6
5
4
3
2
1
0
ADR39
ADR38
ADR37
ADR36
ADR35
ADR34
ADR33
ADR32
Read/Write
R
Reset value
Undefined
Function
Upper 8 bits of an AD conversion result
9
8
7
6
ADREGxH
7 6 5
4
5
4
3
2
1
0
Channel x conversion
result bits
3
2
1
•
•
0
7
6
5
4
3
2
ADREGxL
1 0
Bits 5 to 1 are always read as 1s.
Bit0 (ADRxRF), when set, indicates that the conversion
result has been stored in the ADREGxH/L register pair.
This bit is cleared when either the ADREGxH or the
ADREGxL is read.
Figure 3.11.5 AD Conversion Registers (4)
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3.11.2
Operation
(1) Analog reference voltages
The VREFH and VREFL pins provide the reference voltages for the ADC. These pins
establish the full-scale range for the internal resistor string, which divides the range
into 1024 steps. The digital result of the conversion is derived by comparing the
sampled analog input voltage to the resistor string voltages.
Clearing the VREFON bit in the ADMOD1 turns off the switch between VREFH and
VREFL. Once the VREFON bit is cleared, the internal reference voltage requires a
recovery time of 3 µs to stabilize after the VREFON bit is again set to 1. This recovery
time is independent of the system clock frequency. The ADS bit in the ADMOD0 must
then be set to initiate a conversion.
(2) Selecting an analog input channel(s)
There are two basic conversion modes: Fixed-channel mode and channel scan mode.
The SCAN bit in the ADMOD0 affects the conversion channel(s) that will be selected as
follows.
•
Fixed-channel mode (ADMOD0.SCAN = 0)
When the SCAN bit in the ADMOD0 is cleared, the ADC runs conversions on a
single input channel selected from AN0 to AN7 via the ADCH[2:0] field in the
ADMOD1.
•
Channel scan mode (ADMOD0.SCAN = 1)
When the SCAN bit in the ADMOD0 is set, the ADC runs conversions on
sequential channels in a specific group selected via the ADCH[2:0] field in the
ADMOD1.
Refer to Table 3.11.1. After a reset, the ADMOD0.SCAN bit defaults to 0, and the
ADMOD1.ADCH[2:0] field defaults to 000. Thus, the AN0 pin is selected as the
conversion channel. The AN0 to AN7 pins can be used as general-purpose input ports if
not used as analog input channels.
Table 3.11.1 Analog Input Channel Selection
ADMOD1.ADCH[2:0]
Fixed-channel Mode
ADMOD0.SCAN = 0
Channel Scan Mode
ADMOD0.SCAN = 1
000
AN0
AN0
001
AN1
AN0→AN1
010
AN2
AN0→AN1→AN2
011
AN3
AN0→AN1→AN2→AN3
100
AN4
AN4
101
AN5
AN4→AN5
110
AN6
AN4→AN5→AN6
111
AN7
AN4→AN5→AN6→AN7
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(3) Starting an AD conversion
The ADC initiates a conversion or a sequence of conversions when the ADS bit in the
ADMOD0 is set, or when a falling edge is applied to the ADTRG pin if the ADTRGE bit
in the ADMOD1 is set. When a conversion starts, the busy flag (ADMOD0.ADBF) is
set.
Writing a 1 to the ADS bit causes the ADC to abort any ongoing conversion and start
sampling the selected channel to begin a new conversion. The conversion result store
flag (ADREGxL.ADRxRF) indicates whether the result register contains a valid digital
result at that point.
In external conversion trigger mode, a falling edge on the ADTRG pin is ignored
while a conversion is in progress.
(4) Conversion modes and conversion-done interrupts
The ADC supports the following four conversion modes:
•
Fixed-channel single conversion mode
•
Channel scan single conversion mode
•
Fixed-channel continuous conversion mode
•
Channel scan continuous conversion mode
The REPEAT and SCAN bits in the ADMOD0 select the conversion mode.
The ADC generates the INTAD interrupt and sets the EOCF bit in the ADMOD0 at
the end of the conversion process.
a.
Fixed-channel single conversion mode
This mode is selected by programming the REPEAT and SCAN bits in the
ADMOD0 to 00. In this mode, the ADC performs a single conversion on a single
selected channel. When a conversion is completed, the ADC sets the
ADMOD0.EOCF bit, clears the ADMOD0.ADBF bit and generates the INTAD
interrupt.
b.
Channel scan single conversion mode
This mode is selected by programming the REPEAT and SCAN bits in the
ADMOD0 to 01. In this mode, the ADC performs a single conversion on each of a
selected group of channels. When a single conversion sequence is completed, the
ADC sets the ADMOD0.EOCF bit, clears the ADMOD0.ADBF bit and generates
the INTAD interrupt.
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c.
Fixed-channel continuous conversion mode
This mode is selected by programming the REPEAT and SCAN bits in the
ADMOD0 to 10. In this mode, the ADC repeatedly converts a single selected
channel. When a conversion process is completed, the ADC sets the
ADMOD.EOCF bit. The ADMOD0.ADBF bit remains set.
The ITM0 bit in the ADMOD0 controls interrupt generation in this mode. If the
ITM0 bit is cleared, the ADC generates an interrupt after each conversion. If the
ITM0 bit is set, the ADC generates an interrupt after every four conversions.
d.
Channel scan continuous conversion mode
This mode is selected by programming the REPEAT and SCAN bits in the
ADMOD0 to 11. In this mode, the ADC repeatedly converts the selected group of
channels. When a single conversion sequence is completed, the ADC sets the
ADMOD0.EOCF bit and generates the INTAD interrupt. The ADMOD0.ADBF bit
remains set.
In continuous conversion modes (c and d), clearing the ADMOD0.REPEAT bit
stops the conversion sequence after the ongoing conversion process is completed.
The ADMOD0.ADBF bit is cleared.
If the I2AD bit in the ADMOD1 is cleared, putting the TMP91CW28 in any
HALT mode (IDLE2, IDLE1, or STOP) causes the ADC to be immediately disabled,
even if a conversion is in progress. Once the TMP91CW28 exits the HALT mode,
the ADC restarts a conversion sequence when in a continuous conversion mode (c
or d), but remains inactive when in a single conversion mode (a or b).
Table 3.11.2 summarizes interrupt request generation in each of the conversion
modes.
Table 3.11.2 Interrupt Request Generation in Each AD Conversion Mode
ADMOD0
Interrupt Request
Generation
ITM0
REPEAT
SCAN
Fixed-channel single
conversion mode
After a conversion
X
0
0
Channel scan single
conversion mode
After a scan conversion
sequence
X
0
1
Fixed-channel
continuous
conversion mode
After each conversion
0
After every four
conversions
1
1
0
After each scan
conversion sequence
X
1
1
Mode
Channel scan
continuous
conversion mode
X: Don’t care
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(5) Conversion time
The conversion process requires 84 conversion states per channel. For example, this
results in a conversion time of 16.8 μs with 10 MHz fFPH.
(6) Storing and reading the AD conversion result
Conversion results are loaded into conversion result high/low register pairs
(ADREG04H/L to ADREG37H/L). These registers are read only.
In fixed-channel continuous conversion mode, conversion data goes into the
ADREG04H/L to the ADREG37H/L sequentially. In other modes, channels AN0 and
AN4 share the ADREG04H/L; channels AN1 and AN5 share the ADREG15H/L;
channels AN2 and AN6 share the ADREG26H/L; and channels AN3 and AN7 share
the ADREG37H/L.
Table 3.11.3 shows the relationships between the analog input channels and the AD
conversion result registers.
Table 3.11.3 Relationships between Analog Input Channels and AD Conversion Result Registers
AD Conversion Result Registers
Analog Input Channel
Modes Other Than
Fixed-channel Continuous Conversion
(Port 5)
Fixed-channel Continuous
Mode (<ITM0>=1)
Conversion Mode
AN0
ADREG04H/L
AN1
ADREG15H/L
AN2
ADREG26H/L
AN3
ADREG37H/L
AN4
ADREG04H/L
AN5
ADREG15H/L
AN6
ADREG26H/L
AN7
ADREG37H/L
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
Bit0 (ADRxRF) in each ADREGxL register indicates whether the conversion result
has been read. This bit is set when the conversion result is loaded into the
ADREGxH/L pair, and cleared when either the ADREGxH or ADREGxL is read.
Reading the conversion result clears the end-of-conversion flag (ADMOD0.EOCF).
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Programming examples:
a.
Converting the analog input voltage on the AN3 pin to a digital value and storing the
converted value in a memory location (0800H) using an AD interrupt (INTAD) handler
routine.
Settings in the main routine
7 6 5 4 3 2 1 0
INTE0AD
ADMOD1
ADMOD0
← X 1 0 0 X − − −
← 1 1 X X 0 0 1 1
← X X 0 0 0 0 0 1
Enables INTAD and sets its priority level to 4.
Selects AN3 as the analog input channel.
Starts conversion in fixed-channel single conversion mode.
Interrupt routine processing example
WA
← ADREG37
Loads the conversion result into 16-bit general-purpose register
WA
>>6
Shifts the contents of WA 6 bits to the right, padding 0s to the
(0800H)
← WA
WA from ADREG37L and ADREG37H.
vacated high-order bits.
b.
Stores the contents of WA to address 0800H.
Converting the analog input voltages on AN0 to AN2 sequentially in channel scan
continuous conversion mode.
← X 0 0 0 X − − −
← 1 1 X X 0 0 1 0
Disables INTAD.
ADMOD1
ADMOD0
← X X 0 0 0 1 1 1
Starts conversion in channel scan continuous conversion mode.
INTE0AD
Selects AN2 as analog input channels.
X: Don’t care, −: No change
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3.12 Watchdog Timer (WDT)
The TMP91CW28 contains a watchdog timer (WDT). The WDT is used to regain control of the
system in the event of software or system lockups due to spurious noises, etc. When a watchdog
timer time-out occurs, the WDT generates a nonmaskable interrupt to the CPU.
Connecting the watchdog timer output to the reset pin internally forces a reset. (The level of
external RESET pin is not changed.)
3.12.1
Implementation
Figure 3.12.1 shows a block diagram of the WDT.
WDMOD.RESCR
Reset control
RESET pin
Internal reset
Interrupt request
(INTWD)
WDMOD.
WDTP[1:0]
Selector
2
fSYS
(fFPH/2)
15
2
17
2
19
2
21
Q
22-stage binary counter
R
S
Reset
Internal
reset
Write of
4EF
Write of WDMOD.WDTE
B1H
Watchdog timer control register
(WDCR)
Internal data bus
Figure 3.12.1 WDT Block Diagram
Note: It needs to care designing the total machine set, because Watchdog timer can’t
operate completely by external noise.
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The WDT contains a 22-stage binary counter clocked by the fSYS clock. This binary
counter provides 215, 217, 219, or 221 as a counter overflow signal, as programmed into the
WDTP[1:0] field in the WDMOD.
WDT counter
Overflow
n
0
WDT interrupt
A write of a special
clear-count code
WDT clear
(Via software)
Figure 3.12.2 Default Operation
Also, the counter overflow can be programmed to cause a system reset as the time-out
action. If so programmed, a counter overflow causes the WDT to assert the internal reset
signal for a 22 to 29 state time (70.4 to 92.8 μs when fOSCH = 10 MHz and fFPH = 625 kHz).
After a reset, the fSYS clock (1 cycle = 1 state) is fFPH/2, where fFPH is generated by dividing
the high-speed oscillator clock (fOSCH) by sixteen through the clock gear function.
Overflow
WDT counter
n
WDT interrupt
Internal reset
22 to 29 states (70.4 to 92.8 μs when fOSCH = 10 MHz and fFPH = 625 kHz)
Figure 3.12.3 Reset Operation
91CW28-207
2006-03-24
TMP91CW28
3.12.2
Register Description
The WDT is controlled by two registers called WDMOD and WDCR.
(1) Watchdog timer mode register (WDMOD)
a.
Time-out period (WDMOD.WDTP[1:0])
This 2-bit field determines the duration of the WDT time-out interval. Upon
reset, the WDTP[1:0] field defaults to 00. Figure 3.12.4 shows possible time-out
periods.
b.
WDT enable (WDMOD.WDTE)
Upon reset, the WDTE bit is set to 1, enabling the WDT. To disable the WDT,
the clearing of the WDTE bit must be followed by a write of a special key code
(B1H) to the WDCR register. This prevents a “lost” program from disabling the
WDT operation. The WDT can be re-enabled only by setting the WDTE bit.
c.
System reset (WDMOD.RESCR)
This bit is used to program the WDT to generate a system reset on a time-out.
Upon reset, this bit is cleared, thus the time-out does not cause a system reset.
(2) Watchdog timer control register (WDCR)
This register is used to disable the WDT and to clear the WDT binary counter.
•
Disabling the WDT
The WDT can be disabled by clearing the WDMOD.WDTE to 0 and then writing
the special disable code (B1H) to the WDCR register.
WDMOD
WDCR
•
← 0 − − X X − − 0
← 1 0 1 1 0 0 0 1
Clears the WDTE bit to 0.
Writes the disable code (B1H) to the WDCR.
Enabling the WDT
The WDT can be enabled only by setting the WDTE bit in the WDMOD to 1.
•
Clearing the WDT counter
Writing the special clear-count code (4EH) to the WDCR resets the binary
counter to 0. The counting process begins again.
WDCR
← 0 1 0 0 1 1 1 0
Writes the clear-count code (4EH) to the WDCR.
Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please
refer to setting example.)
Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once.
91CW28-208
2006-03-24
TMP91CW28
Watchdog Timer Mode Register
WDMOD
(0300H)
7
6
Bit symbol
WDTE
WDTP1
Read/Write
R/W
Reset value
Function
1
5
4
3
2
WDTP0
1
I2WDT
R/W
0
Time-out period
0: Disable
01: 2 /fSYS
1: Enable
10: 2 /fSYS
21
11: 2 /fSYS
0
R/W
0
IDLE2
15
0: OFF
17
1: ON
00: 2 /fSYS
−
RESCR
R/W
0
WDT
enable
0
System
reset by
WDT
0
Must be
written as
“0”.
1: Reset
19
System reset
0
Don’t care
1
Internally routes the WDT time-out
signal to the system reset
Operation in IDLE2 mode
0
OFF
1
ON
at fc = 10 MHz
Time-out period
Watchdog Timer Time-out Period
Clock Gear
Value
WDMOD.WDTP[1:0]
SYSCR1.GEAR
[2:0]
00
01
10
11
000 (fc)
6.55 ms
26.21 ms
104.86 ms
419.43 ms
001 (fc/2)
13.11 ms
52.43 ms
209.72 ms
838.86 ms
010 (fc/4)
26.21 ms
104.86 ms
419.43 ms
1677.72 ms
011 (fc/8)
52.43 ms
209.73 ms
838.86 ms
3355.44 ms
100 (fc/16)
104.86 ms
419.43 ms
1677.72 ms
6710.89 ms
WDT enable
0
Disable
1
Enable
Figure 3.12.4 Watchdog Timer Mode Register (WDMOD)
91CW28-209
2006-03-24
TMP91CW28
Watchdog Timer Control Register
7
WDCR
(0301H)
5
4
3
Bit symbol
−
Read/Write
W
Reset value
−
Function
Read-modifywrite
operation is
not
supported.
6
2
1
0
B1H: WDT disable code
4EH: WDT clear-count code
Special code
B1H
4EH
Other values
WDT disable code
WDT clear-count code
Don’t care
Figure 3.12.5 Watchdog Timer Control Register (WDCR)
91CW28-210
2006-03-24
TMP91CW28
3.12.3
Operation
The watchdog timer is a kind of timer that generates an interrupt request if it times out.
The WDT allows the user to program the time-out period in the WDTP[1:0] field in the
WDMOD register. While enabled, the software can reset the counter to 0 at any time by
writing a special clear-count code. If the software is unable to reset the counter before it
reaches the time-out count, the WDT generates the INTWD interrupt. In response to the
interrupt, the CPU jumps to a system recovery routine to regain control of the system.
The WDT begins counting immediately after reset.
When the TMP91CW28 goes into IDLE1 or STOP mode, the WDT counter is reset to 0
automatically and stops counting. The WDT continues counting while an off-chip
peripheral has mastership of the bus (e.g., BUSAK = 0).
In IDLE2 mode, the I2WDT bit in the WDMOD determines whether or not to disable the
WDT. The I2WDT bit can be programmed before putting the TMP91CW28 in IDLE2 mode.
Examples:
1. Clearing the WDT binary counter
WDCR
← 0 1 0 0 1 1 1 0
Writes the clear-count code (4EH) to the WDCR.
2. Programming the time-out interval to 217/fSYS
WDMOD
← 1 0 1 X X − − 0
3. Disabling the watchdog timer
WDMOD
WDCR
← 0 − − X X − − 0
← 1 0 1 1 0 0 0 1
Clears the WDTE bit to 0.
Writes the disable code (B1H) to the WDCR.
91CW28-211
2006-03-24
TMP91CW28
3.13 Key Wakeup Interrupt
In addition to the INT0 to INT4 interrupt source pins, the TMP91CW28 has eight interrupt
channels that enable the pressing of a key to terminate a HALT mode, called key wakeup
interrupts (KWI).
Figure 3.13.1 shows a block diagram of the KWI circuit.
3.13.1
Block Diagram
Internal data bus
Internal data bus
Enable register (KWIEN)
KWI7EN to KWI0EN
Edge select register (KWICR)
KWI7EDGE to KWI0EDGE
INT4
Select rising or falling edge
KWI7 (P57)
Select rising or falling edge
KWI6 (P56)
Select rising or falling edge
KWI5 (P55)
Select rising or falling edge
KWI4 (P54)
Select rising or falling edge
KWI3 (P53)
Select rising or falling edge
KWI2 (P52)
Select rising or falling edge
KWI1 (P51)
Select rising or falling edge
KWI0 (P50)
Figure 3.13.1 KWI Block Diagram
91CW28-212
2006-03-24
TMP91CW28
3.13.2
SFR Descriptions
Key Wakeup Enable Register
KWIEN
(03A0H)
Bit symbol
7
6
5
4
3
2
1
0
KWI7EN
KWI6EN
KWI5EN
KWI4EN
KWI3EN
KWI2EN
KWI1EN
KWI0EN
0
0
0
0
Read/Write
W
Reset value
Function
0
0
0
0
KWI7
interrupt
input
KWI6
interrupt
input
KWI5
interrupt
input
KWI4
interrupt
input
KWI3
interrupt
input
KWI2
interrupt
input
KWI1
interrupt
input
KWI0
interrupt
input
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
Key Wakeup Control Register
KWICR
(03A1H)
Bit symbol
7
6
5
4
3
2
1
0
KWI7EDGE
KWI6EDGE
KWI5EDGE
KWI4EDGE
KWI3EDGE
KWI2EDGE
KWI1EDGE
KWI0EDGE
0
0
0
0
0
0
0
0
Read/Write
W
Reset Value
Function
KWI7 edge
polarity
KWI6 edge
polarity
KWI5 edge
polarity
KWI4 edge
polarity
KWI3 edge
polarity
KWI2 edge
polarity
KWI1 edge
polarity
KWI0 edge
polarity
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
Note: The KWIEN and KWICR do not support read-modify-write operation.
Figure 3.13.2 Key-pressed Wakeup Registers
3.13.3
Control
The P50 to P57 pins function as KWI0 to KWI7 when the corresponding bits
(KWIEN[7:0]) in the KWIEN register are set. The MCU accepts KWI0 to KWI7 inputs as
INT4. The KWI0 to KWI7 pins can be used as external interrupt sources by setting an
interrupt priority level in the I4M[2:0] bits of the INTE34 register.
Example: To detect a falling edge on key wakeup channel 0 to generate an interrupt,
configure registers in the following sequence:
KWICR
←
−
−
−
−
−
−
−
1
Selects falling-edge detection for key wakeup
channel 0.
KWIEN
←
−
−
−
−
−
−
−
1
Enables key wakeup channel 0.
INTE34
←
X
1
0
0
X
−
−
−
Enables INT4 and sets its priority level to 4.
X: Don’t care, −: No change
91CW28-213
2006-03-24
TMP91CW28
3.14 WAKE Pin
The TMP91CW28 can drive out a monitor signal immediately after it recovers from STOP
mode in response to an external interrupt signal. The monitor signal is driven out through a
dedicated N-ch open-drain output pin. External devices can know, in real time, when the
TMP91CW28 enters or exits STOP mode.
This function is useful for a system that requires stop control for peripheral devices connected
to the microcontroller.
VDD
WAKE pin
RESET (Internal reset signal)
(STOP mode trigger signal)
STOP
Figure 3.14.1 WAKE Pin
3.14.1
Basic Operation
While the TMP91CW28 is operating in IDLE1 or IDLE2 mode, logic 0 is driven out from
the WAKE pin. The pin is put into high-impedance state when the TMP91CW28 enters
STOP mode. It is driven low when an external interrupt signal terminates STOP mode. The
WAKE pin is, therefore, low during the warm-up period. It is placed in high-impedance
state while a system reset (including a reset caused by the watchdog timer) is being
performed.
Table 3.14.1 shows the states of the WAKE pin under different conditions. Figure 3.14.2
shows the WAKE signal output timing.
Table 3.14.1 WAKE Pin State
MCU State
WAKE Pin State
During a reset
High impedance
Operating (in IDLE1 or IDLE2 mode)
Low
In STOP mode
High impedance
During a warm up
Low
External reset pin
RESET
Enter
Exit
Warm up
STOP
WAKE pin
High-Z
Low
High-Z
Low
Figure 3.14.2 WAKE Signal Output Timing
91CW28-214
2006-03-24
TMP91CW28
3.15 BCD Adder/Subtractor
The TMP91CW28 has a BCD adder/subtractor that implements operation specific to the
calculation of time data for a CD-ROM system. It can handle six-digit decimal data, consisting
of two minute digits (0 to 99), two second digits (0 to 59) and two frame digits (0 to 74). A
six-digit operand can be added to or subtracted from another six-digit operand.
As a result of calculation, the adder/subtractor stores the six-digit operation result as well
as flags indicating whether there is a carry (CY) or a borrow (BR) produced from the minute
digits.
(Input) Operand A: Minutes (0 to 99) Seconds (0 to 59) Frames (0 to 74)
(Input) Operand B: ± Minutes (0 to 99) Seconds (0 to 59) Frames (0 to 74)
(Output)
Minutes (0 to 99) Seconds (0 to 59) Frames (0 to 74) CY/BR
Operation result:
3.15.1
Block Diagram
BCD Adder/Subtractor
Control Block (bcdctrl)
Calculation Block (bcdcal)
Mode circuit (Mode)
Carry
Borrow
PU sensor
position
information
(Time
information)
Control circuit (Ctrl)
Minutes A
State counter (Count)
±
Minutes B
Registers (bcdreg)
Operand A
Control register
Minutes A
Add/subtract select bit
Operation start bit
CPU
Seconds A
Borrow
Carry
Seconds A
Operation completion flag
±
BR
Seconds B
Frames A
CY
Operand B
Result register
Minutes B
Minutes
Borrow
Carry
Frames A
Memory
address data
±
Frames B
Seconds B
Seconds
Frames B
Frames
Figure 3.15.1 Block Diagram
91CW28-215
2006-03-24
TMP91CW28
3.15.2
SFR Descriptions
Minute Operand Register A
BCDMINA
03B0H
Read-modifywrite
operation is
not
supported.
Bit symbol
7
6
5
4
3
2
1
0
MINA7
MINA6
MINA5
MINA4
MINA3
MINA2
MINA1
MINA0
0
0
0
0
0
0
0
0
3
2
1
0
SECA3
SECA2
SECA1
SECA0
0
0
0
0
Read/Write
Reset value
W
Function
BCD operand A
Second Operand Register A
BCDSECA
03B1H
Read-modifywrite
operation is
not
supported.
Bit symbol
7
6
5
4
SECA7
SECA6
SECA5
SECA4
Read/Write
Reset value
W
0
0
0
0
Function
BCD operand A
Frame Operand Register A
BCDFRAA
03B2H
Read-modifywrite
operation is
not
supported.
Bit symbol
7
6
5
4
3
2
1
0
FRAA7
FRAA6
FRAA5
FRAA4
FRAA3
FRAA2
FRAA1
FRAA0
0
0
0
0
Read/Write
Reset value
Function
W
0
0
0
0
BCD operand A
Figure 3.15.2 BCD Registers (1/4)
91CW28-216
2006-03-24
TMP91CW28
Minute Operand Register B
BCDMINB
03B4H
Bit symbol
Read-modifywrite
operation is
not
supported.
Reset value
7
6
5
4
3
2
1
0
MINB7
MINB6
MINB5
MINB4
MINB3
MINB2
MINB1
MINB0
0
0
0
0
0
0
0
0
Read/Write
W
Function
BCD operand B
Second Operand Register B
BCDSECB
03B5H
Bit symbol
Read-modifywrite
operation is
not
supported.
Reset value
7
6
5
4
3
2
1
0
SECB7
SECB6
SECB5
SECB4
SECB3
SECB2
SECB1
SECB0
0
0
0
0
0
0
0
0
Read/Write
W
Function
BCD operand B
Frame Operand Register B
BCDFRAB
03B6H
Read-modifywrite
operation is
not
supported.
Bit symbol
7
6
5
4
3
2
1
0
FRAB7
FRAB6
FRAB5
FRAB4
FRAB3
FRAB2
FRAB1
FRAB0
0
0
0
0
0
0
0
0
Read/Write
Reset value
Function
W
BCD operand B
Figure 3.15.3 BCD Registers (2/4)
91CW28-217
2006-03-24
TMP91CW28
Minute Result Register
BCDMINR
03B8H
Bit symbol
7
6
5
4
3
2
1
0
MINR7
MINR6
MINR5
MINR4
MINR3
MINR2
MINR1
MINR0
0
0
0
0
0
0
0
0
Read/Write
Reset value
R
Function
BCD operation result
Second Result Register
BCDSECR
03B9H
Bit symbol
7
6
5
4
3
2
1
0
SECR7
SECR6
SECR5
SECR4
SECR3
SECR2
SECR1
SECR0
0
0
0
0
0
0
0
0
Read/Write
Reset value
R
Function
BCD operation result
Frame Result Register
BCDFRAR
03BAH
Bit symbol
7
6
5
4
3
2
1
0
FRAR7
FRAR6
FRAR5
FRAR4
FRAR3
FRAR2
FRAR1
FRAR0
0
0
0
0
0
0
0
0
Read/Write
Reset value
Function
R
BCD operation result
Figure 3.15.4 BCD Registers (3/4)
91CW28-218
2006-03-24
TMP91CW28
BCD Control Register
BCDCR
(03BCH)
Bit symbol
7
6
5
ENDFLAG
CY
BR
Read/Write
Reset value
Function
4
3
R
0
0
Operation
completion
flag
Minute
carry flag
0: During
operation
1: Completed
0
0: Carry not
produced
1: Carry
produced
Minute
borrow
flag
2
1
0
−
CALSEL
START
R/W
R/W
R/W
0
0
0
Must be
written
as “0”.
Add/subtract
select
Operation
start
0: Add
1: Subtract
0: Borrow not
produced
1: Borrow
produced
0: Don’t care
1: Starts
operation.
Operation start
0
Don’t care
1
Starts operation
Add/subtract select
0
Add
1
Subtract
Minute borrow flag
0
Borrow not produced
1
Borrow produced
Minute carry flag
0
Carry not produced
1
Carry produced
Operation completion flag
0
Before or during operation
1
Completed
Note: Bits3 and 4 of the BCDCR are read as undefined.
Figure 3.15.5 BCD Registers (4/4)
91CW28-219
2006-03-24
TMP91CW28
3.15.3
Operation
(1) Operand A
Operand A, to/from which operand B is added/subtracted, is stored in the BCDMINA,
BCDSECA and BCDFRAA registers.
The operand must consist of decimal digits (0 to 9). If it contains a hexadecimal digit
(A to F), operation is performed in decimal correction format, so that the result will not
be an expected hexadecimal value.
The contents of the BCDMINA, BCDSECA, and BCDFRAA cannot be modified
during operation. The operation completion flag must be checked to determine that
operation has completed, before the registers can be modified.
(2) Operand B
Operand B, which is added to or subtracted from operand A, is stored in the
BCDMINB, BCDSECB and BCDFRAB registers.
The operand must consist of decimal digits (0 to 9). If it contains a hexadecimal digit
(A to F), operation is performed in decimal correction format, so that the result will not
be an expected hexadecimal value.
The contents of the BCDMINB, BCDSECB, and BCDFRAB cannot be modified
during operation. The operation completion flag must be checked to determine that
operation has completed, before the registers can be modified.
(3) Operation result
The frame, second and minute digits of the result of addition or subtraction are
sequentially stored in the BCDFRAR, BCDSECR and BCDMINR registers,
respectively, in that order.
(4) Operation start
Writing 1 to the START bit in the BCDCR starts operation. Addition or subtraction is
performed sequentially for frames, seconds and minutes in the stated order. The
START bit is cleared upon the completion of operation.
The START bit cannot be cleared during operation.
(5) Add/subtract select
The CALSEL bit in the BCDCR specifies whether addition or subtraction is
performed. Writing 0 to the bit selects addition and writing 1 to the bit selects
subtraction.
The CALSEL bit cannot be modified during operation.
(6) BR (Borrow) flag
The BR flag bit in the BCDCR indicates whether a borrow is produced as a result of
subtraction on minute digits. If the flag is cleared, that means a borrow is not produced.
If the flag is set, that means a borrow is produced.
The BR flag is read as undefined when addition is performed.
91CW28-220
2006-03-24
TMP91CW28
(7) CY (Carry) flag
The CY flag bit in the BCDCR indicates whether a carry is produced as a result of
addition on minute digits. If the flag is cleared, that means a carry is not produced. If
the flag is set, that means a carry is produced.
The CY flag is read as undefined when subtraction is performed.
(8) Operation completion flag
The ENDFLAG bit in the BCDCR indicates whether operation has completed.
If the flag is cleared, that means operation is still in progress or not yet started. If the
flag is set, that means operation has completed.
The ENDFLAG bit is set to 1 once the operation result for minutes has been stored in
the BCDMINR. Reading any of the BCDMINR, BCDSECR and BCDFRAR causes the
ENDFLAG to be cleared.
(9) Operation completion interrupt
When the BCDCR.ENDFLAG bit is set to 1, an INTBCD interrupt occurs.
91CW28-221
2006-03-24
TMP91CW28
3.15.4
Example
This section shows an example of operation using the BCD adder/subtractor.
1.
Read the START bit of the BCDCR register to determine that no operation is in
progress.
2.
Set six-digit operand A (Minutes, seconds and frames) and six-digit operand B
(Minutes, seconds and frames) in the appropriate registers.
3.
Select addition or subtraction by clearing or setting the BCDCR.CALSEL bit.
4.
Write 1 to the BCDCR.START bit to start operation.
5.
Determine that operation has completed by reading 1 from the BCDCR.ENDFLAG bit
or detecting the occurrence of an INTBCD interrupt.
6.
Read the six-digit operation result (Minutes, seconds and frames) from the BCDMINR,
BCDSECR and BCDFRAR registers as well as the CY and BR flags in the BCDCR.
(BR is read as 0 after addition and CY is read as 0 after subtraction.)
The operand must consist of decimal digits (0 to 9). If it contains a hexadecimal digit (A to
F), operation is performed in decimal correction format, so that the result will not be an
expected hexadecimal value.
(1) Addition
Example: To add 99 minutes, 54 seconds, 32 frames to 1 minute, 5 seconds, 42 frames
and generate an INTBCD interrupt, configure registers as follows:
7
6
5
4
3
2
1
0
A
←
BCDMINA
←
1
0
0
1
1
0
0
0
Stores 98 in BCDMINA.
BCDSECA
←
0
1
0
1
0
1
0
0
Stores 54 in BCDSECA.
BCDFRAA
←
0
0
1
1
0
0
1
0
Stores 32 in BCDFRAA.
BCDMINB
←
0
0
0
0
0
0
0
1
Stores 01 in BCDMINB.
BCDSECB
←
0
0
0
0
0
1
0
1
Stores 05 in BCDSECB.
BCDFRAB
←
0
1
0
0
0
0
1
0
Stores 42 in BCDFRAB.
INTEBCD
←
X
X
X
X
X
1
0
0
Enables INTBCD and sets its priority level to 4.
BCDCR
←
X
X
X
X
X
X
0
1
Selects addition and starts operation.
BCDCR
Transfers the contents of BCDCR to 8-bit general-purpose
register A to determine that no operation is in progress.
Example of interrupt routine processing
A
←
BCDCR
Transfers the contents of BCDCR to 8-bit general-purpose
register A to determine that no operation is in progress.
B
←
BCDMINR
Reads the result of operation for minutes.
C
←
BCDSECR
Reads the result of operation for seconds.
D
←
BCDFRAR
Reads the result of operation for frames.
E
←
BCDCR
Reads the contents of BCDCR to 8-bit general-purpose
register E to determine whether a carry has been
produced.
X: Don’t care, −: No change
91CW28-222
2006-03-24
TMP91CW28
3.16 Program Patch Logic
The TMP91CW28 has a program patch logic, which enables the user to fix the program code
in the on-chip ROM without generating a new mask. Patch program must be read into on-chip
RAM from external memory during the startup routine.
Up to six two-byte sequences, or banks (Twelve bytes in total) can be replaced with patch code.
More significant code correction can be performed by replacing program code with single-byte
instruction code which generates a software interrupt (SWI) to make a branch to a specified
location in the on-chip RAM area.
The program patch logic only compares addresses in the on-chip ROM area; it cannot fix the
program code in the on-chip peripheral, on-chip RAM and external ROM areas.
Each of six banks is independently programmable, and functionally equivalent. In the
following sections, any references to bank0 also apply to other banks.
3.16.1
Block Diagram
ROMRD
CPU
ROMRD
Address bus
ROM
Data bus
Match
signal
Address compare registers (Bank2)
(ROMCMP20 to ROMCMP22)
Address compare registers (Bank3)
(ROMCMP30 to ROMCMP32)
Output
enable
Output control block
Address compare registers (Bank1)
(ROMCMP10 to ROMCMP12)
Address compare block
Address compare registers (Bank0)
(ROMCMP00 to ROMCMP02)
Address substitution registers
(Bank0)
(ROMSUB0L/H)
Address substitution registers
(Bank1)
(ROMSUB1L/H)
Address substitution registers
(Bank2)
(ROMSUB2L/H)
Address substitution registers
(Bank3)
(ROMSUB3L/H)
Address compare registers (Bank4)
(ROMCMP40 to ROMCMP42)
Address substitution registers
(Bank4)
(ROMSUB4L/H)
Address compare registers (Bank5)
(ROMCMP50 to ROMCMP52)
Address substitution registers
(Bank5)
(ROMSUB5L/H)
Figure 3.16.1 Program Patch Logic Diagram
91CW28-223
2006-03-24
TMP91CW28
3.16.2
SFR Descriptions
The program patch logic consists of six banks (0 to 5). Each bank is provided with three
bytes of address compare registers (ROMCMPx0 to ROMCMPx2) and two bytes of address
substitution registers (ROMSUBxL and ROMSUBxH).
Bank0 Address Compare Register 0
ROMCMP00
(0400H)
Bit symbol
7
6
5
4
3
2
1
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
Read/Write
Reset value
0
W
0
Function
Target ROM address (Lower 7 bits)
Bank0 Address Compare Register 1
ROMCMP01
(0401H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Middle 8 bits)
Bank0 Address Compare Register 2
ROMCMP02
(0402H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Upper 8 bits)
Note 1:
The ROMCMP00, ROMCMP01, and ROMCMP02 registers do not support read-modify-write operation.
Note 2:
Bit0 of the ROMCMP00 is read as undefined.
Figure 3.16.2 Address Compare Registers (Bank0)
91CW28-224
2006-03-24
TMP91CW28
Bank1 Address Compare Register 0
ROMCMP10
(0408H)
Bit symbol
7
6
5
4
3
2
1
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
Read/Write
Reset value
0
W
0
Function
Target ROM address (Lower 7 bits)
Bank1 Address Compare Register 1
ROMCMP11
(0409H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Middle 8 bits)
Bank1 Address Compare Register 2
ROMCMP12
(040AH)
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Upper 8 bits)
Note 1:
The ROMCMP10, ROMCMP11, and ROMCMP12 registers do not support read-modify-write operation.
Note 2:
Bit0 of the ROMCMP10 is read as undefined.
Figure 3.16.3 Address Compare Registers (Bank1)
91CW28-225
2006-03-24
TMP91CW28
Bank2 Address Compare Register 0
ROMCMP20
(0410H)
Bit symbol
7
6
5
4
3
2
1
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
Read/Write
Reset value
0
W
0
Function
Target ROM address (Lower 7 bits)
Bank2 Address Compare Register 1
ROMCMP21
(0411H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Middle 8 bits)
Bank2 Address Compare Register 2
ROMCMP22
(0412H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Upper 8 bits)
Note 1:
The ROMCMP20, ROMCMP21, and ROMCMP22 registers do not support read-modify-write operation.
Note 2:
Bit0 of the ROMCMP20 is read as undefined.
Figure 3.16.4 Address Compare Registers (Bank2)
91CW28-226
2006-03-24
TMP91CW28
Bank3 Address Compare Register 0
ROMCMP30
(0418H)
Bit symbol
7
6
5
4
3
2
1
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
Read/Write
Reset value
0
W
0
Function
Target ROM address (Lower 7 bits)
Bank3 Address Compare Register 1
ROMCMP31
(0419H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Middle 8 bits)
Bank3 Address Compare Register 2
ROMCMP32
(041AH)
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Upper 8 bits)
Note 1:
The ROMCMP30, ROMCMP31, and ROMCMP32 registers do not support read-modify-write operation.
Note 2:
Bit0 of the ROMCMP30 is read as undefined.
Figure 3.16.5 Address Compare Registers (Bank3)
91CW28-227
2006-03-24
TMP91CW28
Bank4 Address Compare Register 0
ROMCMP40
(0420H)
Bit symbol
7
6
5
4
3
2
1
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
Read/Write
Reset value
0
W
0
Function
Target ROM address (Lower 7 bits)
Bank4 Address Compare Register 1
ROMCMP41
(0421H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Middle 8 bits)
Bank4 Address Compare Register 2
ROMCMP42
(0422H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Upper 8 bits)
Note 1:
The ROMCMP40, ROMCMP41, and ROMCMP42 registers do not support read-modify-write operation.
Note 2:
Bit0 of the ROMCMP40 is read as undefined.
Figure 3.16.6 Address Compare Registers (Bank4)
91CW28-228
2006-03-24
TMP91CW28
Bank5 Address Compare Register 0
ROMCMP50
(0428H)
Bit symbol
7
6
5
4
3
2
1
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
Read/Write
Reset value
0
W
0
Function
Target ROM address (Lower 7 bits)
Bank5 Address Compare Register 1
ROMCMP51
(0429H)
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Middle 8 bits)
Bank5 Address Compare Register 2
ROMCMP52
(042AH)
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Target ROM address (Upper 8 bits)
Note 1:
The ROMCMP50, ROMCMP51, and ROMCMP52 registers do not support read-modify-write operation.
Note 2:
Bit0 of the ROMCMP50 is read as undefined.
Figure 3.16.7 Address Compare Registers (Bank5)
91CW28-229
2006-03-24
TMP91CW28
Bank0 Address Substitution Register L
ROMSUB0L Bit symbol
(0404H)
Read/Write
Reset value
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
0
0
0
0
W
Function
Patch code (Lower 8 bits)
Bank0 Address Substitution Register H
ROMSUB0H Bit symbol
(0405H)
Read/Write
Reset value
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
0
0
0
0
W
Function
Patch code (Upper 8 bits)
Bank1 Address Substitution Register L
ROMSUB1L Bit symbol
(040CH)
Read/Write
Reset value
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
0
0
0
0
3
2
1
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
W
Function
Patch code (Lower 8 bits)
Bank1 Address Substitution Register H
ROMSUB1H Bit symbol
(040DH)
Read/Write
Reset value
7
6
5
4
ROMS15
ROMS14
ROMS13
ROMS12
W
0
0
0
0
Function
Patch code (Upper 8 bits)
Note:
The ROMSUB0L, ROMSUB0H, ROMSUB1L, and ROMSUB1H registers do not support read-modify-write
operation.
Figure 3.16.8 Address Substitution Registers (Banks 0 and 1)
91CW28-230
2006-03-24
TMP91CW28
Bank2 Address Substitution Register L
ROMSUB2L Bit symbol
(0414H)
Read/Write
Reset value
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
0
0
0
0
W
Function
Patch code (Lower 8 bits)
Bank2 Address Substitution Register H
ROMSUB2H
(0415H)
Bit symbol
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
0
0
0
0
Read/Write
Reset value
W
Function
Patch code (Upper 8 bits)
Bank3 Address Substitution Register L
ROMSUB3L Bit symbol
(041CH)
Read/Write
Reset value
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
0
0
0
0
3
2
1
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
W
Function
Patch code (Lower 8 bits)
Bank3 Address Substitution Register H
ROMSUB3H Bit symbol
(041DH)
Read/Write
Reset value
7
6
5
4
ROMS15
ROMS14
ROMS13
ROMS12
W
0
0
0
0
Function
Patch code (Upper 8 bits)
Note:
The ROMSUB2L, ROMSUB2H, ROMSUB3L, and ROMSUB3H registers do not support read-modify-write
operation.
Figure 3.16.9 Address Substitution Registers (Banks 2 and 3)
91CW28-231
2006-03-24
TMP91CW28
Bank4 Address Substitution Register L
ROMSUB4L Bit symbol
(0424H)
Read/Write
Reset value
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
0
0
0
0
W
Function
Patch code (Lower 8 bits)
Bank4 Address Substitution Register H
ROMSUB4H Bit symbol
(0425H)
Read/Write
Reset value
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
0
0
0
0
W
Function
Patch code (Upper 8 bits)
Bank5 Address Substitution Register L
ROMSUB5L Bit symbol
(042CH)
Read/Write
Reset value
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
0
0
0
0
3
2
1
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
W
Function
Patch code (Lower 8 bits)
Bank5 Address Substitution Register H
ROMSUB5H Bit symbol
(042DH)
Read/Write
Reset value
7
6
5
4
ROMS15
ROMS14
ROMS13
ROMS12
W
0
0
0
0
Function
Patch code (Upper 8 bits)
Note:
The ROMSUB4L, ROMSUB4H, ROMSUB5L, and ROMSUB5H registers do not support read-modify-write
operation.
Figure 3.16.10 Address Substitution Registers (Banks 4 and 5)
91CW28-232
2006-03-24
TMP91CW28
3.16.3
Operation
(1) Replacing data
Two consecutive bytes of data can be replaced for each bank. A two-byte sequence to
be replaced must start at an even address. If only a single byte at an even or odd
address need be replaced, set the current masked ROM data in the other byte.
Correction procedure:
Load the address compare registers (ROMCMP00 to ROMCMP02) with the target
address where ROM data need be replaced. Store 2-byte patch code in the ROMSUBL
and ROMSUBH registers.
When the CPU address matches the value stored in the ROMCMP00 to ROMCMP02
registers, the program patch logic disables RD output to the masked ROM and drives
out the code stored in the ROMSUBL and ROMSUBH to the internal bus. The CPU
thus fetches the patch code.
The following shows some examples:
Examples:
a. Replacing 00H at address FF1230H with AAH
7
6
5
4
3
2
1
ROMCMP00
←
0
0
1
1
0
0
0
0
Stores 30 in address compare register 0 for bank0.
ROMCMP01
←
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank0.
ROMCMP02
←
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank0.
ROMSUB0L
←
1
0
1
0
1
0
1
0
Store AA in address substitution register low for bank0.
ROMSUB0H
←
0
0
0
1
0
0
0
1
Store 11 in address substitution register high for bank0.
000000H
0
On-chip
peripheral
001000H
On-chip RAM
External area
FF0000H
On-chip ROM
a
FF1230H
00H
Replace with AAH.
FF1231H
11H
Replace with 11H
(Same as current
value).
Vector table
FFFFFFH
Figure 3.16.11 Example Patch Code Implementation
91CW28-233
2006-03-24
TMP91CW28
b. Replacing 33H at address FF1233H with BBH
7
6
5
4
3
2
1
0
ROMCMP00
←
0
0
1
1
0
0
1
0
Stores 32 in address compare register 0 for bank0.
ROMCMP01
←
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank0.
ROMCMP02
←
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank0.
ROMSUB0L
←
0
0
1
0
0
0
1
0
Store 22 in address substitution register low for bank0.
ROMSUB0H
←
1
0
1
1
1
0
1
1
Store BB in address substitution register high for bank0.
000000H
On-chip
peripheral
001000H
On-chip RAM
External area
FF0000H
On-chip ROM
b
FF1232H
22H
Replace with 22H
(Same as current
value).
FF1233H
33H
Replace with BBH.
Vector table
FFFFFFH
Figure 3.16.12 Example Patch Code Implementation
c.
Replacing 44H at address FF1234H with CCH and 55H at address FF1235H with
DDH
7
6
5
4
3
2
1
0
ROMCMP00
←
0
0
1
1
0
1
0
0
Stores 34 in address compare register 0 for bank0.
ROMCMP01
←
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank0.
ROMCMP02
←
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank0.
ROMSUB0L
←
1
1
0
0
1
1
0
0
Store CC in address substitution register low for bank0.
ROMSUB0H
←
1
1
0
1
1
1
0
1
Store DD in address substitution register high for bank0.
000000H
On-chip
peripheral
001000H
On-chip RAM
External area
FF0000H
On-chip ROM
c
FF1234H
44H
Replace with CCH.
FF1235H
55H
Replace with DDH.
Vector table
FFFFFFH
Figure 3.16.13 Example Patch Code Implementation
91CW28-234
2006-03-24
TMP91CW28
d.
Replacing 77H at address FF1237H with EEH and 88H at address FF1238H with
FFH (Requiring two banks)
7
6
5
4
3
2
1
0
ROMCMP00
←
0
0
1
1
0
1
1
0
Stores 36 in address compare register 0 for bank0.
ROMCMP01
←
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank0.
ROMCMP02
←
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank0.
ROMSUB0L
←
0
1
1
0
0
1
1
0
Store 66 in address substitution register low for bank0.
ROMSUB0H
←
1
1
1
0
1
1
1
0
Store EE in address substitution register high for bank0.
ROMCMP10
←
0
0
1
1
1
0
0
0
Stores 38 in address compare register 0 for bank1.
ROMCMP11
←
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank1.
ROMCMP12
←
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank1.
ROMSUB1L
←
1
1
1
1
1
1
1
1
Store FF in address substitution register low for bank1.
ROMSUB1H
←
1
0
0
1
1
0
0
1
Store 99 in address substitution register high for bank1.
000000H
On-chip
peripheral
001000H
On-chip RAM
External area
FF0000H
On-chip ROM
d
FF1236H
FF1237H
FF1238H
FF1239H
66H
77H
88H
99H
Replace with 66H
(Same as current
value).
Replace with EEH.
Replace with FFH.
Replace with 99H.
Vector table
FFFFFFH
Figure 3.16.14 Example Patch Code Implementation
91CW28-235
2006-03-24
TMP91CW28
(2) Using an interrupt to cause a branch
A wider range of program code can also be fixed using a software interrupt (SWI).
With a patch code loaded into on-chip RAM, the program patch logic can be used to
replace program code at a specified address with a single-byte SWI instruction, which
causes a branch to the patch program.
Note that this method can only be used if the original masked ROM has been
developed with on-chip RAM addresses specified as SWI vector addresses.
Correction procedure:
Load the address compare registers (ROMCMP00 to ROMCMP02) with the start
address of the program code that is to be fixed. If it is an even address, store an SWI
instruction code (e.g., SWI: F9H) in the ROMSUBL. If the start address is an odd
address, store an SWI instruction code in the ROMSUBH and the current ROM data at
the preceding even address in the ROMSUBL.
When the CPU address matches the value stored in the ROMCMP00 to ROMCMP02
registers, the program patch logic disables RD output to the masked ROM and drives
out the SWI instruction code to the internal bus. Upon fetching the SWI code, the CPU
makes a branch to the internal RAM area to execute the preloaded code.
At the end of the patch program executed from the internal RAM, the CPU directly
rewrites the saved PC value so that it points to the address following the patch code,
and then executes a RETI.
The following shows an example:
Example: Fixing a program within the range from FF5000H to FF507FH
Before developing the original masked ROM, set the SWI1 vector reference address
to 001500H (on-chip RAM area).
Use the startup routine to load the patch code to on-chip RAM (001500H to
0015EFH). Store the start address (FF5000H) of the ROM area to be fixed in the
ROMCMP00 to ROMCMP02. Store the SWI1 instruction code (F9H) in the
ROMSUB0L and the current data at FF5001H (AAH) in the ROMSUB0H. When the
CPU address matches the value stored in ROMCMP00 to ROMCMP02, the program
patch logic replaces the ROM-based code at FF5000H with F9H. The CPU then
executes the SWI1 instruction, which causes a branch to 001500H in the on-chip RAM
area. After executing the patch program the CPU finally rewrites the saved PC value
to FF5080H and executes a RETI.
91CW28-236
2006-03-24
TMP91CW28
000000H
On-chip
peripheral
001000H
Program body
On-chip RAM
001500H
0015EFH
001500H
:
:
Patch
program
Rewrite stack
RETI
0015EFH
FF0000H
On-chip ROM
FF5000H
FF5001H
Defective
area
FF507FH
FF5080H
FFFF00H
FFFF04H
:
FFFF07H
55H
AAH
:
:
:
Return from INT
External area
Branch caused by SW1
001800H
Replace the start address with F9H
(SWI1 instruction code).
Replace with AAH
(Same as current value).
Vector table
001500H
SW1 vector
Figure 3.16.15 Example ROM Correction
91CW28-237
2006-03-24
TMP91CW28
4.
4.1
Electrical Characteristics
Maximum Ratings
Parameter
Symbol
Rating
Supply voltage
Vcc
−0.5 to 3.0
Input voltage
VIN
−0.5 to Vcc + 0.5
Output current (Per pin)
IOL
2
Output current (Per pin)
IOH
−2
Output current (Total)
ΣIOL
80
Output current (Total)
ΣIOH
−80
Power dissipation (Ta = 85°C)
PD
600
Soldering temperature (10 s)
TSOLDER
260
Storage temperature
TSTG
−55 to 125
Operating temperature
TOPR
−20 to 70
Unit
V
mA
mW
°C
Note: Maximum ratings are limiting values of operating and environmental conditions which
should not be exceeded under the worst possible conditions. The equipment manufacturer
should design so that no maximum rating value is exceeded. Exposure to conditions
beyond those listed above may cause permanent damage to the device or affect device
reliability, which could increase potential risks of personal injury due to IC blowup and/or
burning.
Solderability of lead free products
Test
Test condition
Note
(1)
Use of Sn-37Pb solder Bath
Pass:
Solder bath temperature =230°C, Dipping time = 5 seconds
solderability rate until forming ≥ 95%
parameter
Solderability
The number of times = one, Use of R-type flux
(2)
Use of Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature =245°C, Dipping time = 5 seconds
The number of times = one, Use of R-type flux (use of lead free)
91CW28-238
2006-03-24
TMP91CW28
4.2
DC Electrical Characteristics (1/2)
Parameter
High-level input voltage
Low-level input voltage
Power supply voltage
AVcc = DVcc
AVss = DVss = 0 V
Symbol
VCC
Condition
fc = 4 to 10 MHz
Min
1.8
Typ.
(Note)
Max
2.6
V
P00 to P17 (AD0 to AD15)
VIL
VCC = 1.8 to 2.6 V
0.2 Vcc
P20 to P37
VIL1
VCC = 1.8 to 2.6 V
0.2 Vcc
VIL2
VCC = 1.8 to 2.6 V
AM0 to AM1
VIL3
VCC = 1.8 to 2.6 V
0.3
X1
VIL4
VCC = 1.8 to 2.6 V
0.1 Vcc
P00 to P17 (AD0 to AD15)
VIH
VCC = 1.8 to 2.6 V
0.7 Vcc
P20 to P37
VIH1
VCC = 1.8 to 2.6 V
0.8 Vcc
VIH2
VCC = 1.8 to 2.6 V
0.85 Vcc
AM0 to AM1
VIH3
VCC = 1.8 to 2.6 V
Vcc − 0.3
X1
VIH4
VCC = 1.8 to 2.6 V
0.9 Vcc
VOL
IOL = 0.4 mA
VCC =
1.8 to 2.6 V
IOH = −200 μA
VCC =
1.8 to 2.6 V
RESET , NMI ,
P40 to PA7
RESET , NMI ,
P40 to PA7
Low-level output voltage
High-level output voltage
VOH
−0.3
Unit
0.15 Vcc
Vcc +
0.3
V
Ｖ
0.15 Vcc
V
0.8 Vcc
Note: Ta = 25°C, Vcc = 2.0 V, unless otherwise noted.
91CW28-239
2006-03-24
TMP91CW28
DC Electrical Characteristics (2/2)
Parameter
Symbol
Condition
Min
Typ.
(Note 1)
Max
Input leakage current
ILI
0.0 ≤ VIN ≤ Vcc
0.02
±5
Output leakage current
ILO
0.2 ≤ VIN ≤ Vcc − 0.2
0.05
±10
Power down voltage
V IL2 = 0.2 Vcc,
(while RAM is being backed
up in STOP mode)
VSTOP
V IH2 = 0.8 Vcc
1.8
2.6
RESET pull-up resistor
RRST
VCC = 1.8 to 2.2 V
200
1000
VCC = 2.2 to 2.6 V
100
600
Pin capacitance
CIO
fc = 1 MHz
VTH
VCC = 1.8 to 2.6 V
0.3
VCC = 1.8 to 2.2 V
200
1000
VCC = 2.2 to 2.6 V
100
600
10
Unit
μA
V
kΩ
pF
Schmitt width
RESET , NMI , P40 to P43,
0.8
V
KWI0 to KWI7, P60 to PA7
Programmable
pull-up resistor
RKH
NORMAL (Note 2)
VCC = 1.8 to 2.6 V
2.2
4.0
IDLE2
fc = 10 MHz
(Typ. value Vcc = 2.0 V)
0.7
1.6
0.3
0.9
0.1
10
IDLE1
STOP
Icc
VCC = 1.8 to 2.6 V
kΩ
mA
μA
Note 1: Ta = 25°C, VCC = 2.0 V, unless otherwise noted.
Note 2: Test conditions for NORMAL Icc: All blocks operating, output pins open, and input pin levels fixed.
91CW28-240
2006-03-24
TMP91CW28
4.3
AC Electrical Characteristics
(1) VCC = 1.8 to 2.6 V
No.
Equation
Parameter
Symbol
fFPH = 10 MHz
Unit
Min
Max
Min
Max
100
250
100
ns
22
ns
1
fFPH cycle period ( = x)
tFPH
2
A0 to A15 valid to ALE low
tAL
0.5x − 28
3
A0 to A15 hold after ALE low
tLA
0.5x − 35
15
ns
4
ALE pulse width high
tLL
x − 40
60
ns
5
ALE low to RD or WR asserted
tLC
0.5x − 28
22
ns
6
RD negated to ALE high
tCLR
0.5x − 20
30
ns
7
WR negated to ALE high
tCLW
x − 20
80
ns
8
A0 to A15 valid to RD or WR asserted
tACL
x − 75
25
ns
9
A0 to A23 valid to RD or WR asserted
tACH
1.5x − 70
80
ns
10
A0 to A23 hold after RD negated
tCAR
0.5x − 30
20
ns
11
A0 to A23 hold after WR negated
tCAW
x − 30
70
ns
12
A0 to A15 valid to D0 to D15 data in
tADL
3.0x − 76
224
ns
13
A0 to A23 valid to D0 to D15 data in
tADH
3.5x − 82
268
ns
14
RD asserted to D0 to D15 data in
tRD
2.0x − 60
140
15
RD width low
tRR
16
D0 to D15 hold after RD negated
tHR
0
0
ns
17
RD negated to next A0 to A15 output
tRAE
x − 30
70
ns
18
WR width low
tWW
1.5x − 30
120
ns
19
D0 to D15 valid to WR negated
tDW
1.5x − 70
80
ns
20
D0 to D15 hold after WR negated
tWD
x − 50
50
ns
21
A0 to A23 valid to WAIT input
22
A0 to A15 valid to WAIT input
23
WAIT hold after RD or WR asserted
(1 + N)
wait states
(1 + N)
wait states
(1 + N)
wait states
2.0x − 30
170
tAWH
3.5x − 120
230
tAWL
3.0x − 100
200
tCW
24
A0 to A23 valid to port data in
tAPH
25
Port data hold after A0 to A23 valid
tAPH2
26
A0 to A23 valid to port data valid
tAP
2.0x + 0
200
3.5x − 170
3.5x
ns
ns
ns
180
350
3.5x + 170
ns
ns
ns
ns
520
ns
AC measurement conditions:
・Output levels: High 0.7 × Vcc/Low 0.3 × Vcc, CL = 50 pF
・Input levels: High 0.9 × Vcc/Low 0.1 × Vcc
Note: In the above table, the letter x represents the fFPH cycle period, which is half the system clock
(fSYS) cycle period used in the CPU core.
The fFPH cycle period varies, depending on the programming of the clock gear function.
91CW28-241
2006-03-24
TMP91CW28
(2) Read operation timing
tFPH
fFPH
A0 to A23
CS0 to CS3
R/ W
tAWH
tAWL
tCW
WAIT
tAPH2
Port input (Note)
tADH
RD
tACH
tRR
tLC
A0 to A15
AD0 to AD15
tAL
ALE
tCAR
tRD
tADL
tRAE
tHR
D0 to D15
tLA
tCLR
tLL
Note: Since the CPU accesses the internal area to read data from a port, the control signals of external
pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics
of port input/output shown above are typical representation. For details, contact your local
Toshiba sales representative.
91CW28-242
tAPH
2006-03-24
TMP91CW28
(3) Write operation timing
fFPH
A0 to A23
CS0 to CS3
R/ W
WAIT
tAP
Port output (Note)
tCAW
tWW
WR , HWR
tDW
AD0 to AD15
A0 to A15
tWD
D0 to D15
tCLW
ALE
Note: Since the CPU accesses the internal area to write data to a port, the control signals of external
pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics
of port input/output shown above are typical representation. For details, contact your local
Toshiba sales representative.
91CW28-243
2006-03-24
TMP91CW28
4.4
ADC Electrical Characteristics
AVcc = Vcc, AVss = Vss
Condition
Min
Typ.
Max
Analog reference voltage ( + )
Parameter
VREFH
Symbol
VCC = 1.8 to 2.6 V
Vcc
Vcc
Vcc
Analog reference voltage ( − )
VREFL
VCC = 1.8 to 2.6 V
Vss
Vss
Vss
Analog input voltage
VAIN
VREFL
Analog supply ADMOD1.VREFON = 1
IREF
current
ADMOD1.VREFON = 0
Total error
(Not including quantization error)
−
Unit
V
VREFH
VCC = 1.8 to 2.6 V
0.65
1.0
mA
VCC = 1.8 to 2.6 V
0.02
5.0
μA
VCC = 1.8 to 2.6 V
±1.0
±4.0
LSB
Note 1: 1 LSB = (VREFH − VREFL)/1024 (V)
Note 2: Minimum operating frequency
Guaranteed when the frequency of the clock selected with the clock gear is 4 MHz or higher with fc
used.
Note 3: The supply current flowing through the AVCC pin is included in the VCC pin supply current
parameter (ICC).
4.5
SIO Timing (I/O interface mode)
Note: In the tables below, the letter x represents the fFPH cycle period, which is half the system clock (fSYS)
cycle period used in the CPU core.
The fFPH cycle period varies, depending on the programming of the clock gear function.
(1) SCLK input mode
Parameter
SCLK period
Symbol
tSCY
TXD data to SCLK rise or fall*
tOSS
TXD data hold after
SCLK rise or fall*
tOHS
RXD data hold after
SCLK rise or fall*
tHSR
SCLK rise or fall* to RXD data valid
tSRD
RXD data valid to SCLK rise or fall*
tRDS
Equation
Min
10 MHz
Max
Min Max
Unit
1.6
μs
(VCC = 2V ± 10%)
220
ns
tSCY/2 + 2X + 0
1000
ns
310
ns
16X
tSCY/2 − 4X − 180
3X + 10
tSCY − 0
0
1600
0
ns
ns
SCLK rise or fall*: Measured relative to the programmed active edge of SCLK.
Note: The values shown in the “10 MHz” column are measured with tSCY = 16X.
91CW28-244
2006-03-24
TMP91CW28
(2) SCLK output mode
Parameter
Symbol
Equation
10 MHz
Min
Max
16X
8192X
Min
Max
1.6
819
Unit
μs
SCLK period
tSCY
TXD data to SCLK rise or fall*
tOSS
tSCY/2 − 40
760
ns
TXD data hold after SCLK rise or fall*
tOHS
tSCY/2 − 40
760
ns
RXD data hold after SCLK rise or fall*
tHSR
SCLK rise or fall* to RXD data valid
tSRD
RXD data valid to SCLK rise or fall*
tRDS
0
0
tSCY − 1X − 180
1X + 180
ns
1320
280
ns
ns
Note: The values shown in the “10 MHz” column are measured with tSCY = 16X.
tSCY
SCLK
SCK output mode/
active-high SCLK input mode
SCLK
tOHS
tOSS
(Active-low SCLK input mode)
Transmit data
TXD
0
Receive data
RXD
0
1
tSRD
4.6
3
2
3
Valid
Valid
tHSR
tRDS
1
Valid
Valid
2
Event Counters (TA0IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1)
Parameter
Symbol
Equation
Min
Max
10 MHz
Min Max
Unit
Clock cycle period
tVCK
8X + 100
900
ns
Clock low pulse width
tVCKL
4X + 40
440
ns
Clock high pulse width
tVCKH
4X + 40
440
ns
Note: In the above table, the letter x represents the fFPH cycle period, which is half the system clock (fSYS) cycle
period used in the CPU core.
The fFPH cycle period varies, depending on the programming of the clock gear function.
91CW28-245
2006-03-24
TMP91CW28
4.7
Interrupt and Timer Capture
Note: In the tables below, the letter x represents the fFPH cycle period, which is half the system clock (fSYS) cycle
period used in the CPU core.
The fFPH cycle period varies, depending on the programming of the clock gear function.
(1) NMI , and INT0 to INT4 interrupts
Equation
Parameter
10 MHz
Symbol
Unit
Min
Max
Min
Max
Low pulse width for NMI and INT0
to INT4
tINTAL
4X + 40
440
ns
High pulse width for NMI and INT0
to INT4
tINTAH
4X + 40
440
ns
(2) INT5 to INT8 interrupts and capture
The input pulse widths for INT5 to INT8 vary with the selected system clock and
prescaler clock. The following table shows the pulse widths for different operating clocks:
Selected
Prescaler
Clock
PRCK[1:0]
tINTBL (Low pulse width
for INT5 to INT8)
tINTBH (High pulse width
for INT5 to INT8)
Equation
fFPH = 10 MHz
Equation
fFPH = 10 MHz
Min
Min
Min
Min
00 (fFPH)
8X + 100
10 (fc/16)
128Xc + 0.1
8X + 100
900
900
128Xc + 0.1
12.9
12.9
Unit
ns
μs
Note: Xc represents the cycle period of the high-speed oscillator clock (fc).
4.8
SCOUT Pin
Parameter
Equation
Symbol
Min
Max
10 MHz
Min
Max
Condition
Unit
Clock high pulse width
tSCH
0.5T − 25
25
VCC = 1.8 to 2.6 V
ns
Clock low pulse width
tSCL
0.5T − 25
25
VCC = 1.8 to 2.6 V
ns
Note: In the table above, the letter T represents the cycle period of the SCOUT output clock.
Measurement condition:
•
Output levels: High = 0.7 VCC/Low = 0.3 VCC, CL = 10 PF
tSCH
tSCL
SCOUT
91CW28-246
2006-03-24
TMP91CW28
4.9
Bus Request and Bus Acknowledge Signals
BUSRQ
(Note 1)
tCBAL
BUSAK
tBA
(Note 2)
tABA
AD0 to AD15
A0 to A23,
RD , WR
(Note 2)
CS0 to CS3 ,
R/ W , HWR
ALE
Parameter
Symbol
Equation
fFPH = 10 MHz
Min
Max
Min
Max
Condition
Unit
Bus float to
BUSAK asserted
tABA
0
300
0
300
VCC = 1.8 to 2.6 V
ns
Bus float after
BUSAK negated
tBAA
0
300
0
300
VCC = 1.8 to 2.6 V
ns
Note 1: If the current bus cycle has not terminated due to wait-state insertion, the TMP91CW28 does
not respond to BUSRQ until the wait state ends.
Note 2: This broken lines indicate that output buffers are disabled, not that the signals are at
indeterminate states. The pin holds the last logic value present at that pin before the bus is
relinquished. This is dynamically accomplished through external load capacitances. The
equipment manufacturer may maintain the bus at a predefined state by means of off-chip
resistors, but he or she should design, considering the time (Determined by the CR constant)
it takes for a signal to reach a desired state. The on-chip, integrated programmable
pull-up/pull-down resistors remain active, depending on internal signal states.
91CW28-247
2006-03-24
TMP91CW28
4.10 Recommended Oscillator Circuit
The TMP91CW28 is evaluated by the following resonator manufacturer. The results of
evaluation are shown below.
Note:
The additional capacitance of the resonator connecting pins are the sum of load capacitance
C1, C2 and the stray capacitance on the target board. Even when recommended constants
for C1 and C2 are used, actual load capacitance may vary with the board, possibly resulting
in the malfunction of the oscillator. The board should be designed so that the patterns around
the oscillator are as short as possible. Toshiba recommends that the resonator be finally
evaluated after it is mounted on the target board.
(1) Sample crystal circuit
X1
X2
Rd
C2
C1
Figure 4.10.1 High-frequency Oscillator Connection Diagram
(2) Recommended ceramic resonators for the TMP91CW28, manufactured by Murata
Manufacturing Co., Ltd.
MCU
Oscillation
Frequency
[MHz]
4.0
TMP91CW28
8.0
10.0
Recommended
Resonator
Parameter of Elements
C1 [pF] C2 [pF] Rf [Ω]
CSTCR4M00G55-R0
(39)
(39)
CSTLS4M00G56-B0
(47)
(47)
CSTCE8M00G55-R0
(33)
(33)
CSTLS8M00G56-B0
(47)
(47)
CSTCE10M0G52-R0
(10)
(10)
CSTLS10M0G53-B0
(15)
(15)
Running Condition
Rd [Ω]
Voltage of
Power [V]
Tc [°C]
1.8 to 2.6
Open
0
1.9 to 2.6
−20 to +70
1.8 to 2.6
•
The C1 and C2 constants are enclosed in parentheses for resonator models having
built-in capacitors.
•
The product numbers and specifications of the resonators by Murata Manufacturing
Co., Ltd. are subject to change.
For up-to-date information, please refer to the following URL:
http://www.murata.co.jp/search/index.html
91CW28-248
2006-03-24
TMP91CW28
5.
Special Function Register Summary
The special function registers (SFRs) configure and access the I/O ports, and control on-chip
functions. These registers occupy 4-Kbyte addresses from 000000H through 000FFFH.
(1) I/O ports
(2) I/O port control
(3) Interrupt control
(4) Chip select/wait controller
(5) Clock control
(6) 8-bit timer control
(7) 16-bit timer control
(8) UART serial channel
(9) I2C bus serial bus interface
(10) AD converter control
(11) Watchdog timer
(12) Key wakeup
(13) BCD adder/subtractor
(14) Program patch logic
Table Organization
Mnemonic
Register
Address
7
6
1
0
Bit symbol
Read/Write
Reset Value
Function
*
In the following tables, “RMW prohibited” indicates that the register does not support the use
of a read-modify-write instruction.
Example: When setting only bit0 in the PxCR register to 1, the “SET 0, (PxCR)” instruction is
usually used. That is not, however, allowed because RMW is prohibited for the
P0CR. Instead, the LD (Transfer) instruction must be used to write to 8 bits.
Access
R/W:
Read/write. The user can read and write the register bit.
R:
Read only.
W:
Write only.
W*:
The user can read and write the register bit, but a read always returns a
value of 1.
RMW prohibited: The user cannot perform a read-modify-write instruction (EX, ADD, ADC,
BUS, SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET,
RLC, RRC, RL, RR, SLA, SRA, SLL, SRL, RLD, and RRD).
*R/W:
The user cannot use a read-modify-write instruction to control the pull-up
resistor for the port.
91CW28-249
2006-03-24
TMP91CW28
Table 5.1 SFR Address Map (1)
[1] PORT
Address
0000H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
P0
P1
P0CR
P1CR
P1FC
P2
P3
P2CR
P2FC
P3CR
P3FC
P4
P5
P4CR
P4FC
Address
0010H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
P6
P7
P6CR
P6FC
P7CR
P7FC
P8
P9
P8CR
P8FC
P9CR
P9FC
PA
Address
0020H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
PACR
PAFC
PUP
ODE
[2] INTC
Address
0080H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
DMA0V
DMA1V
DMA2V
DMA3V
INTCLR
DMAR
DMAB
IIMC
Address
0090H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
INTE0AD
INTE12
INTE34
INTE56
INTE78
INTETA01
INTETA23
INTETB0
INTETB1
INTETB01V
INTEBCD
INTES1
INTES2
Address
Mnemonic
00A0H INTETC01
1H INTETC23
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
[3] CS/WAIT
Address
00C0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
B0CS
B1CS
B2CS
B3CS
BEXCS
MSAR0
MAMR0
MSAR1
MAMR1
MSAR2
MAMR2
MSAR3
MAMR3
Note: Only the addresses with mnemonics shown in the tables can be accessed.
91CW28-250
2006-03-24
TMP91CW28
Table 5.2 SFR Address Map (2)
[4] CGEAR, DFM
Address
00E0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
SYSCR0
SYSCR1
SYSCR2
EMCCR0
EMCCR1
[5] TMRA
Address
0100H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
TA01RUN
TA0REG
TA1REG
TA01MOD
TA1FFCR
TA23RUN
TA2REG
TA3REG
TA23MOD
TA3FFCR
[6] TMRB
Address
0180H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
Address
TB0RUN
0190H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
TB0MOD
TB0FFCR
TB0RG0L
TB0RG0H
TB0RG1L
TB0RG1H
TB0CP0L
TB0CP0H
TB0CP1L
TB0CP1H
Mnemonic
TB1RUN
TB1MOD
TB1FFCR
TB1RG0L
TB1RG0H
TB1RG1L
TB1RG1H
TB1CP0L
TB1CP0H
TB1CP1L
TB1CP1H
Note: Only the addresses with mnemonics shown in the tables can be accessed.
91CW28-251
2006-03-24
TMP91CW28
Table 5.3 SFR Address Map (3)
2
[7] UART/SIO
Address
0200H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
[8] I C bus/SIO
Mnemonic
Address
0240H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
SC1BUF
SC1CR
SC1MOD0
BR1CR
BR1ADD
SC1MOD1
Mnemonic
SBI0CR1
SBI0DBR
I2C0AR
SBI0CR2/SBI0SR
SBI0BR0
SBI0BR1
SBI1CR1
SBI1DBR
I2C1AR
SBI1CR2/SBI1SR
SBI1BR0
SBI1BR1
[9] 10-bit ADC
Address
02A0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
Address
ADREG04L
ADREG04H
ADREG15L
ADREG15H
ADREG26L
ADREG26H
ADREG37L
ADREG37H
02B0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
ADMOD0
ADMOD1
[10] WDT
Address
0300H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
WDMOD
WDCR
Note: Only the addresses with mnemonics shown in the tables can be accessed.
91CW28-252
2006-03-24
TMP91CW28
Table 5.4 SFR Address Map (4)
[11] Key wakeup
Address
03A0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
[12] BCD adder/subtractor
Mnemonic
Address
KWIEN
KWICR
03B0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
BCDMINA
BCDSECA
BCDFRAA
BCDMINB
BCDSECB
BCDFRAB
BCDMINR
BCDSECR
BCDFRAR
BCDCR
[13] Program patch logic
Address
0400H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
ROMCMP00
ROMCMP01
ROMCMP02
ROMSUB0L
ROMSUB0H
ROMCMP10
ROMCMP11
ROMCMP12
ROMSUB1L
ROMSUB1H
Address
0410H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
ROMCMP20
ROMCMP21
ROMCMP22
ROMSUB2L
ROMSUB2H
ROMCMP30
ROMCMP31
ROMCMP32
ROMSUB3L
ROMSUB3H
Address
0420H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Mnemonic
ROMCMP40
ROMCMP41
ROMCMP42
ROMSUB4L
ROMSUB4H
ROMCMP50
ROMCMP51
ROMCMP52
ROMSUB5L
ROMSUB5H
Note: Only the addresses with mnemonics shown in the tables can be accessed.
91CW28-253
2006-03-24
TMP91CW28
(1) Input/output ports
Mnemonic
P0
Name
Port 0
Address
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
00H
R/W
Data from external port (Output latch register is undefined)
P17
P1
Port 1
P16
P15
P14
01H
P13
P12
P11
P10
R/W
Data from external port (Output latch register is cleared to 0)
P27
P2
Port 2
P26
P25
P24
06H
P23
P22
P21
P20
P31
P30
1
1
R/W
Data from external port (Output latch register is set to 1)
P37
P36
P35
P34
P33
P32
*R/W
P3
Port 3
07H
Data from external port (Output latch register is set to 1)
0 (Output latch register) : Pull-up resistor disabled
−
1 (Output latch register) : Pull-up resistor enabled
P43
P42
P41
P40
*R/W
P4
Port 4
Data from external port
(Output latch register is set to 1)
0CH
0 (Output latch register): Pull-up resistor disabled
1 (Output latch register): Pull-up resistor enabled
P57
P5
Port 5
P56
P55
P54
0DH
P53
P52
P51
P50
P62
P61
P60
R
Data from external port
P66
P65
P64
P63
R/W
Data from external port (Output latch register is set to 1)
P6
Port 6
12H
0(Output latch register) :
Pull-up resistor disabled
−
1(Output latch register):
−
Pull-up resistor enabled
P75
P74
P73
P72
P71
P70
R/W
P7
Port 7
13H
Data from external port (Output latch register is set to 1)
0 (Output latch register) : Pull-up resistor disabled
1 (Output latch register) : Pull-up resistor enabled
P87
P86
P85
P84
P83
P82
P81
P80
P91
P90
R/W
P8
Port 8
18H
Data from external port (Output latch register is set to 1)
0 (Output latch register) : Pull-up resistor disabled
1 (Output latch register) : Pull-up resistor enabled
P96
P95
P94
P93
P92
R/W
P9
Port 9
Data from external port (output latch register is set to 1)
19H
0(Output latch register)
: Pull-up resistor disabled
1(Output latch register)
: Pull-up resistor enabled
−
PA7
PA6
PA5
PA4
PA3
PA2
PA1
−
PA0
R/W
PA
Port A
1EH
Data from external port (Output latch register is set to 1)
0 (Output latch register) : Pull-up resistor disabled
1 (Output latch register) : Pull-up resistor enabled
91CW28-254
2006-03-24
TMP91CW28
(2) Input/output port control (1/2)
Mnemonic
P0CR
Name
Port 0
control
Address
02H
(RMW
prohibited)
7
6
5
4
3
2
1
0
P07C
P06C
P05C
P04C
P03C
P02C
P01C
P00C
0
0
0
0
0
0
0
0
P13C
P12C
P11C
P10C
0
0
0
0
P13F
P12F
P11F
P10F
0
0
0
0
W
0: Input 1: Output
P1CR
Port 1
control
04H
(RMW
prohibited)
P17C
P16C
P15C
P14C
0
0
0
0
W
0: Input 1: Output
P1FC
P2CR
Port 1
function
Port 2
control
05H
(RMW
prohibited)
08H
(RMW
prohibited)
P17F
P16F
P15F
P14F
W
0
0
0
0
P1FC/P1CR = 00: Input port, 01: Output port, 10: AD15 to AD8, 11: A15 to A8
P27C
P26C
P25C
P24C
P23C
P22C
P21C
P20C
0
0
0
0
P23F
P22F
P21F
P20F
0
0
0
0
W
0
0
0
0
0: Input 1: Output
P2FC
Port 2
function
09H
(RMW
prohibited)
P27F
P26F
P25F
P24F
W
0
0
0
0
P2FC/P2CR = 00: Input port, 01: Output port, 10: A7 to A0, 11: A23 to A16
P3CR
Port 3
control
0AH
(RMW
prohibited)
P37C
P36C
P35C
P34C
P33C
P32C
0
0
0
W
0
0
0
−
P36F
P35F
0: Input 1: Output
P3FC
Port 3
function
0BH
0
0
(RMW
prohibited) Must be 0: Port
written as 1: R/ W
“0”.
P34F
P32F
P4CR
control
P30F
W
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
0: Port
1: BUSAK
1: BUSRQ
1: HWR
1: WR
1: RD
P43C
Port 4
P31F
W
P42C
0EH
P41C
P40C
0
0
W
(RMW
prohibited)
0
0
0: Input 1: Output
P43F
P4FC
P6CR
Port 4
0FH
14H
(RMW
prohibited)
P41F
P40F
W
0
(RMW
function
prohibited)
Port 6
control
P42F
P66C
P65C
P64C
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
1: CS3
1: CS2
1: CS1
1: CS0
P63C
P62C
P61C
P60C
0
0
0
0
P62F
P61F
P60F
W
0
0: Input 1: Output
P64F
P6FC
Port 6
function
15H
(RMW
prohibited)
P63F
W
0
0: Port
0
0: Port
1: SCOUT 1: INT0
0
0
0
0: Port
0: Port
0: Port
1: SCL0
1:SDA0/
1: SCK0
SO0
Note: Writing 0 to the P3.P30 bit and 1 to the P3FC.P30F bit causes the P30 to be driven low also when
on-chip address space is accessed.
91CW28-255
2006-03-24
TMP91CW28
Input/output port control (2/2)
Mnemonic
P7CR
Name
Port 7
control
Address
7
6
5
4
3
2
1
0
P75C
P74C
P73C
P72C
P71C
P70C
0
0
0
0
0
0
16H
W
(RMW
prohibited)
0: Input 1: Output
P72F
P7FC
P8CR
P8FC
Port 7
function
Port 8
control
Port 8
function
17H
(RMW
prohibited)
1AH
(RMW
prohibited)
P87C
P86C
P85C
P9FC
PACR
Port 9
control
Port 9
function
Port A
control
0
0
0
P87F
P86F
P85F
0
0
1BH
0
(RMW
prohibited) 0: Port
0: Port
P96C
1CH
(RMW
prohibited)
0
1DH
(RMW
prohibited)
0: Port
1: INT8/
TB1IN1
P95C
0
0
0: Port
1: TA3OUT
1: TA1OUT
P83C
P82C
P81C
P80C
0
0
0
0
P82F
P81F
P80F
0
0
0
0: Port
0: Port
0: Input 1: Output
P84F
P83F
W
0
0
0: Port
1: INT7/
TB1IN0
P94C
0
0: Port
1: TB0OUT1 1: TB0OUT0 1: INT6/
P93C
W
0
0
0
0: Port
1: SCLK
PA6C
PA5C
TB0IN1
P91C
0
0
0
P91F
P90F
W
0
PA7C
0: Port
1: INT5/
TB0IN0
P90C
P92C
0: Input 1: Output
P93F
P92F
P95F
W
(RMW
prohibited)
20H
P84C
0
0: Port
W
1: TB1OUT 1: TB1OUT
P9CR
P71F
W
0: Port
1: TXD
PA4C
0
0
0: Port
1: SCL1
0
0: Port
1: SDA1/
SO1
0: Port
1: SCK1
PA3C
PA2C
PA1C
PA0C
0
0
0
0
PA1F
PA0F
W
0
0
0
0
0: Input 1: Output
PAFC
Port A
function
PA3F
21H
W
(RMW
prohibited)
0
PUP92
PUP
Pull-up
enable
ODE
Serial
open-drain
enable
PA2F
PUP91
PUP62
0
0
INT1 to INT4 input enable
PUP61
0
R/W
2EH
2FH
1
0: Disable
1: Enable
1
0: Disable
1: Enable
ODE92
ODE91
1
0: Disable
1: Enable
1
0: Disable
1: Enable
ODE61
0
0
1: P61ODE
1: P93ODE
0
0
ODE62
R/W
0
1: P92ODE
1: P91ODE
1: P62ODE
ODE93
Note 1: External interrupt INT0
The P6FC.P63F bit enables input. The IIMC.I0LE and IIMC.I0EDGE bits control the interrupt
sensitivity (High level, low level, rising edge or falling edge).
Note 2: External interrupts INT1 to INT4
The PAFC.PA3F to PAFC.PA0F bits enable input. The IIMC.I4EDGE to IIMC.I1EDGE bits control
the edge polarity (Rising or falling).
Note 3: External interrupts INT5 to INT8
The P85F, P84F, P81F, and P80F bits of the P8FC enable input. The TB0MOD and TB1MOD
registers (TMRB registers) control the edge polarity.
91CW28-256
2006-03-24
TMP91CW28
(3) Interrupt control (1/3)
Mnemonic
Name
Address
7
6
5
4
3
2
INTAD
INT0 &
INTE0AD INTAD
enable
IADC
90H
IADM2
IADM1
IADM0
R/W
R
0
1: INTAD
0
I2C
I2M2
I0C
I0M2
INT1 &
INT2
enable
91H
0
0
Interrupt priority level
I2M0
R/W
0
1: INT2
0
I4C
I4M2
0
1: INT0
0
INT3 &
INT4
enable
92H
I1C
I1M2
0
I6C
I6M2
R/W
0
1: INT1
0
0
0
Interrupt priority level
I4M0
I3C
I3M2
INT5 &
INT6
enable
93H
I6M0
R/W
0
1: INT6
0
R/W
0
1: INT3
0
0
0
Interrupt priority level
I5C
I5M2
I8C
I8M2
INTE78
INTTA0 &
INTETA01 INTTA1
enable
94H
0
0
Interrupt priority level
0
1: INT8
ITA1C
95H
I8M0
R/W
0
0
1: INT5
0
0
0
Interrupt priority level
I7C
I7M2
INTTA1 (TMRA1)
ITA1M2
ITA1M1
ITA1M0
R/W
0
1: INTTA1
0
ITA3C
ITA3M2
0
1: INT7
ITA0C
INTETA23
INTTA2 &
INTTA3
enable
96H
0
1: INTTA3
0
INTTA0 (TMRA0)
ITA0M2
ITA0M1
ITA0M0
R/W
0
0
0
Interrupt priority level
ITA2C
ITA2M2
INTTA2 (TMRA4)
ITA3M0
R/W
R
I7M0
0
0
Interrupt priority level
0
1: INTTA0
INTTA3 (TMRA5)
ITA3M1
0
R
0
0
Interrupt priority level
I7M1
R/W
R
0
0
Interrupt priority level
R
I5M0
R/W
INT7
I8M1
R
I5M1
R
INT8
INT7 &
INT8
enable
I3M0
INT5
I6M1
R
I3M1
R
0
0
Interrupt priority level
INT6
INTE56
I1M0
INT3
I4M1
R/W
0
1: INT4
I1M1
R
0
0
Interrupt priority level
R
I0M0
0
0
Interrupt priority level
INT4
INTE34
I0M1
INT1
I2M1
R
0
R/W
R
INT2
INTE12
1
INT0
0
Interrupt priority level
91CW28-257
0
1: INTTA2
ITA2M0
R/W
R
0
ITA2M1
0
0
0
Interrupt priority level
2006-03-24
TMP91CW28
Interrupt control (2/3)
Mnemonic
Name
Address
7
6
5
4
3
INTTB01 (TMRB0)
INTETB0
INTETB1
INTTB00
&
INTTB01
enable
INTTB10
&
INTTB11
enable
ITB01C
99H
0
1: INTTB01
9AH
ITB01M2
ITB11C
R
0
ITB01M1
ITB01M0
R/W
R
9BH
0
0
0
Interrupt priority level
INTTB11 (TMRB1)
ITB11M2 ITB11M1 ITB11M0
R/W
0
0
Interrupt priority level
INTTBOF1 (TMRB1 overflow)
ITF1C
ITF1M2
ITF1M1
ITF1M0
R/W
R
0
(Overflow)
0
INTEBCD
INTES1
INTES2
INTBCD
enable
INTTRX
& INTTX
enable
9DH
INTSBI0
&
INTSBI1
enable
9EH
INTETC23
INTTC0&
INTTC1
enable
INTTC2&
INTTC3
enable
0
0
Interrupt priority level
9CH
ITX1C
R
0
1: INTTX0
IS1C
R
0
1: INTSBI1
INTETC01
0
1: INTTBOF1
A0H
A1H
ITC1C
R
0
ITC3C
R
0
INTTX
ITX1M2
ITX1M1
R/W
ITX1M0
0
0
0
Interrupt priority level
INTSBI1
IS1M2
IS1M1
IS1M0
R/W
0
0
0
Interrupt priority level
INTTC1
ITC1M2
ITC1M1
ITC1M0
R/W
0
INTTC3
ITC3M2
ITC3M1
R/W
0
0
1
ITB00C
ITB00M2
0
0
ITC3M0
0
91CW28-258
0
0
1: INTTB00
ITB10C
R
0
ITB00M1
ITB00M0
R/W
R
1: INTTB11
INTTBOF0
&
INTETB01V INTTBOF1
enable
2
INTTB00 (TMRB0)
0
0
0
Interrupt priority level
INTTB10 (TMRB1)
ITB10M2 ITB10M1 ITB10M0
R/W
0
0
0
Interrupt priority level
INTTBOF0 (TMRB0 overflow)
ITF0C
ITF0M2
ITF0M1
ITF0M0
R/W
R
1: INTTB10
0
1: INTTBOF0
0
IBCDC
R
0
1: INTBCD
IBCDM2
IRX1C
R
0
1: INTRX0
IS0C
R
0
1: INTSBI0
ITC0C
R
0
ITC2C
R
0
0
0
Interrupt priority level
INTBCD
IBCDM1
IBCDM0
R/W
0
0
0
Interrupt priority level
INTRX
IRX1M2
IRX1M1
R/W
IRX1M0
0
0
0
Interrupt priority level
INTSBI0
IS0M2
IS0M1
IS0M0
R/W
0
0
0
Interrupt priority level
INTTC0
ITC0M2
ITC0M1
ITC0M0
R/W
0
0
INTTC2
ITC2M2
ITC2M1
R/W
0
0
0
ITC2M0
0
2006-03-24
TMP91CW28
Interrupt control (3/3)
Mnemonic
DMA0V
Name
DMA 0
request
vector
Address
7
6
5
4
3
2
1
0
DMA0V5
DMA0V4
DMA0V3
DMA0V2
DMA0V1
DMA0V0
0
0
0
0
0
DMA1V1
DMA1V0
0
0
DMA2V1
DMA2V0
0
0
DMA3V1
DMA3V0
0
0
CLRV2
CLRV1
CLRV0
0
0
0
R/W
80H
0
DMA0 startup vector
DMA1V
DMA 1
request
vector
DMA1V5
DMA1V4
DMA1V3
0
0
0
DMA1V2
R/W
81H
0
DMA1 startup vector
DMA2V5
DMA2V
DMA 2
request
vector
DMA2V4
DMA2V3
DMA2V2
R/W
82H
0
0
0
0
DMA2 startup vector
DMA3V5
DMA3V
DMA 3
request
vector
DMA3V4
DMA3V3
DMA3V2
R/W
83H
0
0
0
0
DMA3 startup vector
INTCLR
DMAR
DMAB
IIMC
Interrupt
clear
control
DMA
software
request
register
DMA
burst
request
register
Interrupt
input
mode
control
CLRV5
88H
CLRV4
CLRV3
W
(RMW
prohibited)
0
0
0
Write the DMA startup vector to clear an interrupt.
89H
DMAR3
DMAR2
DMAR1
DMAR0
R/W
R/W
R/W
R/W
0
0
0
0
1: DMA soft request
8AH
DMAB3
DMAB2
DMAB1
DMAB0
R/W
R/W
R/W
R/W
0
0
0
0
1: DMA burst request
8CH
−
I4EDGE
I3EDGE
I2EDGE
I1EDGE
I0EDGE
I0LE
NMIREE
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
Must be
written as
(RMW
“0”.
prohibited)
INT4 edge INT3 edge INT2 edge INT1 edge INT0 edge
polarity
polarity
polarity
polarity
polarity
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
1: Also
INT0
triggered
sensitivity
0: Edgetriggered
1: Levelsensitive
91CW28-259
by NMI
rising
edge
2006-03-24
TMP91CW28
(4) Chip select/wait controller (1/2)
Mnemonic
B0CS
Name
Address
7
6
5
4
3
2
1
0
B0E
B0OM1
B0OM0
B0BUS
B0W2
B0W1
B0W0
W
W
W
W
W
W
W
0
0
0
0
0
C0H
Block 0
0
CS/WAIT
0:
Disable
control
(RMW
register
prohibited) 1: Enable
B1E
B1CS
W
C1H
Block 1
0
CS/WAIT
control
(RMW 0: Disable
register
prohibited) 1: Enable
B2E
B2CS
W
C2H
Block 2
1
CS/WAIT
0:
Disable
control
(RMW
register
prohibited) 1: Enable
BEXCS
MSAR0
MAMR0
MSAR1
MAMR1
000: 2 wait states 1xx: Reserved
01: Reserved
Data bus
width
10: Reserved
0: 16 bits
010: (1 + N) wait states
11: Reserved
1: 8 bits
011: 0 wait states
B1OM0
B1BUS
B1W2
B1W1
B1W0
W
W
W
W
W
W
0
0
0
0
0
0
000: 2 wait states 1xx: Reserved
01: Reserved
Data bus
width
10: Reserved
0: 16 bits
010: (1 + N) wait states
11: Reserved
1: 8 bits
011: 0 wait states
B2OM1
B2OM0
B2BUS
B2W2
B2W1
B2W0
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0: Whole
00: ROM/SRAM
16-Mbyt
01: Reserved
e space
10: Reserved
1: CS
11: Reserved
space
Memory
address
mask
register 0
Memory
start
address
register 1
Memory
address
mask
register 1
Data bus
width
000: 2 wait states 1xx: Reserved
0: 16 bits
010: (1 + N) wait states
1: 8 bits
011: 0 wait states
B3OM0
B3BUS
B3W2
B3W1
B3W0
W
W
W
W
W
W
0
0
0
0
0
0
00: ROM/SRAM
000: 2 wait states 1xx: Reserved
01: Reserved
Data bus
width
10: Reserved
0: 16 bits
010: (1 + N) wait states
11: Reserved
1: 8 bits
011: 0 wait states
S21
001: 1 wait state
BEXBUS
BEXW2
BEXW1
BEXW0
W
W
W
W
0
0
0
0
S22
001: 1 wait state
B3OM1
C7H
External
CS/WAIT
control
(RMW
register
prohibited)
S23
001: 1 wait state
B2M
W
C3H
Block 3
0
CS/WAIT
control
(RMW 0: Disable
register
prohibited) 1: Enable
Memory
start
address
register 0
001: 1 wait state
B1OM1
00: ROM/SRAM
B3E
B3CS
0
00: ROM/SRAM
Data bus
width
000: 2 wait states 1xx: Reserved
0: 16 bits
010: (1 + N) wait states
1: 8 bits
011: 0 wait states
S20
001: 1 wait state
S19
S18
S17
S16
1
1
1
1
R/W
C8H
1
1
1
1
Set A23 to A16 of the start address
V20
V19
V18
V17
V16
V15
V14 to V9
V8
1
1
1
1
R/W
C9H
1
1
1
1
CS0 space size 0: Bit to be compared
S23
S22
S21
S20
S19
S18
S17
S16
1
1
1
1
V8
R/W
CAH
1
1
1
1
V21
V20
V19
V18
1
1
1
1
Set A23 to A16 of the start address
V17
V16
V15 to V9
1
1
1
R/W
CBH
CS1 space size 0: Bit to be compared
91CW28-260
2006-03-24
TMP91CW28
Chip select/wait controller (2/2)
Mnemonic
MSAR2
MAMR2
MSAR3
MAMR3
Name
Memory
start
address
register 2
Memory
address
mask
register 2
Memory
start
address
register 3
Memory
address
mask
register 3
Address
7
6
5
4
3
2
1
0
S23
S22
S21
S20
S19
S18
S17
S16
1
1
1
1
1
1
1
1
V22
V21
V20
V19
V18
V17
V16
V15
1
1
1
1
1
1
1
1
R/W
CCH
Set A23 to A16 of the start address
R/W
CDH
CS2 space size 0: Bit to be compared
S23
S22
S21
S20
1
1
1
1
S19
S18
S17
S16
1
1
1
1
V18
V17
V16
V15
1
1
1
1
R/W
CEH
Set A23 to A16 of the start address
V22
V21
V20
V19
R/W
CFH
1
1
1
1
CS3 space size 0: Bit to be compared
91CW28-261
2006-03-24
TMP91CW28
(5) Clock control
Mnemonic
Name
Address
7
6
−
−
5
4
3
2
1
0
−
−
−
−
PRCK1
PRCK0
W
SYSCR0
System
clock
control
register 0
E0H
R/W
1
0
1
0
0
Must be
written
as “1”.
Must be
written
as “0”.
Must be
written
as “1”.
Must be
written
as “0”.
Must be
written
as “0”.
0
0
0
Must be
Prescaler clock select
written as 00: f
FPH
“0”.
01: Reserved
10: fc/16
11: Reserved
−
GEAR2
W
SYSCR1
E1H
SYSCR2
0
0
High-speed clock gear select
000: High-speed clock
001: High-speed clock/2
010: High-speed clock/4
011: High-speed clock/8
100: High-speed clock/16
Others: Reserved
WUPTM1
WUPTM0
HALTM1
HALTM0
DRVE
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
SCOUT
出力
E2H
1
Must be
written as
“0”.
SCOSEL
0
System
clock
control
register 2
GEAR0
R/W
0
System
clock
control
register 1
GEAR1
Oscillator warm-up
time
0
1: Pins are
driven
in
STOP
mode
00: Reserved
01: STOP mode
00: Reserved
0: Low
level
10: IDLE1 mode
8
01: 2 /input frequency 11: IDLE2 mode
14
10: 2 /input
frequency
1: fFPH
16
11: 2 /input
frequency
EMCCR0
EMC
control
register 0
E3H
PROTECT
−
−
−
ALEEN
EXTIN
−
−
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
Protection Must be
flag
written as
0: Disabled “0”.
1
0
Must be
written as
“1”.
Must be
written as
“0”.
1: Enabled
EMCCR1
Note:
EMC
control
register 1
1
1: ALE
1: External Must be
output
clock
written as
enabled
used as “1”.
fc
Must be
written as
“1”.
On writes: 1FH: Protection disabled
E4H
Other than
1FH: Protection enabled
Enabling protection using the EMCCR1 register prevents writes to the following SFRs:
1. Chip select/wait controller
B0CS, B1CS, B2CS, B3CS, BEXCS,
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3
2. Clock gear (Only the EMCCR1 can be written.)
SYSCR0, SYSCR1, SYSCR2, EMCCR0
91CW28-262
2006-03-24
TMP91CW28
(6) 8-bit timer control
(6−1) TMRA01
Mnemonic
Name
8-bit timer
TA01RUN RUN
register
Address
7
6
5
4
3
TA0RDE
I2TA01
R/W
R/W
0
100H
2
0
0: OFF
0: Disable
1: ON
0
TA01PRUN TA1RUN
TA0RUN
R/W
R/W
R/W
0
0
0
8-bit timer run/stop control
0: Stop and clear
IDLE2
Double
buffering
1
1: Run (count up)
1: Enable
TA0REG
TA1REG
8-bit timer
register 0
8-bit timer
register 1
102H
−
(RMW
prohibited)
W
Undefined
−
103H
(RMW
prohibited)
W
Undefined
TA01M1
TA01M0
PWM01
PWM00
TA1CLK1 TA1CLK0
TA0CLK1
TA0CLK0
0
0
R/W
8-bit timer
source
TA01MOD clock &
mode
register
0
104H
0
0
0
0
0
Operating mode
PWM period
TMRA1 source clock TMRA0 source clock
00: 8-bit interval timer
00: Reserved
00: TA0TRG
00: TA0IN input
6
01: φT1
01: φT1
7
10: φT16
10: φT4
8
11: φT256
11: φT16
01:16-bit interval timer
01: 2
10: 8-bit PPG
10: 2
11: 8-bit PWM
11: 2
TA1FFC1 TA1FFC0
TA1FFIE
R/W
105H
8-bit timer
flip-flop
TA1FFCR
control
(RMW
register
prohibited)
1
1
00: Toggles TA1FF
01: Sets TA1FF to 1
10: Clears TA1FF to 0
11: Don’t care
TA1FFIS
R/W
0
1: TA1FF
toggle
enable
0
TA1FF
toggle
trigger
0: TMRA0
1: TMRA1
91CW28-263
2006-03-24
TMP91CW28
(6−2) TMRA23
Mnemonic
Name
8-bit timer
TA23RUN RUN
register
Address
7
6
5
4
3
TA2RDE
I2TA23
R/W
R/W
0
108H
2
0
0: OFF
0: Disable
1: ON
0
TA2RUN
R/W
R/W
R/W
0
0
0
8-bit timer run/stop control
0: Stop and clear
IDLE2
Double
buffering
1
TA23PRUN TA3RUN
1: Run
1: Enable
TA2REG
TA3REG
8-bit timer
register 0
8-bit timer
register 1
−
10AH
(RMW
prohibited)
W
Undefined
10BH
−
(RMW
prohibited)
W
Undefined
TA23M1
TA23M0
PWM21
PWM20
0
0
0
0
TA3CLK1
TA3CLK0
TA2CLK1
TA2CLK0
0
0
R/W
8-bit timer
source
TA23MOD clock &
mode
register
10CH
0
0
Operating mode
PWM period
TMRA3 source clock
TMRA2 source clock
00: 8-bit interval timer
00: Reserved
00: TA2TRG
00: Reserved
01: 16-bit interval timer 01: 2
6
01: φT1
01: φT1
10: 8-bit PPG
10: 2
7
10: φT16
10: φT4
11: 8-bit PWM
11: 2
8
11: φT256
11: φT16
TA3FFC1
TA3FFC0
TA3FFIE
R/W
10DH
8-bit timer
flip-flop
TA3FFCR
control
(RMW
register
prohibited)
1
R/W
1
00: Toggles TA3FF
01: Sets TA3FF to 1
10: Clears TA3FF to 0
11: Don’t care
TA3FFIS
0
1: TA3FF
toggle
enable
0
TA3FF
toggle
trigger
0: TMRA2
1: TMRA3
91CW28-264
2006-03-24
TMP91CW28
(7) 16-bit timer control (1/2)
(7−1) TMRB0
Mnemonic
Name
16-bit
timer
TB0RUN
RUN
register
Address
180H
7
6
3
2
TB0RDE
−
5
4
I2TB0
TB0PRUN
TB0RUN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Double
buffering
Must be
written as
0: Disable “0”.
1
0
IDLE2
16-bit timer run/stop control
0: OFF
0: Stop and clear
1: ON
1: Run
1: Enable
TB0CT1
TB0ET1
0
16-bit
timer
source
TB0MOD
clock &
mode
register
TB0CP0I
TB0CPM1 TB0CPM0
W*
R/W
0
TB0FF1 toggle
trigger
0: Trigger disabled
(RMW
prohibited) 1: Trigger enabled
When
Upon a
latches
match
UC0 value with timer
into
register 1
capture
182H
TB0CLE
TB0CLK1
TB0CLK0
0
0
R/W
1
0
0
0: Soft
Capture triggers
capture
(TB0IN0, TB0IN1)
1: Undefined 00: Disabled
01: ↑, ↑
10: ↑, ↓
11: ↑, ↓ (TA1OUT)
0
UC0 clear TMRB0 input clock
control
1: Enable 00: TB0IN0 input
01: φT1
10: φT4
11: φT16
register 1
TB0FF1C1 TB0FF1C0 TB0C1T1
TB0C0T1
W*
16-bit
timer
TB0FFCR flip-flop
control
register
TB0RG0L
16-bit
timer
register 0
low
1
TB0E1T1
TB0E0T1 TB0FF0C1 TB0FF0C0
W*
R/W
1
0
183H
TB0FF1 control
(RMW
00: Invert
prohibited) 01: Set
10: Clear
11: Don’t care
* Always read “11”.
0
0
0
TB0FF0 toggle trigger
0: Trigger disabled
1: Trigger enabled
When the up
counter value
is latched into
TB0CP1
When the up
counter value
is latched into
TB0CP0
When the up
counter value
reaches the
TB0RG1
value
188H
−
(RMW
prohibited)
W
When the up
counter value
reaches the
TB0RG0
value
0
0
TB0FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
* Always read “11”.
Undefined
16-bit
timer
TB0RG0H
register 0
high
189H
−
(RMW
prohibited)
W
16-bit
timer
TB0RG1L
register 1
low
18AH
−
(RMW
prohibited)
W
16-bit
timer
TB0RG1H
register 1
high
18BH
−
(RMW
prohibited)
W
Undefined
Capture
TB0CP0L register 0
low
18CH
R
Capture
TB0CP0H register 0
high
18DH
Capture
TB0CP1L register 1
low
18EH
Capture
TB0CP1H register 1
high
18FH
Undefined
Undefined
−
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
91CW28-265
2006-03-24
TMP91CW28
16-bit timer control (2/2)
(7−2) TMRB1
Mnemonic
Name
16-bit
timer
TB1RUN
RUN
register
Address
190H
7
6
3
2
TB1RDE
−
5
4
I2TB1
TB1PRUN
TB1RUN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Double
buffering
Must be
written as
0: Disable “0”.
1
0
IDLE2
16-bit timer run/stop control
0: OFF
0: Stop and clear
1: ON
1: Run
1: Enable
TB1CT1
TB1ET1
R/W
16-bit
timer
source
TB1MOD
clock &
mode
register
0
TB1CP0I
TB1CPM1 TB1CPM0
W*
0
TB1FF1 toggle trogger 0: Soft
capture
0: Trigger disabled
(RMW
1: Undefined
1:
Trigger
enabled
prohibited)
When
Upon a
latches
match
UC0 value with timer
into capture
register 1
register 1
TB1FF1C1 TB1FF1C0 TB1C1T1
0
16-bit
timer
TB1FFCR flip-flop
control
register
TB1RG0L
16-bit
timer
register 0
low
16-bit
timer
TB1RG0H
register 0
high
16-bit
timer
TB1RG1L
register 1
low
16-bit
timer
TB1RG1H
register 1
high
TB1C0T1
TB1FF1 control
193H
00: Invert
(RMW
prohibited) 01: Set
10: Clear
11: Don’t care
* Always read “11”.
0
When the up
counter value
is latched into
TB1CP1
0
0
TB1E0T1 TB1FF0C1 TB1FF0C0
W*
0
When the up
counter value
is latched into
TB1CP0
When the up
counter value
reaches the
TB1RG1 value
1
198H
−
(RMW
prohibited)
W
0
When the up
counter value
reaches the
TB1RG0 value
1
0
0
TB1FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
* Always read “11”.
Undefined
199H
−
(RMW
prohibited)
W
Undefined
19AH
−
(RMW
prohibited)
W
Undefined
19BH
−
(RMW
prohibited)
W
Undefined
19CH
R
−
Undefined
−
19DH
R
high
Undefined
−
19EH
R
Undefined
−
Capture
TB1CP1H register 1
0
UC0 clear TMRB1 input clock
control
00: TB1IN0 input
1: Enable 01: φT1
10: φT4
11: φT16
TB1FF0 toggle trigger
0: Trigger disabled
1: Trigger enabled
Capture
Capture
TB1CP1L register 1
low
TB1E1T1
0
low
TB1CP0H register 0
TB1CLK0
R/W
1
Capture
TB1CP0L register 0
0
Capture triggers
(TB0IN0, TB0IN1)
00: Disabled
01: ↑, ↑
10: ↑, ↓
11: ↑, ↓ (TA1OUT)
W*
1
TB1CLK1
R/W
1
192H
TB1CLE
19FH
R
high
Undefined
91CW28-266
2006-03-24
TMP91CW28
(8) UART serial channel
Mnemonic
Name
Serial
channel 1
SC1BUF
buffer
register
Address
7
6
5
4
3
2
1
0
208H
RB7/TB7
RB6/TB6
RB5/TB5
RB4/TB4
RB3/TB3
RB2/TB2
RB1/TB1
RB0/TB0
FERR
SCLKS
IOC
R (Receive)/W (Transmit)
(RMW
prohibited)
Undefined
RB8
SC1CR
Serial
channel 1
control
register
EVEN
PE
R
209H
Undefined
Bit8 of a
received
character
TB8
OERR
R/W
0
PERR
R (Cleared to “0” when read)
0
Parity type 1: Parity
enable
0: Odd
0
0
R/W
0
0
Error has occurred
Overrun
Parity
Framing
WU
SM1
SM0
0
0
0
0: SCLK↑ 1: SCLK1
input
1: SCLK↓
1: Even
CTSE
RXE
SC1
SC0
0
0
R/W
Serial
channel 1
SC1MOD0
mode
register
0
20AH
0
0
Hand
Bit8 of a
transmitted shake
character control
Receive
control
1: Enables
CTS
operation
−
BR1ADDE
1: Enables
receiver
BR1CK1
0
Wakeup
function
Serial transfer mode
Serial clock (for UART)
00: I/O interface mode
1: Enabled 01: 7-bit UART mode
00: TA0TRG
01: Baud rate generator
10: 8-bit UART mode
10: Internal fSYS clock
11: 9-bit UART mode
11: External clock
(SCLK input)
BR1CK0
BR1S3
BR1S2
BR1S1
BR1S0
0
0
0
0
R/W
BR1CR
Baud rate
control
register
0
20BH
Must be
written as
“0”.
0
0
0
00: φT0
Setting of the divided frequency “N”
function
01: φT2
(0 to F)
1: Enabled
10: φT8
N + (16 − K)/16
11: φT32
BR1K3
Serial
channel 1
BR1ADD
K setting
register
Serial
channel 1
SC1MOD1
mode1
register
BR1K2
BR1K1
BR1K0
0
0
R/W
20CH
0
0
Sets frequency divisor “K”
(Divided by N + (16 − K)/16)
20DH
I2S1
FDPX1
R/W
R/W
0
0
IDLE2
Synchronous
0: OFF
0: Half
duplex
1: ON
1: Full
duplex
91CW28-267
2006-03-24
TMP91CW28
(9) I2C bus serial bus interface (1/2)
2
(9−1) I C/SIO Channel 0
Mnemonic
Name
Address
7
6
5
4
2
1
0
BC2
BC1
BC0
ACK
SCK2
SCK1
SCK0
/SWRMON
R/W
W
W
R/W
240H
W
2
(I C bus
mode)
(RMW
prohibited) 000: 8,
001: 1, 010: 2
0
ACK clock
pulse
000: 5,
001: 6,
010: 7
011: 3,
100: 4, 101: 5
0: No ACK
011: 8,
100: 9,
101: 10
110: 6,
111: 7
1: ACK
110: 11,
111: Reserved
Serial bus
interface
SBI0CR1
control
register 1
240H
(SIO
mode)
0
0
0
Number of bits per transfer
3
0
0
0/1
Serial clock frequency (on writes)
SIOS
SIOINH
SIOM1
SIOM0
SCK2
SCK1
SCK0
W
W
W
W
W
W
W
0
Start
transfer
(RMW
prohibited) 0: Stop
1: Start
0
Abort
transfer
0
0
Transfer mode
0
0
0
Serial clock frequency (on writes)
00: 8-bit transmit mode
0: Continue 10: 8-bit transmit/receive
mode
1: Abort
000: 4,
001: 5,
010: 6
011: 7,
100: 8,
101: 9
110: 10,
111: External clock (input from
the SCK pin)
11: 8-bit receive mode
SBI0DBR
SBI
241H
buffer
(RMW
prohibited)
register
2
I C bus
I2C0AR
address
register
242H
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R (Receive)/W (Transmit)
Undefined
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ALS
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
Address
Recognition
(RMW
prohibited)
Slave address
0 : Recognize
1 : Does not
recognize
When
read
SBI0SR
Serial bus
interface
status
register
243H
2
(I C bus
mode)
Serial bus
interface
write
control
SBI0CR2
register 2
When
When
read
SBI0SR
TRX
BB
PIN
R/W
R/W
R/W
R/W
0
(RMW
prohibited)
Serial bus
interface
status
register
MST
0: Slave
1: Master
0
0
1
Bus status INTSBI0
interrupt
1: Transmit monitor
status
0: Free
0: Receive
1: Busy
0: Asserted
1: Not asserted
Start/stop
condition
generation
0: Start
condition
1: Stop
condition
AL/SBIM1 AAS/SBIM0
R/W
0
Arbitration
lost
detection
monitor
1: Detect
0
Slave
address
match
detection
monitor
1: Detect
Serial bus interface
operating mode
selection
00: Port mode
01: SIO mode
2
10: I C bus mode
11: (Reserved)
(SIO
mode)
91CW28-268
R/W
0
GENERAL
CALL
detection
monitor
1: Detect
0
Last
receive bit
monitor
0: 0
1: 1
Software reset generate
write “10” and “01”, then
an internal software
reset signal is
generated.
−
−
R/W
R/W
W
W
0
0
0
Shift
operation
status
monitor
0: Stopped
1: Terminated
in process
Serial bus interface
operating mode
selection
00: Port mode
01: SIO mode
2
10: I C bus mode
11: (Reserved)
Serial bus
When
interface
write
control
SBI0CR2
register 2
R/W
SEF/
SBIM2
0: Stopped
1: Terminated
in process
(RMW
prohibited)
LRB/
SWRST0
SIOF/
SBIM1
0
Transfer
status
monitor
243H
R/W
AD0/
SWRST
Always
write “0”.
Always
write “0”.
2006-03-24
TMP91CW28
Mnemonic
SBI0BR0
SBI0BR1
Name
Address
7
6
−
I2SBI0
5
4
3
2
1
0
W
R/W
Serial bus
interface
244H
0
0
baud rate
(RMW Must be
IDLE2
register 0 prohibited) written as
0: OFF
“0”.
1: ON
P4EN
−
W
W
Serial bus
245H
0
interface
(RMW
Internal
baud rate
prohibited) clock
register 1
0: OFF
0
Must be
written as
“0”.
1: ON
91CW28-269
2006-03-24
TMP91CW28
I2C bus serial bus interface (2/2)
2
(9−2) I C/SIO Channel 1
Mnemonic
Name
Address
248H
2
(I C bus
mode)
7
6
5
4
BC2
BC1
BC0
W
0
0
0
Number of bits per transfer
(RMW
prohibited)
SBI1CR1
Serial bus
interface
control
register 1
248H
(SIO
mode)
(RMW
prohibited)
SBI1DBR
SBI
249H
buffer
(RMW
prohibited)
register
2
I C bus
I2C1AR
address
register
24AH
3
2
1
ACK
SCK2
SCK1
R/W
W
W
0
SCK0/
SWRMON
R/W
0
0
0/1
0
000: 8,
001: 1,
010: 2
ACK clock
pulse
Serial clock frequency (on writes)
000: 5,
001: 6,
010: 7
011: 3,
100: 4,
101: 5
0: No ACK
011: 8,
100: 9,
101: 10
110: 6,
SIOS
111: 7
SIOINH
1: ACK
110: 11,
SCK2
111: Reserved
SCK1
SCK0
W
W
SIOM1
SIOM0
W
W
W
W
W
0
0
0
0
0
0
0
Start
transfer
Abort
transfer
Transfer mode
Serial clock frequency (on writes)
00: 8-bit transmit mode
000: 4,
001: 5,
010: 6
0: Stop
0:
Continue
10: 8-bit
transmit/receive mode
011: 7,
100: 8,
101: 9
1: Abort
11: 8-bit receive mode
1: Start
DB7
DB6
DB5
110: 10, 111: External clock
(input from the SCK pin)
DB4
DB3
DB2
DB1
DB0
R (Receive)/W (Transmit)
Undefined
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ALS
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
Address
Recognition
(RMW
prohibited)
Slave address
0: Recognize
1: Does not
recognize
When
read
SBI1SR
Serial bus
interface
status
register
24BH
2
(I C bus
mode)
(RMW
prohibited)
Serial bus
When
interface
write
control
SBI1CR2
register 2
MST
TRX
BB
PIN
R/W
R/W
R/W
R/W
0
0
0: Slave
1: Master
0
1
0: Receive Bus status INTSBI1
interrupt
1: Transmit monitor
status
0: Free
1: Busy
0: Asserted
1: Not asserted
AL/SBIM1 AAS/SBIM0
R/W
0
Arbitration
lost
detection
monitor
1: Detect
Serial bus
interface
status
register
0
Slave
address
match
detection
monitor
1: Detect
Start/stop
condition
generation
Serial bus interface
operating mode selection
0: Start
condition
1: Stop
condition
01: SIO mode
00: Port mode
10: I2C bus mode
0
Transfer
status
monitor
24BH
(SIO mode)
0: Stopped
1: Terminated
in process
(RMW
prohibited)
91CW28-270
0
GENERAL
CALL
detection
monitor
1: Detect
0
Last receive
bit monitor
0: 0
1: 1
Software reset generate
write “10” and “01”, then
an internal software
reset signal is
generated.
SEF/
SBIM2
R/W
−
−
W
W
0
0
0
Shift
operation
status
monitor
0: Stopped
1: Terminated
in process
Serial bus interface
operating mode selection
00: Port mode
01: SIO mode
10: I2C bus mode
11: (Reserved)
Serial bus
When
interface
write
control
SBI1CR2
register 2
LRB/
SWRST0
R/W
11: (Reserved)
SIOF/
SBIM1
R/W
When
read
SBI1SR
R/W
AD0/
SWRST
R/W
Always
write “0”.
Always
write “0”.
2006-03-24
TMP91CW28
Mnemonic
SBI1BR0
SBI1BR1
Name
Address
7
6
−
I2SBI1
5
4
3
2
1
0
R/W
R/W
Serial bus
24CH
interface
0
0
(RMW
baud rate
Must
be
IDLE2
register 0 prohibited) written as
0: OFF
“0”.
1: ON
P4EN
−
W
W
Serial bus
24DH
0
interface
(RMW
Internal
baud rate
prohibited) clock
register 1
0: OFF
0
Must be
written as
“0”.
1: ON
91CW28-271
2006-03-24
TMP91CW28
(10) A/D converter control
Mnemonic
Name
Address
7
6
5
4
3
2
1
0
EOCF
ADBF
−
−
ITM0
REPEAT
SCAN
ADS
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
R
0
ADMOD0
AD mode
register 0
2B0H
0
End-ofAD
Must be
conversion conversion written as
flag
busy flag
“0”.
Must be
written as
“0”.
timing in
fixed-channel
Channel
AD
conversion scan
conversion
conversion start
1: Continuous
continuous
1: Conversion 1: Conversion
completed
Interrupt
conversion
in progress
mode
VREFON
I2AD
ADTRGE
R/W
R/W
R/W
0
0
1: VREF
control ON
ADMOD1
AD mode
register 1
0
AD
conversion
start
IDLE2
0: OFF
1: ON
2B1H
ADCH2
ADCH1
ADCH0
R/W
0
0
0
Analog input channel select
000: AN0 AN0
001: AN1 AN0 → AN1
010: AN2 AN0 → AN1 → AN2
011: AN3 AN0 → AN1 → AN2 → AN3
100: AN4 AN4
101: AN5 AN4 → AN5
110: AN6 AN4 → AN5 → AN6
111: AN7 AN4 → AN5 → AN6 → AN7
ADR01
AD result
ADREG04L
register 0/4
low
2A0H
register 0/4
high
register 1/5
low
register 1/5
high
register 2/6
low
register 2/6
high
register 3/7
low
register 3/7
high
ADR05
ADR04
ADR03
ADR02
ADR1RF
R
R
Undefined
0
ADR18
ADR17
ADR16
2A3H
ADR15
ADR14
ADR13
ADR12
R
Undefined
ADR21
2A4H
ADR20
ADR2RF
R
R
Undefined
0
ADR29
ADR28
ADR27
ADR26
2A5H
ADR25
ADR24
ADR23
ADR22
R
Undefined
ADR31
2A6H
ADR30
ADR3RF
R
R
Undefined
ADR39
AD result
ADREG37H
ADR06
ADR10
ADR19
AD result
ADREG37L
ADR07
R
2A2H
AD result
ADREG26H
ADR08
Undefined
AD result
ADREG26L
0
ADR11
AD result
ADREG15H
R
2A1H
AD result
ADREG15L
ADR0RF
Undefined
ADR09
AD result
ADREG04H
ADR00
R
0
ADR38
ADR37
ADR36
2A7H
ADR35
ADR34
ADR33
ADR32
R
Undefined
91CW28-272
2006-03-24
TMP91CW28
(11) Watchdog timer
Mnemonic
WDMOD
WDCR
Name
WDT
mode
register
WDT
control
Address
300H
7
6
5
2
1
0
WDTE
WDTP1
WDTP0
4
3
I2WDT
RESCR
−
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
WDT
control
00: 215/fSYS
IDLE2
01: 217/fSYS
0: OFF
0: Disable
10: 219/fSYS
1: ON
1: Enable
11: 221/fSYS
0
System
reset by
WDT
Must be
written
as “0”.
1: Reset
−
301H
W
(RMW
prohibited)
−
B1H: WDT disable code,
4EH: WDT clear-count code
(12) Key wakeup
Mnemonic
KWIEN
Name
KWI
enable
register
KWI
KWICR
Address
3A0H
(RMW
prohibited)
3A1H
control
register
(RMW
prohibited)
7
6
5
4
3
2
1
0
KWI7EN
KWI6EN
KWI5EN
KWI4EN
KWI3EN
KWI2EN
KWI1EN
KWI0EN
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
KWI7
interrupt
input
KWI6
interrupt
input
KWI5
interrupt
input
KWI4
interrupt
input
KWI3
interrupt
input
KWI2
interrupt
input
KWI1
interrupt
input
KWI0
interrupt
input
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
KWI7EDGE
KWI6EDGE
KWI5EDGE
KWI4EDGE
KWI3EDGE
KWI2EDGE
KWI1EDGE
KWI0EDGE
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
KWI7 edge
polarity
KWI6 edge
polarity
KWI5 edge
polarity
KWI4 edge
polarity
KWI3 edge
polarity
KWI2 edge
polarity
KWI1 edge
polarity
KWI0 edge
polarity
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
0: Rising
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
1: Falling
91CW28-273
0
2006-03-24
TMP91CW28
(13) BCD adder/subtractor
Mnemonic
BCDMINA
BCDSECA
BCDFRAA
BCDMINB
BCDSECB
BCDFRAB
BCDMINR
BCDSECR
BCDFRAR
BCDCR
Name
7
6
5
4
3
2
1
0
BCD
3B0H
minute
(RMW
operand
register A prohibited)
MINA7
MINA6
MINA5
MINA4
MINA3
MINA2
MINA1
MINA0
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
BCD
3B1H
second
(RMW
operand
prohibited)
register A
SECA7
SECA6
SECA5
SECA4
SECA3
SECA2
SECA1
SECA0
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
BCD
3B2H
frame
(RMW
operand
register A prohibited)
FRAA7
FRAA6
FRAA5
FRAA4
FRAA3
FRAA2
FRAA1
FRAA0
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
BCD
3B4H
minute
(RMW
operand
prohibited)
register B
MINB7
MINB6
MINB5
MINB4
MINB3
MINB2
MINB1
MINB0
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
BCD
3B5H
second
(RMW
operand
register B prohibited)
SECB7
SECB6
SECB5
SECB4
SECB3
SECB2
SECB1
SECB0
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
BCD
3B6H
frame
(RMW
operand
prohibited)
register B
FRAB7
FRAB6
FRAB5
FRAB4
FRAB3
FRAB2
FRAB1
FRAB0
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
MINR7
MINR6
MINR5
MINR4
MINR3
MINR2
MINR1
MINR0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
SECR7
SECR6
SECR5
SECR4
SECR3
SECR2
SECR1
SECR0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
FRAR7
FRAR6
FRAR5
FRAR4
FRAR3
FRAR2
FRAR1
FRAR0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
ENDFLAG
CY
BR
−
CALSEL
START
R
R
R
R/W
R/W
R/W
BCD
minute
result
register
BCD
second
result
register
BCD
frame
result
register
BCD
control
register
Address
3B8H
BCD operand A
BCD operand A
BCD operand A
BCD operand B
BCD operand B
BCD operand B
BCD operation result
3B9H
BCD operation result
3BAH
BCD operation result
3BCH
0
0
0
0
Operation
completion
flag
Carry
Borrow
Must be
written
as “0”.
0
0
Add/subtract
select
Operation
start
1: Completed
91CW28-274
2006-03-24
TMP91CW28
(14) Program patch logic (1/3)
Mnemonic
Name
Address
7
ROMC07
ROMCMP00
400H
Address
compare
(RMW
register 00 prohibited)
6
5
4
3
2
1
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
W
0
0
Target ROM address (Lower 7 bits)
ROMC15
401H
Address
ROMCMP01 compare
(RMW
register 01 prohibited)
ROMC14
ROMC13
ROMC12
0
0
0
W
0
Target ROM address (Middle 8 bits)
ROMC23
402H
Address
ROMCMP02 compare
(RMW
register 02 prohibited)
ROMC22
ROMC21
ROMC20
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
W
0
Target ROM address (Upper 8 bits)
ROMS07
Address
404H
substitution
ROMSUB0L
(RMW
register 0
0
prohibited)
low
ROMS06
ROMS15
ROMS14
Address
405H
substitution
ROMSUB0H
(RMW
register 0
prohibited)
high
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
ROMC03
ROMC02
ROMC01
0
0
0
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
W
0
0
0
Patch code (Lower 8 bits)
ROMS13
ROMS12
W
0
0
0
0
ROMC06
ROMC05
Patch code (Upper 8 bits)
ROMC07
408H
Address
ROMCMP10 compare
(RMW
register 10 prohibited)
ROMS05
ROMC04
W
0
0
0
0
Target ROM address (Lower 7 bits)
ROMC15
409H
Address
ROMCMP11 compare
(RMW
register 11 prohibited)
ROMC14
ROMC13
ROMC12
W
0
0
0
0
Target ROM address (Middle 8 bits)
ROMC23
40AH
Address
ROMCMP12 compare
(RMW
register 12 prohibited)
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
W
0
0
0
0
Target ROM address (Upper 8 bits)
ROMS07
Address
40CH
substitution
ROMSUB1L
(RMW
register 1
0
prohibited)
low
ROMS06
ROMS15
ROMS14
Address
40DH
substitution
ROMSUB1H
(RMW
register 1
prohibited)
high
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
W
0
0
0
Patch code (Lower 8 bits)
ROMS13
ROMS12
W
0
0
0
0
Patch code (Upper 8 bits)
91CW28-275
2006-03-24
TMP91CW28
Program patch logic (2/3)
Mnemonic
ROMCMP20
Name
Address
410H
Address
compare
(RMW
register 20 prohibited)
7
6
5
4
3
2
1
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
0
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
W
0
Target ROM address (Lower 7 bits)
411H
Address
ROMCMP21 compare
(RMW
register 21 prohibited)
ROMC15
ROMC14
ROMC13
ROMC12
0
0
0
0
W
Target ROM address (Middle 8 bits)
412H
Address
ROMCMP22 compare
(RMW
register 22 prohibited)
ROMC23
ROMC22
ROMC21
ROMC20
0
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
W
Target ROM address (Upper 8 bits)
ROMS07
Address
414H
substitution
ROMSUB2L
(RMW
register 2
0
prohibited)
low
ROMS06
ROMS15
ROMS14
Address
415H
substitution
ROMSUB2H
(RMW
register 2
prohibited)
high
418H
Address
ROMCMP30 compare
(RMW
register 30 prohibited)
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
ROMC03
ROMC02
ROMC01
0
0
0
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
W
0
0
0
Patch code (Lower 8 bits)
ROMS13
ROMS12
W
0
0
0
0
ROMC07
ROMC06
ROMC05
Patch code (Upper 8 bits)
ROMC04
W
0
0
0
0
Target ROM address (Lower 7 bits)
ROMC15
419H
Address
ROMCMP31 compare
(RMW
register 31 prohibited)
ROMC14
ROMC13
ROMC12
W
0
0
0
0
Target ROM address (Middle 8 bits)
ROMC23
41AH
Address
ROMCMP32 compare
(RMW
register 32 prohibited)
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
W
0
0
0
0
Target ROM address (Upper 8 bits)
ROMS07
Address
41CH
substitution
ROMSUB3L
(RMW
register 3
0
prohibited)
low
ROMS06
ROMS15
ROMS14
Address
41DH
substitution
ROMSUB3H
(RMW
register 3
prohibited)
high
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
W
0
0
0
Patch code (Lower 8 bits)
ROMS13
ROMS12
W
0
0
0
0
Patch code (Upper 8 bits)
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Program patch logic (3/3)
Mnemonic
ROMCMP40
Name
Address
420H
Address
compare
(RMW
register 40 prohibited)
7
6
5
4
3
2
1
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
0
0
0
0
0
0
0
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
W
0
Target ROM address (Lower 7 bits)
421H
Address
ROMCMP41 compare
(RMW
register 41 prohibited)
ROMC15
ROMC14
ROMC13
ROMC12
0
0
0
0
W
Target ROM address (Middle 8 bits)
422H
Address
ROMCMP42 compare
(RMW
register 42 prohibited)
ROMC23
ROMC22
ROMC21
ROMC20
0
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
W
Target ROM address (Upper 8 bits)
ROMS07
Address
424H
substitution
ROMSUB4L
(RMW
register 4
0
prohibited)
low
ROMS06
ROMS15
ROMS14
Address
425H
substitution
ROMSUB4H
(RMW
register 4
prohibited)
high
428H
Address
ROMCMP50 compare
(RMW
register 50 prohibited)
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
ROMC03
ROMC02
ROMC01
0
0
0
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
W
0
0
0
Patch code (Lower 8 bits)
ROMS13
ROMS12
W
0
0
0
0
ROMC07
ROMC06
ROMC05
Patch code (Upper 8 bits)
ROMC04
W
0
0
0
0
Target ROM address (Lower 7 bits)
ROMC15
429H
Address
ROMCMP51 compare
(RMW
register 51 prohibited)
ROMC14
ROMC13
ROMC12
W
0
0
0
0
Target ROM address (Middle 8 bits)
ROMC23
42AH
Address
ROMCMP52 compare
(RMW
register 52 prohibited)
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
W
0
0
0
0
Target ROM address (Upper 8 bits)
ROMS07
Address
42CH
substitution
ROMSUB5L
(RMW
register 5
0
prohibited)
low
ROMS06
ROMS15
ROMS14
Address
42DH
substitution
ROMSUB5H
(RMW
register 5
prohibited)
high
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
W
0
0
0
Patch code (Lower 8 bits)
ROMS13
ROMS12
W
0
0
0
0
Patch code (Upper 8 bits)
91CW28-277
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TMP91CW28
6.
I/O Port Equivalent-circuit Diagrams
•
How to read circuit diagrams
The circuit diagrams in this chapter are drawn using the same gate symbols as for the
74HCxx series standard CMOS logic ICs.
The signal named STOP has a unique function. This signal goes active-high if the CPU sets
the HALT bit when the HALTM[1:0] field in the SYSCR2 register is programmed to 01 (e.g.,
STOP mode) and the drive enable (DRVE) bit in the same register is cleared. If the DRVE bit is
set, the STOP signal remains inactive (at logic 0).
•
■
The input protection circuit has a resistor in the range of several tens to several hundreds of
ohms.
Port 0 (AD0 to AD7), Port 1 (AD8 to AD15, A8 to A15), Port 2 (A16 to A23, A0 to A7)
VCC
Output data
P-ch
Output enable
STOP
N-ch
Input/output
Input data
Input enable
■
P30 ( RD ), P31 ( WR )
Vcc
Output data
P-ch
Output
STOP
N-ch
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■ P32 to P37
Vcc
Output data
P-ch
Output enable
STOP
Vcc
Programmable
pull-up resistor
N-ch
Input/output
Input data
Input enable
■
Port 5 (AN0 to AN7)
Analog input
channel select
P-ch
Analog input
Input
N-ch
Input data
Input enable
KWI0 to KWI7
Schmitt trigger
ADTRG
(P53 only)
■
P63 (INT0)
Vcc
Output data
P-ch
Output enable
STOP
N-ch
Input data
Input/output
Schmitt trigger
■
P40 to P43, P70 to P75, P80 to P87, PA0 to PA7
Vcc
Output data
P-ch
Output enable
STOP
N-ch
Input data
Vcc
Programmable
pull-up resistor
Input/output
Schmitt trigger
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■
P61 (SO0/SDA0), P62 (SI0/SCL0), P91 (SO1/SDA1), P92 (SI1/SCL1), P93 (TXD1)
Vcc
Output data
P-ch
Open-drain output
enable
Vcc
N-ch
Programmable
pull-up resistor
STOP
Pull-up enable
Input/output
Input data
Schmitt trigger
■
P60, P64 to P66, P90, P93 to P96
Vcc
Output data
P-ch
Output enable
STOP
N-ch
Input/output
Input data
Schmitt trigger
■
NMI
NMI
Input
Schmitt trigger
■
AM0, AM1
Input
■
ALE
Vcc
Internal ALE
P-ch
Output
Output enable
N-ch
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■
RESET
Vcc
P-ch
Input
Reset
Schmitt trigger
WDTOUT
Reset enable
■
X1, X2
Oscillator circuit
P-ch
High-frequency
oscillator enable
x2
N-ch
x1
Clock
VREFH, VREFL
VREFON
P-ch
VREFH
Ladder resistors
■
VREFL
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7.
Points of Note and Restrictions
(1) Notations and terms
a.
I/O register fields are often referred to as <register_mnemonic>.<field_name> for the
interest of brevity. For example, TRUN.T0RUN means the T0RUN bit in the TRUN
register.
b.
Read-modify-write instructions
Read-modify-write instructions allow the CPU to read data from memory, manipulate the
data and then write the result to the same memory address, through the execution of a
single instruction.
•
Example 1: SET 3, (TRUN)
Sets bit3 of the TRUN register.
Example 2: INC 1, (100H)
Increments the data at address 100H by one.
Read-modify-write instructions supported by the TLCS-900.
Exchange
EX
(mem), R
Arithmetical operation
ADD (mem), R/#
SUB (mem), R/#
INC #3, (mem)
Logical operation
AND (mem), R/#
XOR (mem), R/#
OR
Bit manipulation
STCF #3/A, (mem)
SET #3, (mem)
TSET #3, (mem)
RES #3, (mem)
CHG #3, (mem)
Rotation and shift
RLC (mem)
RL
(mem)
SLA (mem)
SLL (mem)
RLD (mem)
c.
ADC (mem), R/#
SBC (mem), R/#
DEC #3, (mem)
RRC
RR
SRA
SRL
RRD
(mem), R/#
(mem)
(mem)
(mem)
(mem)
(mem)
fc, fFPH, fSYS, state
fOSCH, fc: Clock frequency supplied via the X1 and X2 pins
fFPH: Clock frequency selected by the GEAR[2:0] bit in the SYSCR1
fSYS: System clock frequency, created by dividing fFPH by two
1 state: One period of fSYS
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(2) Precautions and restrictions
a.
AM0 and AM1 pins
The AM0 and AM1 pins must be connected to the DVCC pin to ensure that their signal
levels do not fluctuate during chip operation.
b.
EMU0 and EMU1 pins
The EMU0 and EMU1 pins must be left open.
c.
Reserved address space
The TMP91CW28 does not have any address space reserved.
d.
Oscillator warm-up counter
If an external crystal is utilized, an interrupt signal programmed to bring the
TMP91CW28 out of STOP mode triggers the on-chip warm-up counter. The system clock is
not supplied to the on-chip logic until the warm-up counter expires.
e.
Programmable pull-up resistors
When port pins are configured as input ports, the integrated pull-up resistors can be
enabled and disabled under software control. The pull-up resistors are not programmable
when port pins are configured as output ports, except for P61, P62, P91 and P92.
The relevant port registers (e.g., the P6 register) must be programmed by using store
instructions; read-modify-write instructions cannot be used.
f.
External bus mastership
The pin states while the bus is granted to an external device are described in section 3.5,
I/O ports.
g.
Watchdog timer
Upon reset, the watchdog timer is enabled. If the watchdog timer function is not required,
it must be disabled after reset.
h.
Watchdog timer
When relevant pins are configured as bus arbitration signals, the I/O peripherals
including the watchdog timer can operate during external bus mastership.
i.
AD converter
The ladder resistor network between the VREFH and VREFL pins can be disconnected
under software control. If it is necessary to reduce power dissipation in STOP mode, the
ladder resistor network should be disconnected before executing the HALT instruction.
j.
CPU (Micro DMA)
Only the “LDC cr, r” and “LDC r, cr” instructions can write or read control registers
within the CPU, such as the transfer source register (DMASn).
k.
Undefined bits in I/O registers
Undefined I/O register bits are read as undefined states. Therefore, software must be
coded without relying on the states of any undefined bits.
l.
POP SR instruction
The POP SR instruction must be executed in DI mode.
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8.
Package Dimensions
P-LQFP100-1414-0.50F
Unit: mm
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