TOSHIBA TMP88CP34NG

TMP88CS34/CP34
CMOS 8-Bit Microcontroller
TMP88CS34NG/FG, TMP88CP34NG/FG
The TMP88CS34/CP34 is the high speed and high performance 8-bit single chip microcomputers. This
MCU contain CPU core, ROM, RAM, input/output ports, four Multi-function timer/counters, serial bus
interface, on-screen display, PWM output, 8-bit AD converter, and remote control signal preprocessor on
chip.
Product No.
ROM
TMP88CS34NG/FG
64 K × 8-bit
TMP88CP34NG/FG
48 K × 8-bit
RAM
1.5 K × 8-bit
Package
P-SDIP42-600-1.78
P-QFP44-1414-0.80D
OTP MCU
TMP88PS34NG/FG
Features
◆ 8-bit single chip microcomputer TLCS-870/X Series
◆ Instruction execution time: 0.25 μs (at 16 MHz)
◆ 842 basic instructions
• Multiplication and Division (8 bits × 8 bits, 16 bits × 8 bits, 16 bits/8 bits)
• Bit manipulations (Set/Clear/Complement/Move/Test/Exclusive or)
• 16-bit data and 20-bit data operations
• 1-byte jump/subroutine-call (Short relative jump/Vector call)
RESTRICTIONS ON PRODUCT USE
20070701-EN
• The information contained herein is subject to change without notice.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety
in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc.
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer,
personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These
TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high
quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury
(“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical
instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall
be made at the customer’s own risk.
• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third
parties.
• Please contact your sales representative for product-by-product details in this document regarding RoHS
compatibility. Please use these products in this document in compliance with all applicable laws and regulations that
regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring
as a result of noncompliance with applicable laws and regulations.
88CS34-1
2007-09-12
TMP88CS34CP34
◆ I/O ports: Maximum 33 (High current output: 4)
◆ 15 interrupt sources: External 6, Internal 10
• All sources have independent latches each, and nested interrupt control is available.
• Edge-selectable external interrupts with noise reject
• High-speed task switching by register bank changeover
◆ ROM corrective function
◆ Two 16-bit timer/counters: TC1, TC2
• Timer, Event-counter, Pulse width measurement, External trigger timer, Window modes
◆ Two 8-bit timer/counters: TC3, TC4
• Timer, Event counter, Capture (Pulse width/duty measurement) mode
◆ Time base timer (Interrupt frequency: 0.95 Hz to 31250 Hz)
◆ Watchdog timer
• Interrupt source/reset output
◆ Serial bus interface
• I2C bus, 8-bit SIO mode (Selectable two I/O channels)
◆ On-screen display circuit
• Font ROM characters: Mono font 383 characters, color font 96 characters or mono font 447
characters, color font 64 characters
• Characters display: 32 columns × 12 lines
• Composition: 16 × 18 dots
• Size of character: 4 kinds (line by line)
• Color of character: 8 or 27 kinds (character by character)
• Variable display position: Horizontal 256 steps, Vertical 625 steps
• Fringing, Smoothing, Slant, Underline , Blinking function
◆ Jitter elimination
◆ DA conversion (Pulse Width Modulation) outputs
• 14/12-bit resolution (2 channels)
• 12-bit resolution (2 channels)
◆ 8-bit successive approximate type AD converter with sample and hold
◆ High current output: 1 pin (typ. 20 mA)
◆ Remote control signal preprocessor
◆ Two power saving operating modes
• STOP mode: Oscillation stops. Battery/Capacitor back-up. Port output hold/high-impedance.
• IDLE mode: CPU stops, and Peripherals operate using high-frequency clock. Release by
interrupts.
◆ Operating voltage: 4.5 to 5.5 V at 16 MHz
◆ Emulation POD: BM88CS34N0A-M15
88CS34-2
2007-09-12
TMP88CS34CP34
Pin Assignments
Package
P-SDIP42-600-1.78
P-SDIP42-600-1.78
TMP88CS34NG
TMP88CP34NG
TMP88PS34NG
VSS
( PWM0 ) P40
( PWM1 ) P41
( PWM2 ) P42
( PWM3 ) P43
P44
P45
P46
P47
(TC2/ INT0 ) P50
(SI1/SCL1) P51
(SO1/SDA1) P52
( KWU0 / SCK1 /INT2/TC1/AIN0) P53
( KWU1 /AIN1) P54
( KWU2 /AIN2) P55
( KWU3 /AIN3) P56
( KWU 4 /Y/BLIN/AIN4) P60
( KWU5 /BIN/AIN5) P61
(GIN) P62
(RIN) P63
(I) P57
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
P33 (TC4)
P32
VVSS
P35 (SDA0)
P34 (SCL0)
P31 (INT4/TC3)
P30 (INT3/RXIN)
P20 ( INT5 / STOP )
RESET
XOUT
XIN
TEST
OSC2
OSC1
P71 ( VD )
P70 ( HD )
P67 (Y/BL)
P66 (B)
P65 (G)
P64 (R)
Package
P-QFP44-1414-0.80D
XOUT
XIN
TEST
OSC2
OSC1
P71 (VD)
TMP88CS34FG
RESET
P34 (SCL0)
P31 (INT4/TC3)
P30 (INT3/RXIN)
P20 (INT5/STOP)
P-QFP44-1414-0.80D
1
2
3
4
5
6
7
8
9
10
11
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P70 ( HD )
P67 (Y/BL)
P66 (B)
P65 (G)
P64 (R)
N.C.
P57
P63 (RIN)
P62 (GIN)
P61 (BIN//AIN5/ KWU5 )
P60 (Y/BLIN/AIN4/ KWU4 )
P44
P45
P46
P47
(TC2/INT0) P50
(SI1/SCL1) P51
(SO1/SDA1) P52
(KWU0/SCK1/INT2/TC1/AIN0) P53
(KWU1/AIN1) P54
(KWU2/AIN2) P55
(KWU3/AIN3) P56
(SDA0) P35
VVSS
P32
(TC4) P33
N.C.
VDD
VSS
( PWM0 ) P40
( PWM1 ) P41
( PWM2 ) P42
( PWM3 ) P43
33
32
31
30
29
28
27
26
25
24
23
TMP88CP34FG
TMP88PS34FG
88CS34-3
2007-09-12
TMP88CS34CP34
Pin Functions (1/2)
Pin Name
P20 ( INT5 / STOP )
I/O
I/O (Input)
P35 (SDA0)
I/O (Input/Output)
P34 (SCL0)
I/O (Input/Output)
P33 (TC4)
P32
I/O (Input)
I/O
P31 (INT4/TC3)
I/O (Input)
P30 (INT3/RXIN)
I/O (Input)
P47
I/O
P46
I/O
P45
I/O
P44
I/O
P43 ( PWM3 )
I/O (Output)
P42 ( PWM2 )
I/O (Output)
P41 ( PWM1 )
I/O (Output)
P40 ( PWM0 )
I/O (Output)
P57 (I)
I/O (Output)
P56 ( KWU3 /AIN3)
I/O (Input)
P55 ( KWU2 /AIN2)
I/O (Input)
P54 ( KWU1 /AIN1)
I/O (Input)
P53
( KWU0 /AIN0/TC1
/INT2/ SCK1 )
I/O
P52 (SDA1/SO1)
P51 (SCL1/SI1)
P50 (TC2/ INT0 )
(Input/Input/Input
/Input/Output)
1-bit input/output port with latch.
When used as an input port, the
latch must be set to “1”.
6-bit programmable input/output
port. Each bit of these ports can be
individually configured as an input or
an output under software control.
During reset, all bits are configured
as inputs. When used as a serial bus
interface input/output, the latch must
be set to “1”.
External interrupt input 5 or STOP
mode release signal input
2
I C bus serial data input/output 0
2
I C bus serial clock input/output 0
Video signal input 1 or Composite
sync input
External interrupt input 4 or
Timer/Counter input 3
External interrupt input 3 or Remote
control signal preprocessor input
8-bit programmable input/output
port. Each bit of these ports can be
individually configured as an input or
an output under software control.
During reset, all bits are configured
as inputs.
12-bit DA conversion (PWM) outputs
14/12-bit DA conversion (PWM)
outputs
8-bit programmable input/output
port. Each bit of these ports can be
individually configured as an input or
an output under software control.
During reset, all bits are configured
as inputs. When used as a serial bus
interface input/output, the latch must
be set to “1”.
Translucent signal output
Key on wake-up inputs or AD
converter analog inputs
Key on wake-up input or AD
converter analog input or
Timer/counter input 1 or External
interrupt input 2 or SIO serial clock
input/output 1
2
I/O
(Input/Output/Output)
I C bus serial data Input/Output 1 or
SIO serial data output 1
I/O
(Input/Output/Input)
I C bus serial data Input/Output 1 or
SIO serial data input 1
2
I/O
Timer/Counter input 2 or External
interrupt input 0
(Input/Input)
P67 (Y/BL)
I/O (Output)
P66 (B)
I/O (Output)
P65 (G)
I/O (Output)
P64 (R)
I/O (Output)
P63 (RIN)
I/O (Input)
P62 (GIN)
I/O (Input)
P61
( KWU5 /BIN/AIN5)
I/O (Input)
P60
( KWU4 /YBLIN/AIN4)
Function
I/O (Input)
8-bit programmable input/output
port. (P67 to 61: Tri-State, P60: High
current output) Each bit of these
ports can be individually configured
as an input or an output under
software control. During reset, all
bits are configured as inputs. When
used P64 to P67 as port, each bit of
the P6 port data selection register
(bit 7 to 4 in ORP6S) must be set to
“1”.
P63 to P61 output “0” after a reset.
When these dual-function pins are
used as ports, be sure to set
ORP6S2 to “1”.
88CS34-4
Y or BL output
R/G/B outputs
R input
G input
Key on wake-up input 5 or B input or
AD converter analog input 5
Key on wake-up input 4 or Y/BL
input or AD converter analog input 4
2007-09-12
TMP88CS34CP34
Pin Functions (2/2)
Pin Name
I/O
P71 ( VD )
I/O (Input)
P70 ( HD )
I/O (Input)
XIN, XOUT
Input, Output
RESET
TEST
I/O
Input
Function
2-bit programmable input/output
port. Each bit of these ports can be
individually configured as an input or
an output under software control.
During reset, all bits are configured
as inputs.
Vertical synchronous signal input
Horizontal synchronous signal input
Resonator connecting pins. For inputting external clock, XIN is used and
XOUT is opened.
Reset signal input or watchdog timer output/address-trap-reset
output/system-clock-rest output
Test pin for out-going test. Be tied to low.
OSC1, OSC2
Input, Output
Resonator connecting pins for on-screen display circuitry
VDD, VSS, VVSS
Power Supply
+5 V, 0 V (GND)
88CS34-5
2007-09-12
TMP88CS34CP34
Block Diagram
I/O Ports
P64 to P67 P70, 71 P57
Display
Memory
OSC Connecting
Pins for On-Screen
Display OSC1
VD
I
HD
On-screen display circuit
OSC2
Power VDD
Supply VSS
R, G, B,
Jitter
Y/BL
Elimination
Character
ROM
P6
TLCS-870/X
CPU core
Data Memory
(RAM)
P7
P5
ROM corrective circuit
VVSS
Reset I/O Test Pin
RESET
TEST
Program Counter
Interrupt Controller
System Controller
Standby Controller
Resonator
Connecting Pins
XIN
XOUT
Time Base
Timer
Timing Generator
High
Clock
frequency Generator
Watchdog
Timer
16-bit
Timer
TC1 TC2
Program Memory
(ROM)
8-bit
Timer/Counter
TC3
TC4
Inst. Register
Inst. Decoder
P2
P4
DA Converter
(PWM)
P20 P40 to P47
P5
P50 to P56
8-bit
AD
Key on
wake up
P6
P60 to P63
Remote
control signal
P3
Serial Bus
Interface
Y/BLIN
RIN
GIN
BIN
P30 to P35
I/O Ports
88CS34-6
2007-09-12
TMP88CS34/CP34
Operational Description
CPU Core Functions
1.
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, the
external memory interface, and the reset circuit.
1.1
Memory Address Map
The TMP88CS34/CP34 memory consists of four blocks: ROM, RAM, SFR (Special Function
Register), and DBR (Data Buffer Register). They are all mapped to a 1-Mbyte address space.
Figure 1.1.1 shows the TMP88CS34/CP34 memory address map. There are 16 banks of the
general-purpose register. The register banks are also assigned to the RAM address space.
00000H
00000H
SFR
RAM
0003FH
00040H
000BFH
000C0H
64 bytes
128 bytes
0003FH
00040H
128 bytes
000BFH
000C0H
1536 bytes
1536 bytes
006BFH
006BFH
00F80H
00F80H
128 bytes
DBR
64 bytes
128 bytes
00FFFH
00FFFH
04000H
04000H
48896 bytes
65280 bytes
13EFFH
0FEFFH
ROM
FFF00H
FFF3FH
FFF40H
FFF7FH
FFF80H
FFF00H
64 bytes
64 bytes
FFF3FH
FFF40H
FFF7FH
FFF80H
128 bytes
FFFFFH
64 bytes
64 bytes
128 bytes
FFFFFH
TMP88CS34
TMP88CP34
ROM: Read Only Memory includes
Program memory, Character data memory for OSD
RAM: Random Access Memory includes
Data memory, Stack, General-purpose register banks
SFR: Special Function Register includes
I/O ports, Peripheral hardware control registers, Peripheral hardware status registers
System control registers, Interrupt control registers, Program status word
DBR: Data Buffer Register includes
Control register for on-screen display (OSD)
Remote-control-receive control/status registers, ROM correction control registers
Test video signal control registers
Figure 1.1.1 Memory Address Map
88CS34-7
2007-09-12
TMP88CS34/CP34
1.2
Program Memory (ROM)
The TMP88CS34 contains a 64-Kbyte program memory (mask ROM) at addresses from
04000 to 13EFFH and FFF00 to FFFFFH.
The TMP88CP34 contains a 48-Kbyte program memory (mask ROM) at address from 04000
to 0FEFFH and FFF00 to FFFFFH.
Addresses FFF00 through FFFFFH in the program memory are also used for a particular
purpose.
1.3
Data Memory (RAM)
The TMP88CS34/CP34 has a 1.5-Kbyte data memory (Static RAM) address from 0040 to
06BFH.
The first 128 bytes (addresses 00040 through 000BFH) in the built-in RAM are also available
as general-purpose register banks.
The general-purpuse registers are mapped in the RAM; therefore, do not clear RAM at the
current bank addresses.
Example: Clears RAM to “00H” except the bank 0 (TMP88CS34/CP34):
LD
HL, 0048H
; Sets start address to HL register pair
LD
A, H
; Sets initial data (00H) to A register
LD
BC, 0677H
; Sets number of byte to BC register pair
SRAMCLR: LD
(HL+), A
DEC BC
JRS
F, SRAMCLR
Note:
1.4
The data memory contents become unstable when the power supply is turned on; therefore,
the data memory should be initialized by an initialization routine. Note that the
general-purpose registers are mapped in the RAM; therefore, do not clear RAM at the
current bank addresses.
System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a stand-by
controller.
Timing generator control register
TBTCR
Clock
generator
XIN
00036H
fc
High-frequency
clock oscillator
Timing
generator
Stand-by controller
XOUT
00039H
00038H
System clocks
Clock generator control
SYSCR1
SYSCR2
System control registers
Figure 1.4.1 System Clock Controller
88CS34-8
2007-09-12
TMP88CS34/CP34
1.4.1
Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied
to the CPU core and peripheral hardware. It contains oscillation circuit: one for the
high-frequency clock.
The high-frequency (fc) clock can be easily obtained by connecting a resonator between
the XIN/XOUT pin, respectively. Clock input from an external oscillator is also possible. In
this case, external clock is applied to XIN pin with XOUT pin not connected.
High-frequency clock
XIN
XOUT
XIN
XOUT
(open)
(a) Crystal/Ceramic
resonator
(b) External oscillator
Figure 1.4.2 Examples of Resonator Connection
Note: Accurate adjustment of the oscillation frequency:
Although hardware to externally and directly monitor the basic clock pulse is not
provided, the oscillation frequency can be adjusted by making the program to output
fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse.
With a system requiring adjustment of the oscillation frequency, the adjusting program
must be created beforehand.
1.4.2
Timing Generator
The timing generator generates from the basic clock the various system clocks supplied
to the CPU core and peripheral hardware. The timing generator provides the following
functions:
1. Generation of main system clock
2.
Generation of source clocks for time base timer
3.
Generation of source clocks for watchdog timer
4.
Generation of internal source clocks for timer/counters TC1 to TC4
5.
Generation of warm-up clocks for releasing STOP mode
6.
Generation of a clock for releasing reset output
(1) Configuration of Timing Generator
The timing generator consists of a 21-stage divider with a divided-by-3 prescaler, a main
system clock generator, and machine cycle counters.
During reset and at releasing STOP mode, the prescaler and the divider are cleared to “0”,
however, the prescaler is not cleared.
An input clock to the 7th stage of the divider depends on the operating mode.
A divided-by-256 of high-frequency clock (fc/28) is input to the 7th stage of the divider.
88CS34-9
2007-09-12
TMP88CS34/CP34
fm
Machine cycle counters
States
DV1CK
Prescaler
High-frequency
clock
Machine cycles
fc
0 1 2
Divider
S
A
Y
Divider
1 2 3 4 5 6
fc/2
8
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
B
Reset circuit
Stand-by
controller
Timer/
Counters
Watchdog
Timer
Time Base
Timer
fc
D1
D0
FC8OUT
MK8 MHz
JITTA
Figure 1.4.3 Configuration of Timing Generator
CGCR
(00030H)
“0”
“0”
DV1CK
DV1CK
“0”
“0”
“0”
“0”
“0”
Selection of input clock to 0: fc/4
the 1’st stage of the divider. 1: fc/8
(Initial value: 0000 0000)
R/W
Note 1:
fc: high-frequency clock [Hz]
Note 2:
The all bits except DV1CK are cleared to “0”.
*: Don’t care
Figure 1.4.4 Divider Control Register
FC8CR
(00FEEH)
D1
D1
D0
FC8OUT
1
0
1/2 fc
0
0
1/1 fc
D0
Read/Write (Initial value: 0000 0010)
Figure 1.4.5 FC8 Control Register
88CS34-10
2007-09-12
TMP88CS34/CP34
(2) Machine Cycle
Instruction execution and peripheral hardware operation are synchronized with the
main system clock. The minimum instruction execution unit is called a “machine cycle”.
There are a total of 15 different types of instructions for the TLCS-870/X Series: ranging
from 1-cycle instructions which require one machine cycle for execution to 15-cycle
instructions which require 15 machine cycles for execution.
A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system
clock.
1/fc
Main System Clock
fm
State
S0
S1
S2
S3
S0
S1
S2
S3
Machine cycle
(0.25 μs at fc = 16 MHz)
Figure 1.4.6 Machine Cycle
1.4.3
Stand-by Controller
The stand-by controller starts and stops the switches the main system clock. These
modes are controlled by the system control registers (SYSCR1, SYSCR2).
Figure 1.4.7 shows the operating mode transition diagram and Figure 1.4.8 shows the
system control registers.
Single-clock mode
In the single-clock mode, the machine cycle time is 4/fc [s] (0.25 μs at fc = 16 MHz).
1.
NORMAL mode
In this mode, both the CPU core and on-chip peripherals operate using the
high-frequency clock.
2.
IDLE mode
In this mode, the internal oscillation circuit remains active. The CPU and the
watchdog timer are halted; however, on-chip peripherals remain active (operate using
the high-frequency clock). IDLE mode is started by setting IDLE bit in the system
control register 2 (SYSCR2), and IDLE mode is released to NORMAL mode by an
interrupt request from on-chip peripherals or external interrupt inputs. When IMF
(interrupt master enable flag) is “1” (interrupt enable), the execution will resume upon
acceptance of the interrupt, and the operation will return to normal after the interrupt
service is completed. When IMF is “0” (interrupt disable), the execution will resume
with the instruction which follows IDLE mode start instruction.
3.
STOP mode
In this mode, the internal oscillation circuit is turned off, causing all system
operations to be halted.
The internal status immediately prior to the halt is held with the lowest power
consumption during this mode.
STOP mode is started by setting STOP bit in the system control register 1 (SYSCR1),
and STOP mode is released by an input (either level-sensitive or edge-sensitive can be
programmably selected) to the STOP pin. After the warming-up period is completed,
the execution resumes with the next instruction which follows the STOP mode start
instruction.
88CS34-11
2007-09-12
TMP88CS34/CP34
RESET
Reset release
Software
IDLE
mode
NORMAL
mode
Interrupt
Software
STOP
STOP
mode
pin input
(a) Single-clock mode
Note: NORMAL mode is generically called NORMAL; STOP mode is called STOP; and IDLE mode is
called IDLE.
Operating Mode
Frequency
CPU Core
High-frequency Low-frequency
RESET
NORMAL
Single-Clock
Reset
Turning on
oscillation
IDLE
STOP
On-chip
Machine
Peripherals Cycle Time
Turning off
oscillation
Reset
4/fc [s]
Operate
Operate
Halt
Turning off
oscillation
Halt
−
Figure 1.4.7 Operating Mode Transition Diagram
88CS34-12
2007-09-12
TMP88CS34/CP34
System Control Register 1
SYSCR1
(00038H)
7
6
5
4
STOP
RELM
“0”
“1”
3
2
1
0
WUT
(Initial value: 0000 00** )
0: CPU core and peripherals remain active
STOP
STOP mode start
RELM
Release method for STOP mode
1: CPU core and peripherals are halted
(start STOP mode)
0: Edge-sensitive release (Rising Edge)
1: Level-sensitive release (“H” Level)
Return to NORMAL mode
Warming-up time at releasing
STOP mode
WUT
00
01
DV1CK = 0
DV1CK = 1
3 × 2 /fc
16
3 × 2 /fc
16
2 /fc
R/W
17
17
2 /fc
10
Reserved
Reserved
11
Reserved
Reserved
Note 1:
Always set bit 5 in SYSCR1 to “0”.
Note 2:
When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless of the
RETM contents.
Note 3:
fc: High-frequency clock [Hz]
*: Don’t care
Note 4:
Bits 1 and 0 in SYSCR1 are read in as undefined data when a read instruction is executed.
Note 5:
Always set bit 4 in SYSCR1 to “1” when STOP mode is started.
System Control Register 2
SYSCR2
(00039H)
7
6
5
4
“1”
“0”
“0”
IDLE
IDLE
IDLE mode start
3
2
1
0
(Initial value: 1000 **** )
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (start IDLE mode)
Note 1:
*: Don’t care
Note 2:
Always set bit 7, 6 and 5 in SYSCR2 to “100”.
R/W
Figure 1.4.8 System Control Registers
88CS34-13
2007-09-12
TMP88CS34/CP34
1.4.4
Operating Mode Control
(1) STOP mode
STOP mode is controlled by the system control register 1 (SYSCR1) and the STOP pin
input. The STOP pin is also used both as a port P20 and an INT5 (external interrupt input
5) pin. STOP mode is started by setting STOP (bit 7 in SYSCR1 ) to “1”. During STOP mode,
the following status is maintained.
1.
Oscillations are turned off, and all internal operations are halted.
2.
The data memory, registers and port output latches are all held in the status in effect
before STOP mode was entered.
3.
The prescaler and the divider of the timing generator are cleared to “0”.
4.
The program counter holds the address of the instruction following the instruction
which started the STOP mode.
STOP mode includes a level-sensitive release mode and an edge-sensitive release mode,
either of which can be selected with RELM (bit 6 in SYSCR1).
a.
Level-sensitive release mode (RELM = 1)
In this mode, STOP mode is released by setting the STOP pin high. This mode is
used for capacitor back-up when the main power supply is cut off and long term battery
back-up.
When the STOP pin input is high, executing an instruction which starts the STOP
mode will not place in STOP mode but instead will immediately start the release
sequence (warm-up). Thus, to start STOP mode in the level-sensitive release mode, it is
necessary for the program to first confirm that the STOP pin input is low. The
following method can be used for confirmation:
Using an external interrupt input INT5 ( INT5 is a falling edge-sensitive input).
Example: Starting STOP mode with an INT5 interrupt.
PINT5: TEST (P2) . 0
; To reject noise, the STOP mode does not
JRS F, SINT5
start if port P20 is at high
LD
(SYSCR1), 01010000B
; Sets up the level-sensitive release mode.
SET (SYSCR1) . 7
; Starts STOP mode
LDW (IL), 1110011101010111B ; IL12, 11, 7, 5, 3 ← 0 (Clears interrupt latches)
SINT5: RETI
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Confirm by program that the
STOP pin input is low and
start STOP mode.
Warm-up
NORMAL
operation
STOP mode is released by the hardware.
Always released if the STOP
pin input is high.
Note 1:
After warming up is started, when STOP pin input is changed “L” level, STOP mode is not placed.
Note 2:
When changing to the level-sensitive release mode from the edge-sensitive release mode, the release
mode is not switched until a rising edge of the STOP pin input is detected.
Figure 1.4.9 Level-sensitive Release Mode
88CS34-14
2007-09-12
TMP88CS34/CP34
b.
Edge-sensitive release mode (RELM = 0)
In this mode, STOP mode is released by a rising edge of the STOP pin input. This is
used in applications where a relatively short program is executed repeatedly at
periodic intervals. This periodic signal (for example, a clock from a low-power
consumption oscillator) is input to the STOP pin.
In the edge-sensitive release mode, STOP mode is started even when the STOP pin
input is high.
Example: Starting STOP mode from NORMAL mode
LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive mode
VIH
STOP pin
XOUT pin
STOP
operation
NORMAL
operation
Warm-up
STOP mode started
by the program.
NORMAL
operation
STOP
operation
STOP mode is released by the hardware at the rising
edge of STOP pin input.
Figure 1.4.10 Edge-sensitive Release Mode
STOP mode is released by the following sequence:
1.
When returning to NORMAL, clock oscillator is turned on.
2.
A warming-up period is inserted to allow oscillation time to stabilize. During warm-up,
all internal operations remain halted. Two different warming-up times can be selected
with WUT (bits 2 and 3 in SYSCR1) as determined by the resonator characteristics.
3.
When the warming-up time has elapsed, normal operation resumes with the
instruction following the STOP mode start instruction (e.g. [SET (SYSCR1). 7]). The
start is made after the divider of the timing generator is cleared to “0”.
Table 1.4.1 Warming-up Time Example
Warming-up Time [ms]
WUT
Return to NORMAL mode
DV1CK = 0
00
3 × 2 /fc
DV1CK = 1
16
(12.29)
3 × 2 /fc
16
17
17
(24.58)
01
2 /fc
(4.10)
2 /fc
(8.20)
10
Reserved
( - )
Reserved
( - )
11
Reserved
( - )
Reserved
( - )
Note: The warming-up time is obtained by dividing the basic clock by the divider: therefore,
the warming-up time may include a certain amount of error if there is any fluctuation
of the oscillation frequency when STOP mode is released. Thus, the warming-up
time must be considered an approximate value.
88CS34-15
2007-09-12
88CS34-16
Divider
0
Instruction Halt
execution
Main
system
clock
Program
counter
Oscillator Turn
circuit
off
input
STOP pin
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
Turn on
Turn on
n
Count up
Warming up
a+2
n+2
n+3
a+3
(b) STOP Mode Release
0
1
Instruction at address a + 2
a+4
a+5
n+4
2
Instruction at address a + 3
(a) STOP Mode Start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
n+1
SET (SYSCR1). 7
a+3
3
Instruction at address a + 4
a+6
0
Halt
Turn off
TMP88CS34/CP34
Figure 1.4.11 STOP Mode Start/Release
2007-09-12
TMP88CS34/CP34
STOP mode can also be released by setting the RESET pin low, which immediately
performs the normal reset operation.
Note: When STOP mode is released with a low hold voltage, the following cautions must be
observed.
The power supply voltage must be at the operating voltage level before releasing STOP
mode. The RESET pin input must also be high, rising together with the power supply
voltage. In this case, if an external time constant circuit has been connected, the RESET
pin input voltage will increase at a slower rate than the power supply voltage. At this time,
there is a danger that a reset may occur if input voltage level of the RESET pin drops
below the non-inverting high-level input voltage (hysteresis input).
(2) IDLE mode
IDLE mode is controlled by the system control register 2 and maskable interrupts. The
following status is maintained during IDLE mode.
1.
Operation of the CPU and watchdog timer is halted. On-chip peripherals continue to
operate.
2.
The data memory, CPU registers and port output latches are all held in the status in
effect before IDLE mode was entered.
3.
The program counter holds the address of the instruction following the instruction
which started IDLE mode.
Example: Starting IDLE mode.
SET (SYSCR2) . 4
;
IDLE ← 1
Starting IDLE mode
by instruction
CPU, WDT are halted
Reset input
Yes
Reset
No (high)
No
Interrupt request
Normal
release mode
No
Yes
IMF = 1
Yes (Interrupt release mode)
Interrupt processing
Execution of the
instruction which follows
the IDLE mode start
instruction
Figure 1.4.12 IDLE Mode
88CS34-17
2007-09-12
TMP88CS34/CP34
IDLE mode includes a normal release mode and an interrupt release mode. Selection is
made with the interrupt master enable flag (IMF). Releasing the IDLE mode returns from
IDLE to NORMAL.
a.
Normal release mode (IMF = “0”)
IDLE mode is released by any interrupt source enabled by the individual interrupt
enable flag (EF) or an external interrupt 0 ( INT0 pin) request. Execution resumes with
the instruction following the IDLE mode start instruction (e.g. [SET (SYSCR2).4]).
Normally, IL (Interrupt Latch) of interrupt source to release IDLE mode must be
cleared by load instructions.
b.
Interrupt release mode (IMF = “1”)
IDLE mode is released and interrupt processing is started by any interrupt source
enabled with the individual interrupt enable flag (EF) or an external interrupt 0 ( INT0
pin) request. After the interrupt is processed, the execution resumes from the
instruction following the instruction which started IDLE mode.
Note: When a watchdog timer interrupt is generated immediately before the IDLE mode is
started, the watchdog timer interrupt will be processed but IDLE mode will not be
started.
88CS34-18
2007-09-12
88CS34-19
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Halt
Halt
Halt
Watchdog
timer
Main
system
clock
Halt
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
a+3
(b) IDLE Mode Release
(II) Interrupt Release Mode
a+3
a+3
Operate
Operate
Acceptance of interrupt
Instruction at address a + 2
a+4
(a) IDLE Mode Start (Example: starting with the SET instruction located at address a)
(I) Normal Release Mode
Operate
SET (SYSCR2). 4
Instruction
execution
Watchdog
timer
a+2
Program
counter
Interrupt
request
Main
system
clock
Halt
TMP88CS34/CP34
Figure 1.4.13 IDLE Mode Start/Release
2007-09-12
TMP88CS34/CP34
IDLE mode can also be released by setting the RESET pin low, which immediately
performs the reset operation. After reset, the TMP88CS34/CP34 is placed in NORMAL
mode.
88CS34-20
2007-09-12
TMP88CS34/CP34
1.5
Interrupt Controller
The TMP88CS34/CP34 has a total of 16 interrupt sources; 6 externals and 10 internals.
Multiple interrupts with priorities are also possible. Two of the internal sources are pseudo
non-maskable interrupts; the remainder are all maskable interrupts.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and
independent vectors. The interrupt latch is set to “1” by the generation of its interrupt request
which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software
using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one
interrupts are generated simulaneously, interrupts are accepted in order which is dominated by
hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Table 1.5.1 Interrupt Sources
Interrupt source
Internal/
External
(Reset)
Internal
Internal
External
Internal
External
Internal
External
Internal
Internal
Internal
External
External
Internal
Internal
External
Internal
INTSW
INTWDT
INT0
INTTC1
INTKWU
INTTBT
INT2
INTTC3
INTTSBI
INTTC4
INT3
INT4
INTADC
INTTC2
INT5
INTOSD
Enable condition
Non-Maskable
(Software interrupt)
(Watchdog timer interrupt)
(External interrupt 0)
(16-bit TC1 interrupt)
(Key-On-Wake-Up)
(Time base timer interrupt)
(External interrupt 2)
(8-bit TC3 interrupt)
(SBI interrupt)
(8-bit TC4 interrupt)
(External interrupt 3)
(External interrupt 4)
(AD Converter interrupt)
(16-bit TC2 interrupt)
(External interrupt 5)
(OSD interrupt)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pseudo non-maskable
IMF･EF3 = 1, INT0EN = 1
IMF･EF4 = 1
IMF･EF5 = 1
IMF･EF6 = 1
IMF･EF7 = 1
IMF･EF8 = 1
IMF･EF9 = 1
IMF･EF10 = 1
IMF･EF11 = 1
IMF･EF12 = 1
IMF･EF13 = 1
IMF･EF14 = 1
IMF･EF15 = 1
IMF･EF16 = 1
IMF･EF17 = 1
IMF･EF18 = 1
IMF･EF19 = 1
IMF･EF20 = 1
IMF･EF21 = 1
IMF･EF22 = 1
IMF･EF23 = 1
IMF･EF24 = 1
IMF･EF25 = 1
IMF･EF26 = 1
IMF･EF27 = 1
IMF･EF28 = 1
IMF･EF29 = 1
IMF･EF30 = 1
IMF･EF31 = 1
Interrupt
latch
Vector table
address
−
FFFFCH
High 0
−
IL2
IL3
IL4
IL5
IL6
IL7
IL8
IL9
IL10
IL11
IL12
IL13
IL14
IL15
IL16
IL17
IL18
IL19
IL20
IL21
IL22
IL23
IL24
IL25
IL26
IL27
IL28
IL29
IL30
IL31
FFFF8H
FFFF4H
FFFF0H
FFFECH
FFFE8H
FFFE4H
FFFE0H
FFFDCH
FFFD8H
FFFD4H
FFFD0H
FFFCCH
FFFC8H
FFFC4H
FFFC0H
FFFBCH
FFFB8H
FFFB4H
FFFB0H
FFFACH
FFFA8H
FFFA4H
FFFA0H
FFF9CH
FFF98H
FFF94H
FFF90H
FFF8CH
FFF88H
FFF84H
FFF80H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Low 31
Priority
Note : Before you change each enable flag (EF) and/or each interrupt latch (IL), be sure to clear the
interrupt master enable flag (IMF) to “0” (to disable interrupts).
1. After a DI instruction is executed.
2. When an interrupt is accepted, IMF is autamatically cleared to “0”.
However, to enable nested interrupts change EF and/or IL before setting IMF to “1” (to enable
interrupts).
If the individual enable flags (EF) and interrupts (IL) are set under conditions other than the above,
proper operation cannot be guararteed.
88CS34-21
2007-09-12
INTOSD
INTKOW
INTTC1
INT0
INTWDT
INTSW
88CS34-22
IL31 to 3 write data
Digital noise reject circuit
External interrupts control register
EINTCR
INT0EN
Internal reset
Write
strobe
for IL
Q
Q
Q
S
Q
RIL16
R IL5
S
R IL4
S
R IL3
S
Interrupt latch
S
Q
R IL2
Interrupt enable flag
EF31 to EF3
IL16 to IL2
[DI] Instruction
Instruction which
clears IMF to “0”
R S
IMF
Q
Instruction which sets
IMF to “1”
[RETN] instruction only when
IMF was set before
interrupt was accepted
[EI] instruction
[RETI] instruction during
maskable interrupt
service
Interrupt master enable flag
Interrupt
acceptance
Vector table
address
Vector
table
address
generator Non-maskable interrupts request
Interrupt request
Maskable
interrupts
Release IDLE mode
request
request
&
Priority
encoder
TMP88CS34/CP34
Figure 1.5.1 Interrupt Controller Block Diagram
2007-09-12
TMP88CS34/CP34
Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources.
Each interrupt vector is independent.
The interrupt latch is set to “1” when an interrupt request is generated, and requests the
CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled
and disabled by program using the interrupt master enable flag (IMF) and the individual
interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the
interrupt is accepted in the highest priority order as determined by the hardware. Figure 1.5.1
shows the interrupt controller.
(1) Interrupt Latches (IL31 to IL2)
Interrupt latches are provided for each source, except for a software interrupt. The latch
is set to “1” when an interrupt request is generated, and requests the CPU to accept the
interrupt. The latch is cleared to “0” just after the interrupt is accepted. All interrupt
latches are initialized to “0” during reset.
The interrupt latches are assigned to addresses 0003CH, 0003DH, 0002EH and 0002FH
in the SFR. Except for IL2, each latch can be cleared to “0” individually by an instruction;
however, the read-modify-write instruction such as bit manipulation or operation
instructions cannot be used. When interrupt occurred during order execution, the reason is
because interrupt request is cleared. Thus, interrupt requests can be canceled and
initialized by the program. Note that request the interrupt latches cannot be set to “1” by
an instruction. For example, it may be that each latch is cleared even if an interrupt
request is generated during instruction exection.
The contents of interrupt latches can be read out by an instruction. Therefore, testing
interrupt request by software is possible.
Example 1: Clears interrupt latches
DI
LDW (ILL), 1110100000111111B
;
;
Disable interrupt
IL12, IL10 to IL6 ← 0
Example 2: Reads interrupt latches
LD
WA, (ILL)
;
W ← ILH, A ← ILL
;
if IL7 = 1 then jump
Example 3: Tests an interrupt latch
TEST (ILL). 7
JR
F, SSET
(2) Interrupt Enable Register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts,
except for the pseudo non-maskable interrupts (software and watchdog timer interrupts).
Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR;
however, the pseudo non-maskable interrupt cannot be nested more than once at the same
time.
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt
enable flags (EF). These registers are assigned to addresses 0003AH, 0003BH, 0002CH and
0002DH in the SFR, and can be read and written by an instruction (including
read-modify-write instruction such as bit manipulation instructions).
Note: Do not use the read-modify-write instruction for the EIRL (address 0003AH) during
pseudo non-maskable interrupt service task. If the read-modify-write instruction is used,
the IMF is not set to “1” after RETN.
88CS34-23
2007-09-12
TMP88CS34/CP34
1.
Interrupt Master enable Flag (IMF)
The interrupt master enable flag (IMF) enables and disables the acceptance of all
maskable interrupts. Clearing this flag to “0” disables the acceptance of all maskable
interrupts. Setting to “1” enables the acceptance of interrupts.
When an interrupt is accepted, this flag is cleared to “0” to temporarily disable the
acceptance of other maskable interrupts. After execution of the interrupt service
program, this flag is set to “1” by the maskable interrupt return instruction [RETI] to
again enable the acceptance of interrupts. If an interrupt request has already been
occurred, interrupt service starts immediately after execution of the [RETI]
instruction.
Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this
case, the IMF is set to “1” only when pseudo non-maskable interrupt service is started
with interrupt acceptance enabled (IMF = 1). Note that the IMF remains “0” when
cleared by the interrupt service program.
The IMF is assigned to bit 0 at address 0003AH in the SFR, and can be read and
written by an instruction. The IMF is normally set and cleared by the [EI] and [DI]
instructions, and the IMF is initialized to “0” during reset.
2.
Individual interrupt Enable Flags (EF16 to EF3)
These flags enable and disable the acceptance of individual maskable interrupts,
except for an external interrupt 0. Setting the corresponding bit of an individual
interrupt enable flag to “1” enables acceptance of an interrupt, setting the bit to “0”
disables acceptance.
Example 1: Sets EF for individual interrupt enable, and sets IMF to “1”.
DI
; Disable interrupt
LD
(EIRE), 00000001B
; EF16 ← 1
LDW
(EIRL), 1110100010100001B
EF15 to EF13, EF11, EF7, EF5, IMF ← 1
Example 2: Sets an individual interrupt enable flag to “1”.
SET
(EIRH). 4
; EF12 ← 1
88CS34-24
2007-09-12
TMP88CS34/CP34
Interrupt Latches (IL)
IL
(0002E,
0002FH)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IL31
IL30
IL29
IL28
IL27
IL26
IL25
IL24
IL23
IL22
IL21
IL20
IL19
IL18
IL17
IL16
ILD (0002FH)
ILE (0002EH)
(Initial value: 00000000
IL
(0003C,
0003DH)
IL15
IL14
IL13
IL12
IL11
IL10
IL9
IL8
IL7
IL6
IL5
IL4
ILH (0003DH)
IL3
00000000)
IL2
INF
ILE (0003CH)
(Initial value: 00000000
000000**)
Interrupt Enable Registers (EIR)
EIR
(0002C,
0002DH)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EIRD (0002DH)
EIRE (0002CH)
(Initial value: 00000000
EIR
(0003A,
0003BH)
0
EF31 EF30 EF29 EF28 EF27 EF26 EF25 EF24 EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16
EF15 EF14 EF13 EF12 EF11 EF10
EF9
EF8
EF7
EF6
EF5
EIRH (0003BH)
EF4
EF3
00000000)
IMF
EIRL (0003AH)
(Initial value: 00000000
Note 1:
Do not clear IL with read-modify-write instructions such as bit operations.
Note 2:
Do not set IMF to “1” during non-maskable interrupt service program.
Note 3:
Bits 1 and 0 in ILL are read in as undefined data when a read instruction is executed.
Note 4:
*: Don’t care
Note 5:
Do not clear IL2 to “0” by an instruction.
Note 6:
At TMP88CS34/CP34, IL17 to IL31 and IF17 to IF31 are not used.
Note 7:
After IMF is cleared, modify EF and IL.
00000**0)
Figure 1.5.2 Interrupt Latches (IL) and Interrupt Enable Registers (EIR)
1.5.1
Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is
cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 12
machine cycles (3 μs at fc = 16 MHz in the NORMAL mode) after the completion of the
current instruction execution. The interrupt service task terminates upon execution of an
interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo
non-maskable interrupts). Figure 1.5.3 shows the timing chart of interrupt acceptance
processing.
(1) Interrupt acceptance
Interrupt acceptance processing is as follows.
1.
The interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the
acceptance of any following maskable interrupts. When a non-maskable interrupt is
accepted, the acceptance of any following interrupts is temporarily disabled.
2.
The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
3.
The contents of the program counter (PC) and the program status word (PSW) are
saved (pushed) on the stack in sequence of PSWH, PSWL, PCE, PCH, PCL. The stack
pointer (SP) is decremented five times.
4.
The entry address of the interrupt service program is read from the vector table, and
set to the program counter.
88CS34-25
2007-09-12
TMP88CS34/CP34
5.
The RBS control code is read from the vector table. The lower 4-bit of this code is added
to the RBS.
6.
The instruction stored at the entry address of the interrupt service program is
executed.
Example:
Correspondence between vector table address for INTTBT and the entry address
of the interrupt service program.
Entry address
Vector table address
FFFE4H
43H
FFFE5H
D2H
FFFE6H
0CH
FFFE7H
06H
CD243H
Vector
CD244H
CD245H
RBS
control
Interrupt
service
program
CD246H
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable
interrupt higher than the level of current servicing interrupt is occurred.
When nested interrupt service is necessary, the IMF is set to “1” in the interrupt service
program. In this case, acceptable interrupt sources are selectively enabled by the individual
interrupt enable flags.
Note: Do not use the read-modify-write instruction for the EIRL (address 0003AH) during
pseudo non-maskable interrupt service task.
88CS34-26
2007-09-12
TMP88CS34/CP34
Interrupt service task
1-machine cycle
INT5
INTTBT
IL15
IL6
IMF
Execution
Instruction
Address
bus
PC
Interrupt acceptance
a+1
a
FFFE4 FFFE5 FFFE6 FFFE7
a+1
a
n
Instruction
n−1 n−2 n−3 n−4
a
SP
b
n − 1 n −2 n − 3 n − 4
n
RBS
b
b+1 b+2
b+1 b+2 b+3
n−5
k = i + (FFFE7H). 3 − 0
i
INF
(a) Interrupt acceptance
Interrupt service task
IMF
RETI Instruction
Execution
Address
bus
PC
SP
c
c
c+1 n−4 n−3 n−2 n−1
c+1
c+2
n−5
n−4 n−3 n−2 n−1
RBS
k
n
a+1
a
a
a+1 a+2
n
i
INF
(b) Return from interrupt instruction
Note1:
a: return address, b: entry address, c: address which the RETI instruction is stored
Note2:
The maximum response time from when an IL is set until an interrupt acceptance processing starts is 62/fc
[s] with interrupt enabled.
Figure 1.5.3 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
88CS34-27
2007-09-12
TMP88CS34/CP34
(2) Saving/Restoring general-purpose registers
During interrupt acceptance processing, the program counter (PC) and the program
status word (PSW) are automatically saved on the stack, but not the accumulator and other
registers. These registers are saved by the program if necessary. Also, when nesting
multiple interrupt services, it is necessary to avoid using the same data memory area for
saving registers.
The following method is used to save/restore the general-purpose registers.
1.
General-purpose register save/restore by automatic register bank changeover
The general-purpose registers can be saved at high-speed by switching to a register
bank that is not in use. Normally, the bank 0 is used for the main task and the banks 1
to 15 are assigned to interrupt service tasks. To increase the efficiency of data memory
utilization, the same bank is assigned for interrupt sources which are not nested.
The switched bank is automatically restored by executing an interrupt return
instruction [RETI] or [RETN]. Therefore, it is not necessary for a program to save the
RBS.
…
Example: Register bank changeover
PINTxx:
interrupt processing
RETI
VINTxx:
2.
DP
DB
PINTxx
1
;
RBS ← RBS + 1
General-purpose register save/restore by register bank changeover
The general-purpose registers can be saved at high-speed by switching to a register
bank that is not in use. Normally, the bank 0 is used for the main tank and the banks 1
to 15 are assigned to interrupt service tasks.
…
Example: Register bank changeover
PINTxx: LD RBS, n
interrupt processing
RETI
;
VINTxx:
DP
DB
Main task
Bank m
Acceptance
of interrupt
Interrupt
service task
PINTxx
0
;
Switch to bank n by
LD, RBS and n
instruction
Restores bank and Returns
Interrupt service routine entry address
Main task
m
Acceptance
of interrupt
Interrupt
service task
m
n
Time
m
Interrupt return
Saving
registers
Switch to bank n
automatically
Restore to bank m
automatically by
[RETI]/[RETN]
Restoring
registers
Interrupt return
(a) Saving/Restoring by register bank changeover
(b) Saving/Restoring using push/pop or data transfer instructions
Figure 1.5.4 Saving/Restoring General-purpose Registers
88CS34-28
2007-09-12
TMP88CS34/CP34
3.
General-purpose registers save/restore using push and pop instructions
To save only a specific register, and when the same interrupt source occurs more
than once, the general-purpose registers can be saved/restored using the push/pop
instructions.
Example: Register save/restore using push and pop instructions
PINTxx: PUSH
WA
; Save WA register pair
interrupt processing
POP
WA
; Restore WA register pair
RETI
; Return
Address (example)
SP
0023AH
A
SP
W
0023B
SP
0023C
PCL
PCL
PCL
0023D
PCH
PCH
PCH
0023E
PCE
PCE
PCE
0023F
PSWL
PSWL
PSWL
PSWH
PSWH
PSWH
At acceptance
of an interrupt
4.
At execution
of a push
instruction
At execution
of a pop
instruction
00240
SP
00241
At execution of an
interrupt return
instruction
General-purpose registers save/restore using data transfer instructions
Data transfer instruction can be used to save only a specific general-purpose register
during processing of single interrupt.
Example: Saving/restoring a register using data transfer instructions
PINTxx: LD
(GSAVA), A
; Save A register
interrupt processing
LD
A, (GSAVA)
; Restore A register
RETI
; Return
88CS34-29
2007-09-12
TMP88CS34/CP34
(3) Interrupt return
The interrupt return instructions [RETI]/[RETN] perform the following operations.
[RETI] Maskable interrupt return
[RETN] Non-maskable interrupt return
1. The contents of the program counter and the
program status word are restored from the stack.
1. The contents of the program counter and program
status word are restored from the stack.
2. The stack pointer is incremented 5 times.
2. The stack pointer is incremented 5 times.
3. The interrupt master enable flag is set to “1”.
3. The interrupt master enable flag is set to “1” only
when a non-maskable interrupt is accepted in
interrupt enable status. However, the interrupt
master enable flag remains at “0” when so clear by
an interrupt service program.
4. The interrupt nesting counter is decremented, and
the interrupt nesting flag is changed.
4. The interrupt nesting counter is decremented, and
the interrupt nesting flag is changed.
Interrupt requests are sampled during the final cycle of the instruction being executed.
Thus, the next interrupt can be accepted immediately after the interrupt return instruction
is executed.
Note: When the interrupt processing time is longer than the interrupt request generation time,
the interrupt service task is performed but not the main task.
1.5.2
Software Interrupt (INTSW)
Executing the [SWI] instruction generates a software interrupt and immediately starts
interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a
non-maskable interrupt is already underway, executing the SWI instruction will not
generate a software interrupt but will result in the same operation as the [NOP]
instruction.
Use the [SWI] instruction only for detection of the address error or for debugging.
1.
Address error detection
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction
from a non-existent memory address. Code FFH is the SWI instruction, so a software
interrupt is generated and an address error is detected. The address error detection
range can be further expanded by writing FFH to unused areas of the program memory.
Address-trap reset is generated in case that an instruction is fetched from RAM, SFR
or DBR areas.
2.
Debugging
Debugging efficiency can be increased by placing the SWI instruction at the software
break point setting address.
1.5.3
External Interrupts
The TMP88CS34/CP34 each have five external interrupt inputs ( INT0 , INT2, INT3,
INT4, and INT5 ). Three of these are equipped with digital noise rejection circuits (pulse
inputs of less than a certain time are eliminated as noise). Edge selection is also possible
with INT2, INT3 and INT4.
The INT0 /P50 pin can be configured as either an external interrupt input pin or an
input/output port, and is configured as an input port during reset.
Edge selection, noise rejection control except INT3 pin input and INT0 /P50 pin function
selection are performed by the external interrupt control register (EINTCR). Edge selecting
and noise rejection control for INT3 pin input are preformed by the Remote control signal
preprocessor control registers. (refer to the section of the Remote control signal
preprocessor.) When INT0EN = 0, the IL3 will not be set even if the falling edge of INT0
pin input is detected.
88CS34-30
2007-09-12
TMP88CS34/CP34
Table 1.5.1 External Interrupts
Source
INT0
Pin
INT0
Secondary
function pin
P50/TC2
Enable conditions
Edge
Digital noise rejection
IMF = 1, INT0EN = 1, EF3 = 1
Falling edge
Any pulse shorter than 2/fc
[s] is regarded as noise and
removed. Pulses not shorter
than 7/fc [s] are definitely
regarded as signals.
IMF･EF7 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s]
are eliminated as noise.
Pulses equal to or more than
25/fc [s] are regarded as
signals.
Refer to the section of the
Remote control preprocessor
P53/TC1/
INT2
INT2
SCK1
/AIN0/
KWU0
INT3
INT3
P30/RXIN
IMF･EF11 = 1
Falling edge,
Rising edge or
Falling/Rising
edge
INT4
INT4
P31/TC3
IMF･EF12 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s]
are eliminated as noise.
Pulses of 25/fc [s] or more
are considered to be signals.
Falling edge
Any pulse shorter than 2/fc
[s] is regarded as noise and
removed. Pulse not shorter
than 7/fc [s] are definitely
regarded as signals.
INT5
INT5
P20/ STOP
IMF･EF15 = 1
Note 1: The noise rejection function is also affected for timer/counter input (TC1 pin).
Note 2: If a noiseless signal is input to the external interrupt pin in the NORMAL or IDLE mode, the maximum
time from the edge of input signal until the IL is set is as follows:
(1) INT2, INT4 pin 31/fc [s]
(2) INT3 pin
Refer to the section of the Remote control preprocessor.
Note 3: If a dual-function pin is used as an output port, changing data or switching between input and output
generates a pseudo interrupt request signal. To ignore this signal, it is necessary to reset the interrupt
enable flag.
Note 4: If INT0EN = “0”, detecting the falling edge of the INT0 pin input does not set the interrupt latch IL3.
88CS34-31
2007-09-12
TMP88CS34/CP34
EINTCR
(00037H)
7
6
INT0
EN
“0”
INT0EN
INT4ES
INT2ES
Note 1:
5
−
4
INT4
ES
P50/ INT0 pin configuration
INT4 and INT2 edge select
3
−
2
INT2
ES
1
0
“0”
−
(Initial value: 00*0 *00*)
0: P50 input/output port
1: INT0 pin (Port P50 should be set to an input mode)
Write
only
0: Rising edge
1: Falling edge
fc: High-frequency clock [Hz], *: Don’t care
Note 2:
Edge detection during switching edge selection is invalid.
Note 3:
Do not change EINTCR only when IMF = 1. After changing EINTCR, interrupt latches of external interrupt
inputs must be cleared to “0” using load instruction.
Note 4:
In order to change of external interrupt input by rewriting the contents of INT2ES and INT4ES during
NORMAL mode, clear interrupt latches of external interrupt inputs (INT2 and INT4) after 8 machine cycles
from the time of rewriting.
Note 5:
In order to change an edge of timer counter input by rewritng the contents of INT2ES during NORMAL
mode, rewrite the contents after timer counter is stopped (TC*s = 0) , that is, interrupt disable state.
Then, clear a interrupt latch of external interrupt input (INT2) after 8 machine cycles from the time of
rewriting to change to interrupt enable state. Finally, start timer counter.
Example:
When changing TC1 pin inputs edge in external trigger timer mode from rising edge falling edge.
LD (TC1CR), 01001000B
;
TC1S ← 00 (stops TC1)
DI
;
IMF ← 0 (disables interrupt service)
LD (EINTCR), 00000100B
;
INT2ES ← 1 (change edge selection)
NOP
8-machine to
cycles NOP
LD (ILL), 01111111B
;
IL7 ← 0 (clears interrupt latch)
EI
;
IMF ← 1 (enables interrupt service)
LD (TC1CR), 01111000B
;
TC1S ← 11 (starts TC1)
Figure 1.5.5 External Interrupt Control Register
88CS34-32
2007-09-12
TMP88CS34/CP34
1.6
Reset Circuit
The TMP88CS34/CP34 has four types of reset generation procedures: an external reset input,
an address trap reset output, a watchdog timer reset output and a system clock reset output.
Table 1.6.1 shows on-chip hardware initialization by reset action.
The malfunction reset output circuit such as watchdog timer reset, address trap reset and
system clock reset is not initialized when power is turned on. The RESET pin can output level
“L” at the maximum 24/fc [s] (1.5 μs at 16 MHz) when power is turned on.
Table 1.6.1 Initializing Internal Status by Reset Action
On-chip hardware
Initial value
Program counter
(PC)
(FFFFEH to FFFFCH)
Stack pointer
(SP)
not initialized
General-purpose registers
(W, A, B, C, D, E, H, L)
not initialized
Register bank selector
(RBS)
0
(JF)
1
Zero flag
(ZF)
Not initialized
Carry flag
(CF)
Not initialized
Half carry flag
(HF)
Not initialized
Sign flag
(SF)
Not initialized
Overflow flag
(VF)
Not initialized
(IMF)
0
Jump status flag
Interrupt master enable flag
Interrupt individual enable flags
1.6.1
−
Enable
Refer to I/O port
circuitry
Control registers
Refer to each of
control register
RAM
Not initialized
0
−
0
Output latches of I/O ports
0
(IL)
Initial value
Prescaler and Divider of timing
generator
Watchdog timer
(EF)
Interrupt latches
On-chip hardware
External Reset Input
The RESET pin contains a Schmitt trigger (hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the
power supply voltage within the operating voltage range and oscillation stable, a reset is
applied and the internal state is initialized.
When the RESET pin input goes high, the reset operation is released and the program
execution starts at the vector address stored at addresses FFFFCH to FFFFEH.
VDD
Reset input
RESET
Watchdog timer reset
Sink open drain
Malfunction
reset output
circuit
Address trap reset
System clock reset
Figure 1.6.1 Reset Circuit
88CS34-33
2007-09-12
TMP88CS34/CP34
1.6.2
Address-Trap-Reset
If the CPU should start looping for some cause such as noise and an attempt be made to
fetch an instruction from the on-chip RAM, DBR or the SFR area, address-trap-reset will
be generated. Then, the RESET pin output will go low. The reset time is about 8/fc to 24/fc
[s] (0.5 to 1.5 μs at 16 MHz).
Instruction
execution
JP
a
Reset release
Address-trap is occurred
(“L” output)
RESET output
8/fc to 24/fc [s]
Note 1:
Instruction at address
(High-Z)
4/fc
to
12/fc [s]
20/fc [s]
(No wait)
Letter “a” represents an address in the built-in RAM, SFR, or DBR area.
If the ROM corrective function is enabled, no address trap occurs in a RAM area of 002C0H to 06BFH.
If the ROM corrective function is disabled, an address trap occurs in the following area:
00000H ≤ a ≤ 00FFFH
If the ROM corrective function is enabled, an address trap occurs in the following area:
00000H ≤ a ≤ 002BFH or 006C0H ≤ a ≤ 00FFFH
Note 2:
During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Figure 1.6.2 Address-Trap-Reset
1.6.3
Watchdog Timer Reset
Refer to Section “2.4 Watchdog Timer”.
1.6.4
System-Clock-Reset
Clearing bits 7 in SYSCR2 to “0”, system clock stops and causes the microcomputer to
deadlock. This can be prevented by automatically generating a reset signal whenever bits 7,
6 and 5 in SYSCR2 = 000 is detected to continue the oscillation. The RESET pin output
goes low from high-impedance. The reset time is about 8/fc to 24/fc [s] (0.5 to 1.5 μs at 16
MHz).
88CS34-34
2007-09-12
TMP88CS34/CP34
1.7
ROM Corrective Function
The ROM corrective function can patch the part (s) of on-chip ROM with some bugs.
The ROM corrective function have two modes. One is to replaced the instruction on a certain
address in the ROM with the jump instruction to branch into the RAM area where the patched
codes (Program Jump Mode). The other is to replace a byte or a word (2 or 3 bytes) length data
in the ROM with the patched data (Data Replacement Mode). Four independent location can be
patched.
Note 1: When use ROM corrective circuit, it is necessary to contain a program which operates to load
patched program and/or replacement data from external memory into an internal data RAM
in an initial routine.
Note 2: The address of an instruction for IDLE mode cannot be specificated as start address of
corrective area.
Note 3: The BM88CS34N0A-M15 does not support the ROM corrective circuit. Use the TMP88PS34
to debug a program of this circuit.
Example:
ROM corrective circuit
ROMCDR
RAM
ROMCDR
Serial
Bus
Interface
88CS34-35
• Correction mode
• Correction code
• Patch program
2007-09-12
TMP88CS34/CP34
Match
Signal
Address Compare Circuit
23
to
Register 6
Selection
5
Circuit
4
3
2
1
0
5
BANK3
Data Bus
BANK2
Address Bus
BANK1
Configuration
BANK0
1.7.1
Instruction Fetch Control Circuit
to
to
the lower
the middle
the upper
the lower
Compare Address Register
the middle
the upper
Data Register
CM CM CM CM
0 1 2 3
Corrective Mode Signal
Write Data Count
Register Write Signal
ROMCDR
WDC
CM3-0
ROM Corrective
Data Register
Write Data
Count Register
ROM Corrective
Control Register
Figure 1.7.1 ROM Corrective Circuit
88CS34-36
2007-09-12
TMP88CS34/CP34
1.7.2
Control
The ROM corrective function is controlled by ROM corrective control register (ROMCCR)
and ROM corrective data register (ROMCDR).
ROM Corrective Control Register
ROMCCR
(00FE0H)
7
6
5
4
3
2
1
0
−
−
−
−
CM3
CM2
CM1
CM0
CM3
Corrective mode setting
(BANK3)
CM2
Corrective mode setting
(BANK2)
CM1
Corrective mode setting
(BANK1)
CM0
Corrective mode setting
(BANK0)
(Initial value: **** 0000)
0: Program jump mode
R/W
1: Data replacement mode
ROM Corrective Status Register
ROMCSR
(00FE1H)
7
6
5
−
−
−
WDC
Write data counter
4
3
2
WDC
1
0
(Initial value: ***0 0000)
Read
only
Counting the number of the byte written in ROMCDR
ROM Corrective Data Register
ROMCDR
(00FE2H)
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
ROMC
Write
only
ROM Corrective data register
Figure 1.7.2 ROM Corrective Control Register, Status Register and ROM Corrective Data Register
(1) Enable and disable
The ROM corrective function is disabled after releasing reset. It is enabled after setting
the data for one bank into ROMCDR. And the address-trap-reset is not generated when
fetching an instruction from the RAM area except the address 02C0H to 06BFH.
After the ROM corrective function is enabled, it is neccesary to reset the micro controller
in order to disable it.
(2) Data replacement mode
The ROM corrective function has the program jump mode and the data replacement
mode.
By setting CMx (x: 0 to 3) in ROMCCR, the data replacement mode is selected.
(3) The ROM corrective data register writing
The ROM corrective data register has four banks corresponding to four independent
locations to patch. The write data counter (WDC) points each bank set. (Figure 1.7.2)
88CS34-37
2007-09-12
TMP88CS34/CP34
ROM Corrective Data Register
ROMCDR
(00FE2H) ROMC7 ROMC6 ROMC5 ROMC4 ROMC3 ROMC2 ROMC1 ROMC0
(Initial value: 0000 0000)
The value of WDC after writing a data to ROMCDR
00000 (Initial value)
BANK 0
BANK 1
BANK 2
BANK 3
The lower start address of the corrective area (8 bits)
00001
The middle start address of the corrective area (8 bits)
00010
The upper start address of the corrective area (4 bits)
00011
The lower 8 bit of the jump address/replacement data
00100
The middle 8 bit of the jump address/replacement data
00101
The upper 4 bit of the jump address/replacement data
00110
The lower start address of the corrective area (8 bits)
00111
The middle start address of the corrective area (8 bits)
01000
The upper start address of the corrective area (4 bits)
01001
The lower 8 bit of the jump address/replacement data
01010
The middle 8 bit of the jump address/replacement data
01011
The upper 4 bit of the jump address/replacement data
01100
The lower start address of the corrective area (8 bits)
01101
The middle start address of the corrective area (8 bits)
01110
The upper start address of the corrective area (4 bits)
01111
The lower 8 bit of the jump address/replacement data
10000
The middle 8 bit of the jump address/replacement data
10001
The upper 4 bit of the jump address/replacement data
10010
The lower start address of the corrective area (8 bits)
10011
The middle start address of the corrective area (8 bits)
10100
The upper start address of the corrective area (4 bits)
10101
The lower 8 bit of the jump address/replacement data
10110
The middle 8 bit of the jump address/replacement data
10111
The upper 4 bit of the jump address/replacement data
00000
Note 1:
Note 2:
WDC value equals to the number of the byte stored in ROMCDR.
ROMCDR is set in order of the lower (8 bits), the middle (8 bits) and the upper (4 bits) start address of the
corrective area, the lower (8 bits), the middle (8 bits) and the upper (4 bits) of the jump address/the
replacement data.
Figure 1.7.3 Banks and WDC Value of the Program Corrective Data Register
Whenever ROMCDR is written, WDC is incremented to indicate what data is writen via
ROMCDR. During reset, WDC is intialized to “0”.
(1) The lower start address of the corrective area (8 bits)
(2) The middle start address of the corrective area (8 bits)
(3) The upper start address of the corrective area (4 bits)
(4) The lower jump address/replacement data (8 bits)
(5) The middle jump address/replacement data (8 bits)
(6) The upper jump address (4 bits)/replacement data
Note 1: Corrective addresses must have over five addresses each other.
Note 2: The address of an instruction for IDLE mode cannot be specificated as start address of
corrective area.
88CS34-38
2007-09-12
TMP88CS34/CP34
1.7.3
Functions
The ROM corrective function can correct maximum four ROM areas with their
corresponding four banks of ROM corrective registers. Either program jump mode or data
replacement mode is selected for each bank by CM0 to CM3 respectively.
(1) Program jump mode
In the program jump mode, the system executes a jump instruction when the program
execution reaches the instruction at the corrective ROM address, skips from the instruction
which would have been executed, and executes an instruction at a preset jump address.
Clearing ROMCCR CMx (x: 0 to 3) to “0” puts the system in the program jump mode. Use
ROMCDR to set the corrective ROM address and jump address.
When the start address of an erroneous program is a corrective ROM address, and that of
the patch program is a jump address, the bug in the erroneous program can be fixed. Note
that the patch program should end with a jump instruction, which causes a return to the
built-in ROM.
Note: For program jump mode, the address to be corrected must be the start address of the
instruction.
Example 1: Setting the Program Correction Circuit with the Initial Routine
Using the initial routine program, which is executed right after reset, set the
program correction circuit's register and stores the patch program into the built-in
RAM as follows.
1.
Read the flag, which indicates whether to use the program correction circuit, from
the external memory.
2.
If that circuit is not used, perform normal initial processing.
3.
If it is used, clear CMx to 0 to establish the program jump mode.
4.
Read the corrective ROM address and jump address from the external memory.
5.
Set the corrective ROM address and jump address, which were read in step 4., in
ROMCDR.
6.
Read the number of bytes for the patch program from the external memory.
7.
Read the program with a number of bytes, equal to the byte count read in step 6.,
from the external memory, and store that program into the built-in RAM.
8.
Repeat steps 4. through 7. as many times as there are required banks.
Example 2: There is bugs on the locations from 0C020H to 0C085H
The corrective address, the jump vector, the program patch codes and other
information to patch the ROM with the bugs must be read out from any of memory
storage that holds them during initial program routine. CMn = 0 specifies the program
jump mode. Subsequently, the patch program codes are loaded into RAM (00400H to
004EFH). The start address (0C020H) of the ROM necessary to patch is written to the
corrective ROM address registers, and the start address (00400H) of the RAM area to
patch is loaded onto the jump address registers. When the instruction at 0C020H is
fetched, the instruction to jump into 00400H is unconditionally executed instead of the
instruction at 0C020H, and the subsequent patch program codes are executed. The
jump instruction at the end of the patch program codes returns to the ROM at 0C086H.
88CS34-39
2007-09-12
TMP88CS34/CP34
00000H
SFR
0003FH
00040H
00400H
Patch
program
RAM
006BFH
JP 0C086H
004EFH
004F0H
00F80H
DBR
00FFFH
Return
04000H
ROM
0C020H
0C085H
Bug area
0C086H
FFFFFH
Note:
Corrective address must be assigned to 1st byte of instruction codes on the program jump
mode.
(2) Data replacement mode
In the data replacement mode, the system replaces reference data stored in the ROM
area with the new instead of correcting the data reference instruction when that reference
data is changed.
The program jump mode reduces the complexity of correcting the processing routine.
However, when this mode is used, if there is a need to replace only the fixed data in ROM,
the instruction to reference this ROM data should be corrected. Thus, a large amount of
ROM is required for the patch program. To avoid this, the system has the data replacement
mode. With this mode, three consecutive bytes of data can be replaced for each bank. (For
an instruction which accesses only one byte, only the first byte can be replaced. For an
instruction which accesses only two bytes, the two consecutive bytes can be replaced.)
Setting ROMCCR CMx (x: 0 to 3) to “1” puts the system in the data replacement mode.
Specify the start address of ROM data to be replaced as the corrective ROM address. Then,
specify the new three-byte data as the patch data.
Note: For data replacement mode, the corrective address should be the address of fixed data
(including a vector). (The operation code and operand cannot be changed.)
Example 1: Setting the Program Correction Circuit with the Initial Routine
Using the initial routine program, which is executed right after reset, set the
program correction circuit's register as follows.
1.
Read the flag, which indicates whether to use the program correction circuit, from
the external memory.
2.
If that circuit is not used, perform normal initial processing.
3.
If it is used, set CMx to “1” to establish the data replacement mode.
4.
Read the address of the data to be replaced and the patch data from the external
memory.
5.
Set the address and patch data, which were read in step 4., in ROMCDR.
6.
Repeat steps 4. and 5. as many times as there are required banks.
88CS34-40
2007-09-12
TMP88CS34/CP34
Example 2: Replacing data 55H at 0C020H with 33H
Using the initial routine program, which is executed right after reset, read the start
address of the data to be replaced and the patch data from the external memory. Set
CMx (x: 0 to 3) to “1” to change the correction mode to the data replacement mode.
Specify the start address (0C020H) of the data to be replaced as the corrective ROM
address. Then, specify the new three-byte data (33H for 0C020H, CCH for 0C021H,
and C3H for 0C022H) as the patch data.
00000H
SFR
0003FH
00040H
RAM
006BFH
00F80H
DBR
00FFFH
04000H
ROM
0C020H
55H
33H
0C021H
AAH
CCH
0C022H
A5H
3CH
replacement data
FFFFFH
1.
2.
3.
4.
At HL = 0C020H, Executing LD A, (HL) loads 33H in A. (Data replacement)
At HL = 0C021H, Executing LD A, (HL) loads AAH in A. (No data replacement)
At HL = 0C020H, Executing LD WA, (HL) loads CC33H in WA. (Data replacement)
At HL = 0C020H, Executing LD IX, (HL) loads CCC33H in IX. (Data replacement)
Note 1: Corrective address must be assigned to constant data area on the data
replacement mode. (Ope-code and Ope-rand cannot be replaced by ROM
correction circuit.)
Note 2: Instructions which includes “(HL +)” or “(− HL) ” operation cannot be replaced by
ROM corrective circuit on the data replacement mode.
88CS34-41
2007-09-12
TMP88CS34/CP34
2.
On-Chip Peripheral Functions
2.1
Special Function Registers (SFR) and Data Buffer Registers (DBR)
The TLCS-870/X series uses the memory mapped I/O system and all peripheral control and
data transfers are performed through the special function registers (SFR) and data buffer
registers (DBR).
The SFR are mapped to addresses 00000H to 0003FH, and DBR are mapped to address
00F80H to 00FFFH.
Figure 2.1.1 shows the list of the TMP88CS34/CP34 SFRs and-DBRs.
Address
00000H
00001
00002
00003
00004
00005
00006
00007
00008
00009
0000A
0000B
0000C
0000D
0000E
0000F
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
0001A
0001B
0001C
0001D
0001E
0001F
Read
Write
Reserved
Reserved
P2 port
P3 port
P4 port
P5 port
P6 port
P7 port
−
P5CR1 (P5 port I/O control1)
−
P7CR (P7 port I/O control)
Reserved
Reserved
−
P4CR (P4 port I/O control)
−
P6CR (P6 port I/O control)
ADCCRA (AD converter control A)
ADCCRB (AD converter control B)
TC1DRAL
(Timer register 1A)
TC1DRAH
TC1DRBL
−
(Timer register 1B)
−
TC1DRBH
TC1CR (TC1 control)
−
TC2CR (TC2 control)
−
TC2DRL
−
TC2DRH
(Timer register 2)
TC3DRA (Timer register 3A)
−
TC3DRB (Timer register 3B)
−
TC3CR (TC3 control)
−
TC4DR (Timer register 4)
−
TC4CR (TC4 control)
ORDSN (OSD control)
ORCRAL (OSD control)
ORCRAH (OSD control)
Address
00020H
00021
00022
00023
00024
00025
00026
00027
00028
00029
0002A
0002B
0002C
0002D
0002E
0002F
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
0003A
0003B
0003C
0003D
0003E
0003F
Read
Write
SBISRA (SBI status A)
SBICRA (SBI control register A)
SBIDBR (SBI Data buffer)
−
I2CAR (I2C Bus address)
SBISRB (SBI status B)
SBICRB (SBI control register B)
−
ORDMAL (OSD control)
−
ORDMAH (OSD control)
RCSR (TC3 status)
RCCR (TC3 control)
PMPXCR (Port control)
−
PWMCR1A (PWM control1A)
−
PWMCR1B (PWM control1B)
−
PWMDBR1 (PWMDBR1)
−
P3CR1 (P3 I/O control)
EIRE
(Interrupt enable register)
EIRD
ILE
(Interrupt latch)
ILD
CGCR (Divider control)
ADCDR1 (AD conversion result)
ADCDR2 (AD conversion result)
Reserved
−
WDTCR1
−
WDTCR2
Watch-dog timer
control
TBTCR (TBT/TG control)
−
EINTCR (External interrupt control)
SYSCR1
(System control)
SYSCR2
EIRL
(Interrupt enable register)
EIRH
ILL
(Interrupt latch)
ILH
PSWL
(Program status word)
PSWH
(a) Special function registers
Note 1:
Do not access reserved areas by the program.
Note 2:
−: Cannot be accessed.
Note 3:
Write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation
instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Note 4:
When defining address 0003FH with assembler symbols, use GRBS.
Address 0003EH must be GPSW/GFLAG.
Figure 2.1.1 (a) SFR
88CS34-42
2007-09-12
TMP88CS34/CP34
Address
00F80H
81H
B9H
Read
Write
ORDON (OSD Control)
−
OSD Control Register
−
OSD Control Register
ORIRC (OSD Display Counter)
ORIRC (OSD Interrupt Control)
−
CEH
CFH
D0H
D1H
OSD Control Register
−
OSD Control Register
Reserved
IDLEINV (Key-on Wake-up Status)
IDLECR (Key-on Wake-up Control)
Reserved
Reserved
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
ROMCCR (ROM Corrective Control)
−
ROMCC (Data Register Count)
−
ROMCDR (ROM Corrective Data)
Reserved
JECR (Jitter Elimination Control)
−
JESR (Jitter Elimination Status)
Reserved
Reserved
RXCR1 (Remote Control Receive Control)
RXCR2 (Remote Control Receive Control)
RXCTR (Remote Control Receive Counter)
−
RXDBR (Remote Control Receive Data)
−
−
RXSR (Remote Control Receive Status)
Reserved
−
FC8CR (Frequency Division Circuit Control)
Reserved
−
SCCRA (Baud Rate Control A)
SCCRB (Baud Rate Control B)
SCSR (Baud Rate Status)
Reserved
Reserved
FEH
FFH
−
PSELCR (Port3 and 5 Output Status Control)
−
DGINE (Input Control)
(b) Data buffer register
Note 1:
Do not access reserved areas by the program.
Note 2:
−: Cannot be accessed.
Note 3:
Write-only registers cannot use the read-modify-write instructions (bit manipulation instructions such as
SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Figure 2.1.1 (b) DBR
88CS34-43
2007-09-12
TMP88CS34/CP34
2.2
I/O Ports
The TMP88CS34/CP34 has 6 parallel input/output ports (33 pins) as follows:
Primary Function
Secondary Functions
Port P2
1-bit I/O port
External interrupt input, and STOP mode release signal input
Port P3
6-bit I/O port
External interrupt input, remote control signal input, data slicer analog
input, timer/counter input, serial bus interface input/output
Port P4
8-bit I/O port
Pulse width modulation output
Port P5
8-bit I/O port
External interrupt input, timer/counter input, key-on wake-up input,
serial bus interface input/output, analog input and I output from OSD
circuitry.
Port P6
8-bit I/O port
R, G, B and Y/BL output from OSD circuitry, R.G.B and Y/BL input,
analog input, and key-on wake-up input
Port P7
2-bit I/O port
Horizontal synchronous pulse input and vertical synchronous pulse
input to OSD circuitry
Each output port contains a latch, which holds the output data. All input ports do not have
latches, so the external input data should either be held externally until read or reading should
be performed several times before processing. Figure 2.2.1 shows input/output timing
examples.
External data is read from an I/O port in the S1 state of the read cycle during execution of the
read instruction. This timing can not be recognized from outside, so that transient input such as
chattering must be processed by the program. Output data changes in the S2 state of the write
cycle during execution of the instruction which writes to an I/O port.
Fetch cycle
Fetch cycle
Read cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Instruction
execution
cycle
Ex: LD A, (x)
Input strobe
Data input
(a) Input timing
Fetch cycle
Fetch cycle
Write cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Instruction
execution
cycle
Ex: LD
(x), A
Output latch
pulse
Data output
(b) Output timing
NOTE:
The positions of the read and write cycles may vary, dispending on the instruction.
Figure 2.2.1 Input/Output Timing (Example)
88CS34-44
2007-09-12
TMP88CS34/CP34
When reading an I/O port except programmable I/O ports, whether the pin input data or the
output latch contents are read depends on the instructions, as shown below:
(1) Instructions that read the output latch contents
1.
XCH r, (src)
2.
SET/CLR/CPL (src).b
3.
SET/CLR/CPL (pp).g
4.
LD (src).b, CF
5.
LD (pp).b, CF
6.
ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), n
7.
(src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)
(2) Instructions that read the pin input data
2.2.1
1.
Instructions other than the above (1)
2.
(HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)
Port P2 (P20)
Port P2 is a 1bit input/output port. It is also used as an external interrupt input, and a
STOP mode release signal input. When used as an input port, or a secondary function pin,
the output latch should be set to “1”. During reset, the output latch is initialized to “1”.
It is recommended that pin P20 should be used as an external interrupt input, a STOP
mode release signal input, or an input port. If used as an output port, the interrupt latch is
set on the falling edge of the P20 output pulse.
When a read instruction for port P2 is executed, bits 7 to 1 in P2 are read in as undefined
data.
SET/CLR/CPL/others
Output latch
D
Data input
Q
P20 ( INT5 / STOP )
Data input
Control input
STOP
OUTEN
7
6
5
4
3
2
1
P2
(00002H)
Note:
0
P20
INT5
STOP
(Initial value: **** ***1)
*: Don’t care
Figure 2.2.2 Port P2
88CS34-45
2007-09-12
TMP88CS34/CP34
2.2.2
Port P3 (P35 to P30)
Port P3 is an 6-bit input/output port which can be configured as an input or an output in
one-bit unit under software control. Input/output mode is specified by the corresponding bit
in the port P3 input/output control register 1 (P3CR1). Port P3 is configured as an input if
its corresponding P3CR1 bit is cleared to “0”, and as an output if its corresponding P3CR1
bit is set to “1”. During reset, P3CR1 is initialized to “0”, which configures port P3 as an
input. The P3 output latches are also initialized to “1”. Data is written into the output latch
regardless of the P3CR1 contents. Therefore initial output data should be written into the
output latch before setting P3CR1.
Port P3 is also used as an external interrupt input, Remote-control signal input a
timer/counter input, and serial bus interface input/output. When used as a secondary
function input pin except I2C bus interface input/output, the input pins should be set to the
input mode. When used as a secondary function output pin except I2C bus interface
input/output, the output pins should be set to the output mode and beforehand the output
latch should be set to “1”. When P34 and P35 are used as I2C bus interface input/output,
P3CR2 bits should be set to the sink open drain mode, the output latches should be set to
“1”, and the output pins should be set to the output mode.
Note: Input mode port is read the state of input pin. When input/output mode is used mixed,
the contents of output latch setting input mode may be changed by executing bit
manipulation instructions.
Example 1: Outputs an immediate data 5AH to port P3
(P3), 5AH
; P3 ← 5AH
LD
Example 2: Inverts the output of the lower 4 bits (P33 to P30) in port P3
(P3), 00001111B
; P33 to P30 ← P33 to P30
XOR
88CS34-46
2007-09-12
TMP88CS34/CP34
STOP
OUTEN
STOP
OUTEN
P3jCR1
Data input
P3jCR1
Data input
Control input
P3iCR2
Data output
Control output
Control input (*1)
D
Data output
Q
D
P3i
Output latch
Q
(b) P33 to P30
(a) P35 to P34
7
6
P3
(00003H)
P3CR1
7
5
P35
SDA0
4
P34
SCL0
3
P33
TC4
2
P32
5
4
3
2
6
(0002BH)
1
P31
INT4
TC3
0
P30
INT3
RXIN
1
0
P35CR1 P34CR1 P33CR1 P32CR1 P31CR1 P30CR1
P3CR1
7
6
(0FFEH)
“0”
“0”
P3CR2
5
(Initial value: **11 1111)
(Initial value: **00 0000)
0: Input mode
I/O Control for P3
PSELCR
P3j
Output latch
VIN (*2)
Write
only
1: Output mode
4
P35CR2 P34CR2
I/O Control for P3
3
2
“0”
1
P52CR2 P51CR2
0
“0”
(Initial value: 0*00 *00*)
0: Sink open drain
Write
only
1: Tri-state
(*1) only P33, P31, P30
(*2) only P33, P32
Note 1:
*: Don’t care, i = 5 to 4, j = 3 to 0
Note 2:
P3CR1 cannot used the read-modify-write instructions.
(Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)
Note 3:
Clear bit 7, 6, 3 and 0 to “0” in PSELCR.
Figure 2.2.3 Port P3 and P3CR
88CS34-47
2007-09-12
TMP88CS34/CP34
2.2.3
Port P4 (P47 to P40)
Port P4 is an 8-bit input/output port which can be configured as an input or an output in
one-bit unit under software control. Input/Output mode is specified by the corresponding
bit in the port P4 input/output control register (P4CR). Port P4 is configured as an input if
its corresponding P4CR bit is cleared to “0”, and as an output if its corresponding P4CR bit
is set to “1”. During reset, P4CR is initialized to “0”, which configures port P4 as an input.
The P4 output latches are also initialized to “1”. Data is written into the output latch
regardless of the P4CR contents. Therefore initial output data should be written into the
output latch before setting P4CR.
Port P4 is also used as a pulse width modulation (PWM) output. When used as a PWM
output pin, the output pins should be set to the output mode and beforehand the output
latch should be set to “1”.
Note: Input mode port is read the state of input pin. When input/output mode is used mixed,
the contents of output latch setting input mode may be changed by executing bit
manipulation instructions.
STOP
OUTEN
P4iCR
Data input
Data output
D Q
P4i
Output latch
PWMj
P4
(00004H)
P4CR
(0000CH)
7
6
5
4
P47
P46
P45
P44
3
P43
2
P42
1
P41
P40
0
PWM3
PWM2
PWM1
PWM0
7
6
5
4
3
2
1
0
P47CR
P46CR
P45CR
P44CR
P43CR
P42CR
P41CR
P40CR
P4CR
I/O Control for port P4
Note 1:
i = 7 to 0
Note 2:
j = 3 to 0
Note 3:
(Initial value: 1111 1111)
(Initial value: 0000 0000)
0: Input mode
Write
only
1: Output mode
P4CR cannot be used with the read-modify-write instructions.
(Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)
Figure 2.2.4 Ports P4 and P4CR
88CS34-48
2007-09-12
TMP88CS34/CP34
2.2.4
Port P5 (P57 to P50)
Port P5 is an 8-bit input/output port which can be configured as an input or an output in
one-bit unit under software control. Input/output mode is specified by the corresponding bit
in the port P5 input/output control register 1 (P5CR1). Port P5 is configured as an input if
its corresponding P5CR1 bit is cleared to “0”, and as an output if its corresponding P5CR1
bit is set to “1”. During reset, P5CR1 is initialized to “0”, which configures port P5 as an
input. The P5 output latches are also initialized to “1”. Data is written into the output latch
regardless of the P5CR1 contents. Therefore initial output data should be written into the
output latch before setting P5CR1.
Port P5 is also used as is also used as AD converter analog input, external interrupt
input, timer/counter input, serial bus interface input/output, and an on screen display
(OSD) output (I signal). When used as a secondary function input pin except I2C bus
interface input/output, the input pins should be set to the input mode. When used as a
secondary function output pin except I2C bus interface input/output, the output pins should
be set to the output mode and beforehand the output latch should be set to “1”. When P52
and P51 are used as I2C bus interface input/output, P5CR2 bits should be set to the sink
open drain mode, the output latches should be set to “1”, and the output pins should be set
to the output mode. When P57 is used as an OSD output pin, the output pin should be set to
the output mode and beforehand the port 6 data selection register (PIDS) should be clear to
“0”. When used as port P5, the port 6 data selection register (PIDS) should be set to “1”.
Note: Input mode port is read the state of input pin. When input/output mode is used mixed,
the contents of output latch setting input mode may be changed by executing bit
manipulation instructions.
88CS34-49
2007-09-12
TMP88CS34/CP34
DGINEx
Analog input
AINDS
SAIN
STOP
OUTEN
P5jCR1
STOP
OUTEN
P5iCR1
Data input
Data input
Data output
D
B Y
A
S
Q
Output latch
I
P5i
Data output
D
Q
P5j
Output latch
(b) P56 to P54
PIDS
(a) P57
DGINEx
Analog input
AINDS
SAIN
STOP
OUTEN
P5kCR1
STOP
OUTEN
P5lCR1
Data input
Control input
P5lCR2
Data input
Control input
Data output
D
D
Data output
Q
P5k
Output latch
Control output
Q
P5l
Output latch
Control output
(d) P52 to P51
(c) P53
STOP
OUTEN
P5mCR1
Data input
Control input
Data output
D
Q
Output latch
P5m
Control output
(e) P50
P5
(00005H)
7
P57
I
6
P56
AIN3
5
P55
AIN2
4
P54
AIN1
3
P53
INT2
TC1
2
P52
SO1
SDA1
1
P51
SL1
SCL1
0
P50
INT0
TC2
2
1
0
(Initial value: 1111 1111)
SCK1
AIN0
P5CR1
(00008H)
7
6
5
4
3
P57CR1 P56CR1 P55CR1 P54CR1 P53CR1 P52CR1 P51CR1 P50CR1
P5CR1
PSELCR
7
6
(00FFEH)
“0”
“0”
P5CR2
0: Input mode
1: Output mode
I/O Control for P5
5
4
P35CR2 P34CR2
I/O Control for P5
3
“0”
2
(Initial value: 0000 0000)
Write
only
1
P52CR2 P51CR2
0: Sink open drain
1: Tri-state
0
(Initial value: 0*00 *00*)
Write
only
Figure 2.2.5 Ports P5 (1/2)
88CS34-50
2007-09-12
TMP88CS34/CP34
ORP6S
(00FBAH)
7
6
5
4
3
2
P67S
P66S
P65S
P64S
PIDS
YBLCS
Selection of the output data
for port P57
PIDS
DGINE
7
6
(00FFFH)
−
−
5
4
DGINE1
Input control register
DGINE2
DGINE3
Note 2:
0
MPXS
(Initial value: 0000 0000)
0: The OSD output (I)
1: Port P57 output latch
3
2
1
Write
only
0
DGINE5 DGINE4 DGINE3 DGINE2 DGINE1 DGINE0
DGINE0
Note 1:
1
(Initial value: **11 1111)
0: P53 port input/TC1 input/S10 input/INT2 input disable
1: P53 port input/TC1 Input/S10 input/INT2 input enable
0: P54 port input disable
1: P54 port input enable
0: P55 port input disable
1: P55 port input enable
0: P56 port input disable
1: P56 port input enable
Write
only
*: Don’t care, i = 7, j = 6 to 4, k = 3, l = 2 to 1, m = 0
P5CR1 cannot be used with the read-modify-write instructions.
(Bit manipulation instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)
Note 3:
Clear bit 7, 6 and 3 to “0” in PSELCR.
Figure 2.2.6 Ports P5 (2/2)
2.2.5
Port P6 (P67 to P60)
Port P6 is an 8-bit input/output port which can be configured as an input or an output in
one-bit unit under software control. Input/output mode is selected by the corresponding bit
in the port P6 input/output control register (P6CR). Port P6 is configured as an input if its
corresponding P6CR bit is cleared to “0”, and as an output if its corresponding P6CR bit is
set to “1” and P6nS bit is set to “1”. P63 to P60 are sink open drain ports. During reset,
P6CR is initialized to “0”, which configures port P6 as an input. The P6 output latches are
also initialized to “1”.
Data is written into the output latch regardless of the P6CR contents. Therefore initial
output data should be written into the output latch before setting P6CR.
Port P6 is used as an on screen display (OSD) output (R, G, B, and Y/BL signal)/input
(RIN, GIN BIN, Y/BLIN signal), a test video signal output and AD converter analog input.
When used as a secondary function input, the input pins should be set to the input mode.
When used as an OSD output pin, the output pins should be set to the output mode and
beforehand the port P6 data selection register (P67S to P64S) should be clear to “0”. When
used as port P6, the signal control register (P67 to P64) should be set to “1”.
Note1: Input mode port is read the state of input pin. When input/output mode is used mixed,
the contents of output latch setting input mode may be changed by executing bit
manipulation instructions.
Note2: P63 to P61 output “0” after a reset. When these dual-function pins are used as ports, be
sure to set ORP6S2 to “1”
Example: Sets the lower 4 bits (P63 to P60) in port P6 to the output mode, and the other bit
to the input mode.
LD
(P6CR), 0FH
;
P6CR ← 00001111B
88CS34-51
2007-09-12
TMP88CS34/CP34
STOP
OUTEN
STOP
OUTEN
P6iCR
P6jCR
Data input
Data input
RIN, GIN
Data output
R, G, B, Y/BL
D
A Y
Q
Output latch
P6i
BS
D
Data output
Q
P6j
Output latch
P6iS
(b) P63 to P62
(a) P67 to P64
DGINEx
Analog input
AINDS
SAIN
STOP
OUTEN
P6kCR
Data input
BIN, Y/BLIN
Data output
D
Q
P6k
Output latch
(c) P61 to P60
P6
(00006H)
P6CR
(0000DH)
7
P67
Y/BL
6
P66
B
5
P65
G
4
P64
R
3
P63
RIN
2
P62
GIN
1
P61
BIN
AIN5
0
P60
Y/BLIN
AIN4
7
6
5
4
3
2
1
0
P67CR
P66CR
P65CR
P64CR
P63CR
P62CR
P61CR
P60CR
P6CR
ORP6S
(00FBAH)
0: Input mode
1: Output mode
I/O Control for port P6
7
6
5
4
3
2
P67S
P66S
P65S
P64S
PIDS
YBLCS
P67S to P64S
DGINE
7
6
(00FFFH)
−
−
5
4
3
2
1
0
MPXS
(Initial value: 0000 0000)
1
0:
1:
0:
1:
Input Control register
DGINE5
ORP6S2
7
6
5
4
(00FA1H)
−
−
−
−
P60 port input/YIN/BLIN disable
P60 port input/YIN/BLIN enable
P61 port input/BIN disable
P61 port input/BIN enable
3
2
1
Fixed at 1 Fixed at 1 Fixed at 1
Note 1:
(Initial value: **11 1111)
Write
only
0
−
Be sure to fix these bits to “1”, using the initial routine.
Note 2:
Write
only
0
DGINE5 DGINE4 DGINE3 DGINE2 DGINE1 DGINE0
DGINE4
(Initial value: 0000 0000)
Write
only
0: The OSD output (R, G, B, Y/BL)
1: Port P6i output latch
Selection of the output data
for port P6i
(Initial value: 1111 1111)
(Initial value: **** 000*)
Write
only
*: Don’t care, i = 7 to 4, j = 1 to 0
P6CR and ORP6S cannot be used with the read-modify-write instructions. (Bit manipulations such as SET,
CLR, etc. and logical operation such as AND, OR, etc.)
Note3:
P63 to P61 output “0” after a reset. When these dual-function pins are used as port, be sure to set ORP6S2
to “1”.
Figure 2.2.7 Ports P6, P6CR, and P67S to P64S
88CS34-52
2007-09-12
TMP88CS34/CP34
2.2.6
Port P7 (P71 to P70)
Port P7 is a 2bit input/output port, and is also used as a vertical synchronous signal ( VD )
input and a horizontal synchronous signal ( HD ) input for the on screen display (OSD)
circuitry.
The output latches, are initialized to “1” during reset. When used as an input port or a
secondary function pin, the output latch should be set to “1”.
When a read instruction for port P7 is executed, bits 7 to 2 in P7 are read in as undefined
data.
STOP
OUTEN
P7iCR
Data input
HD , VD
Data output
D
Q
P7i
Output latch
7
6
5
4
3
2
P7
(00007H)
P7CR
7
6
5
4
3
Note 1:
I/O Control for P7
0
P70
VD
HD
2
(00009H)
P7CR
1
P71
1
0
P71CR
P70CR
0: Input mode
1: Output mode
(Initial value: **** **11)
(Initial value: **** **00)
Write
only
i = 1 to 0, *: Don’t care
Figure 2.2.8 Ports P7
88CS34-53
2007-09-12
TMP88CS34/CP34
2.3
Time Base Timer (TBT)
The time base timer generates time base for key scanning, dynamic displaying, etc. It also
provides a time base timer interrupt (INTTBT). The time base timer is controlled by a control
register (TBTCR) shown in Figure 2.3.1.
An INTTBT is generated on the first rising edge of source clock (the divider output of the
timing generator) after the time base timer has been enabled. The divider is not cleared by the
program; therefore, only the first interrupt may be generated ahead of the set interrupt period.
The interrupt frequency (TBTCK) must be selected with the time base timer disabled (When
the time base timer is changed from enabling to disabling, the interrupt frequency can’t be
changed.)
Both frequency selection and enabling can be performed simultaneously.
Example: Sets the time base timer frequency to fc/216 [Hz] and enables an INTTBT interrupt.
LD
(TBTCR) , 00000010B
;
TB TCK="010"
LD
(TBTCR) , 00001010B
;
TBTEN="1"
SET
(EIRL). 6
23
24
fc/2 , fc/2
21
22
fc/2 , fc/2
16
17
fc/2 , fc/2
14
15
fc/2 , fc/2
13
14
fc/2 , fc/2
12
13
fc/2 , fc/2
11
12
fc/2 , fc/2
9
10
fc/2 , fc/2
MPX
INTTBT
interrupt
A
request
B
C
Source clock
Source clock Rising
D Y
edge
E
detector
F
TBTEN
G
HS
INTTBT
3
TBTCK
TBTEN
Enable TBT
TBTCR
Interrupt
period
Time Base Timer Control Register
(a) Configuration
(b) Time Base Timer Interrupt
Figure 2.3.1 Time Base Timer
88CS34-54
2007-09-12
TMP88CS34/CP34
TBTCR
(00036H)
7
6
5
4
3
“0”
−
−
“0”
TBTEN
TBTEN
2
1
0
TBTCK
(Initial value: 0**0 0***)
0: Disable
Time base timer
enable/disable
1: Enable
NORMAL, IDLE mode
DV1CK = 0
DV1CK = 1
23
fc/2 [Hz]
fc/2
21
fc/2
22
010
fc/2
16
fc/2
17
011
fc/2
14
fc/2
15
100
fc/2
13
fc/2
14
101
fc/2
12
fc/2
13
fc/2
11
fc/2
12
fc/2
9
fc/2
10
000
001
TBTCK
Time base timer interrupt
frequency select
110
111
fc/2 [Hz]
24
Write
only
Note 1:
fc: High-frequency clock [Hz], *: Don’t care
Note 2:
TBTCR is a write-only register and must not be used with any of read-modify-write instructions.
Note 3:
Set bit 7 and 4 in TBTCR to “0”.
Figure 2.3.2 Time Base Timer and Divider Output Control Register
Table 2.3.1 Time Base Timer Interrupt Frequency (Example: at fc = 16MHz)
Time Base Timer Interrupt Frequency [Hz]
TBTCK
NORMAL, IDLE mode
DV1CK = 0
DV1CK = 1
000
1.90
0.95
001
7.62
3.81
010
244.14
122.07
011
976.56
488.28
100
1953.12
976.56
101
3906.25
1953.12
110
7812.50
3906.25
111
31250
15625
88CS34-55
2007-09-12
TMP88CS34/CP34
2.4
Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to rapidly detect the CPU malfunctions such as
endless looping caused by noise or the like, or deadlock and resume the CPU to the normal
state.
The watchdog timer signal for detecting malfunction can be selected either a reset output or a
pseudo non-maskable interrupt request. However, selection is possible only once after reset. At
first the reset output is selected.
When the watchdog timer is not being used for malfunction detection, it can be used as a
timer to generate an interrupt at fixed intervals.
2.4.1
Watchdog Timer Configuration
Reset release signal from T.G.
MPX
23
24
A
B
C
D
fc/2 , fc/2
21
22
fc/2 , fc/2
19
20
fc/2 , fc/2
17
18
fc/2 , fc/2
R
Binary Counters
Y
Clock
Overflow
1
S
Reset output
WDT output
2
S
Q
RESET
Clear
Interrupt request
2
INTWDT
Internal reset
Q
S
WDTT
R
WDTEN
Writing
disable code
Writing
clear code
WDTOUT
Controller
00034H
WDTCR1
00035H
WDTCR2
MPX: Multiplexer
Watchdog timer control registers
Figure 2.4.1 Watchdog Timer Configuration
2.4.2
Watchdog Timer Control
Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The
watchdog timer is automatically enabled after reset.
(1) Malfunction detection methods using the watchdog timer
The CPU malfunction is detected at follows.
1.
Setting the detection time, selecting output, and clearing the binary counter.
2.
Repeatedly clearing the binary counter within the setting detection time.
Note:
The watchdog timer consists of an internal divider and two-stage binary counter.
Writing the clear code (4EH) clears the binary counter, but not the internal divider.
The minimum overflow time for the binary counter might be three quarters of the
WDTCR1 (WDTT) time setting depending on when the clear code (4EH) is written
into the WDTCR2 register. So, write the clear code on a cycle which is shorter than
that minimum overflow time.
88CS34-56
2007-09-12
TMP88CS34/CP34
If the CPU malfunctions such as endless looping or deadlock occur for any cause, the
watchdog timer output will become active at the rising of an overflow from the binary
counters unless the binary counters are cleared. At this time, when WDTOUT = 1 a reset is
generated, which drivers the RESET pin low to reset the internal hardware and the
external circuit. When WDTOUT = 0, a watchdog timer interrupt (INTWDT) is generated.
The watchdog timer temporarily stops counting in STOP mode including warm-up or
IDLE mode, and automatically restarts (continues counting) when the STOP/IDLE mode is
released.
88CS34-57
2007-09-12
TMP88CS34/CP34
Example: Sets the watchdog timer detection time to 221/fc [s] and resets the CPU malfunction.
LD
(WDTCR2), 4EH
; Clears the binary counters
LD
(WDTCR1), 00001101B ;
WDTT ← 10, WDTOUT ← 1
LD
(WDTCR2), 4EH
Clears the binary counters
;
Within 3/4 of WDT
(always clear immediately before
and after changing WDTT)
detection time
LD
(WDTCR2), 4EH
;
Clears the binary counters
LD
(WDTCR2), 4EH
;
Clears the binary counters
Within 3/4 of WDT
detection time
Watchdog Timer Register 1
WDTCR1
(00034H)
7
6
5
4
3
2
WDTEN
WDTEN
1
0
WDTOUT
WDTT
(Initial value: **** 1001)
0: Disable (It is necessary to write the disable code to
WDTCR2)
Watchdog timer
enable/disable
1: Enable
NORMAL mode
DV1CK = 0
WDTT
Note 1:
2 /fc
21
2 /fc
19
2 /fc
2 /fc
10
2 /fc
Write
only
26
2 /fc
23
01
24
22
20
2 /fc
11
WDTOUT
DV1CK = 1
25
2 /fc
00
Watchdog timer
detection time [s]
0: Interrupt request
Watchdog timer
output select
1: Reset output
WDTOUT cannot be set to “1” by program after clearing WDTOUT to “0”.
Note 2:
fc: High-frequency clock [Hz], *: Don’t care
Note 3:
WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions.
Note 4:
The watchdog timer must be disabled or the counter must be cleared immediately before entering to the
STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing
the STOP mode.
Note 5:
Just right before disabling the watchdog timer, disable the acceptance of interrupts (DI) and clear the
watchdog timer.
If the watchdog timer is disabled under conditions other than the above, the proper operation cannot be
guaranteed.
Watchdog Timer Register 2
WDTCR2
7
6
5
4
3
2
1
0
(Initial value: **** ****)
(00035H)
WDTCR2
Watchdog timer control
code write register
4EH: Watchdog timer binary counter clear (clear code)
B1H: Watchdog timer disable (disable code)
Others: Invalid
Note 1:
The disable code is invalid unless written when WDTEN = 0.
Note 2:
*: Don’t care
Note 3:
The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4:
Write
only
Clears the binary counter does not clear the source clock.
It is recommended that the time to clear is set to 3/4 of the detecting time.
Note 5:
The watchdog timer counter must be disabled by writing the disable code (B1H) to WDRCR2 after writing
WDTCR2 to. “4EH”.
Figure 2.4.2 Watchdog Timer Control Registers
88CS34-58
2007-09-12
TMP88CS34/CP34
(2) Watchdog timer enable
The watchdog timer is enabled by setting WDTEN (bit 3 in WDTCR1) to “1”. WDTEN is
initialized to “1” during reset, so the watchdog timer operates immediately after reset is
released.
Example: Disables watchdog timer
LDW (WDTCR1), 00001000B
;
WDTEN ← 1
(3) Watchdog timer disable
To disable the watchdog timer, clear the interrupt mask enable flag (IMF) to “0” and
write the clear code (4EH) into WDTCR2. Then, clear WDTEN (bit 3 in WDTCR1) to “0”.
When WDTEN is “0”, the watchdog timer is disabled by writing the disable code (B1H)
into WDTCR2. If WDTEN is cleared to “0” after the disable code has been written into
WDTCR2, the watchdog timer is not disabled. While it is disabled, its binary counter is
cleared.
Example:
DI
LD
LDW
EI
;
;
;
;
(WDTCR2), 4EH
(WDTCR1), B101H
Disables interrupt acceptance.
Clears the watchdog timer.
Disables the watchdog timer.
Enables interrupt acceptance.
Table 2.4.1 Watchdog Timer Detection Time (Example: fc = 16 MHz)
Watchdog timer detection time [s]
WDTT
2.4.3
NORMAL mode
DV1CK = 0
DV1CK = 1
00
2.097
4.194
01
524.288 m
1.048
10
131.072 m
262.1 m
11
32.768 m
65.5 m
Watchdog Timer Interrupt (INTWDT)
This is a pseudo non-maskable interrupt which can be accepted regardless of the
contents of the EIR. If a watchdog timer interrupt or a software interrupt is already
accepted, however, the new watchdog timer interrupt waits until the previous interrupt
processing is completed (the end of the [RETN] instruction execution).
The stack pointer (SP) should be initialized before using the watchdog timer output as an
interrupt source with WDTOUT.
Example: Watchdog timer interrupt setting up
LD
SP, 023FH
;
LD
(WDTCR1), 00001000B
;
2.4.4
Sets the stack pointer
WDTOUT ← 0
Watchdog Timer Reset
If the watchdog timer output becomes active, a reset is generated, which drivers the
RESET pin (sink open drain input/output with pull-up) low to reset the internal hardware.
The reset output time is about 8/fc to 24/fc [s] (0.5 to 1.5 μs at fc = 16.0 MHz).
Note: If there is any fluctuation in the oscillation frequency at the start of clock oscillation, the
reset time includes error. Thus, regard the reset time as an approximate value.
88CS34-59
2007-09-12
TMP88CS34/CP34
19
2 /fc [s]
17
2 /fc
(WDTT = 11B)
Clock
Binary counter
1
2
3
0
1
2
3
0
Overflow
INTWDT interrupt
WDT reset output
(High-Z)
(“L” output)
Writes 4EH to WDTCR2
Figure 2.4.3 Watchdog Timer Interrupt/Reset
88CS34-60
2007-09-12
Note:
B
A
12
S A Y
88CS34-61
2
Clock
Timer/counter 1 control register
SCAP1
Capture
Window mode
S
AY
B
MPX
Clear
Set Q
Command start
METT1
TC1CR
A
B Y
C
S
D
MPX
TC1CK
B
MPX
Falling
Ext.
trigger
Edge detector
Rising
fc/2 , fc/2
7
8
fc/2 or fc/2
3
4
fc/2 or fc/2
11
TC1 pin
INT2ES
Pulse width
measurement
mode
Ext.
trigger start
Decoder
2
TC1S
TC1DRA
CMP
16-bit timer registers 1A, 1B
TC1DRB
16-bit up-counter
Clear
INTTC1 interrupt
Match
CMP: Comparator
MPX: Multiplexer
Pulse width
measurement
mode
2.5.1
MPX
Y
2.5
S
MCAP1
TMP88CS34/CP34
16-Bit Timer/Counter1 (TC1A)
Configuration
Be sure to set the function of input/output pins correctly. For details, see the section on I/O port control registers.
Figure 2.5.1 Timer/Counter 1
2007-09-12
TMP88CS34/CP34
2.5.2
Control
The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two
16-bit timer registers (TC1DRA and TC1DRB).
TC1DRA
(00010, 00011H)
15
14
13
12
11
10
9
8
7
6
TC1DRAH (00011H)
5
4
3
2
1
0
TC1DRAL (00010H)
Read/Write
TC1DRB
(00012, 00013H)
TC1DRBH (00013H)
TC1DRBL (00012H)
Read only
TC1CR
(00014H)
TC1M
7
6
5
“0”
ACPAP1
MCAP1
METT1
4
3
TC1S
TC1 operating mode select
2
TC1CK
00:
01:
10:
11:
1
0
Read/Write
TC1M
(Initial value: 0000 0000)
Timer/external trigger timer/event counter mode
Window mode
Pulse width measurement mode
Reserved
NORMAL, IDLE mode
DV7CK = 0, DVCK = 00
DV1CK = 0
TC1CK
TC1 source clock select [Hz]
fs/2
fc/2
7
fc/2
8
fc/2
3
fc/2
4
fc/2
01
10
DV1CK = 1
11
00
11
12
R/W
External clock (TC1 pin input)
Timer Extend Event Window Pulse
TC1S
TC1 start control
00: Stop and counter clear
○
○
01: Command start
○
×
10: External trigger start at the rising edge
×
○
11: External trigger start at the falling edge
×
○
0: Auto-capture disable
1: Auto-capture enable
ACAP1
Auto capture control
MCAP1
Pulse width measurement
mode control
0: Double edge capture
1: Single edge capture
METT1
External trigger timer
mode control
0: Trigger start
1: Trigger start and stop
○
○
○
×
×
×
○
○
○
○
○
○
PPG
○
×
○
○
Note 1:
fc: High-frequency clock [Hz]
Note 2:
The timer register consists of two shift registers. A value set in the timer register is put in effect at the rising
edge of the first source clock pulse that occurs after the upper data (TC1DRAH) are written. Therefore, the
lower byte must be written before the upper byte (it is recommended that a 16-bit access instruction be
used in writing). Writing only the lower data (TC1DRAL) does not put the setting of the timer register in
effect.
Note 3:
Set the mode, source clock PPG control and timer F/F control when TC1 stops (TC1S = 00).
Note 4:
Auto-capture can be used in only timer, event counter, and window modes.
Note 5:
Values to be loaded to timer registers must satisfy the following condition.
TC1DRA > TC1DRB, TC1DRA > 1
Note 6:
Always write “0” to TFF1 except PPG output mode.
Note 7:
On entering STOP mode, the TC1 start control (TC1S) is cleared to “00” automatically. So, the timer stops.
Once the STOP mode has been released, to start using the timer counter, set TC1S again.
Note 8:
In the Auto-capture function, when the capture value is read after stop and clear counter or Auto-capture
disable is executed by the TC1 start control (TC1S), the correct capture value might not be able to be
read.When using Auto-capture function, set capture to enable.
Note 9: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting
TC1CR<ACAP1> to “1”. Therefore, to read the captured value, wait at least one cycle of the internal source
clock before reading TC1DRB for the first time.
Figure 2.5.2 Timer Registers and TC1 Control Register
88CS34-62
2007-09-12
TMP88CS34/CP34
2.5.3
Function
Timer/counter 1 has five operating modes: timer, external trigger timer, event counter,
window, pulse width measurement.
(1) Timer mode
In this mode, counting up is performed using the internal clock. The contents of TC1DRA
are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is
generated, and the counter is cleared to “0”. Counting up resumes after the counter is
cleared. The current contents of up-counter can be transferred to TC1DRB by setting
ACAP1 (bit 6 in TC1CR) to “1” (software capture function). (Auto-capture function)
Table 2.5.1 Source Clock (internal clock) for Timer/Counter 1 (Example: at fc = 16.0 MHz)
NORMAL, IDLE mode
DV1CK = 0
TC1CK
DV1CK = 1
Maximum time
setting [s]
Resolution [μs]
Resolution [μs]
Maximum time
setting [s]
16.78
00
128.0
8.39
256.0
01
8.0
0.524
16.0
1.049
10
0.5
32.77 m
1.0
65.54 m
Example 1: Sets the timer mode with source clock fc/211 [Hz] and generates an interrupt 1
later (at fc = 16 MHz)
LDW
(TC1DRA), 1E84H
;
Sets the timer register
(1 s ÷ 211/fc = 1E84H)
DI
SET
(EIRL). 4
;
Enable INTTC1
EI
LD
(TC1CR), 00000000B
;
Selects the source clock and mode
LD
(TC1CR), 00010000B
;
Starts TC1
Example 2: Auto-capture
LD
(TC1CR), 01010000B
:
:
LD
WA, (TC1DRB)
88CS34-63
;
;
;
ACAP1 ← 1 (Capture)
Wait at least one cycle of the
internal source clock
Reads the capture value
2007-09-12
TMP88CS34/CP34
Count start
Source clock
Up-counter
0
TC1DRA
?
1
2
3
n −1 n 0
4
1
2
3
4
5
6
7
n
Match detect
INTTC1 interrupt
Counter clear
(a) Timer mode
Source clock
Up-counter
TC1DRB
m−2
?
m−1
m+1
m
m−1
m+2
Capture
m
m+1
n−1
m+2
n
n−1
n+1
Capture
n
n+1
ACAP1
(b) Auto-capture
Figure 2.5.3 Timer Mode Timing Chart
(2) External trigger timer mode
In this mode, counting up is started by an external trigger. This trigger is the edge of the
TC1 pin input. Either the rising or falling edge can be selected with TC1S. Source clock is
an internal clock. The contents of TC1DRA is compared with the contents of up-counter. If a
match is found, an INTTC1 interrupt is generated, and the counter is cleared to “0” and
halted. The counter is restarted by the selected edge of the TC1 pin input.
When METT1 (bit 6 in TC1CR) is “1”, inputting the edge to the reverse direction of the
trigger edge to start counting clears the counter, and the counter is stopped. Inputting a
constant pulse width can generate interrupts. When METT1 is “0”, the reverse directive
edge input is ignored. The TC1 pin input edge before a match detection is also ignored.
The TC1 pin input has the noise rejection; therefore, pulses of 7/fc [s] or less are rejected
as noise. A pulse width of 13/fc [s] or more is required for edge detection in NORMAL or
IDLE mode.
Example 1: Detects rising edge in TC1 pin input and generates an interrupt 100 μs later.
(at fc = 16.0 MHz, DV1CK = 1)
LDW
(TC1DRA), 0064H
; 100 μs ÷ 24/fc = 64H
DI
SET
(EIRL). 4
; INTTC1 interrupt enable
EI
LD
(TC1CR), 00001000B
; Selects the source clock and mode
LD
(TC1CR), 00101000B
; TC1 external trigger start, METT1 = 0
Example 2: Generates an interrupt, inputting “L” level pulse (pulse width: 4 ms or more) to
the TC1 pin. (at fc = 16.0 MHz, DV1CK = 1)
LDW
(TC1DRA), 00FAH
; 4 ms ÷ 28/fc = FAH
DI
SET
(EIRL). 4
; INTTC1 interrupt enable
EI
LD
(TC1CR), 00000100B
; Selects the source clock and mode
LD
(TC1CR), 01110100B
; TC1 external trigger start, METT1 = 1
88CS34-64
2007-09-12
TMP88CS34/CP34
Count start
Count start
TC1S = 10
at the rising edge
TC1 pin input
Internal clock
Up-counter
0
1
TC1DRA
2
3
n−1
4
n
Match detect
n
0
1
2
3
Counter clear
INTTC1 interrupt
(a) Trigger start (METT1 = 0)
Count start
Count clear
TC1S = 10
at the rising edge
Count start
TC1 pin input
Internal clock
Up-counter
0
2
1
TC1DRA
m−1 m
3
0
1
2
n−1 n
3
0
n
Match detect
INTTC1 interrupt
(b) Trigger start and Stop (METT1 = 1)
Counter clear
Note: m < n
Figure 2.5.4 External Trigger Timer Mode Timing Chart
(3) Event counter mode
In this mode, events are counted at the edge of the TC1 pin input and bit 4 or 5 in TC1CR.
Either the rising or falling edge can be selected with the external trigger. The contents of
TC1DRA are compared with the contents of up-counter. If a match is found, an INTTC1
interrupt is generated, and the counter is cleared.
Match detect is executed on other edge of count-up. A match can not be detected and
INTTC1 is not generated when the pulse is still in same state.
Setting ACAP1 to “1” transfers the current contents of up-counter to TC1DRB
(Auto-capture function).
Count start
TC1S = 10
at the falling
edge
TC1 pin input
0
Up-counter
TC1DRA
INTTC1 interrupt
?
1
2
n−1
n
0
1
2
n
Match detect
Counter clear
Figure 2.5.5 Event Counter Mode Timing Chart
88CS34-65
2007-09-12
TMP88CS34/CP34
Table 2.5.2 Input Pulse Width for Timer/Counter 1
Minimum pulse width [s]
NORMAL/IDLE
3
“H” width
2 /fc
“L” width
2 /fc
3
(4) Window mode
Counting up is performed on the rising edge of the pulse that is the logical AND-ed
product of the TC1 pin input (window pulse) and an internal clock. The contents of
TC1DRA are compared with the contents of up-counter. If a match is found, an INTTC1
interrupt is generated, and the counter is cleared. Positive or negative logic for the TC1 pin
input can be selected with bit4 or 5 in TC1CR.
It is necessary that the maximum applied frequency be such that the counter value can
be analyzed by the program. That is; the frequency must be considerably slower than the
selected internal clock.
Count start
Count stop
Count start
Command start
TC1 pin input
Internal clock
Up-counter
0
?
TC1DRA
1
2
3
5
4
6
7 0
1
2
3
7
Match detect
INTTC1interrupt
Counter clear
(a) Positive logic (at TC1S = 10)
Command start
Count start
Count stop
Count start
TC1 pin input
Internal clock
Up-counter
0
?
TC1DRA
1
2
3
4
5
6
7
8
9 0
1
9
INTTC1 interrupt
Match detect
Counter
clear
(b) Negative logic (at TC1S = 11)
Figure 2.5.6 Window Mode Timing Chart
(5) Pulse width measurement mode
In this mode, counting is started by the external trigger (set to external trigger start by
TC1CR). The trigger can be selected either the rising or falling edge of the TC1 pin input.
The source clock is used an internal clock. On the next falling (rising) edge, the counter
contents are transferred to TC1DRB and an INTTC1 interrupt is generated. The counter is
cleared when the single edge capture mode is set. When double edge capture is set, the
counter continues and, at the next rising (falling) edge, the counter contents are again
transferred to TC1DRB. If a falling (rising) edge capture value is required, it is necessary to
read out TC1DRB contents until a rising (falling) edge is detected. Falling or rising edge is
selected with the external trigger TC1S (bit4 or 5 in TC1CR), and single edge or double
edge is selected with MCAP1 (bit 6 in TC1CR).
88CS34-66
2007-09-12
TMP88CS34/CP34
Note 1: Be sure to read the captured value from TC1DRB before the next trigger edge is
detected. If fail to read it, it becomes undefined. It is recommended that a 16-bit access
instruction be used to read from TC1DRB.
Note 2: If either the falling or rising edge is used in capturing values, the counter stops at “1”
after a value has been captured until the next edge is detected. So, the value captured
next will become “1” larger than the value captured right after capturing starts.
Note 3: In the Pulse width measurement mode, the capture value of the first time after the timer
starts might not be a correct value. Thus, execute the dummy read once.
Example: Duty measurement (resolution fc/27 [Hz] DV1CK = 0)
CLR (INTTC1SW). 0
; INTTC1 service switch initial setting:
Clears Bit 0 of INTTC1SW. This bit is
inverted by CPL instruction before
INTTC1 is generated.
LD
(TC1CR), 00000110B
; Sets the TC1 mode and source clock
DI
SET
(EIRL). 4
; Enables INTTC1
EI
LD
(TC1CR), 00100110B
; Starts TC1 with an external trigger
..
at MCAP1 = 0
..
..
PINTTC1: CPL
(INTTC1SW). 0
; Complements INTTC1 service switch
JRS
F, SINTTC1
LD
WA, (TC1DRBL)
; Reads TC1DRB
(“H” level pulse width)
Lower address in TC1DRBL:
TC1DRB
LD
(HPULSE), WA
RETI
SINTTC1: LD
WA, (TC1DRBL)
; Reads TC1DRB (Period)
LD
(WIDTH), WA
..
.
RETI
; Duty calculation
..
.
VINTTC1: DW
PINTTC1
; Sets INTTC1
WIDTH
HPULSE
TC1 pin
INTTC1
INTTC1SW
88CS34-67
2007-09-12
88CS34-68
INTTC1 interrupt
TC1DRB
Up-counter
Internal clock
TC1 pin input
INTTC1 interrupt
TC1DRB
Up-counter
Internal clock
TC1 pin input
0
1
1
Count start
0
Count start
2
2
3
3
4
4
n
Capture
n 0
1
n
1
m
m−1 m 0
n
n+2
Capture
n+1
Count start
2
Capture
(b) Double edge capture (MCAP1 = 0)
n−1
(a) Single edge capture (MCAP1 = 1)
n−1
Count start
4
1
m
Capture
m−1 m 0
3
[Application]
2
n’
n’ + 1 n’ + 2
n’
Capture
(1) Period/Frequency measurement
(2) Duty measurement
n’ − 1
[Application] High or low pulse width measurement
3
Trigger
TMP88CS34/CP34
Figure 2.5.7 Pulse Width Measurement Mode Timing Chart
2007-09-12
TMP88CS34/CP34
2.6
16-Bit Timer/Counter 2 (TC2A)
2.6.1
Configuration
TC2S
Port
(Note)
TC2 pin
H
Window
23
24
fc/2 or fc/2
13
14
fc/2 or fc/2
8
9
fc/2 or fc/2
3
4
fc/2 or fc/2
A
B
CY
D
Clear
B
Timer/
event counter
Y
Source
A clock
S
16-bit up-counter
TC2M
CMP
S
3
TC2CK
INTTC2
interrupt
TC2S
TC2DR
TC2CR
16-bit timer register 2
MPX: Multiplexer
CMP: Comparator
TC2 control register
Note:
Propagation of control input/output requires the correct I/O port setting. For details, see the section on I/O
ports.
Figure 2.6.1 Timer/Counter 2 (TC2)
88CS34-69
2007-09-12
TMP88CS34/CP34
2.6.2
Control
The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a
16-bit timer register 2 (TC2DR). Reset does not affect TC2DR.
TC2DR
(00016,
00017H)
15
TC2CR
(00015H)
7
TC2M
14
13
12
11
10
9
8
7
6
TC2DRH (00017H)
5
4
3
2
1
0
TC2DRL (00016H)
Read/Write
6
5
TC2S
TC2
operating mode select
4
3
2
1
TC2CK
0
TC2M
(Initial value: **00 00*0)
0: Timer/event counter mode
1: Window mode
NORMAL1/2, IDLE1/2 mode
DV1CK = 0
fc/2
fc/2
24
fc/2
13
fc/2
14
fc/2
8
fc/2
9
011
fc/2
3
fc/2
4
100
Reserved
101
Reserved
000
001
TC2CK
TC2S
TC2
source clock select [Hz]
TC2
start control
DV1CK = 1
23
010
Write
only
Reserved
Reserved
110
Reserved
111
External clock (TC2 pin input)
0: Stop and counter clear
1: Start
Note 1:
fc: High-frequency clock [Hz], *: Don’t care
Note 2:
Writing to the lower byte of timer register 2 (TC2DRL), the comparison is inhibited until the upper byte
(TC2DRH) is written. After writing to the upper byte, any match during 1 machine cycle (instruction
execution cycle) is ignored.
Note 3:
Set the mode and source clock when the TC2 stops (TC2S = 0).
Note 4:
Values to be loaded to timer register must satisfy the following condition.
TC2DR > 1
Note 5:
Note 6:
TC2CR are write-only registers and must not be used with any of the read-modify-write instructions.
When STOP mode is started, timer counter is stopped and cleared. Set TC2S to “1” after STOP mode is
released for restarting timer counter.
Figure 2.6.2 Timer Register 2 and TC2 Control Register
88CS34-70
2007-09-12
TMP88CS34/CP34
2.6.3
Function
The timer/counter 2 has three operating modes: timer, event counter and window modes.
(1) Timer mode
In this mode, the internal clock is used for counting up. The contents of TC2DR are
compared with the contents of up-counter. If a match is found, a timer/counter 2 interrupt
(INTTC2) is generated, and the counter is cleared. Counting up is resumed after the
counter is cleared.
Table 2.6.1 Source Clock (internal clock) for Timer/Counter 2 (at fc = 16.0 MHz)
NORMAL, IDLE mode
DV1CK = 0
TC2CK
DV1CK = 1
Maximum
time setting
Resolution
Resolution
Maximum
time setting
1.05 [s]
19.1 [h]
000
524.3 [ms]
9.54 [h]
001
512.0 [μs]
33.6 [s]
1.02 [ms]
010
16.0 [μs]
1.05 [s]
32.0 [μs]
2.09 [s]
65.5 [ms]
1.12 [min]
011
0.5 [μs]
32.8 [ms]
1.0 [μs]
100
Reserved
Reserved
Reserved
Reserved
101
Reserved
Reserved
Reserved
Reserved
Example: Sets the source clock fc/24 [Hz] and generates an interrupt event 25 ms
(at fc = 16 MHz, DV1CK = 1)
LDW (TC2DR), 61A8H
; Sets TC2DR (25 ms ÷ 24/fc = 61A8H)
DI
SET
(EIRH).6
; Enable INTTC2 interrupt
EI
LD
(TC2CR), 00001100B
; Selects TC2 source clock
LD
(TC2CR), 00101100B
; Starts TC2
Count start
Source clock
Up-Counter
0
1
2
3
n−1 n 0
4
Match detect
Timer register
1
2
3
Counter clear
n
INTTC2 interrupt
Figure 2.6.3 Timer Mode Timing Chart
88CS34-71
2007-09-12
TMP88CS34/CP34
(2) Event counter mode
In this mode, events are counted on the rising edge of the TC2 pin input. The contents of
TC2DR are compared with the contents of the up-counter. If a match is found, an INTTC2
interrupt is generated, and the counter is cleared. The minimum pulse width to the TC2 pin
is shown in Table 2.6.2. Two or more machine cycles are required for both the “H” and “L”
levels of the pulse width. Match detect is executed on the falling edge of the TC2 pin. A
match can not be detected and INTTC2 is not generated when the pulse is still in a falling
state.
Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts
later.
LDW (TC2DR), 640
; Sets TC2DR
DI
SET
(EIRH). 6
; Enables INTTC2 interrupt
EI
LD
(TC2CR), 00011100B
; Selects TC2 source clock
LD
(TC2CR), 00111100B
; Starts TC2
Table 2.6.2 Timer/Counter 2 External Clock Source
Minimum pulse width [S]
NORMAL, IDLE mode
3
“H” width
2 /fc
“L” width
2 /fc
3
Count start
TC2 pin input
Up-counter
0
1
2
n−1
3
Match detect
Timer register
n
0
1
2
3
Counter clear
n
INTTC2 interrupt
Figure 2.6.4 Event Counter Mode Timing Chart
88CS34-72
2007-09-12
TMP88CS34/CP34
(3) Window mode
In this mode, counting up performed on the rising edge of an internal clock during TC2
external pin input (window pulse) is “H” level. The contents of TC2DR are compared with
the contents of up-counter. If a match found, an INTTC2 interrupt is generated, and the
up-counter is cleared.
The maximum applied frequency (TC2 input) must be considerably slower than the
selected internal clock.
Example: Generates an interrupt, inputting “H” level pulse width of 120 ms or more.
(at fc = 16.0 MHz, DV1CK = 1)
LDW (TC2DR), 0075H
; Sets TC2DR (120 ms ÷ 214/fc = 0075H)
DI
SET
(EIRH). 6
; Enables INTTC2 interrupt
EI
LD
(TC2CR), 00000101B
; Selects TC2 source clock
LD
(TC2CR), 00100101B
; Starts TC2
TC2 pin input
Internal clock
Up-counter
TC2DR
0
1
2
n−3
n−2
n−1 n 0
1
2
3
n
Match detect
INTTC2 interrupt
Counter clear
Figure 2.6.5 Window Mode Timing Chart
88CS34-73
2007-09-12
TMP88CS34/CP34
2.7
8-Bit Timer/Counter3 (TC3B)
2.7.1
Configuration
Rising
Edge
detector
TC3S
INTTC3
interrupt
Falling
TC3ES
Clear
TC3 pin
A
Y
B
H
A
B
C
Y
D
E
F
G
S
fc/213 or fc/214
fc/212 or fc/213
fc/211 or fc/212
fc/210 or fc/211
fc/29 or fc/210
fc/28 or fc/29
fc/27 or fc/28
Source clock
8-bit up-counter
Overflow
TC3S
Comparator
Match detect
A
Y
B
3
Capture
Capture
TC3DRB
S
TC3DRA
TC3CK
ACAP
8-bit timer register
TC3S
TC3M
TC3CR
TC3 control register
Note:
Propagation of control input/output requires the correct I/O port setting. For details, see the section on I/O
pots.
Figure 2.7.1 Timer/Counter 3 (TC3)
88CS34-74
2007-09-12
TMP88CS34/CP34
2.7.2
Control
The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two
8-bit timer registers (TC3DRA and TC3DRB) and port multiplex control register
(PMPXCR).
TC3DRA
(0018H)
TC3DRB
(0019H)
7
6
TC3CR
(001AH)
7
5
4
3
2
1
0
Read/Write (Initial value: 1111 1111)
Read only (Initial value: 1111 1111)
6
5
ACAP
4
3
TC3S
2
1
TC3M
TC3
operating mode set
TC3M
0
TC3K
(Initial value: *0*0 0000)
0: Timer/event counter
1: Capture
NORMAL, IDLE mode
DV1CK = 0
000
001
TC3CK
010
TC3
source clock select [Hz]
011
ACAP
Auto-capture control
fc/2
14
fc/2
12
fc/2
13
fc/2
11
fc/2
12
fc/2
10
fc/2
11
fc/2
10
100
fc/2
101
fc/2
8
fc/2
9
fc/2
7
fc/2
8
111
TC3S
13
9
110
TC3
start control
DV1CK = 1
fc/2
Write
only
External clock (TC3 pin input)
0: Stop and clear
1: Start
0: −
1: Auto-capture enable
Note 1:
fc: High-frequency clock [Hz], *: Don’t care
Note 2:
Set the mode and the source clock when the TC3 stops (TC3S = 0).
Note 3:
Values to be loaded to timer register 3A must satisfy the following condition.
TC3DRA > 0 (in the timer and event counter mode)
Note 4:
Auto-capture can be used only in the timer and event counter mode.
Note 5:
Before setting TC3DRA or switching the operating mode, stop the TC3 (TC3S = 0).
Note 6:
When STOP mode is started, timer counter is stopped and TC3 start control (TC3S) is cleared to “0”
automatically. Set TC3S to “1” after STOP mode is released for restarting timer counter.
Note 7:
PMPXCR
(0027H)
TC3CR, TCESCR is a write-only register and must not be used with any of read-modify-write instructions.
7
6
“0”
CHS
TC3ES
Note 8:
5
4
3
2
1
0
TC4ES
TC3ES
(Initial value: 00** **00)
0: Normal
1: Invert
TC3 input control
Write
only
Always write “0” to bit 7 in PMPXCR.
Figure 2.7.2 Timer Register 3 and TC3 Control Register
88CS34-75
2007-09-12
TMP88CS34/CP34
2.7.3
Function
The timer/counter 3 has three operating modes: timer, event counter, and capture mode.
When it is used in the capture mode, the noise rejection time of TC3 pin input can be set
by remote control receive control register.
(1) Timer mode
In this mode, the internal clock is used for counting up. The contents of TC3DRA are
compared with the contents of up-counter. If a match is found, a timer/counter 3 interrupt
(INTTC3) is generated, and the up-counter is cleared. The current contents of up-counter
are loaded into TC3DRB by setting ACAP (bit6 in TC3CR) to “1” (Auto-capture function).
The contents of up-counter can be easily confirmed by executing the read instruction (RD
instruction) of TC3DRB. Loading the contents of up-counter is not synchronized with
counting up. The contents of over flow (FFH) and 00H can not be loaded correctly. It is
necessary to consider the count cycle.
Clock
FE
Counter
FF
00
FE
TC3DRB
FF/00
01
01
Table 2.7.1 Source Clock (internal clock) for Timer/Counter 3 (Example: at fc = 16.0 MHz)
NORMAL, IDLE mode
DV1CK = 0
TC3CK
Resolution [μs]
DV1CK = 1
Maximum setting
time [ms]
Resolution [μs]
Maximum setting
time [ms]
000
512
130.6
1024
261.1
001
256
65.3
512
130.6
010
128
32.6
256
65.3
011
64
16.3
128
32.6
100
32
8.2
64
16.3
101
16
4.1
32
8.2
110
8
2.0
16
4.1
88CS34-76
2007-09-12
TMP88CS34/CP34
Count start
Source clock
Up-counter
1
0
Timer register B
2
3
n−1 n 0
4
1
2
3
4
5
6
7
n
?
Match detect
INTTC3 interrupt
Counter clear
(a) Timer Mode
Source clock
m−2
Up-counter
Timer register B
m−1
m−1
?
m
m+1
Capture
m
m+1
m+2
m+2
n−1
n
n−1
n+1
Capture
n
n+1
ACAP1
(b) Auto-capture
Figure 2.7.3 Timer Mode Timing Chart
(2) Event counter mode
In this mode, the TC3 pin input pulses are used for counting up Either the rising on
falling edge can be selected with TC3ES (bit 0 in PMPXCR). The contents of TC3DRA are
compared with the contents of the up-counter. If a match is found, an INTTC3 interrupt is
generated and the counter is cleared. Match detect is executed on the falling edge of the
TC3 pin. A match can not be detected, and INTTC3 is not generated when the pulse is still
in a falling state.
The maximum applied frequency is shown in Table 2.7.2. Two or more machine cycles are
required for both the high and low levels of the pulse width.
The current contents of up-counter are loaded into TC3DRB by setting ACAP (bit 6 in
TC3CR) to “1” (Auto-capture funcion).
The contents of up-counter can be easily confirmed by executing the read instruction (RD
instruction) of TC3DRB. Loading the contents of up-counter is not synchronized with
counting up. The contents of over flow (FFH) and 00H can not be loaded correctly. It is
necessary to consider the count cycle.
Example: Generates an interrupt every 0.5 s, inputting 50 Hz pulses to the TC3 pin.
LD
(TC3CR), 00001110B
; Sets TC3 mode and source clock
LD
(TC3DRA), 19H
; 0.5 s ÷ 1/50 = 25 = 19H
LD
(TC3CR), 00011100B
; Starts TC3
Table 2.7.2 Source Clock (External Clock) for Timer/Counter
Minimum applied frequency [Hz]
NORMAL, IDLE Mode
2
"H" width
2 /fc
"L" width
2 /fc
2
88CS34-77
2007-09-12
TMP88CS34/CP34
Count start
TC3 pin input
Up-counter
0
1
2
n−1
3
Match detect
Timer register
n
0
1
2
3
Counter clear
n
INTTC3 interrupt
Figure 2.7.4 Event Counter Mode Timing Chart
(3) Capture mode
In this mode, the pulse width, period and duty of the TC3 pin input are measured in this
mode, which can be used in decoding the remote control signals or distinguishing AC 50/60
Hz, etc. The TC3 pin input can have its polarity changed between normal and inverse by
using the TC3ES Register.
a.
If TC3ES = “0” (non-inverting input)
Once command operation has started, the counter free-runs on an internal source
clock.
When the falling edge of the TC3 pin input is detected, the counter value is loaded
into TC3DRB. When the rising edge is detected, the counter value is loaded into
TC3DRA, and the counter is cleared, generating an INTTC3 interrupt.
If the rising edge is detected right after command operation has started, no capture
to TC3DRB and an INTTC3 interrupt occurs only on capture to TC3DRA. If a read
instruction is executed for TC3DRB, the value that exists at the end of the previous
capture (immediately after a reset, “FF”) is read.
b.
If TC3ES = “1” (inverse input)
Once command operation has started, the counter free-runs on an internal clock.
When the rising edge of the TC3 pin input is detected, the counter value is loaded
into TC3DRB. When the falling edge is detected, the counter value is loaded into
TC3DRA, and the counter is cleared, generating an INTTC3 interrupt.
If the falling edge is detected right after command operation has started, the counter
value is not captured into TC3DRB and an INTTC3 interrupt occurs only on capture to
TC3DRA. If a read instruction is executed for TC3DRB, the value that exists at end of
the previous capture (immediately after a reset, “FF”) is read.
The minimum acceptable input pulse width is equal to the length of one source clock
period selected by TC3CR <TC3CK>.
Table 2.7.3 TC3INV-Based Capture Input Edges
TC3ES
Capture into TC3DRB
“0”
(non-inverting input)
Falling edge
Rising edge
“1”
(inverting input)
Rising edge
Falling edge
Note:
Capture into TC3DRA
INTTC3 interrupt
Capture of the TC3 pin input requires at least 1 cycle of the selected source clock.
88CS34-78
2007-09-12
88CS34-79
Reading TC3DRA
INTTC3 interrupt
TC3DRB
TC3DRA
Internal waveform
(invert)
TC3 pin input
Up-counter
Source clock
TC3S
Reading TC3DRA
INTTC3 interrupt
TC3DRB
TC3DRA
Internal waveform
(normal)
TC3 pin input
Up-counter
Source clock
TC3S
1
0
1
Command start
0
Command start
i−1
i−1
i
i
i
1
capture
0
i
i+1
k−1
k
k
1
m−1
m
m
m+1
k
m
1
capture
m−1m 0
2
capture
n−2
n−3 n−2 n−1 n 0
b) In case of TC3ES = “1” (invert)
k +1
n
1
capture
n−1 n 0
a) In case of TC3ES = “0” (normal)
capture
k−1 k 0
n
1
3
1
3
2
3
2
FF (overflow)
2
overflow
1
When TC3DRA is not read, capture
and overflow detection are stopped.
FE FF
FE
FE FF
TMP88CS34/CP34
Figure 2.7.5 Capture Mode Timing Chart
2007-09-12
TMP88CS34/CP34
The edge of TC3 pin input is detected in the remote control receive circuit with noize
rejection. The remote control receive circuit is controlled by the remote control receive
control register (RCCR). The romote control receive status register (RCSR) can monitor the
porality selection and noize rejection circuit.
Rising
TC3IN
8
Polarity
select
Noise reject circuit
(5-bit up-down counter)
MPX
A
9
fc/2 or fc/2
TC3
Capture
control
Edge detector
Falling
B Y
S
Source clock
RCSCK
RPOLS
5
RCNC
RCNF
RCOVF
RNCM
RCCR/RCSR
MPX: Multiplexer
Remote control receive control/status register
Figure 2.7.6 Remote Control Receiving Circuit
88CS34-80
2007-09-12
TMP88CS34/CP34
RCCR
(00026H)
RCEN
RPOLS RCSCK
RCNC
Noise reject time select
RCNC
(Initial value: 0001 1111)
Write
only
(Source clock) × (RCNC − 1) [s]
02H ≤ RCNC ≤ 1FH
NORMAL, IDLE mode
DV1CK = 0
Noise reject circuit
RCSCK
Source clock select
0
9
2 /fc
2 /fc
1
RPOLS
RCEN
RCSR
(00026H)
Remote control signal polarity
0: Positive
select
1: Negative
Remote control receive circuit
0: Disable
operation control
1: Enable
DV1CK = 1
8
TC3CK
R/W
Note 2
Write
only
Note 1:
Set RPOLS and RCSCK when the timer/counter stops (TC3S = 0)
Note 2:
Source clock of timer/counter 3
Note 3:
fc: High-frequency clock [Hz], *: Don’t care
Note 4:
RCCR includes a write-only register and must not be used with any of read-modify-write instructions.
Note 5:
Values to be loaded to RCNC must satisfy the following condition. 02 ≤ RCNC ≤ 1F
RCNF
RPOLS RCSCK RCOVF
RNCM
RCOVF
RNCM
(Initial value: 0000 0***)
Remote control signal monitor
0: Low level
after noise rejecter
1: High level
Noise reject circuit Overflow
0: Signal and definition by overwriting the noise reject time
RCNC
flag
Read
only
1: Overflow
NORMAL, IDLE mode
DV1CK = 0
Noise reject circuit
RCSCK
Source clock select
0
1
RPOLS
RCNF
Remote control signal polarity
0: Positive
select
1: Negative
Remote control signal monitor
0: Without noise
after noise rejecter
1: With noise
Note 1:
Reading out the register RCSR resets RCNF and RCOVF.
Note 2:
Source clock of timer/counter 3
DV1CK = 1
8
9
2 /fc
2 /fc
TC3CK
R/W
Note 2
Read
only
Note 3:
When a 5-bit up-down counter counts down to “0” after counting up, the RCNF defines to be noise.
Note 4:
fc: High-frequency clock [Hz], *: Don’t care
Figure 2.7.7 Remote Control Receive Control Register and Remote Control Receive Status Register
Table 2.7.4 Combination between The Polarity and The Edge Selection
RPOLS
TC3 pin input pulse
(Interrupt occurrence is shown as allow.)
Measurement
0
1
Note:
When TC3CK is used in RCSCK, do not select an external clock to the TC3CK.
88CS34-81
2007-09-12
88CS34-82
RCNC
Writing RCCR
Reading RCSR
RCNF
RCOVF
RNCM
TC3 pin input
Up-down counter
Source clock
Reading RCSR
RCNF
RCOVF
RNCM
TC3 pin input
Up-down counter
Source clock
0
0
08H
1
1
3
3
4
0
1
1
(a) Noise (RPOLS = 0, RCNC = 03H)
0
2
2
1
1
(b) Noise rejection circuit overflow flag (RPOLS = 1, RCNC = 08H to 03H)
2
2
03H
0
0
Reset
Reset
TMP88CS34/CP34
Figure 2.7.8 Remote Control Receive Circuit Timing Chart
2007-09-12
TMP88CS34/CP34
2.8
8-Bit Timer/Counter 4 (TC4)
2.8.1
Configuration
TC4S
11
10
fc/2 or fc/2
7
8
fc/2 or fc/2
5
6
fc/2 or fc/2
3
4
fc/2 or fc/2
A
B
C
D
AS
Y
B
Clear
8-bit up-counter
Y
TC4ES
TC4 pin
Source
clock
Comparator
Match
detect
H
S
3
TC4S
TC4CK
TC4M
2
TC4CR
TC4DR
Timer/Counter 4 Control Register
8-bit Timer Register 4
Note:
Overflow
detect
INTTC4
interrupt
request signal
Set the input/output control correctly for the substitutive input/output pins. For details, see the description of
the input/output port control register.
Figure 2.8.1 Timer/Counter 4 (TC4)
88CS34-83
2007-09-12
TMP88CS34/CP34
2.8.2
Control
The timer/counter 4 is controlled by a timer/counter 4 control register (TC4CR) and an
8-bit timer register 4 (TC4DR).
TC4DR
(0001BH)
7
6
5
4
3
2
1
0
TC4CR
(0001CH)
7
6
5
4
3
2
1
0
Write only (Initial value: 1111 1111)
TC4S
TC4CK
TC4M
Write only (Initial value: **00 0000)
00: Timer/event counter mode
TC4S
01: Reserved
TC4 start control
10: Reserved
11: Reserved
NORMAL, IDLE mode
DV1CK = 0
000
TC4CK
TC4 source clock select [Hz]
(Note 4)
fc/2
DV1CK = 1
11
fs/2
12
−
−
001
fc/2
7
010
fc/2
5
011
fc/2
3
100
Reserved
Reserved
−
101
Reserved
Reserved
−
110
Reserved
Reserved
−
111
fs/2
8
fs/2
6
−
fs/2
4
−
R/W
External clock (TC4 pin input)
00: Timer/event counter mode
TC4M
01: Reserved
TC4 operating mode select
10: Reserved
11: Reserved
Note 1:
fc: High-frequency clock [Hz], *; Don’t care
Note 2:
Values to be loaded to the timer register must satisfy the following condition. 1 ≤ TC4DR ≤ 255
Note 3:
When the TC4 is started (TC4S = 0 → 1) or disabled (TC4S = 1 → 0) or while the TC4 is operating (TC4S =
1 → 1), do not write to TC4M and TC4CK in TC4CR. If these registers are selected/changed during these
operations, counting up is not performed properly.
Note 4:
When STOP mode is started, timer counter is stopped and cleared. Set TC4S to “1” after STOP mode is
released for restarting timer counter.
PMPXCR
(00027H)
TC4ES
Note 5:
Undefined values are read from bits 6 and 7 of TC4CR.
Note 6:
Do not change TC4DR while the TC4 is operating.
7
6
“0”
CHS
5
3
2
1
0
TC4ES (TC3ES) (Initial value: 00** **00)
TC4 edge select
Note 1:
4
0: Rising edge
1: Falling edge
Write
only
TC4CR, TC4DR and PMPXCR are write only register and must not be used with any of the
read-modify-write instructions such as SET, CLR, etc.
Figure 2.8.2 Timer Register 4 and TC4 Control Register
88CS34-84
2007-09-12
TMP88CS34/CP34
2.8.3
Function
The timer/counter 4 has two operating modes: timer, event counter mode.
(1) Timer mode
In this mode, the internal clock is used for counting up. The contents of TC4DR are
compared with the contents of up-counter. If a match is found, an INTTC4 interrupt is
generated and the up-counter is cleared to “0”. Counting up resumes after the up-counter is
cleared.
Table 2.8.1 Source Clock (internal clock) for Timer/Counter 4 (Example: at fc = 16.0 MHz)
NORMAL, IDLE mode
DV1CK = 0
TC4CK
Resolution [μs]
DV1CK = 1
Maximum setting
time [ms]
Resolution [μs]
Maximum setting
time [ms]
000
128.0
32.6
256.0
65.3
001
8.0
2.0
16.0
4.1
010
2.0
0.510
4.0
1.0
100
0.5
0.128
1.0
0.255
(2) Event counter mode
In this mode, the TC4 pin input (external clock) pulse is used for counting up. Either the
rising or falling edge can be selected with TC4ES (bit 1 PMPXCR). The contents of TC4DR
are compared with the contents of the up-counter. If a match is found, an INTTC4 interrupt
is generated and the counter is cleared. The maximum applied frequency is shown Table
2.8.2. Two or more machine cycles are required for both the high and low level of the pulse
width.
Note:
The event counter mode can only be used in NORMAL or IDLE mode.
Table 2.8.2 Timer/Counter 4 External Clock Source
Minimum input pulse width [s]
NORMAL1, IDLE1 mode
3
“H” width
2 /fc
“L” width
2 /fc
3
88CS34-85
2007-09-12
TMP88CS34/CP34
2.9
Serial Bus Interface (SBI-ver. D)
The TMP88CS34/CP34 has a 1-channel serial bus interface which employs a
clocked-synchronous 8-bit serial bus interface and an I2C bus (a bus system by Philips). The
serial bus interface pins are selectively used as either channel 0 or channel 1.
The serial interface is connected to external devices through P35 (SDA0)/P52 (SDA1) and P34
(SCL0)/P51 (SCL1) in the I2C bus mode; and through P53 ( SCK1 ), P52 (SO1) and P51 (SI1) in
the clocked-synchronous 8-bit SIO mode.
The serial bus interface pins are also used for the P3/P5 port. When used for serial bus
interface pins, set the P3/P5 output latches of these pins to “1”. When not used as serial bus
interface pins, the P3/P5 port is used as a normal I/O port.
Note 1: When P3 and P5 is used as serial bus interface pins, P35, P34, P51 and P50 should be set
as a sink open drain output by clearing PSELCR to “0”.
Note 2: The I2C of TMP88CS34/CP34 can be used only in the Standard mode of I2C. The Fast mode
and the High Speed mode can not be used.
2.9.1
Configuration
INTSBI Interrupt Request
SCL
SCK
SIO
Clock
Control
fc/2
fc/4
Source Clock
Generator
P52
Input/ (SDA1/SO1)
Output
P51
Control
(SCL1/SI1)
Divider
I C bus
Clock
Sync.
+
Control
Shift
Register
SBICRB/
SBISR
I2CAR
2
SBI Control Register B/ I C bus
Address Register
SBI Status Register
SO
SIO
Data Control
Transfer
Control
Circuit
2
Noise
Canceller
P53
( SCK )
SBIDBR
SBI data
Buffer Register
SI
2
I C bus
Data
Control
Noise
Canceller
SDA
P35
(SDA0)
P34
(SCL0)
SBICRA
SBI Control Register A
Figure 2.9.1 Serial Bus Interface (SBI)
88CS34-86
2007-09-12
TMP88CS34/CP34
2.9.2
Control
The following registers are used for control the serial bus interface and monitor the
operation status.
• Serial bus interface control register A (SBICRA)
•
Serial bus interface control register B (SBICRB)
•
Serial bus interface data buffer register (SBIDBR)
•
I2C bus address register (I2CAR)
•
Serial bus interface status register A (SBISRA)
•
Serial bus interface status register B (SBISRB)
•
Serial clock source control register (SCCRB)
•
Serial clock control status register (SCSR)
The above registers differ depending on a mode to be used. Refer to Section “2.9.7 I2C bus
mode control” and “2.9.9 Clocked-synchronous 8-bit SIO mode control”.
2.9.3
Serial Clock Source Control
A serial bus interface circuit can reduce the power consumption by stopping a serial clock
generater.
Serial Clock Source Control Register
SCCRB
(00FF1H)
7
6
5
4
3
2
1
0
SCEN
(Initial value: 0*** ****)
SCEN
Note:
0: Do not generate source clock
Serial clock source control
Write
only
1: Generate source clock
When SCRQ and SCEN are “1”, SCEN cannot be cleared to “0”. When SCRQ is “0”, SCEN is cleared to “0”.
Serial Clock Control Status Register
SCSR
(00FF1H)
7
6
5
4
3
2
1
0
SCRQ
SCRQ
(Initial value: 0*** ****)
Serial clock source request
0: No source clock request from serial bus interface
1: Source clock request from serial bus interface
Read
only
SCRQ
SCEN
Source clock
Clock generation
“1” → SCEN Write data except
“00” to SBIM
Write data
“0” → SCEN
“00” to SBIM
Figure 2.9.2 Serial Clock Source
88CS34-87
2007-09-12
TMP88CS34/CP34
2.9.4
Channel Select
A serial bus interface circuit can select I/O pin when a serial bus interface is used for I2C
bus mode.
Port Switching register
PMPXCR
(00027H)
7
6
5
“0”
CHS
4
3
2
0
(TC4ES) (TC3ES) (Initial value: 00** **00)
0: Channel 0
2
I C bus Channel Select
CHS
1
R/W
1: Channel 1
Note 1:
When SIO mode, don’t use channel 0. Therefore, set to “1” in PMPXCR at SIO mode.
Note 2:
Always write “0” to bit 7 in PMPXCR.
Note 3:
*: Don’t care
Figure 2.9.3 Channel Select
2.9.5
Software Reset
A serial bus interface circuit has a software reset function, when a serial bus interface
circuit is locked by an external noise, etc.
To occur software reset, write “01”, “10” into the SWRST (bit 1, 0 in SBICRB). During
software reset, the SWRMON (bit 0 in SBISRA) is clear to “0”.
2.9.6
The Data Format in The I2C bus Mode
The data format when using the TMP88CS34/CP34 in the I2C bus mode are shown in as
below.
(a) Addressing format
8 bits
S
Slave address
1
R A
/ C
W K
1 to 8 bits
Data
1
A
C
K
1 to 8 bits
Data
1
A
C P
K
1 or more
1
(b) Addressing format (with restart)
8 bits
S
Slave address
1
R A
/ C
W K
1 to 8 bits
Data
1
A
C S
K
8 bits
Slave address
1 or more
1
1
R A
/ C
W K
1 to 8 bits
Data
1
A
C P
K
1 or more
1
(c) Free data format
1
A
C
K
8 bits
S
Data
Data
1
A
C
K
1 to 8 bits
Data
1
A
C P
K
1 or more
1
Notes:
1 to 8 bits
S: Start condition
R/ W : Direction bit
ACK: Acknowledge bit
P: Stop condition
Figure 2.9.4 Data Format in I2C Bus Mode
88CS34-88
2007-09-12
TMP88CS34/CP34
2.9.7
I2C Bus Mode Control
The following registers are used to control the serial bus interface (SBI) and monitor the
operation status in the I2C bus mode.
Serial Bus Interface Control Register A
SBICRA
(00020H)
7
6
5
BC
4
3
2
1
ACK
SCK
BC
BC
000
001
010
011
100
101
110
111
ACK
Number of transferred bits
Acknowledgement mode
specification
ACK
0
(Initial value: 0000 *000)
ACK = 0
Number of
Bits
Clock
8
8
1
1
2
2
3
3
4
4
5
5
6
6
7
7
Master mode
ACK = 1
Number of
Bits
Clock
9
8
2
1
3
2
4
3
5
4
6
5
7
6
8
7
Slave mode
Write
only
0
Not generate a clock
pulse for an
acknowledgement.
Not count a clock pulse for
an acknowledgement.
1
Generate a clock
pulse for an
acknowledgement.
Count a clock pulse for an
acknowledgement.
R/W
DV1CK = 0
DV1CK = 1
000: Reserved (Note 3)
000: Reserved (Note 3)
001: Reserved (Note 3)
001: Reserved (Note 3)
010:
Reserved
(Note
3)
010:
58.8 kHz
Serial clock selection
Write
SCK
011: 60.6 kHz
011: 30.3 kHz
(At fc = 16 MHz, Output on SCL pin)
only
100: 30.7 kHz
100: 15.4 kHz
101: 15.5 kHz
101:
7.7 kHz
110:
7.8 kHz
110:
3.9 kHz
111 : Reserved
111 : Reserved
Note 1: Set the BC to “000” before switching to 8-bit SIO bus mode.
Note 2: SBICRA cannot be used with any of read-modify-write instructions such as bit manipulation, etc.
Note 3: This I2C bus circuit does not support the Fast mode. It supports the Standard mode only. Although
the I2C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I2C
specification is not guaranteed in that case.
Serial Bus Interface Data Buffer Register
SBIDBR
(00021H)
7
6
5
4
3
2
1
0
(Initial value: **** ****)
Note 1:
Note 2:
R/W
For writing transmitted data, start from the MSB (bit 7).
The data which was written into SBIDBR cannot be read, since a write data buffer and a read buffer are
independent in SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions
such as bit manipulation, etc.
2
I C bus Address Register
I2CAR
(00022H)
7
6
SA6
SA5
5
4
3
Slave address
SA4
SA3
SA2
2
1
SA1
SA0
0
ALS
(Initial value: 0000 0000)
SA
Slave address selection
Write
Address recognition mode
0: Slave address recognition
only
ALS
specification
1: Non slave address recognition
Note 1: I2CAR is write-only register and cannot be used with any of read-modify-write instruction such as bit
manipulation, etc.
Note 2: Do not set I2CAR to “00H” to avoid the incorrect response of acknowledgment in slave mode. If “00H” is set
to I2CAR as the Slave Address and received “01H” in slave mode, the device might transmit the
acknowledgement incorrectly.
Figure 2.9.5 Serial Bus Interface Control Register A, Serial Bus Interface Data Buffer Register
and I2C Bus Address Register In The I2C Bus Mode
88CS34-89
2007-09-12
TMP88CS34/CP34
Serial Bus Interface Control Register B
SBICRB
(00023H)
7
6
5
4
MST
TRX
BB
PIN
MST
TRX
BB
PIN
SBIM
3
2
SBIM
0:
1:
0:
Transmitter/Receiver selection
1:
0:
Start/Stop generation
1:
0:
Cancel interrupt service request
1:
00:
01:
Serial bus interface operating
mode selection
10:
11:
Master/Slave selection
SWRST1
Software reset start bit
SWRST0
1
0
SWRST1SWRST0
(Initial value: 0001 0000)
Slave
Master
Receiver
Transmitter
Generate a stop condition when MST, TRX and PIN are “1”.
Generate a start condition when MST, TRX and PIN are “1”.
Write
−
only
Cancel interrupt service request
Port mode (Serial bus interface output disable)
Clocked synchronous 8-bit SIO mode
2
I C bus mode
Reserved
Software reset starts by first writing “10” and next writing “01”.
Note 1:
Switch a mode to port after confirming that the bus is free.
Note 2:
Switch a mode to I C bus mode or clock synchronous 8-bit SIO mode after confirming that the port is
2
high-level.
Note 3:
SBICRB has write-only register and must not be used with any of read-modify-write instructions such as bit
manipulation, etc.
Note 4:
When the SWRST (bit 1, 0 in SBICRB) is written to “01”, “10”, software reset (four machine cycles) is
occurred.
This time, control the serial bus interface and monitor the operation status registers except the SBIM (bit 3,
2 in SBICRB) and the CHS (bit 6 in PMPXCR) are reseted.
Control the serial bus interface and monitor the operation status registers are SBICRA, SBICRB, SBIDBR,
I2CAR, SBISRA, SBISRB, SCCRA and SCSR.
Serial Bus Interface Status Register A
7
6
5
SBISRA
(00020H)
4
3
2
1
SWR
MON
ACK
(Initial value: **** ***1)
0: During software reset
SWRMON Software reset monitor
Note 1:
0
Read
only
1: − (Initial)
*: Don’t care
Serial Bus Interface Status Register B
SBISRB
(00023H)
7
6
5
4
3
2
1
0
MST
TRX
BB
PIN
AL
AAS
AD0
LRB
MST
Master/Slave selection status
monitor
0: Slave
TRX
Transmitter/Receiver selection
status monitor
0: Receiver
(Initial value: 0001 0000)
1: Master
1: Transmitter
0: Bus free
BB
Bus status monitor
PIN
Interrupt service requests
status monitor
AL
Arbitration lost detection
monitor
0: −
AAS
Slave address match detection
monitor
0: Not detect slave address match or “GENERAL CALL”
AD0
“GENERAL CALL” detection
monitor
0: Not detect “GENERAL CALL”
LRB
Last Received bit monitor
1: Bus busy
0: Requesting interrupt service
1: Releasing interrupt service request
Read
only
1: Arbitration lost detected
1: Detect slave address match or “GENERAL CALL”
1: Detect “GENERAL CALL”
0: Last receive bit is “0”
1: Last receive bit is “1”
Figure 2.9.6 Serial Bus Interface Control Register B and Serial Bus Interface
Status Register A/B in the I2C Bus Mode
88CS34-90
2007-09-12
TMP88CS34/CP34
(1) Acknowledgement mode specification
a.
Acknowledgement mode (ACK = “1”)
To set the device as an acknowledgement mode, the ACK (bit4 in SBICRA) should be
set to “1”. When a serial bus interface circuit is a master mode, an additional clock
pulse is generated for an acknowledge signal. In a slave mode, a clock is counted for the
acknowledge signal.
In the master transmitter mode, the SDA pin is released in order to receive an
acknowledge signal from the receiver during additional clock pulse cycle. In the master
receiver mode, the SDA pin is set to low level generation an acknowledge signal during
additional clock pulse cycle.
In a slave mode, when a received slave address matches to a slave address which is
set to the I2CAR or when a “GENERAL CALL” is received, the SDA pin is set to low
level generating an acknowledge signal. After the matching of slave address or the
detection of “GENERAL CALL”, in the transmitter the SDA pin is released in order to
receive an acknowledge signal from the receiver during additional clock pulse cycle. In
a receiver, the SDA pin is set to low level generation an acknowledge signal during
additional clock pulse cycle after the matching of slave address or the detection of
“GENERAL CALL”.
The Table 2.9.1 shows the SCL and SDA pins status in acknowledgement mode.
Table 2.9.1 SCL and SDA Pins Status in Acknowledgement Mode
Mode
Pin
Transmitter
SCL
Master
An additional clock pulse is generated.
Released in order to receive
and acknowledge signal.
SDA
SCL
Slave
b.
SDA
Receiver
Set to low level generating an
acknowledge signal.
A clock is counted for the acknowledge signal.
When slave address
matches or a general
call is detected
−
Set to low level generating an
acknowledge signal.
After matching of slave
address or general call
Released in order to receive
an acknowledge signal.
Set to low level generating an
acknowledge signal.
Non-acknowledgement mode (ACK = “0”)
To set the device as a non-acknowledgement mode, the ACK should be cleared to “0”.
In the master mode, a clock pulse for an acknowledge signal is not generated. In the
slave mode, a clock for a acknowledge signal is not counted.
(2) Number of transfer bits
The BC (bits 7 to 5 in SBICRA) is used to select a number of bits for next transmitting
and receiving data.
Since the BC is cleared to “000” as a start condition, a slave address and direction bit
transmissions are always executed in 8 bits. Other than these, the BC retains a specified
value.
88CS34-91
2007-09-12
TMP88CS34/CP34
(3) Serial clock
a.
Clock source
The SCK (bits 2 to 0 in SBICRA) is used to select a maximum transfer frequency
output from the SCL pin in the master mode. Set a communication baud rate that
meets the I2C bus specification, such as the shortest pulse width of tLOW, based
on the equations shown below.
Four or more machine cycles are required for both high and low levels of pulse width
in the external clock which is input from SCL pin.
Note: Since the I2C of TMP88CS34/CP34 can not be used as the Fast mode and the High
Speed mode, do not set SCK as the frequency that is over 100 kHz.
tHIGH
tLOW
1/fscl
tLOW = 2 /fc
n
n
SCK
(bits 2 to 0 in the SBICRA)
DV1CK = 0
DV1CK = 1
000
001
010
011
100
101
110
4
5
6
7
8
9
10
5
6
7
8
9
10
11
tHIGH = 2 /fc + 8/fc
n
fscl = 1/(tLow + tHIGH)
Note: fc: High-frequency clock
tSCKL tSCKH
Note: tcyc = 4/fc (in NORMAL mode, IDLE mode)
tSCKL , tSCKH > 4 tcyc
Figure 2.9.7 Clock Source
b.
Clock synchronization
In the I2C bus mode, in order to drive a bus with a wired AND, a master device which
pulls down a clock pulse to low will, in the first place, invalidate a clock pulse of
another master device which generates a high-level clock pulse.
The serial bus interface circuit has a clock synchronization function. This function
ensures normal transfer even if there are two or more masters on the same bus.
The example explains clock synchronization procedures when two masters
simultaneously exist on a bus.
SCL pin (Master 1)
SCL pin (Master 2)
wait
Count start
Count reset
Count reset
SCL (Bus)
a
b
c
Figure 2.9.8 Clock Synchronization
As Master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of the
bus becomes the low level. After detecting this situation, Master 2 resets counting a
clock pulse in the high level and sets the SCL pin to the low level.
Master 1 finishes counting a clock pulse in the low level at point “b” and sets the SCL
88CS34-92
2007-09-12
TMP88CS34/CP34
pin to the high level. Since Master 2 holds the SCL line of the bus at the low level,
Master 1 waits for counting a clock pulse in the high level. After Master 2 sets a clock
pulse to the high level at point “c” and detects the SCL line of the bus at the high level,
Master 1 starts counting a clock pulse in the high level. Then, the master, which has
finished the counting a clock pulse in the high level, pulls down the SCL pin to the low
level.
The clock pulse on the bus is deteminded by the master device with the shortest
high-level period and the master device with the longest low-level period from among
those master devices connected to the bus.
(4) Slave address and address recognition mode specification
When the serial bus interface circuit is used with an addressing format to recognize the
slave address, clear the ALS (bit 0 in I2CAR) to “0”, and set the SA (bits 7 to 1 in I2CAR) to
the slave address.
When the serial bus interfac circuit is used with a free data format not to recognize the
slave address, set the ALS to “1”. With a free data format, the slave address and the
direction bit are not recognized, and they are processed as data from immediately after
start condition.
(5) Master/slave selection
To set a master device, the MST (bit 7 in SBICRB) should be set to “1”. To set a slave
device, the MST should be cleared to “0”.
When a stop condition on the bus or an arbitration lost is detected, the MST is cleared to
“0” by the hardware.
(6) Transmitter/receiver selection
To set the device as a transmitter, the TRX (bit 6 in SBICRB) should be set to “1”. To set
the device as a receiver, the TRX should be cleared to “0”. When data with an addressing
format is transferred in the slave mode, the TRX is set to “1” by a hardware if the direction
bit (R/ W ) sent from the master device is “1”, and is cleared to “0” by a hardware if the bit is
“0. In the master mode, after an acknowledge signal is returned from the slave device, the
TRX is cleared to “0” by a hardware if a transmitted direction bit is “1”, and is set to “1” by a
hardware if it is “0”. When an acknowledge signal is not returned, the current condition is
maintained.
When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to
“0” by the hardware. The following table show TRX changing conditions in each mode and
TRX value after changing.
Mode
Direction Bit
Conditions
TRX after Changing
Slave
mode
“0”
A received slave address is the
same value set to I2CAR
“0”
Master
mode
“1”
“0”
“1”
ACK signal is returned
“1”
“1”
“0”
When a serial bus interface circuit operates in the free data format, a slave address and a
direction bit are not recognized. They are handled as data just after generating a start
condition. The TRX is not changed by a hardware.
88CS34-93
2007-09-12
TMP88CS34/CP34
(7) Start/Stop condition generation
When the BB (bit 5 in SBICRB) is “0”, a slave address and a direction bit which are set to
the SBIDBR are output on a bus after generating a start condition by writing “1” to the
MST, TRX, BB and PIN. It is necessary to set transmitted data to the SBIDBR and set “1”
to ACK beforehand.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
A6
A5
A4
A3
A2
A1
A0
R/ W
slave address and the direction bit
Start
condition
9
Acknowledge
signal
Figure 2.9.9 Start Condition Generation and Slave Address Generation
When the BB is “1”, sequence of generating a stop condition is started by writeng “1” to
the MST, TRX and PIN, and “0” to the BB. Do not modify the contents of MST, TRX, BB
and PIN until a stop condition is generated on a bus.
SCL pin
SDA pin
Stop condition
Figure 2.9.10 Stop Condition Generation
When a stop condition is generated and the SCL line on a bus is pulled-down to low level
by another device, a stop condition is generated after releasing the SCL line.
The bus condition can be indicated by reading the contents of the BB (bit 5 in SBISRB).
The BB is set to “1” when a start condition on a bus is detected and is cleared to “0” when a
stop condition is detected.
(8) Interrupt service request and cancel
When a serial bus interface circuit is in the master mode and transferring a number of
clocks set by the BC and the ACK is complete, a serial bus interface interrupt request
(INTSBI) is generated.
In the slave mode, the conditions of generating INTSBI are follows:
•
At the end of acknowledge signal when the received slave address matches to the value
set by the I2CAR
•
At the end of acknowledge signal when a “GENERAL CALL” is received
•
At the end of transferring or receiving after matching of slave address or receiving of
“GENRAL CALL”
When a serial bus interface interrupt request occurs, the PIN (bit 4 in SBISR) is cleared
to “0”. During the time that the PIN is “0”, the SCL pin is pulled-down to low level.
Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to “1”.
The time from the PIN being set to “1” until the SCL pin is released takes tLOW.
Although the PIN (bit 4 in SBICRB) can be set to “1” by the program, the PIN can not be
cleared to “0” by the program.
Note:
If the arbitration lost occurs, when the slave address does not match, the PIN is not
cleared to “0” even thought INTSBI is generated.
88CS34-94
2007-09-12
TMP88CS34/CP34
(9) Serial bus interface operating mode selection
The SBIM (bit 3 and 2 in SBICRB) is used to specify a serial bus interface operation
mode.
Set the SBIM to “10” in order to change a operation mode to I2C bus mode. Before
changing operation mode, confirm serial bus interface pins in a high level. And switch a
mode to port after confirming that a bus is free.
(10) Arbitration lost detection monitor
Since more than one master device can exist simultaneously on a bus in the I2C bus mode,
a bus arbitration procedure is implemented in order to guarantee the contents of
transferred data.
Data on the SDA line is used for bus arbitration of the I2C bus.
The following shows an example of a bus arbitration procedure when two master devices
exist simultaneously on a bus. Master 1 and Master 2 output the same data until point “ a”.
After Master 1 outputs “1” and Master 2, “0”, the SDA line of a bus is wired AND and the
SDA line is pulled-down to the low level by Master 2. When the SCL line of a bus is
pulled-up at point “b”, the slave device reads data on the SDA line, that is data in Master 2.
Data transmitted from Master 1 becomes invalid. The state in Master 1 is called
“arbitration lost”. A master device which loses arbitration releases the SDA pin and the
SCL pin in order not to effect data transmitted from other masters with arbitration. When
more than one master sends the same data at the first word, arbitration occurs
continuously after the second word.
SCL (Bus)
SDA pin (Master 1)
SDA pin becomes “1” after losing arbitration.
SDA pin (Master 2)
SDA (Bus)
a
b
Figure 2.9.11 Arbitration Lost
88CS34-95
2007-09-12
TMP88CS34/CP34
The serial bus interface circuit compares levels of a SDA line of a bus with its those SDA
pin at the rising edge of the SCL line. If the levels are unmatched, arbitration is lost and
the AL (bit 3 in SBISRB) is set to “1”.
When the AL is set to “1”, the MST and TRX are cleared to “0” and the mode is switched
to a slave receiver mode.
The AL is cleared to “0” by writing or reading data to or from the SBIDBR or writing data
to the SBICRB.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
SCL pin
1
2
3
4
5
6
7
8
9
1
2
3
D7A’
D6A’
D5A’
Master
A
Master
B
9
Stop clock output
SDA pin
D7B
D6B
Releasing SDA pin and SCL pin to high level as losing arbitration.
AL
MST
TRX
Accessed to
SBIDBR or SBICRB
INTSBI
Figure 2.9.12 Example of when a Serial Bus Interface Circuit is a Master B
(11) Slave address match detection monitor
In the slave mode, the AAS (bit 2 in SBISR) is set to “1” when the received data is
“GENERAL CALL” or the received data matches the slave address setting by I2CAR with
an address recognition mode (ALS = 0).
When a serial bus interface circuit operates in the free data format (ALS = 1), the AAS is
set to “1” after receiving the first 1-word of data.
The AAS is cleared to “0” by writing data to the SBIDBR or reading data from the
SBIDBR.
(12) GENERAL CALL detection monitor
The AD0 (bit 1 in SBISR) is set to “1” when all 8-bit received data is “0” immediately after
a start condition in a slave mode. The AD0 is cleared to “0” when a start or stop condition is
detected on a bus.
(13) Last received bit monitor
The SDA value stored at the rising edge of the SCL is set to the LRB (bit0 in SBISRB). In
the acknowledge mode, immediately after an INTSBI interrupt request is generated, an
acknowledge signal is read by reading the contents of the LRB.
88CS34-96
2007-09-12
TMP88CS34/CP34
2.9.8
Data Transfer of I2C Bus
(1) Device initialization
For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”. Specify the
data length to 8 bits to count clocks for an acknowledge signal. Set a transfer frequency to
the SCK in SBICRA.
Next, set the slave address to the SA in I2CAR and clear the ALS to “0” to set an
addressing format.
After confirming that the serial bus interface pin is high-level, for specifying the default
setting to a slave receiver mode, clear “0” to the MST, TRX and BB in SBICRB, set “1” to the
PIN, “10” to the SBIM, and “00” to bits SWRST1 and SWRST0.
Note: The initialization of a serial bus interface circuit must be complete within the time from all
devices which are connected to a bus have initialized to and device does not generate a
start condition. If not, the data can not be received correctly because the other device
starts transferring before an end of the initialization of a serial bus interface circuit.
(2) Start condition and slave address generation
Confirm a bus free status (when BB = 0).
Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to the
SBIDBR.
By writing “1” to the MST, TRX, BB and PIN, the start condition is generated on a bus
and then, the slave address and the direction bit which are set to the SBIDBR are output.
An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle, and the
PIN is cleared to “0”. The SCL pin is pulled-down to the low level while the PIN is “0”.
When an interrupt request occurs the TRX changes by the hardware according to the
direction bits only when an acknowledge signal is returned from the slave device.
Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If data
is written to the SBIDBR, data to been outputting may be destroyed.
Note 2: The bus free must be confirmed by software within 98.0 μs (the shortest transmitting
time according to the I2C bus standard) after setting of the slave address to be output.
Only when the bus free is confirmed, set “1” to the MST, TRX, BB, and PIN doesn’t finish
within 98.0 μs, the other masters may start the transferring and the slave address data
written in SBIDBR may be broken.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
A6
A5
A4
A3
A2
A1
A0
R/ W
Start condition
Slave address + direction bit
9
Acknowledge
signal from a
slave device
PIN
INTSBI
interrupt
request
Figure 2.9.13 Start Condition Generation and Slave Address Transfer
88CS34-97
2007-09-12
TMP88CS34/CP34
(3) 1-word data transfer
Check the MST by the INTSBI interrupt process after an 1-word data transfer is
completed, and determine whether the mode is a master or slave.
a.
When the MST is “1” (Master mode)
Check the TRX and determine whether the mode is a transmitter or receiver.
1.
When the TRX is “1” (Transmitter mode)
Test the LRB. When the LRB is “1”, a receiver does not request data. Implement the
process to generate a stop condition (described later) and terminate data transfer.
When the LRB is “0”, the receiver requests next data. When the next transmitted
data is other than 8 bits, set the BC, set the ACK to “1”, and write the transmitted data
to the SBIDBR. After writing the data, the PIN becomes “1”, a serial clock pulse is
generated for transferring a next 1-word of data from the SCL pin, and then the 1-word
data is transmitted. After the data is transmitted, and an INTSBI interrupt request
occurs. The PIN become “0” and the SCL pin is set to low level. If the data to be
transferred is more than one word in length, repeat the procedure from the LRB test
above.
Write to SBIDBR
SCL pin
1
2
3
4
5
6
7
8
SDA pin
D7
D6
D5
D4
D3
D2
D1
D0
9
Acknowledge
signal from a
receiver
PIN
INTSBI interrupt
request
Figure 2.9.14 Example of when BC = “000”, ACK = “1”
2.
When the TRX is “0” (Receiver mode)
When the next transmitted data is other than of 8 bits, set the BC again. Set the
ACK to “1” and read the received data from the SBIDBR (reading data is undefined
immediately after a slave address is sent). After the data is read, the PIN becomes “1”.
A serial bus interface circuit outputs a serial clock pulse to the SCL to transfer next
1-word of data and sets the SDA pin to “0” at the acknowledge signal timing.
An INTSBI interrupt request occurs and the PIN becomes “0”. Then a serial bus
interface circuit outputs a clock pulse for 1-word of data transfer and the acknowledge
signal each time that received data is read from the SBIDBR.
Read to SBIDBR
SCL pin
1
2
3
4
5
6
7
8
SDA pin
D7
D6
D5
D4
D3
D2
D1
D0
PIN
9
New D7
Acknowledge
signal to a
transmitter
INTSBI interrupt
Figure 2.9.15 Example of when BC = “000”, ACK = “1”
88CS34-98
2007-09-12
TMP88CS34/CP34
To make the transmitter terminate transmit, clear the ACK to “0” before reading
data which is 1-word before the last data to be received. A serial bus interface circuit
does not generate a clock pulse for the acknowledge signal by clearing ACK. In the
interrupt routine of end of transmission, when the BC is set to “001” and read the data,
PIN is set to “1” and generates a clock pulse for a 1-bit data transfer. In this case, since
the master device is a receiver, the SDA line on a bus keeps the high-level. The
transmitter receives the high-level signal as an ACK signal. The receiver indicates to
the transmitter that data transfer is complete.
After 1-bit data is received and an interrupt request has occurred, generates the stop
condition to terminate data transter.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
D7
D6
D5
D4
D3
D2
D1
D0
1
Acknowledge signal
sent to a transmitter
PIN
INTSBI interrupt
request
“001” → BC
Read SBIDBR
“0” → ACK
Read SBIDBR
Figure 2.9.16 Termination of Data Transfer in Master Receiver Mode
b.
When the MST is “0” (Slave mode)
In the slave mode, a serial bus interface circuit operates either in normal slave mode or in
slave mode after losing arbitration.
In the slave mode, the conditions of generating INTSBI are follows:
•
When the received slave address matches to the value set by the I2CAR
•
When a “GENERAL CALL” is received
•
At the end of transferring or receiving after matching of slave address or receiving of
“GENERAL CALL”
A serial bus interface circuit changes to a slave mode if arbitration is lost in the master
mode. And an INTSBI interrupt request occurs when word data transfer terminates after
losing arbitration. The behavior of INTSBI and PIN after losing arbitration are shown in
Table 2.9.2.
Table 2.9.2 The Behavior of INTSBI and PIN after Losing Arbitration
When the arbitration occurs during transmission
of slave address as a master
INTSBI
PIN
When the arbitration occurs during transmission
of data as a master transmit mode
INTSIB is generated at the terminatin of word data.
When the slave address matches the value set by
I2CAR, the PIN is cleared to “0” by generating of
INTSBI. When the slave address doesn’t match
the value set by I2CAR, the PIN keeps “1”.
PIN keeps “1”.
Check the AL (bit 3 in the SBISR), the TRX (bit 6 in the SBISR), the AAS (bit 2 in the
SBISR), and the AD0 (bit 1 in the SBISR) and implements processes according to
conditions listed in Table 2.9.3.
88CS34-99
2007-09-12
TMP88CS34/CP34
Table 2.9.3 Operation in the Slave Mode
TRX
AL
AAS
AD0
Conditions
Process
1
1
1
0
A serial bus interface circuit loses arbitration
when transmitting a slave address. And
receives a slave address of which the value
of the direction bit sent from another master
is “1”.
Set the number of bits in 1 word to the BC
and write transmitted data to the SBIDBR.
0
1
0
In the slave receiver mode, a serial bus
interface circuit receives a slave address of
which the value of the direction bit sent from
the master is “1”.
0
0
In the slave transmitter mode, 1-word data is
transmitted.
Test the LRB. If the LRB is set to “1”, set the
PIN to “1” since the receiver does not
request next data. Then, clear the TRX to “0”
release the bus. If the LRB is set to “0”, set
the number of bits in 1-word to the BC and
write transmitted data to the SBIDBR since
the receiver requests next data.
1
1/0
A serial bus interface circuit loses arbitration
when transmitting a slave address. And
receives a slave address of which the value
of the direction bit sent from another master
is “0” or receives a “GENERAL CALL”.
Read the SBIDBR for setting the PIN to “1”
(reading dummy data) or write “1” to the PIN.
0
0
A serial bus interface circuit loses arbitration
when transmitting a slave address or data.
And terminates transferring word data.
A serial bus interface circuit is changed to
slave mode. To clear AL to “0”, read the
SBIDBR or write the data to SBIDBR.
1
1/0
In the slave receiver mode, a serial bus
interface circuit receives a slave address of
which the value of the direction bit sent from
the master is “0” or receives “GENERAL
CALL”.
Read the SBIDBR for setting the PIN to “1”
(reading dummy data) or write “1” to the PIN.
0
1/0
In the slave receiver mode, a serial bus
interface circuit terminates receiving of
1-word data.
Set the number of bits in 1-word to the BC
and read received data from the SBIDBR.
0
1
0
Note: In the slave mode, if the slave address set in I2CAR is “00000000B”, the TRX changes to “1” by receiving the
start byte data “00000001B”.
(4) Stop condition generation
When the BB is “1”, a sequence of generating a stop condition is started by setting “1” to
the MST, TRX, and PIN, and clear “0” to the BB. Do not modify the contents of the MST,
TRX, BB, PIN until a stop condition is generated on a bus.
When a SCL line on a bus is pulled-down by other devices, a serial bus interface circuit
generates a stop condition after they release a SCL line.
“1” → MST
“1” → TRX
“0” → BB
“1” → PIN
Stop condition
SCL pin
SDA pin
PIN
BB (Read)
Figure 2.9.17 Stop Condition Generation
88CS34-100
2007-09-12
TMP88CS34/CP34
(5) Restart
Restart is used to change the direction of data transfer between a master device and a
slave device during transferring data. The following explains how to restart a serial bus
interface circuit.
Clear “0” to the MST, TRX and BB and set “1” to the PIN. The SDA pin retains the
high-level and the SCL pin is released. Since a stop condition is not generated on a bus, a
bus is assumed to be in a busy state from other devices. Test the BB until it becomes “0” to
check that the SCL pin a serial bus interface circuit is released. Test the LRB until it
becomes “1” to check that the SCL line on a bus is not pulled-down to the low-level by other
devices. After confirming that a bus stays in a free state, generate a start condition with
procedure (2).
In order to meet setup time when restarting, take at least 4.7 μs of waiting time by
software from the time of restarting to confirm that a bus is free until the time to generate a
start condition.
Note: When restarting after receiving in master receiver mode, because the divice doesn’t
send an acknowledgement as a last data, the level of SCL line can not be conrirmied by
reading LRB. Therefore, confirm the status of SCL line by reading P5PRD register.
“0” → MST
“0” → TRX
“0” → BB
“1” → PIN
“1” → MST
“1” → TRX
“1” → BB
“1” → PIN
4.7 μs (Min)
Start condition
SCL (Bus)
SCL (pin)
SDA (pin)
LRB
BB
PIN
Figure 2.9.18 Timing Diagram when Restarting
88CS34-101
2007-09-12
TMP88CS34/CP34
2.9.9
Clocked-synchronous 8-Bit SIO Mode Control
The following registers are used to control the serial bus interface (SBI) and monitor the
operation in the clocked-synchronous 8-bit SIO mode.
Serial Bus Interface Control Register A
SBICRA
7
6
(00020H)
SIOS
SIOINH
SIOS
SIOINH
SIOM
SCK
Note 1:
Note 2:
Note 3:
5
4
SIOM
3
2
“0”
0:
1:
0:
1:
00:
01:
10:
11:
Indicate transfer start/stop
Continue/abort transfer
Transfer mode select
Serial clock selection
(At fc = 16 MHz, Output on SCK
pin)
1
0
(Initial value: 0000 *000)
SCK
Stop
Start
Continue transfer
Abort transfer (automatically cleared after abort)
8-bit transmit mode
reserved
8-bit transmit/receive mode
8-bit receive mode
DV1CK = 0
000: 1000.0 kHz
001: 500.0 kHz
010: 250.0 kHz
011: 125.0 kHz
100:
62.5 kHz
101:
31.2 kHz
110:
15.6 kHz
111: External clock (Input
from SCK pin)
DV1CK = 1
000: 500.0 kHz
001: 250.0 kHz
010: 125.0 kHz
011:
62.5 kHz
100:
31.2 kHz
101:
15.6 kHz
110:
7.8 kHz
111: External clock (Input
from SCK pin)
Write
only
fc: High-frequency clock [Hz], *: Don’t care
Clear the SIOS to “0” and set the SIOINH to “1” when setting the transfer mode and serial clock.
SBICRA is write-only register and cannot be used with any of read-modify-write instructions such as bit
manipulation, etc.
Serial Bus Interface Data Register
SBIDBR
7
6
5
4
3
2
1
0
(00021H)
(Initial value: **** ****) R/W
Note1 :
The data which was written into SBIDBR cannot be read, since a write buffer and a read buffer are
independent in SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions
such as bit manipulation, etc.
Note 2: *: Don’t care
Serial Bus Interface Control Register B
SBICRB
7
6
5
4
(00023H)
“0”
“0”
“0”
“1”
SBIM
Serial bus interface operation
mode selection
SWRST1
Software reset start bit
SWRST0
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
3
2
SBIM
00:
01:
10:
11:
1
0
SWRST1 SWRST0
(Initial value: **** 0000)
Port mode (serial bus interface output disable)
SIO mode
2
I C bus mode
reserved
Write
only
Software reset starts by first writing “10” and next writing “01”
*: Don’t care
Switch a mode to port after data transfer is complete.
2
Switch a mode to I C bus mode or clock synchronous 8-bit SIO mode after confirming that the port is
high-level.
SBICRB is a write-only register and cannot be used with any of read-modify-write instructions such as bit
manipulation, etc.
Clear bit 7 to 5 in SBICRB to “0”, and set bit 4 to “1”.
When the SWRST (bit 1, 0 in SBICRB) is written to “01”, “10”, software reset is occurred.
This time, control the serial bus interface and monitor the operation status registers except the SBIM (bit 3,
2 in SBICRB) and the CHS (bit 6 in PMPXCR) are reseted.
Control the serial bus interface and monitor the operation status registers are SBICRA, SBICRB, SBIDBR,
I2CAR, SBISRA, SBISRB, SCCRA, SCCRB and SCSR.
Figure 2.9.19 Control Register/Data Buffer Register/Status Register in SIO Mode (1)
88CS34-102
2007-09-12
TMP88CS34/CP34
Serial Bus Interface Status Register A
SBISRA
7
6
5
4
3
2
1
0
(00020H)
SWR
MON
SWRMON
(Initial value: **** ***1)
0: During software reset
Software reset monitor
Read
only
1: − (Initial)
Serial Bus Interface Status Register B
SBISRB
7
6
5
4
3
2
1
0
(00023H)
“1”
“1”
“1”
“1”
SIOF
SEF
“1”
“1”
SIOF
SEF
Note:
0: Transfer terminated
Serial transfer operating status
monitor
1: Transfer in process
Read
only
0: Shift operation terminated
Shift operating status monitor
1: Shift operation in process
Set bit 7 to 4, bit 1 and bit 0 in SBISRB to “1”.
Figure 2.9.20 Control Register/Data Buffer Register/Status Register in SIO Mode (2)
(1) Serial clock
a.
Clock source
The SCK (bits 2 to 0 in SBICRA) is used to select the following functions.
1.
Internal clock
In an internal clock mode, any of seven frequencies can be selected. The serial clock
is output to the outside on the SCK pin. The SCK pin becomes a high-level when data
transfer starts. When writing (in the transmit mode) or reading (in the receive mode)
data cannot follow the serial clock rate, an automatic-wait function is executed to stop
the serial clock automatically and hold the next shift operation until reading or writing
is complete.
Automatic-wait function
SCK pin output
SO pin output
Write transmitted data
1
2
a0
a1
3
7
a2 a5
a6
a
8
a7
1
2
b0
b1
b
6
7
8
1
2
3
b4 b5 b6 b7 c 0 c 1
c2
c
Figure 2.9.21 Automatic Wait Function
2.
External (SCK = “111”)
An external clock supplied to the SCK pin is used as the serial clock. In order to
ensure shift operation, a pulse width of at least 4-machine cycles is required for both
high and low levels in the serial clock. The maximum data transfer frequency is 500
KHz (fc = 16.0 MHz).
SCK pin
tSCKL tSCKH
tSCKL, tSCKH > 4 tcyc
Note: tcyc = 4/fc (in NORMAL mode, IDLE mode)
Figure 2.9.22 The Maximum Data Transfer Frequency in The External Clock Input
88CS34-103
2007-09-12
TMP88CS34/CP34
b.
Shift edge
The leading edge is used to transmit data, and the trailing edge is used to receive data.
1.
Leading edge
Data is shifted on the leading edge of the serial clock (at a falling edge of the SCK
pin input/output).
2.
Trailing edge
Data is shifted on the trailing edge of the serial clock (at a rising edge of the SCK pin
input/output).
SCK pin
SO pin
Bit 0
Shift register
Bit 1
Bit 2
76543210 *7654321 **765432
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
***76543
****7654
*****765
******76
*******7
Bit 5
Bit 6
Bit 7
(a) Leading edge
SCK pin
SI pin
Bit 0
Shift register
********
Bit 1
0*******
Bit 2
10******
Bit 3
210*****
Bit 4
3210****
43210***
(b) Trailing edge
543210** 6543210* 76543210
*: Don’t care
Figure 2.9.23 Shift Edge
(2) Transfer mode
The SIOM (bits 5 and 4 in SBICRA) is used to select a transmit, receive, or
transmit/receive mode.
a.
8-bit transmit mode
Set a control register to a transmit mode and write transmit data to the SBIDBR.
After the transmit data is written, set the SIOS to “1” to start data transfer. The
transmitted data is transferred from the SBIDBR to the shift register and output to the
SO pin in synchronous with the serial clock, starting from the least significant bit
(LSB). When the transmit data is transferred to the shift register, the SBIDBR
becomes empty. The INTSBI (buffer empty) interrupt request is generated to request
new data.
When the internal clock is used, the serial clock will stop and automatic-wait
function will be initiated if new data is not loaded to the data buffer register after the
specified 8-bit data is transmitted. When transmit new data is written, automatic-wait
function is canceled.
When the external clock is used, data should be written to the SBIDBR before new
data is shifted.
The SO pin is “1” from the time transmission starts until the first data bit is sent.
When SIOF becomes “0”, the shift register is cleared. So, output of an undefined value
is not prevented at the start of the next transmission.
The transfer speed is determined by the maximum delay time between the time
when an interrupt request is generated and the time when data is written to the
SBIDBR by the interrupt service program.
88CS34-104
2007-09-12
TMP88CS34/CP34
Transmitting data is ended by cleaning the SIOS to “0” by the buffer empty interrupt
service program or setting the SIOINH to “1”. When the SIOS is cleared, the
transmitted mode ends when all data is output. In order to confirm if data is surely
transmitted by the program, set the SIOF (bit 3 in the SBISRB) to be sensed. The SIOF
is cleared to “0” when transmitting is complete. When the SIOINH is set, transmitting
data stops. The SIOF turns “0”.
When the external clock is used, it is also necessary to clear the SIOS to “0” before
new data is shifted; otherwise, dummy data is transmitted and operation ends.
Clear SIOS
SIOS
SIOF
SEF
SCK pin (output)
a0
SO pin
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
b5
b6
b7
INTSBI interrupt
request
SBIDBR
a
b
Write transmitted data
(a) Internal clock
Clear SIOS
SIOS
SIOF
SEF
SCK pin (input)
a0
SO pin
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
INTSBI interrupt
request
SBIDBR
a
b
Write transmitted data
(b) External clock
Figure 2.9.24 Transfer Mode
88CS34-105
2007-09-12
TMP88CS34/CP34
Example: Program to stop transmitting data. (When external clock is used)
STEST1: TEST (SBISRB) . SEF
; If SEF = 1 then loop
JRS
F, STEST1
STEST2: TEST (P5) . 3
; If SCK = 0 then loop
JRS
T, STEST2
LD
(SBICRA) , 00000111B
; SIOS ← 0
SCK pin
SIOF
SO pin
Bit 6
Bit 7
tSODH = Min 3.5/fc [s] (In normal mode, IDLE mode)
Figure 2.9.25 Transmitted Data Hold Time at End of Transmit
b.
8-bit receive mode
Set a control register to a receive mode and the SIOS to “1” for switching to a receive
mode.
Data is received from the SI pin to the shift register in synchronous with the serial clock,
starting from the least significant bit (LSB). When the 8-bit data is received, the data is
transferred from the shift register to the SBIDBR. The INTSBI (buffer full) interrupt
request is generated to request of reading the received data. The data is read from the
SBIDBR by the interrupt service program.
When the external clock is used, since shift operation is synchronized with the clock
pulse provided externally, the received data should be read from SBIDBR before next serial
clock is input. If the received data is not read, further data to be received is canceled.
When the internal clock is used, the automatic wait function is executed until received
data is read from SBIDBR.
The maximum transfer speed when the external clock is used is determined by the delay
time between the time when an interrupt request is generated and the time when received
data is read.
Received data disappears if this data is not completely read before reception of the next
data terminates. In this case, the next data received is read.
Receiving data is ended by clearing the SIOS to “0” by the buffer full interrupt service
program or setting the SIOINH to “1”. When the SIOS is cleared, received data is
transferred to the SBIDBR in complete blocks. The received mode ends when the transfer is
complete. In order to confirm if data is surely received by the program, set the SIOF (bit 3
in SBIDBR) to be sensed. The SIOF is cleared to “0” when receiving is complete. After
confirming that receiving has ended, the last data is read. When the SIOINH is set,
receiving data stops. The SIOF turns “0” (the received data becomes invalid, therefore no
need to read it).
Note:
When the transfer mode is switched, the SBIDBR contents are lost. In case that the
mode needs to be switched, receiving data is concluded by clearing the SIOS to “0”,
read the last data, and then switch the mode.
88CS34-106
2007-09-12
TMP88CS34/CP34
Clear SIOS
SIOS
SIOF
SEF
SCK pin (output)
SI pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSBI interrupt
request
SBIDBR
a
Read received data
b
Read received data
Figure 2.9.26 Receive Mode (Example: Internal clock)
88CS34-107
2007-09-12
TMP88CS34/CP34
c.
8-bit transmit/receive mode
Set a control register to a transmit/receive mode and write data to the SBIDBR. After the
data is written, set the SIOS to “1” to start transmitting/receiving. When transmitting, the
data is output from the SO pin on the leading edges in synchronous with the serial clock,
starting from the least significant bit (LSB). When receiving, the data is input to the SI pin
on the trailing edges of the serial clock. 8-bit data is transferred from the shift register to
the SBIDBR, and the INTSBI interrupt request occurs. The interrupt service program
reads the received data from the data buffer register and writes data to be transmitted. The
SBIDBR is used for both transmitting and receiving. Transmitted data should always be
written after received data is read.
When the internal clock is used, automatic-wait function is initiated until received data
is read and next data is written.
When the external clock is used, since the shift operation is synchronized with the
external clock, received data is read and transmitted data is written before new shift
operation is executed. The maximum transfer speed when the external clock is used is
determined by the delay time between the time when an interrupt request is generated and
the time when received data is read and transmitted data is written.
When transmission starts, a value which is the same as the last bit of previously
transmitted data is output from the time SIOF is set to “1” until the falling edge of SCK
occurs.
Transmitting/receiving data is ended by cleaning the SIOS to “0” by the INTSBI
interrupt service program or setting the SIONH to “1”. When the SIOS is cleared, received
data is transferred to the SBIDBR in complete blocks. The transmit/receive mode ends
when the transfer is complete. In order to confirm if data is surely transmitted/received by
the program, set the SIOF (bit 3 in SBISRB) to be sensed. The SIOF becomes “0” after
transmitting/receiving is complete. When the SIONH is set, transmitting/receiving data
stops. The SIOF turns “0”.
Note:
When the transfer mode is switched, the SBIDBR contents are lost. In case that the
mode needs to be switched, conclude transmitting/receiving data by clearing the SIOS
to “0”, read the last data, and then switch the transfer mode.
Clear SIOS
SIOS
SIOF
SEF
SCK pin
(output)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
SI pin
c0
c1
c2
c3
c4
c5
c6
c7
d0
d1
d2
d3
d4
d5
d6
d7
INTSBI interrupt
request
SBIDBR
a
Write transmitted
data (a)
c
b
Read received Write transmitted
data (c)
data (b)
d
Read received
data (d)
Figure 2.9.27 Transmit/Receive Mode (Example: Internal clock)
88CS34-108
2007-09-12
TMP88CS34/CP34
SCK pin
SIOF
SO pin
Bit 6
Bit 7 in last transmitted word
tSODH = Min 4/fc [s] (In normal mode, idle mode)
Figure 2.9.28 Transmitted Data Hold Time at End of Transmit/Receive
88CS34-109
2007-09-12
TMP88CS34/CP34
2.10 Remote Control Signal Preprocessor/External Interrupt 3 Input Pin
The remote control signal waveform can be determined by inputting the remote control signal
waveform from which the carrier wave was eliminated by the receive circuit to P30
(INT3/RXIN) pin. When the remote control signal preprocessor/external interrupt 3 pin is also
used as the P30 port, set the P30 port output latch to “1”. When it is not used as the remote
control signal preprocessor/external interrupt 3 input pin, it can be used for normal port.
2.10.1
Configuration
11
fc/2
10
fc/2
8
fc/2
7
fc/2
6
fc/2
5
fc/2
2
fc/2
Receive bit
counter
Receive bit counter value monitor (RBCTM)
Selector
RNC
INT3/RXIN
Polarity
select
Noise canceller to
RNCM
INT3
Interrupt
request
Interrupt
select
INT.
EINT
Measurement
width select
Selector
8-bit upcounter
Match detect
6
2 3
RPOLS
fc/2
8
fc/2
10
fc/2
12
fc/2
2
SRM
2
RCCK
RXCR1
Remote control receive
control register 1
Remote control receive
counter register (RXCTR)
RMM
4
RCS CREGA
Shift register
Remote control receive
data buffer register
(RXDBR)
RXCR2
Remote control receive
control register 2
Figure 2.10.1 Remote Control Signal Preprocessor
2.10.2
Remote Control Signal Preprocessor Control
When the remote control signal preprocessor is used, operating states are controlled and
monitored by the following registers. Interrupt requests also use the remote control signal
preprocessor/external interrupt 3 input pin.
Remote control receive control register 1 (RXCR1)
Remote control receive control register 2 (RXCR2)
Remote control receive counter register (RXCTR)
Remote control receive data buffer register (RXDBR)
Remote control receive status register (RXSR)
When this pin is used for the external interrupt 3 input, set EINT in RXCR1 to other
than “11”.
88CS34-110
2007-09-12
TMP88CS34/CP34
Remote control receive control register 1
RXCR1
7
(00FE8H)
6
RCCK
5
4
RPOLS
3
2
1
EINT
0
(Initial value: 0000 0000)
RNC
6
00: fc/2 (Hz)
8-bit up-counter source clock
select
RCCK
Remote control signal polarity
select
RPOLS
01: fc/2
8
10: fc/2
10
11: fc/2
12
0:
Positive
1:
Negative
00: Rising edge
EINT
01: Falling edge (at RPOLS = 0)
Interrupt source select
10: Rising/Falling edge
R/W
11: 8-bit receive end
001: 2 /fc × 7 − 1/fc (s)
2
010: 2 /fc × 7 − 1/fc
5
011: 2 /fc × 7 − 1/fc
6
100: 2 /fc × 7 − 1/fc
7
Noise canceler noise
eliminating time select
RNC
101: 2 /fc × 7 − 1/fc
8
110: 2 /fc × 7 − 1/fc
10
111: 2 /fc × 7 − 1/fc
11
000: Noise canceler disable
Note 1:
fc: High-frequency clock [Hz]
Note 2:
After reset, RPOLS do not change the set value in the receiving remote control signal. For setting interrupt
edge and measurement data, use EINT and RMM.
Remote control receive control register 2
RXCR2
7
6
(00FE9H)
5
4
CREGA
3
2
RCS
RMCEN
CREGA
Setting of detect time for
match with 8-bit up-counter
upper 4 bits
RCS
8-bit up-counter start control
RMCEN
Remote control signal
preprocesser Enable/Disable
1
0
RMM
(Initial value: 0000 0000)
Match detect time (Tth) = 16 × CREGA/RCCK [s]
CREGA = 0H to FH
CREGA = 2H, RCCK = fc/2 [Hz], at fc = 16 MHz,
DV1CK = 0
Tth = 128 [μs]
6
Example:
0:
Stop and counter clear
1:
Start
0:
Disable
1:
Enable
R/W
00:
RMM
Measurement mode select
(invalid when EINT = “10”)
01:
Refer to Table 2.10.1
10:
11:
Note 1:
fc: High-frequency clock [Hz]
Note 2:
When an interrupt source is set for rising/falling edge, low and high widths are forcibly measured
separately.
Note 3:
Set CREGA (0H to FH) before EINT sets to 8-bit receive end.
Figure 2.10.2 Remote Control Receive Control Register 1, 2
88CS34-111
2007-09-12
TMP88CS34/CP34
Remote control receive counter register
RXCTR
7
6
5
4
3
2
1
0
Read Only
(Initial value: 0000 0000)
3
2
1
0
Read Only
(Initial value: 0000 0000)
3
2
1
0
OVFF
SRM
RNCM
Read Only
(Initial value: 0000 *000)
(00FEAH)
Remote control receive data buffer register
RXDBR
7
6
5
4
(00FEBH)
Remote control receive status register
RXSR
7
6
(00FECH)
5
4
RBCTM
RBCTM
Receive bit counter value
monitor
OVFF
8-bit up-counter overflow flag
SRM
Data buffer register input
monitor
RNCM
Note 1:
0:
No overflow
1:
Overflow
0:
Upper 4 bits of 8-bit up-counter < CREGA
1:
Upper 4 bits of 8-bit up-counter ≥ CREGA
Read
only
Remote control signal monitor
after passing through noise
canceler
*: Don’t care
Figure 2.10.3 Remote Control Receive Counter Register, Data Buffer Register, Status Register
88CS34-112
2007-09-12
TMP88CS34/CP34
Table 2.10.1 Combination of Interrupt Source and Measurement Mode
RPOLS
EINT
RMM
Interrupt source
Measurement mode
00
00
10
11
01
0
01
10
11
10
−
00
11
Receive end
10
00
00
10
11
01
1
01
10
11
10
−
00
11
Receive end
10
88CS34-113
2007-09-12
TMP88CS34/CP34
2.10.3
Noise Elimination Time Setting
The remote control receive circuit has a noise canceler. By setting RNC in RXCR1, input
signals shorter than the fixed time can be eliminated as noise.
Table 2.10.2 Noise Elimination Time Setting (fc = 16 MHz)
2.10.4
RNC
Minimum signal pulse width
000
−
Maximum noise width to be eliminated
−
001
(2 + 5)/fc
(2.31 μs)
(2 × 7 − 1)/fc
(1.69 μs)
010
(2 + 5)/fc
(16.31 μs)
(2 × 7 − 1)/fc
(13.88 μs)
011
(2 + 5)/fc
(32.31 μs)
(2 × 7 − 1)/fc
(27.88 μs)
100
(2 + 5)/fc
(64.31 μs)
(2 × 7 − 1)/fc
(55.88 μs)
101
(2 + 5)/fc
(128.3 μs)
(2 × 7 − 1)/fc
(111.9 μs)
110
(2 + 5)/fc
(512.3 μs)
(2 × 7 − 1)/fc
(447.9 μs)
111
(2 + 5)/fc
(1.024 ms)
(2 × 7 − 1)/fc
(895.9 μs)
5
8
9
10
11
13
14
2
5
6
7
8
10
11
Operation
(1) Interrupts at rising, falling, or rising/falling edge, and measurement modes
First set EINT and RMM. Next, set RCS to “1”; the 8-bit up-counter is counted up by the
internal clock. After measurement, the 8-bit up-counter value is saved in RXCTR. Then,
the 8-bit up-counter is cleared, an INT3 request is generated, and the 8-bit up-counter
resumes counting.
If the 8-bit up-counter overflows (FFH) before measurement is completed, an INT3
request is generated and the overflow flag (OVFF) is set to “1”. Then, the 8-bit up-counter is
cleared. An overflow can be detected by reading OVFF by the interrupt processing. To
restart the 8-bit up-counter, set RCS to “1”.
Setting RCS to “1” zero-clears OVFF.
88CS34-114
2007-09-12
88CS34-115
RXCTR
8-bit
up-counter value
RXCTR
8-bit
up-counter value
RXCTR
8-bit
up-counter value
INT3 request
RCCK
RNCM
I−3 I−2 I−1
I−3 I−2 I−1
I−3 I−2 I−1
I
I
I
I
I
1
1
1
2
2
2
3
3
3
5
1
2
6
7
8
m
m
1
(c) High width measurement
m − 2m − 1
2
(b) Rising edge cycle measurement
4
m
(a) Low width measurement
m − 2m − 1
n−2 n−1
3
n−2 n−1
m−4m−3 m−2 m−1
3
n
m
n
m
n
1
1
1
2
2
2
3
3
3
TMP88CS34/CP34
Figure 2.10.4 Rising Edge Interrupt Timing Chart (RPOLS = 0)
2007-09-12
88CS34-116
RXCTR
8-bit
up-counter value
RXCTR
8-bit
up-counter value
RXCTR
8-bit
up-counter value
INT3 request
RCCK
RNCM
I−3 I−2 I−1
I−3 I−2 I−1
I−3 I−2 I−1
I
I
I
I
I
1
1
1
2
2
2
3
3
3
m
5
6
7
8
1
2
m
m
1
(c) Low width measurement
m − 2m − 1
2
(b) Falling edge cycle measurement
4
(a) High width measurement
m − 2m − 1
n−2 n−1
3
n−2 n−1
m−4m−3 m−2 m−1
3
n
m
n
m
n
1
1
1
2
2
2
3
3
3
TMP88CS34/CP34
Figure 2.10.5 Falling Edge Interrupt Timing Chart (RPOLS = 0)
2007-09-12
RXCTR
8-bit
up-counter value
INT3 request
RCCK
RNCM
I−3 I−2 I−1
I
I
1
2
3
88CS34-117
m
m
1
2
(a) High and low width measurement
m − 2m − 1
3
n−2 n−1
n
n
1
2
3
TMP88CS34/CP34
Figure 2.10.6 Rising/Falling Edge Interrupt Timing Chart
2007-09-12
TMP88CS34/CP34
(2) 8-bit receive end interrupts and measurement modes
By determining one-cycle remote control signal as one-bit data set to “0” or one-pulse
width remote control signal as one-bit data set to “1”, an INT3 request is generated after
8-bit data is received. When “0” is determined, this means the upper four bits in the 8-bit
up-counter have not reached the CREGA value. When “1” is determined, this means the
upper four bits in the 8-bit up-counter have reached or exceeded the CREGA value. The
8-bit up-counter value is saved in RXCTR after one bit is determined. The determined data
is saved, bit by bit, in RXDBR at the rising edge of the remote control signal (when RPOLS
= 1, falling edge). The number of bits saved in RXDBR is counted by the receive bit counter
and saved in RBCTM. RBCTM is set to “0001B” at the rising edge of the input (when
RPOLS = 1, falling edge) after the INT3 request is generated.
RNCM
RCCK
8-bit up-counter
value
FE
FF
1
Set to “1” by command
RCS
OVFF
Receive bit
counter value*
n−1
n
RBCTM*
n−1
n
INT3 request
Note:
*: Valid only when 8 bits are received.
Figure 2.10.7 Overflow Interrupt Timing Chart
88CS34-118
2007-09-12
88CS34-119
RXDBR
SRM
8-bit up-counter
value
CREGA
INT3 request
Receive bit
counter value
RNCM
01 02 03 04 05 06 07
1
8-bit receive end interrupt setting
01 02
1
0
7
01 02
80H
1
8
[Application] Low width measurement
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
(a) Rising Edge cycle measurement
07
6
TMP88CS34/CP34
Figure 2.10.8 8-Bit Receive End Interrupt Timing Chart (RPOLS = 0)
2007-09-12
TMP88CS34/CP34
Table 2.10.3 Count Clock for Remote Control Preprocessor Circuit (at fc = 16 MHz)
Count clock (RCCK)
Resolution [μs]
Maximum setting time [ms]
00
4
1.024
01
16
4.096
10
64
16.38
11
256
65.53
88CS34-120
2007-09-12
TMP88CS34/CP34
2.11 8-Bit AD Converter (ADC)
The TMP88CS34/CP34 has a 8-bit successive approximation type AD converter.
Figure 2.11.1 shows the circuit configuration of the AD converter.
The AD converter includes control registers ADCCRA and ADCCRB, conversion result
registers ADCDR1 and ADCDR2, a DA converter, a sample hold circuit, a comparator, and
sequential transducer circuit.
To use P5 and P6 as analog inputs, clear the output latch for P5 and P6 to “0”. Also, clear the
input/output control registers (P5CR1 and P6CR) to “0”. P63 to P61 output “0” after a reset.
When these dual-function pins are used as ports, be sure to set ORP6S2 to “1”.
2.11.1
Configuration
VDD
VSS
DA converter
A
B
AIN0
AIN1
Y
Reference
voltage
Sample hold
circuit
Analog input multiplexer
ADS
8
Analog
comparator
E
F
AIN4
AIN5
S
EN
SAIN
Successive approximate circuit
3
Shift clock
AINDS
6
AD8TRG
External
trigger signal
INTADC
Control circuit
EN
3
2
EOCF
ADRS
P5CR, P6CR
ADCCRA
P5, P6 port input/output control register
ADBF
8
ACK
AMD
ADCCRB
AD converter control register
ADCDR1, ADCDR2
AD conversion result register
Figure 2.11.1 AD Converter (ADC)
2.11.2
Control Register
The following register are used foe AD converter.
•
AD converter control register 1 (ADCCRA)
•
AD converter control register 2 (ADCCRB)
•
AD conversion result register (ADCDR1/ADCDR2)
(1) AD converter control register 1 (ADCCRA)
ADCCRA control AD conversion start, AD operation mode select, analog input control
and analog input channel select.
(2) AD converter control register 2 (ADCCRB)
ADCCRB control AD conversion time select.
(3) AD conversion result register (ADCDR1)
AD conversion result is stored after end of conversion.
(4) AD conversion result register (ADCDR2)
For monitoring status of conversion.
Figure 2.11.2 and Figure 2.11.3 show AD converter control register.
88CS34-121
2007-09-12
TMP88CS34/CP34
AD Converter Control Register 1
ADCCRA
7
(0000EH)
ADRS
6
5
AMD
4
3
AINDS
“0”
2
1
0
SAIN
(Initial value: 0001 0000)
The ADRS bit is automatically cleared after starting AD conversion.
ADRS
AD conversion start
AMD
AD Operating mode select
AINDS
SAIN
Note 1:
Analog input control
Analog input channel select
During AD conversion, setting ADRS to “1” initializes the ADRS bit
and resets conversion.
0: −
1: AD conversion restart
00: STOP mode
01: Software start mode
10: Trigger start mode
11: reserved
0: Analog input enable
1: Analog input disable
000: Selects AIN0
001: Selects AIN1
010: Selects AIN2
011: Selects AIN3
100: Selects AIN4
101: Selects AIN5
110: −
111: −
R/W
Select analog input when AD converter stops.
Note 2:
When the analog input is all use disabling, the AINDS should be set to “1”.
Note 3:
During conversion, do not perform output instruction to maintain a precision for all of the pins.
And port near to analog input, do not input intense signaling of change.
Note 4:
The ADRS is automatically cleared to “0” after starting conversion.
Note 5:
Always set bit 3 in ADCCRA to “0”.
Note 6:
Do not set ADRS (bit 7 in ADCCRA) to “1” during AD conversion. Re-set it after confirming with EOCF (bit 5
in ADCDR2) that the conversion is completed or after generating an interrupt signal (INTADC) (by the
interrupt processing routine or the like).
Note 7
In the trigger mode, the system does not accept the second and subsequent triggers after accepting the first
trigger for starting AD conversion. To restart AD conversion by a trigger, set AMD (bits 6 and 5 in ADCCRA)
to “00” and then put the system in trigger start mode again (with AMD = “10”).
Note 8:
When the system enters STOP mode, AD converter control register 1 (ADCCRA) is initialized.
Re-set this register after the system reenters NORMAL mode.
AD Converter Control Register 2
ADCCRB
7
(0000FH)
6
5
4
“0”
“1”
3
2
1
0
ACK
ACK
“0”
(Initial value: **0* 000*)
DV1CK = 0
DV1CK = 1
Conversion
time
fc = 16 MHz fc = 8 MHz fc = 16 MHz fc = 8 MHz
000
Reserved
001
010
ACK
AD conversion time select
011
156/fc [s]
−
19.5
−
100
312/fc [s]
19.5
39.0
39
78
101
624/fc [s]
39.0
78.0
78
156
110
1248/fc [s]
78.0
−
156
−
111
39
R/W
Reserved
Note 1:
Do not use setting except the above list.
Note 2:
Set conversion time by analog reference voltage (VDD) as follows.
Note 3:
Always set bit 0 and bit 5 in ADCCRB to “0” and set bit 4 in ADCCRB to “1”.
Note 4:
When a read instruction for ADCCRB, bit 6 to 7 in ADCCRB read in as undefined data.
VDD = 4.5 to 5.5 V (15.6 μ or more)
Note 5:
fc: High-frequency clock [Hz]
Note 6:
When the system enters STOP mode, AD converter control register 2 (ADCCRA) is initialized.
Re-set this register after the system reenters NORMAL mode.
Figure 2.11.2 AD Converter Control Register
88CS34-122
2007-09-12
TMP88CS34/CP34
AD Conversion Result Register
ADCDR1
7
6
5
4
3
2
1
0
(00031H)
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
ADCDR2
7
6
5
4
3
2
1
0
(00032H)
−
−
EOCF
ADBF
−
−
−
−
EOCF
AD conversion end flag
ADBF
AD conversion busy flag
Note 1:
0:
1:
0:
1:
(Initial value: 0000 0000)
(Initial value: **00 ****)
Under conversion or Before conversion
End of conversion
During stop of AD conversion
During AD conversion
Read
only
The EOCF is cleared to “0” when reading the ADCDR1.
Therefore, the AD conversion result should be read to ADCDR1 more first than ADCDR2.
Note 2:
ADBF is set to “1” by starting AD conversion and cleared to “0” by end of AD conversion. Additionally,
ADBF is cleared to “0” by setting AMD = “00” in ADCCR2 or entering to the STOP mode.
Note 3:
If the pin is used as an analog input pin, reset the DGINE register to “0” to disable all inputs other than
analog inputs.
Figure 2.11.3 AD Converter Result Register
2.11.3
AD Converter Operation
The high side of an analog reference voltage is applied to VDD, and the low side is
applied to VSS pin. Dividing a reference voltage between VDD and VSS to the voltage
corresponding to a bit by a rudder resistance and comparing it with the analog input
voltage converts the AD.
Table 2.11.1 AD Converter Operation mode
Mode
AD converter disable mode
Function
AD converter stop mode. This mode is always used to change
modes.
Software start mode
Single AD conversion of 1 channel which specifies input.
Trigger start mode
Single AD conversion of 1 channel which specifies input
(AD8TRG) from Key-On-Wake-Up circuit as a trigger.
2.11.4
Interrupt
Interrupt request signal occur at the timing when the EOCF bit is set to “1”.
88CS34-123
2007-09-12
TMP88CS34/CP34
2.11.5
AD Converter Operation Modes
When the MCU places in the STOP mode during the AD conversion, the conversion is
stopped and the ADCDR2 content becomes indefinite. After returning from the STOP mode,
the EOCF and INTADC does not occur. Therefore, the AD conversion must be restarted
after returning from the STOP mode.
ADS
ADCDR2
Invalid
Result
Invalid
Invalid
Result
EOCF
Processing
Read Start
Read Start
Start
Figure 2.11.4 AD Conversion Timing Chart
(1) AD conversion in STOP mode
When the AD converter stop mode is specified during AD conversion, the AD conversion
is stopped immediately. The AD conversion is not implemented, so the undefined value is
not written to the AD conversion result register. The AD conversion start commands which
occur is the AD converter stop mode are ignored.
This mode is automatically selected by reset.
This mode is used to change the AD converter operation mode.
(2) Single mode
When the AMD (bit 6, 5 to in ADCCRA) set to “01”, the AD conversion signal mode.
This mode does AD conversion of single channel, and conversion result is stored in
ADCDR1. The EOCF (bit 5 in ADCDR2) is set to “1” at end of one conversion, and an
intcrrupt request signal occurs. The EOCF is cleared to “0” by reading the AD conversion
registers.
But when the AD conversion is restarted before the ADCDR is read, the EOCF is cleared
to “0” and the last AD conversion result is maintained till next conversion end.
Do not set ADRS (bit 7 in ADCCRA) during AD conversion. Again set it after confirming
with EOCF (bit 5 in ADCDR2) that the conversion is completed or after generating an
interrupt signal (INTADC) (by the interrupt processing routine or the like).
ADS
ADCDR2
Invalid
AD conversion result
EOCF
ADBF
Conversion time
(Reference to ADCCRB register)
Start
Read
Figure 2.11.5 Single Mode
88CS34-124
2007-09-12
TMP88CS34/CP34
Example: The AD conversion starts after 19.5 μs (at fc = 16 MHz) and AIN4 pin are selected
as the conversion time and the analog input channel. Confirming the EOCF, the
converted value is read out, and the 8 bits data is stored to address 009EH in
RAM. The operation mode is a signal mode.
; AIN SELECT
LD
(P5), 00000000B
LD
(P5CR1), 00000000B
LD
(P6), 00000000B
LD
(P6CR), 00000000B
LD
(ADCCRA), 00100100B
; Selects AIN4, Selects the software start
mode
LD
(ADCCRB), 00011000B
; Selects the conversion time and the
operation mode.
; AD CONVERT START
SET
(ADCCRA) . 7
SLOOP: TEST
(ADCCR2) . 5
JRS
T, SLOOP
; RESULT DATA READ
LD
(9EH), (ADCDR1)
;
;
ADRS = 1
EOCF = 1 ?
(3) Trigger start mode
The AD conversion of a specified single channel is executed when input (AD8TRG) from
Key-On-Wake-Up circuit is set as trigger, the conversion result is stored in the ADCDR1.
The EOCF (bit 5 in ADCDR2) is set to “1” at end of one conversion, and an interrupt
request signal occurs.
It needs to be set the STOP mode by bit 5 to 6 in ADCCRA before the AD conversion is
executed again.
2.11.6
Analog Input Voltage and AD Conversion Result
The analog input voltage is corresponded to the 8-bit digital value converted by the AD as
shown in Figure 2.11.6.
AD Conversion
result
FFH
FEH
FDH
03H
02H
01H
0
1
2
3
253
254
255
256
×
VDD − VSS
Analog input voltage
256
Figure 2.11.6 Analog Input Voltage and AD Conversion Result (typ.)
88CS34-125
2007-09-12
TMP88CS34/CP34
2.11.7
STOP Modes during AD Conversion
When standby mode (STOP mode) is entered forcibly during AD conversion, the AD
convert operation is suspended and the AD converter is initialized. (ADCCRA and
ADCCRB are initialized to initial value.) Also, the conversion result is indeterminate.
(Conversion results up to the previous operation are cleared, so be sure to read the
conversion results before entering standby mode.) When restored from standby mode, AD
conversion is not automatically restarted, so it is necessary to restart AD conversion after
setting ADCCRA and ADCCRB. Note that since the analog reference voltage is
automatically disconnected, there is no possibility of current flowing into the analog
reference voltage.
2.11.8
Notice of AD converter
(1) Analog input voltage range
Voltage range of analog input (AIN0 to AIN5) must be forced from VSS to VDD. If input
voltage of which out of range is forced to analog input pin, AD conversion result to unknown.
Also, this cause other analog input pin unstable.
(2) I/O port with analog input
Analog input pins (AIN0 to AIN5) are also I/O port. During AD conversion using any
analog input pin, don’t operate other I/O port with analog input. Because, AD accuracy
would be worse. Also, other electrically swinging port without analog input may cause noise
to near analog input pin.
(3) Reduce to noise
Figure 2.11.7 is shown as internal equivalent circuit of analog input pin.
Increasing output impedance of analog input supply, cause noise or other non-good
condition.
Therefore, output impedance of analog input supply must be less than 5kΩ.
And we recommend to connect capacitance to analog input pin.
AINx
Analog input
supply impedance
5 kΩ (max.)
Internal resistance
R = 5 kΩ (typ.)
Analog converter
Internal Capacitance
C = 22 pF (typ.)
DA converter
Figure 2.11.7 Analog Input Equivalent Circuit and Analog Input Pin
88CS34-126
2007-09-12
TMP88CS34/CP34
2.12 Key-On-Wake-Up
In this MCU the IDLE mode is also released by Low active port inputs. The low input voltage
is regulated higher than the other normal ports. Therefore the ports can be enabled by analog
input level.
2.12.1
Configuration
PORT P53
AIN0
AD Converter
VIL ≤ VDD × 0.65
KWU0
AD8TRG
KWU1
PORT P54
KWU2
PORT P55
KWU3
PORT P56
KWU 4
PORT P60
KWU5
PORT P61
AIN1
Noise
reject
circuit
AIN2
AIN3
INTKWU
AIN4
AIN5
INTAD
EN
*
IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0
EN
EN
EN
EN
EN
EN
IDLECR (00FD0H)
*
*
IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0
IN
IN
IN
IN
IN
IN
IDLEIN (00FD0H)
Figure 2.12.1 Key-On-Wake-Up Control Circuit
2.12.2
Control
P53 to P56 and P60, P61 ports can be controlled by IDLE control register (IDLECR).
It can be configured as enable/disable in one-bit unit. When those pins are used by IDLE
mode release, those pins must be set input mode (P5CR1, P5, P6CR, P6, ADCCRA).
IDLE mode is controlled by system control register 2 (SYSCR2) and maskable interrupts.
After the individual enable flag (EF5) is set to “1”, the IDLE mode must starts. When
enabled port input generates INTKWU interrupt, the IDLE mode is released. Low level
input voltage in those ports is regulated to less than VDD × 0.65 (V).
IDLE port monitorring register (IDLEIN) can be used to check state of ports.
INTADEN can enable to generate AD8TRG, which is used as trigger of AD converter
trigger start mode.
Noise reject circuit eliminate noise, which is less than 24 μs period.
88CS34-127
2007-09-12
TMP88CS34/CP34
IDLE control register
IDLECR
(00FD0H)
7
INTAD
EN
6
5
4
3
2
1
0
*
IDLE5
EN
IDLE4
EN
IDLE3
EN
IDLE2
EN
IDLE1
EN
IDLE0
EN
INTADEN
Generation of AD8TRG
IDLE5EN
Release IDLE mode by KWU 5
IDLE4EN
Release IDLE mode by KWU 4
IDLE3EN
Release IDLE mode by KWU 3
IDLE2EN
Release IDLE mode by KWU 2
IDLE1EN
Release IDLE mode by KWU1
IDLE0EN
Release IDLE mode by KWU 0
Note :
0:
Disable
1:
Enable
0:
Disable
1:
Enable
0:
Disable
1:
Enable
0:
Disable
1:
Enable
0:
Disable
1:
Enable
0:
Disable
1:
Enable
0:
Disable
1:
Enable
(Initial value: 0*00 0000)
Write
only
*: Don’t care
IDLE port monitorring register
IDLEIN
(00FD0H)
7
6
5
4
3
2
1
0
*
*
IDLE5
IN
IDLE4
IN
IDLE3
IN
IDLE2
IN
IDLE1
IN
IDLE0
IN
IDLE5IN
IDLE4IN
IDLE3IN
Input level of KWU 5
Input level of KWU 4
Input level of KWU 3
IDLE2IN
Input level of KWU 2
IDLE1IN
Input level of KWU1
IDLE0IN
Note :
Input level of KWU 0
0:
“0” detect
1:
“1” detect
0:
“0” detect
1:
“1” detect
0:
“0” detect
1:
“1” detect
0:
“0” detect
1:
“1” detect
0:
“0” detect
1:
“1” detect
0:
“0” detect
1:
“1” detect
(Initial value: **00 0000)
Read
only
*: Don’t care
Figure 2.12.2 Key-On-Wake-Up Control Register
88CS34-128
2007-09-12
TMP88CS34/CP34
2.13 Pulse Width Modulation Circuit Output
The TMP88CS34/CP34 has four 12-bit resolution PWM output channels including two 14-bit
resolution selectable.
DA converter output can easily be obtained by connecting an external low-pass filter. PWM
outputs are multiplexed with general purpose I/O ports as; P40 ( PWM0 ) to P43 ( PWM3 ). PWM
output is negative logic. When these ports are used PWM outputs, the corresponding bits of P4,
P5 output latches and input/output control latches should be set to “1”.
In STOP mode, PWM output pin keeps high-level. When operation mode is changed from
STOP mode to NORMAL mode, PWM control register (PWMCR1A, PWMCR1B) are initialized.
2.13.1
Configuration
12-Bit Resolution PWM output
Internal counter (2)
Internal counter (1)
14 13 12 11 10 9
8 7 6 5 4 3 2 1
Additional pulse
generate circuit
PWM0
clock
2
(fc/2 or fc/2 )
Compare circuit
ALL “0”
13
8
7
PWM2
PWM3
S
R
0
PWM Data Latch
5
PWM1
PWM Data Latch
0
Transfer Buffer (the upper)
7
7
0
Transfer Buffer (the lower)
0
PWMDBR1
2
0
PWMCR1B
PWM Control Register 1B
6
0
PWMCR1A
PWM Control Register 1A
Figure 2.13.1 PWM Output Circuit
88CS34-129
2007-09-12
TMP88CS34/CP34
2.13.2
PWM Output Wave Form
(1) PWM0 to PWM1 Outputs
PWM0 and PWM1 output can be selected 12-bit or 14-bit resolution PWM outputs.
1.
12-bit Resolution PWM Output
When these are used as 12-bit PWM output, one period is TM = 213/fc [s] (When
DV1CK = 0) and TM = 214/fc [s] (When DV1CK = 1) and sub-period is TS = TM/16.
The lower 8-bit of the PWM data latch controls the low level pulse width with a cycle
of TS. The lower 8-bit of the PWM data latch is n (n = 1 to 255), the low level pulse
width with a cycle becomes n x t0 [s] (t0 = 2/fc [s] when DV1CK = 0, t0 = 4/fc [s] when
DV1CK = 1).
The upper 4-bit of the PWM data latch controls a position to output the additional
pulses. When the upper 4-bit of the PWM data latch is m, the additional pulses are
generated in each of m periods out of 16 periods contained in a TM period.
The relationship between the 4-bit data and the position of TS period where the
additional pulses are generated is shown in Table 2.13.1.
Table 2.13.1 The addition pulse (12 bit mode)
Bit position of the lower 4 bits of PWMDRxH
Bit 11
Bit 10
Bit 9
Bit 8
Relative position of TS in TM period where the additional
pulse is generated. (Number of TS (I) is listed)
a)
0
0
0
0
No additional pulse
b)
0
0
0
1
8
c)
0
0
1
0
4, 12
d)
0
1
0
0
2, 6, 10, 14
e)
1
0
0
0
1, 3, 5, 7, 9, 11, 13, 15
Note 1:
Note 2:
The bit positions of a) to e) can be combined.
If the low order eight bits for the PWM data latch are set to “FFH”, be sure to set the high order four bits for
this latch to “00H”.
2.
14-bit Resolution PWM Output
When these are used as 14-bit PWM output, one period is TM = 215/fc [s] (When
DV1CK = 0) and TM = 216/fc [s] (When DV1CK = 1) and sub-period is TS = TM/64.
The lower 8-bit of the PWM data latch controls the low level pulse width with a cycle
of TS. The lower 8-bit of the PWM data latch is n (n = 1 to 255), the low level pulse
width with a cycle becomes n x t0 [s] (t0 = 2/fc [s] when DV1CK = 0, t0 = 4/fc [s] when
DV1CK = 1).
The upper 6-bit of the PWM data latch controls a position to output the additional
pulses. When the upper 6-bit of the PWM data latch is m, the additional pulses are
generated in each of m periods out of 64 periods contained in a TM period.
The relationship between the 6-bit data and the position of TS period where the
additional pulses are generated is shown in Table 2.13.2.
Table 2.13.2 The addition pulse (14 bit mode)
Bit position of the lower 6 bits of PWMDRxH
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
a)
b)
c)
d)
e)
f)
g)
Note 1:
Note 2:
Relative position of TS in TM period where the additional
pulse is generated. (Number of TS (I) is listed)
No additional pulse
32
16, 48
8, 24, 40, 56
4, 12, 20, 28, 36, 44, 52, 60
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33,
35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63
The bit positions of a) to g) can be combined.
If the low order eight bits for the PWM data latch are set to “FFH”, be sure to set the high order six bits for
this latch to “00H”.
88CS34-130
2007-09-12
TMP88CS34/CP34
(2) PWM2 to PWM3 Outputs
PWM2 and PWM3 output are 12-bit resolution PWM outputs.
One period is TM = 213/fc [s] (When DV1CK = 0) and TM = 214/fc [s] (When DV1CK = 1)
and sub-period is TS = TM/16.
The lower 8-bit of the PWM data latch controls the low level pulse width with a cycle
of TS. The lower 8-bit of the PWM data latch is n (n = 1 to 255), the low level pulse width
with a cycle becomes n x t0 [s] (t0 = 2/fc [s] when DV1CK = 0, t0 = 4/fc [s] when DV1CK =
1).
The upper 4-bit of the PWM data latch controls a position to output the additional
pulses. When the upper 4-bit of the PWM data latch is m, the additional pulses are
generated in each of m periods out of 16 periods contained in a TM period.
The relationship between the 4-bit data and the position of TS period where the
additional pulses are generated is shown in Table 2.13.1.
14-bit resolution PWM mode: the additional pulse Ts (1) and Ts (63)
TM = 64 TS
TS (0)
TS (1)
TS (63)
t0
t0
n × t0
PWM0
to
PWM1
Pulse width = n × t0
Pulse width = (n + 1) t0
12-bit resolution PWM mode: the additional pulse Ts (1) and Ts (15)
TS (0)
TS (1)
TS (15)
t0
t0
n × t0
PWM2
to
PWM3
Pulse width = n × t0
Pulse width = (n + 1) t0
Note 1:
If the pulse width is set to “00H”, PWM will not operate. Its output will remain high.
Note 2:
If the pulse width is set to “FFH”, settings for additional pulses cannot be made. Be sure to set the pulse
width to “00H”.
Figure 2.13.2 PWM Output Wave Form
88CS34-131
2007-09-12
TMP88CS34/CP34
2.13.3
Control
PWM output is controlled by PWM Control Register (PWMCR1A, PWMCR1B) and PWM
Data Buffer Register (PWMDBR1).
PWM Control Register 1A
7
PWMCR1A
(00028H)
6
−
5
4
3
2
ABORT1 START3 START2 START1 START0
ABORT1
Abort PWM operation of
channel 3 to 0
START3
Start channel 3
START2
Start channel 2
START1
Start channel 1
START0
Start channel 0
RESOLUTION1 Select channel 1 resolution
RESOLUTION2 Select channel 0 resolution
Note 1:
1
0
RESOLUTION
1
0
(Initial value: *000 0000)
0:
Operation
1:
PWM Abort (PWM outputs are fixed to a high-level.)
0:
Stop PWM3
1:
Start PWM3
0:
Stop PWM2
1:
Start PWM2
Write
only
0:
Stop PWM1
1:
Start PWM1
0:
Stop PWM0
1:
Start PWM0
0:
14-bit resolution
1:
12-bit resolution
0:
14-bit resolution
1:
12-bit resolution
*: Don’t care
Note 2
After set the ABORT1 to “1”, the ABORT1 is cleared to “0” automatically.
Note 3:
PWMCR1A is write-only register and cannot be used with any of the read-modify-write instructions such
as SET, CLR, etc.
PWM Control Register 1B
7
6
5
4
3
PWMCR1B
2
1
PWMCHS1
(00029H)
0
PWMHL
(Initial value: **** *000)
00: Channel 0
PWMCHS1
Select the PWM data latch of
12-bit PWM channels
01: Channel 1
10: Channel 2
Write
only
11: Channel 3
PWMHL
Select upper or lower data
transfer buffer (PWMDBR1)
0:
Lower 8-bit
1:
Upper 4-bit or 6-bit
Note 1:
*: Don’t care
Note 2:
PWMCR1B is write-only register and cannot be used with any of the read-modify-write instructions such
as SET, CLR, etc.
PWM Data Buffer Register 1
7
6
5
4
3
2
PWMDBR1
(0002AH)
Note 1:
1
0
Write only
(Initial value: 0000 0000)
PWMDBR1 is write-only register and cannot be used with any of the read-modify-write instructions such
as SET, CLR, etc.
Note 2:
When operation mode is changed from STOP mode to NORMAL mode, PWMCR1A, PWMCR1B are
initialized.
Figure 2.13.3 PWM Control Register 1A/1B and PWM Data Buffer Register 1
88CS34-132
2007-09-12
TMP88CS34/CP34
Binary Counter Control Register
7
6
5
4
3
2
1
0
“0”
“0”
DV1CK
“0”
“0”
“0”
“0”
“0”
CGCR
(00030H)
Select of input clock to
1st divider
DV1CK
0:
fc/4
1:
fc/8
Note 1:
*: Don’t care
Note 2:
The all bits except DV1CK are cleared to “0”.
(Initial value: 0000 0000)
R/W
Figure 2.13.4 DIVIDER Control Register
(1) Internal Counter
The internal counter of PWM outputs is a free running counter. The all bits of counter are
set to “1” and are not counted up at one of the following conditions.
1.
During reset
2.
The operation mode is changed to STOP mode.
3.
Setting ABORT1 to “1”.
4.
The START3 to 0 are “0” in 12-bit PWM outputs.
5.
The lower 8-bit of PWM data latch in 12-bit PWM outputs is “00H”. The PWM data
latch in 7-bit PWM outputs is “00H”.
(2) Outputs control and Programming of PWM data
The PWM outputs are fixed to a high-level immediately when the ABORT1 is set to “1”.
The PWM outputs starts the operation when the STARTx (x: 0 to 3) is set to “1”.
The data from the transfer buffer to a PWM data latch is transferred when the all bits of
internal counter are set to “1”. Therefore, the data is transferred to a PWM data latch
immediately when the internal counter is initialized. And the data is transferred to a PWM
data latch at the beginning of the next cycle when all bits of the internal counter are not set
to “1”.
The sequence of writing the output data to PWM data latches is shown as follows;
1.
PWM0 to PWM1
a.
Write the channel number of PWM data latch to PWMCHS1 (bit 2 and 1 in
PWMCR1B) and clear PWMHL (bit 0 in PWMCR1B) to “0”.
b.
Write the lower 8-bit PWM output data to PWMDBR1.
c.
Write the channel number of PWM data latch to PWMCHS1 and set PWMHL to
“1”.
d.
Write the upper 4-bit or 6-bit PWM output data to PWMDBR1.
e.
Select the resolution of PWM output to RESOLUTIONx (x: 0, 1) (bit 0 and 1 in
PWMCR1A) and set STARTx (x: 0, 1) (bit 2 and 3 in PWMCR1B) to “1”.
Note:
PWM output data must be write to PWMDBR1 in the order of the lower 8-bit PWM
output data, the upper 4-bit (or 6-bit) PWM output data. If the upper 4-bit (or 6-bit)
PWM output data is write to PWMDBR1, the lower 8-bit PWM output data is not
changed (Except when lower 8-bit PWM output data is “00H”.).
88CS34-133
2007-09-12
TMP88CS34/CP34
2.
PWM2 to PWM3
a.
Write the channel number of PWM data latch to PWMCHS1 and clear PWMHL to
“0”.
b.
Write the lower 8-bit PWM output data to PWMDBR1.
c.
Write the channel number of PWM data latch to PWMCHS1 and set PWMHL to
“1”.
d.
Write the upper 4-bit PWM output data to PWMDBR1.
e.
Set STARTx (x: 2, 3) to “1”.
1) Data transfer timing and STOP/ABORT timing (X: 0 to 3)
TM
TM
TS
TS
PWMx
m × t0
n × t0
Writing PWMDBR1
(data m to n)
TS
PWMx
STARTx = 0
or
The lower 8-bit of PWM data latch = 00H
TS
PWMx
ABORT1 = 1
or
STOP mode
2) Restart timing when operating for 1ch or more
TM
TM
PWM0
PWM1
Restarting PWM1
Restarts after one cycle.
3) Restart timing after all channels stop
TM
TM
Start command
Figure 2.13.5 Wave form of PWM0 to PWM3
Note: PWM output data must be write to PWMDBR1 in the order of the lower 8-bit PWM output data, the
upper 4-bit (or 6-bit) PWM output data. If the upper 4-bit (or 6-bit) PWM output data is write to
PWMDBR1, the lower 8-bit PWM output data is not changed (Except when lower 8-bit PWM output
data is “00H”.).
88CS34-134
2007-09-12
TMP88CS34/CP34
Example: At fc = 16 MHz, DV1CK = 0
PWM0 pin outputs a 14-bit resolution PWM wave form with a low-level of 32 μs width and
no additional pulse.
PWM1 pin outputs a 12-bit resolution PWM wave form with a low-level of 16 μs width and
no additional pulse.
LD (CGCR), 00H
; DV1CK = 0
LD
LD
LD
LD
LD
LD
LD
LD
LD
;
;
;
;
;
;
;
;
;
(PWMCR1B),00H
(PWMDBR1),80H
(PWMCR1B),01H
(PWMDBR1),00H
(PWMCR1B),02H
(PWMDBR1),40H
(PWMCR1B),03H
(PWMDBR1),01H
(PWMCR1A),0DH
Select the lower 8-bit of PWM0 output data latch
32 μs ÷ 4/fc = 80H
Select the upper 6-bit of PWM0 output data latch
No additional pulse = 00H
Select the lower 8-bit of PWM0 output data latch
16 μs ÷ 4/fc = 40H
Select the upper 4-bit of PWM0 output data latch
Additional pulse (Ts (8)) = 01H
Start PWM0 and PWM1 ,
PWM0 : 14-bit resolution, PWM1 : 12-bit resolution
88CS34-135
2007-09-12
TMP88CS34/CP34
2.14 On-Screen Display (OSD) Circuit
The TMP88CS34/CP34 features a built-in on-screen display circuit used to display characters
and symbols on the TV screen. There are 383 characters of mono font and 96 characters of color
font (447 characters of mono font and 64 characters of color font) and any characters can be
displayed in an area of 32 columns × 12 lines (include 2 columns for solid space). With an OSD
interrupt, additional lines can be displayed.
OSD circuit functions are as follows :
(1) Number of character fonts
: mono font 383 and color font 96
mono font 447 and color font 64
(2) Number of display characters
: 384 (32 columns × 12 lines).
(3) Composition of character
: horizontal 16 × vertical 18 dots
(4) Character sizes
: 3 kinds for large, middle and small characters
(Selectable line by line)
(5) Character ornamentation function
Fringing function
: mono font
Smoothing function
: mono font
Slant function (Italics)
: mono font
Blinking function
Underline
(6) Solid space
(7) Area plane function
: 2 planes
(8) Full-raster blanking function
(9) Display colors
Character colors
Fringe color
Background color
Area plane color
Raster color
:
:
:
:
:
8 or 27 colors (selectable character by character)
8 or 27 colors (selectable page by page)
8 or 27 colors (selectable page by page)
8 or 27 colors (selectable each of 2 planes)
8 or 27 colors (selectable page by page)
(10) Display position
: 256 horizontal steps and 625 vertical steps for code plane
: 512 horizontal steps and 625 vertical steps for Area plane
(11) Window function
: 625 vertical steps
(12) Half transparency output function
(13) 27 colors display function
(14) Color palette
(15) PAL100/NTSC120 display
Note:
The function of the OSD circuit don’t meet the requirements of on-screen display functions
of closed caption decoders based on FCC standards.
88CS34-136
2007-09-12
TMP88CS34/CP34
The TMP88CS34/CP34 outputs OSD through 3 planes; code, area, and raster. 3 planes
function independently. In addition, they are displayed simultaneously. There is the priority
among these 3 planes, so they are displayed on a screen according to the priority.
These 3 planes have the priority such as
Code > Area > Raster.
1.
Code plane
OSD character is displayed on the code plane.
The code plane consists of 32 characters × 1 row and a total of 12 planes. The 12 planes
have the priority such as code 1 > code 2 >･･･> code 11 > code 12.
On the code plane, characters of 16 × 18 dots is displayed. These fonts are called
characters, and read from character ROM and display memory through the character code
on the display memory.
2.
Area plane
The area on a screen is displayed on the area plane.
The area plane can display 2 square areas of any size by specifying coordinates. The 2
planes have the priority such as area plane 1 > area plane 2.
88CS34-137
2007-09-12
TMP88CS34/CP34
2.14.1
OSD Configuration
Shown below is the block diagram of the OSD circuit.
TLCS-870/X CPU
ROM: 64 Kbytes
RAM: 1.5 Kbytes
OSD interrupt
LC oscillation
control
Jitter
elimination
circuit
XIN
XOUT
Oscillator
for OSD
OSC1
OSC2
OSD control
Horizontal position
counter
P70 ( HD )
P71 ( VD )
Interrupt control
circuit
Clock
generator
Horizontal position
decoder
I
Display RAM
32 × 12 × 16 bits
6 Kbytes
Vertical position
counter
Vertical position
decoder
I
Y/BL
Display B
output
G
control
R
Output
signal
selecter
G
R
G
To the
lower row
(A)
R
P57 (I)
Output timing
Y/BL
B
B
Caracter ROM
384 × 16 × 18 bits
96 × 16 × 18 × 3 bits
24 Kbyte (mono)
+ 18Kbyte
I
(A)
Y/BL
Intermediate-value enable signal
Color palette
circuit
synchronization
circuit
Data signal
P67 (Y/BL)
P66 (B)
P65 (G)
P64 (R)
OSD control
Figure 2.14.1 OSC Block Diamgram
2.14.2
Monochrome and Color Fonts
The TMP88CS34 can display both monochrome and color fonts.
The monochrome font is intended for monochromic display. Each character in the font
consists of 18 vertical × 16 horizontal dots. For the color font, each display dot in each
character can be specified separately for R (red), G (green), and B (blue). Each character
consists of 18 vertical × 16 horizontal dots.
The monochrome and color fonts can be mixed on one display row.
88CS34-138
2007-09-12
TMP88CS34/CP34
2.14.3
Character ROM and Display Memory
(1) Character ROM
The character ROM incorporates 383 different monochrome font character data items
and 96 different color font character data items (447 different monochrome font character
data items and 64 different color font character data items). Users can define font data.
Each monochrome character ROM data item consists of 16 × 18 dots. Each monochrome
font dot corresponds to one character ROM bit. A value of “1” represents a display state,
and a value of “0” represents a non-display state.
Each color font character ROM data item consists of 16 × 18 dots for red, 16 × 18 dots for
green, and 16 × 18 dots for blue. Each color font dot corresponds to three character ROM
bits (with each bit corresponding to red, green, or blue).
The character ROM start address for each character code is calculated as listed in Table
2.14.1.
Table 2.14.1 Number of Character Patterns and Character Codes
Number of usable character patterns
Monochrome font
Color font
383
447
Usable character codes
Register for switching number of
fonts, ROMACH
Monochrome font
Color font
(bit 4 in ORDON)
96
1 to 17FH
180H to 1DFH
0
64
1 to 17FH,
1C0H to 1FFH
180H to 1BFH
1
Table 2.14.2 Monochrome/Color Font Character ROM Start Address
ROMACH
Character ROM start address
Monochrome font (CRA = 1 to 17FH)
Character ROM start address = CRA × 40H + 20000H
0
Color font (CRA = 180H to 1DFH)
Character ROM start address for red = CRA × 40H + 26000H
Character ROM start address for green = CRA × 40H + 27800H
Character ROM start address for blue = CRA × 40H + 29000H
Monochrome font
Character ROM start address = CRA × 40H + 20000H (CRA = 1 to 17FH)
Character ROM start address = CRA × 40H + 27000H (CRA = 1C0H to 1DFH)
Character ROM start address = CRA × 40H + 28C00H (CRA = 1E0H to 1EFH)
1
Character ROM start address = CRA × 40H + 2A400H (CRA = 1F0H to 1FFH)
Color font (CRA=180H to 1BFH)
Character ROM start address for red = CRA × 40H + 26000H
Character ROM start address for green = CRA × 40H + 27800H
Character ROM start address for blue = CRA × 40H + 29000H
Figure 2.14.2 (a) shows an example of configuring a character font (character code 001H)
as well as monochrome font ROM addresses and the related data. Figure 2.14.2 (b) shows a
character ROM dump list for this character font (character code 001H).
Figure 2.14.3 (a) shows an example of configuring a character font (character code 180H)
as well as color font ROM addresses and the related data. Figure 2.14.4 (b) shows a
character ROM dump list for this character font.
88CS34-139
2007-09-12
TMP88CS34/CP34
Note 1: A data cannot be read from character ROM by software.
Note 2: When ordering a mask, load the data to character ROM at addresses 20000H to 2A7FFH.
And the data in unused are of character ROM are must be specified to FFH.
Note 3: Do not use character code 000H
Address Data
(Hex) (Hex)
20040
3F
20041
7F
20042
E0
20043
C0
20044
00
20045
00
20046
00
20047
01
20048
03
20049
07
2004A
0E
2004B
1C
2004C
38
2004D
70
2004E
FF
2004F
FF
20050
00
20051
00
Bit
Bit
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
Address Data
(Hex) (Hex)
20060
C0
20061
E0
20062
70
20063
30
20064
30
20065
70
20066
E0
20067
C0
20068
80
20069
00
2006A
00
2006B
00
2006C
00
2006D
00
2006E
F0
2006F
F0
20070
00
20071
00
(Character code 001H)
(a) Character font configuration of mono font
20000/
20010/
20020/
20030/
20040/
20050/
20060/
20070/
00
00
00
00
3F
00
C0
00
00
00
00
00
7F
00
E0
00
00
FF
00
FF
E0
FF
70
FF
00
FF
00
FF
C0
FF
30
FF
00
FF
00
FF
00
FF
30
FF
00
FF
00
FF
00
FF
70
FF
00
FF
00
FF
00
FF
E0
FF
00
FF
00
FF
01
FF
C0
FF
00
FF
00
FF
03
FF
80
FF
00
FF
00
FF
07
FF
00
FF
00
FF
00
FF
0E
FF
00
FF
00
FF
00
FF
1C
FF
00
FF
00
FF
00
FF
38
FF
00
FF
00
FF
00
FF
70
FF
00
FF
00
FF
00
FF
FF
FF
F0
FF
00
FF
00
FF
FF
FF
F0
FF
(b) ROM dump list of mono font
Note:
Shaded portions indicate unused data.
Figure 2.14.2 Character Font Configuration and ROM Dump List
88CS34-140
2007-09-12
TMP88CS34/CP34
R data
Address Data
(Hex) (Hex)
26000
00
26001
3F
26002
3F
26003
30
26004
30
26005
30
26006
30
26007
30
26008
3F
26009
3F
2600A
37
2600B
33
2600C
31
2600D
30
2600E
30
2600F
30
26010
30
26011
00
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Bit
43
0 0
1 1
1 1
1 0
1 0
1 0
1 0
1 0
1 1
1 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
0 0
2
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
7
0
1
1
0
0
0
0
0
1
1
0
1
1
1
0
0
0
0
6
0
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
5
0
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
Bit
4 3
0 0
1 0
1 1
1 1
0 1
0 1
0 1
1 1
1 1
1 0
0 0
0 0
0 0
0 0
1 0
1 1
1 1
0 0
2
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Address
(Hex) (Hex)
00
26020
F0
26021
F8
26022
1C
26023
0C
26024
0C
26025
0C
26026
1C
26027
F8
26028
F0
26029
00
2602A
80
2602B
C0
2602C
E0
2602D
70
2602E
38
2602F
1C
26030
00
26031
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Address
(Hex) (Hex)
00
27820
F0
27821
F8
27822
1C
27823
0C
27824
0C
27825
00
27826
00
27827
00
27828
7C
27829
7C
2782A
0C
2782B
0C
2782C
0C
2782D
1C
2782E
F8
2782F
F0
27830
00
27831
(Character code 180H)
Synthesized data used for
color font display
G data
Address Data
(Hex) (Hex)
27800
00
27801
0F
27802
1F
27803
38
27804
30
27805
30
27806
30
27807
30
27808
30
27809
30
2780A
30
30
2780B
30
2780C
30
2780D
38
2780E
1F
2780F
0F
27810
00
27811
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
Bit
43
0 0
0 1
1 1
1 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 1
1 1
0 1
0 0
2
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
7
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
6
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
5
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
Bit
4 3
0 0
1 0
1 1
1 1
0 1
0 1
0 0
0 0
0 0
1 1
1 1
0 1
0 1
0 1
1 1
1 1
1 0
0 0
2
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Character code 180H)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
5
7
7
7
7
7
7
7
7
7
7
7
7
5
5
0
0
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
0
0
7
7
2
0
0
0
1
5
4
0
0
0
0
2
3
3
0
0
7
7
0
0
0
0
1
5
4
4
0
0
0
0
3
3
0
0
7
7
0
0
0
0
1
5
4
4
4
0
0
0
3
3
0
0
7
7
0
0
0
0
1
5
4
4
4
4
0
0
3
3
0
0
7
7
0
0
0
0
1
5
4
0
4
4
4
0
3
3
0
0
7
7
0
0
0
0
1
5
6
2
0
4
4
4
3
3
0
0
7
7
1
0
0
1
1
5
6
2
0
0
4
4
7
3
0
0
6
7
7
1
1
1
5
5
7
2
0
0
0
7
7
7
0
0
0
6
7
7
7
5
4
5
3
3
3
3
3
3
7
4
0
0
0
0
6
6
6
4
4
0
3
3
3
3
3
3
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Character code 180H)
B data
Address Data
(Hex) (Hex)
29000
00
29001
3F
29002
3F
29003
30
29004
30
29005
30
29006
30
29007
3F
29008
3F
29009
30
2900A
30
2900B
30
2900C
30
2900D
30
2900E
30
2900F
3F
29010
3F
29011
00
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Bit
43
0 0
1 1
1 1
1 0
1 0
1 0
1 0
1 1
1 1
1 0
1 0
1 0
1 0
1 0
1 0
1 1
1 1
0 0
2
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
7
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
6
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
5
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
Bit
4 3
0 0
0 0
1 0
1 1
0 1
0 1
1 1
1 0
1 1
1 1
0 1
0 1
0 1
0 1
1 1
1 1
1 0
0 0
2
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Address
(Hex) (Hex)
00
29020
E0
29021
F0
29022
18
29023
0C
29024
0C
29025
1C
29026
F0
29027
F8
29028
1C
29029
0C
2902A
0C
2902B
0C
2902C
0C
2902D
1C
2902E
F8
2902F
F0
29030
00
29031
0
1
2
3
4
5
6
7
:
:
:
:
:
:
:
:
R G B
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Color
Transparent or black
Blue
Green
Cyan
Red
Magenta
Yellow
White
(Character code 180H)
Note 1:
Specifying primary color outputs by color palette specification causes the ROM-specified color to be displayed.
.
(a) Example of configuring a color font character pattern (CRA = 180H)
Figure 2.14.3 (1/2)
88CS34-141
2007-09-12
TMP88CS34/CP34
26000/
26010/
26020/
26030/
00
30
00
1C
3F
00
F0
00
3F
FF
F8
FF
30
FF
1C
FF
30
FF
0C
FF
30
FF
0C
FF
30
FF
0C
FF
30
FF
1C
FF
3F
FF
F8
FF
3F
FF
F0
FF
37
FF
00
FF
33
FF
80
FF
31
FF
C0
FF
30
FF
E0
FF
30
FF
70
FF
30
FF
38
FF
27800/
27810/
27820/
27830/
00
0F
00
F0
0F
00
F0
00
1F
FF
F8
FF
38
FF
1C
FF
30
FF
0C
FF
30
FF
0C
FF
30
FF
00
FF
30
FF
00
FF
30
FF
00
FF
30
FF
7C
FF
30
FF
7C
FF
30
FF
0C
FF
30
FF
0C
FF
30
FF
0C
FF
38
FF
1C
FF
1F
FF
F8
FF
29000/
29010/
29020/
29030/
00
3F
00
F0
3F
00
E0
00
3F
FF
F0
FF
30
FF
18
FF
30
FF
0C
FF
30
FF
0C
FF
30
FF
1C
FF
3F
FF
F0
FF
3F
FF
F8
FF
30
FF
1C
FF
30
FF
0C
FF
30
FF
0C
FF
30
FF
0C
FF
30
FF
0C
FF
30
FF
1C
FF
3F
FF
F8
FF
(b) Color font ROM dump list (CRA = 180H)
Note:
Shading indicates data in unused areas.
Figure 2.14.4 (2/2)
88CS34-142
2007-09-12
TMP88CS34/CP34
(2) Display memory
Each character of the 384 characters displayed in 32 columns × 12 lines consists of 16 bits
in the display memory. Five data items are written to the display memory: character code,
color data, blinking specification, underline enable, and slant enable.
There are two modes for writing display data to the display memory. One mode is used
for writing all display data (character code, color data, blinking specification, underline
enable, and slant enable) simultaneously. The other mode is used for changing either
character codes or the remaining data items (color data, blinking specification, underline
enable, and slant enable). How to write display data to the display memory is described in
section 2.14.6.7 (1).
Note:
The display memory is in an unknown state at reset.
Display memory configuration
•
Character code specification register (9 bits) ........... CRA8 to CRA0
•
Color data specification register (4 bits) ................... IDT/RDT/GDT/BDT
•
Blinking specification register (1 bit)........................ BLF
•
Underline enable register (1 bit) ............................... EUL
•
Slant enable register (1 bit) ....................................... SLNT
•
Flag (1 bit) for specifying whether to
turn on or off the character-specific background ..... ECBKD
• If ECHDSN = 0
SLNT
EUL
BLF
ECBKD
RDT
GDT
BDT
CRA8
CRA7
CRA6
Character color
CRA5
CRA4
CRA3
CRA2
CRA1
CRA0
CRA2
CRA1
CRA0
26
28
30
Character code specification register
Flag for specifying whether to turn on or off the character-specific background
Blinking specification register
Underline enable register
Slant enable register
•
If ECHDSN = 1
RBDT
GBDT
BLF
ECBKD
RDT
GDT
BDT
CRA8
CRA7
CRA6
CRA5
Character color
CRA4
CRA3
Character code
Flag for specifying whether to turn on or off the character-specific background
Blinking specification flag
Character-specific background color of red
Character-specific background color of green
Figure 2.14.5 Display Memory Bit Configuration
Column
1
Line
1
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
29
31
32
000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F
020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F
040
060
080
0A0
0C0
0E0
100
120
140
160
17F
Note:
Numerals in the table indicate (hexadecimal) addresses in the display memory.
Figure 2.14.6 Display Memory Address Configuration
88CS34-143
2007-09-12
TMP88CS34/CP34
(3) Color palette
The color palette can contain eight colors out of 27 colors and the display colors are
specified by the color palette registers (ORCPT0-7). The color palette registers (ORCPT0-7)
are assigned by the RGB setting register for each display mode (character, background,
fringe,area, raster).
•
RGB setting register values and their corresponding color palette registers
RGB = 000b → ORCPT0
RGB = 010b → ORCPT2
RGB = 100b → ORCPT4
RGB = 110b → ORCPT6
•
Register
Name
RGB = 001b → ORCPT1
RGB = 011b → ORCPT3
RGB = 101b → ORCPT5
RGB = 111b → ORCPT7
Configuration of the color palette registers
Address
Bit 7
Bit 6
Bit 5
Bit 4
R
Bit 3
Bit 2
G
Bit 1
Bit 0
B
Color palette composition register 0
CPT1MD1: OSD color select register
CPT1MD1 0 (fixed) CPT0R1 CPT0R0 CPT0G1 CPT0G0 CPT0B1 CPT0B0 (x = 1, 2)
CPT1MD1 = 0: 8−color mode
CPT1MD1 = 1: 27−color mode
ORCPT0
00FC6
ORCPT1
00FC7
−
−
CPT1R1 CPT1R0 CPT1G1 CPT1G0 CPT1B1 CPT1B0 Color palette composition register 1
ORCPT2
00FC8
−
−
CPT2R1 CPT2R0 CPT2G1 CPT2G0 CPT2B1 CPT2B0 Color palette composition register 2
ORCPT3
00FC9
−
−
CPT3R1 CPT3R0 CPT3G1 CPT3G0 CPT3B1 CPT3B0 Color palette composition register 3
ORCPT4
00FCA
−
−
CPT4R1 CPT4R0 CPT4G1 CPT4G0 CPT4B1 CPT4B0 Color palette composition register 4
ORCPT5
00FCB
−
−
CPT5R1 CPT5R0 CPT5G1 CPT5G0 CPT5B1 CPT5B0 Color palette composition register 5
ORCPT6
00FCC
−
−
CPT6R1 CPT6R0 CPT6G1 CPT6G0 CPT6B1 CPT6B0 Color palette composition register 6
ORCPT7
00FCD
−
−
CPT7R1 CPT7R0 CPT7G1 CPT7G0 CPT7B1 CPT7B0 Color palette composition register 7
•
Color palette setting and output colors
27-color mode (CPT1MD1 = 1) 3-value output
n = 0 to 7
x=R
CPTnx1/CPTnx0 = 1/1
Bright red
CPTnx1/CPTnx0 = 1/0 or 0/1
Dark red
CPTnx1/CPTnx0 = 0/0
No output
x=G
Bright green
Dark green
No output
x=B
Bright blue
Dark blue
No output
8-color mode (CPT1MD1 = 0) 2-value output
n = 0 to 7
x=R
CPTnx1/CPTnx0 = 1/1
Bright red
CPTnx1/CPTnx0 = 1/0 or 0/1
Bright red
CPTnx1/CPTnx0 = 0/0
No output
x=G
Bright green
Bright green
No output
x=B
Bright blue
Bright blue
No output
•
Setting the display colors
The color palette registers are assigned by setting RGB data for each display mode.
The display colors are then specified in the color palette registers.
Setting the character color to bright red and the background color to dark blue for
the code plane.
•
•
Setting character color: After setting the character code, set ORDSN (RDT = 0, GDT = 1, BDT = 0). (Assign a
color palette register.)
RGB-010b corresponds to color palette register ORCPT2.
To set the character color to bright red, set ORCPT2=00110000b. (Set the display color
in color palette register.)
Setting background color: Set background setting register ORBK (0FA5h) (RBDT = 0, GBDT = 0, BBDT = 1).
(Assign a color palette register.)
RGB = 001b corresponds to color palette register ORCPT1.
To set the background color to dark blue, set ORCPT1 = 00000001b. (Set the display
color in color palette register.)
88CS34-144
2007-09-12
TMP88CS34/CP34
(4) Color font
For the color font, the display color (R, G, B) can be specified on a dot-by-dot basis. The
size of the color font is 18 dots long by 16 dots wide, which is the same as the size of the
normal font (mono font). A dot of the color font is comprised of three bits. Font data is
combination of three bits (R, G, B) and they are arranged in the order of R (upper), G
(middle), B (lower). The color palette registers are assigned by combining these three bits of
data.
P O N M L K J I H G F E D C B A
P O N M L K J I H G F E D C B A
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
R data (Upper)
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P O N M L K J I H G F E D C B A
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G data (Middle)
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B data (Lower)
P O N M L K J I H G F E D C B A
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
5
7
7
7
7
7
7
7
7
7
7
7
7
5
5
0
0
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
0
0
7
7
2
0
0
0
1
5
4
0
0
0
0
2
3
3
0
0
7
7
0
0
0
0
1
5
4
4
0
0
0
0
3
3
0
0
7
7
0
0
0
0
1
5
4
4
4
0
0
0
3
3
0
0
7
7
0
0
0
0
1
5
4
4
4
4
0
0
3
3
0
0
7
7
0
0
0
0
1
5
4
0
4
4
4
0
3
3
0
0
7
7
0
0
0
0
1
5
6
2
0
4
4
4
3
3
0
0
7
7
1
0
0
1
1
5
6
2
0
0
4
4
7
3
0
0
6
7
7
1
1
1
5
5
7
2
0
0
0
7
7
7
0
0
0
6
7
7
7
5
4
5
3
3
3
3
3
3
7
4
0
0
0
0
6
6
6
4
4
0
3
3
3
3
3
3
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Combined data
Figure 2.14.7
•
Assignment of the color palette registers for the color font
RGB data
Color palette register
RGB = 000b 0
RGB = 001b 1
RGB = 010b 2
RGB = 011b 3
RGB = 100b 4
RGB = 101b 5
RGB = 110b 6
RGB = 111b 7
ORCPT0
ORCPT1
ORCPT2
ORCPT3
ORCPT4
ORCPT5
ORCPT6
ORCPT7
88CS34-145
2007-09-12
TMP88CS34/CP34
The following shows how the color font shown on the preceding page is displayed by
setting the color palette registers.
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N M
0 0
5 5
5 7
7 7
7 7
7 7
7 7
7 7
7 7
7 7
7 7
7 7
7 7
7 7
7 7
5 7
5 5
0 0
L
0
7
7
2
0
0
0
1
5
4
0
0
0
0
2
3
3
0
K
0
7
7
0
0
0
0
1
5
4
4
0
0
0
0
3
3
0
J
0
7
7
0
0
0
0
1
5
4
4
4
0
0
0
3
3
0
I
0
7
7
0
0
0
0
1
5
4
4
4
4
0
0
3
3
0
H
0
7
7
0
0
0
0
1
5
4
0
4
4
4
0
3
3
0
G
0
7
7
0
0
0
0
1
5
6
2
0
4
4
4
3
3
0
F
0
7
7
1
0
0
1
1
5
6
2
0
0
4
4
7
3
0
E
0
6
7
7
1
1
1
5
5
7
2
0
0
0
7
7
7
0
D
0
0
6
7
7
7
5
4
5
3
3
3
3
3
3
7
4
0
C
0
0
0
6
6
6
4
4
0
3
3
3
3
3
3
0
4
0
B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Color Palette Setting
Output Color
ORCPT0 = 00000000b
ORCPT1 = 00000011b
ORCPT2 = 00001100b
ORCPT3 = 00110000b
ORCPT4 = 00001111b
ORCPT5 = 00111100b
ORCPT6 = 00110011b
ORCPT7 = 00111111b
Black
Blue
Green
Red
Cyan
Yellow
Magenta
White
When background = OFF, dots in which is written are
displayed in black.
When background = ON, dots in which is written
show no OSD display.
However, if area-plane data and raste data exist in
the background of the display these colors are
displayed.
OSD output waveform when display line 9
R
G
B
Y
* Background = ON
* Background = OFF
Y
Figure 2.14.8
88CS34-146
2007-09-12
TMP88CS34/CP34
Note: Do not use the color font in the first character display position. The color font can be used in the
second and subsequent character display positions. If you want to use a color font character in the
first character display position as counted from the left side of the TV screen, display a transparent
character in the first character display position, and use the color font in the second character
display position. Prepare a monochrome font character with no dot as a transparent character. It is
recommended that character code CRA = 0x20H be prepared as a transparent character.
Example of display
First character display position: Transparent character.
Second character display position: Color font
First character display position
Second character display position
Transparent character
Color font
88CS34-147
2007-09-12
TMP88CS34/CP34
(5) Dark color setting function
The dark color setting function is intended to control OSD intermediate-value outputs,
using High, High-Z, and Low outputs. Setting CPT1MD1 (bit 7 in ORCP1) to “1” enables
this function.
Producing 3-value outputs requires installing an external circuit.
R1
Microcontroller’s
RGB outputs
R2
C2
To VCD IC
C1
Note:
R3
The resistor and capacitor values used in the external circuit vary depending on the voltage potential you
want to generate. Please make adjustments for yourself.
Figure 2.14.9 Example of an External Circuit for Creating Colors between Primary Colors
88CS34-148
2007-09-12
TMP88CS34/CP34
(6) Switching the OSD ROM area
When the TMP88CS34 is initialized, it is configured for 383 characters of mono font and
96 characters of color font. By setting ROMACH (bit 5 of ORDON) to 1, this configuration
can be changed to 447 characters of mono font and 64 characters of color font, as shown
below.
In character colde order
ROMACH = 0
CRA
000H
MCU Mode
Address
20000H
Mono font data
384 characters 25FFFH
26000H
17FH
180H
CRA
05800H
000H
0B7FFH
0B800H
17FH
180H
Color font
R data
277FFH
27800H
96
characters
0CFFFH
0D000H
Color font
G data
64
characters
1BFH
1C0H
28FFFH
29000H
1DFH
1E0H
0E7FFH
0E800H
Color font
B data
1DFH
ROMACH = 1
EPROM Mode
Address
1EFH
1F0H
2A7FFH
1FFH
0FFFFH
MCU Mode
Address
20000H
Mono font data
384 characters 25FFFH
26000H
Color font
R data
26FFFH
27800H
Color font
G data
EPROM Mode
Address
05800H
0B7FFH
0B800H
0C7FFH
0D000H
287FFH
29000H
0DFFFH
0E800H
29FFFH
Mono font data 27000H
32 characters 277FFH
Mono font data 28C00H
16 characters 28FFFH
Mono font data 2A400H
0E7FFH
0C800H
Color font
B data
16 characters
0CFFFH
0E400H
0E7FFH
0FC00H
2A7FFH
0FFFFH
MCU Mode
Address
EPROM Mode
Address
In ROM address order
ROMACH = 0
CRA
000H
MCU Mode
Address
20000H
Mono font data
384 characters 25FFFH
26000H
17FH
180H
CRA
05800H
000H
0B7FFH
0B800H
17FH
180H
Color font
R data
1BFH
1C0H
277FFH
27800H
96
characters
0CFFFH
0D000H
Color font
G data
0E7FFH
0E800H
Color font
B data
Note:
1DFH
180H
1BFH
1E0H
28FFFH
29000H
1DFH
ROMACH = 1
EPROM Mode
Address
1EFH
180H
1BFH
1F0H
2A7FFH
0FFFFH
1FFH
20000H
Mono font data
384 characters 25FFFH
26000H
Color font R data
64 characters/3 26FFFH
Mono font data 27000H
05800H
0B7FFH
0B800H
0C7FFH
0C800H
32 characters 277FFH
Color font G data 27800H
64 characters/3 287FFH
Mono font data 28C00H
0CFFFH
0D000H
16 characters 28FFFH
Color font B data 29000H
64 characters/3 29FFFH
Mono font data 2A400H
0E7FFH
0E800H
16 characters
2A7FFH
0DFFFH
0E400H
0F7FFH
0FC00H
0FFFFH
Do not CRA code 000H at 88Cx34.
Figure 2.14.10
88CS34-149
2007-09-12
TMP88CS34/CP34
2.14.4
OSD Circuit Control
The OSD circuit performs control functions using the OSD control registers which reside
in addreses 0001DH to 0001FH and 00024H to 00025H in the special function registers
(SFR), and in addresses 00F80H to 00FCEH in the data buffer register (DBR). Section
2.14.6.8 shows the OSD control registers. The OSD control registers are used to set display
start position, display character designs (that is, fringing, smoothing, color data, character
size, and etc.), display memory addresses, and character codes.
Setting the display on-off control bit, DON, (bit 0 in ORDON) to “1” enables display
(starts display). Setting DON to “0” disables display (halts display).
2.14.5
OSD Control Register Write
There is a list of the OSD control registers on pages 199 to 201.
When data is written into a shaded register, the data is transferred to the OSD circuit,
and then the data becomes valid. After data is written into an unshaded register, the data
is transferred to the OSD circuit, and then the data becomes valid.
To transfer the contents of a control register to the OSD circuit, use data transfer request
register RGWR (bit 2 in ORDON).
Setting “1” in the RGWR register outputs the transfer request signal to the OSD circuit.
Three instruction cycles later, transfer of the written data to the OSD circuit starts. While
the data is being transferred, data transfer status monitoring flag RGWR (bit 2 in ORDON)
is “1”. When this transfer is completed, the flag is cleared to “0”.
Written data transfer register (1 bit) … RGWR (Bit 2 in ORDON)
“0”
… Initialized state
… Transfers written data to OSD circuit.
“1”
(After transfer, RGWR is reset to 0.)
Note:
Don’t write “0” to RGWR.
88CS34-150
2007-09-12
TMP88CS34/CP34
(1) RGWR system
OSD circuit
Q
D
Transfer pulse by RGWR = 1
LE
Register specified by RGWR
Figure 2.14.11 RGWR System
(2) Transfer timing
1.
No display area
When having set RGWR to “1” during no display area, the timing OSD register
can be transferred is at the falling edge of HD signal.
HD
RGWR Register
Set RGWR Register to “1”
Clear RGWR
Data Transfer Pulse
Transfer the contents of OSD registers
into OSD circuit
Figure 2.14.12 Data Transfer Timing in No Display Area
2.
Display area (including any lines specified as display off by character size)
When having set RGWR to “1” during display area, the timing OSD register can
be transferred is at the falling edge of HD signal when the display line has been
finished.
HD
Display Line
RGWR Register
Set RGWR Register to “1”
Clear RGWR
Data Transfer Pulse
Transfer the contents of OSD registers
into OSD circuit
Figure 2.14.13 Data Transfer Timing in Display Area
88CS34-151
2007-09-12
TMP88CS34/CP34
2.14.6
OSD Function
2.14.6.1 Signal Control (Port I/O)
(1) P6 port output select function
This function is used to select whether the contents of port P57, P67 to P64 will
be output or I, R, G, B, Y/BL signals of the OSD circuit will be output on pins P57,
P67 to P64.
P57 port output select registers (1 bits): PIDS (bit 3 in ORP6S)
P57
PIDS = 0
PIDS = 1
I
Port
P67 to P64 port output select registers (4 bits): P67S, P66S, P65S, P64S, (bit 7 to
4 in ORP6S)
P6nS = 0
P64
R
P65
G
P66
B
P67
Y/BL
P6nS = 1
Port
Note: Be sure to write “0EH” to the ORP6S2 register (0x0FA1H).
(2) OSD pin output polarity control function
This function is used to select the polarity of the OSD outputs for RGB, I and
Y/BL.
Output polarity control register (4 bits) … BLIV, YIV, RGBIV, IIV (bit 3 to 0 in
ORIV)
“0”
“1”
… Active high
… Active low
(3) OSD pin input polarity control
Input polarity control
Input polarity control register of RIN/GIN/BIN/Y/BLIN (2 bits)
For Y/BLIN
For RIN, GIN, and BIN
Input polarity control
… YBLII (Bit 5 in ORIV)
… RGBII (Bit 4 in ORIV)
RGBII
“0”
… Active high
“1”
… Active low
Input polarity control register of HD / VD (2 bits)
For VD … VDPOL (Bit 7 in ORIV)
For HD … HDPOL (Bit 6 in ORIV)
Input polarity control
VDPOL, HDPOL
“0”
… Not invert input signal
“1”
… Invert input signal
Note: To direct P64 (R), P65 (G), and P66 (B) to produce three-value outputs (High,
High-Z, and Low), be sure to write “0” to the output polarity control register (4
bits).
88CS34-152
2007-09-12
TMP88CS34/CP34
Input waveform to P70, P71
Register setting for the
following waveform
P71 ( VD )
VDPOL = 0
P70 ( HD )
HDPOL = 0
P71 ( VD )
VDPOL = 1
P70 ( HD )
HDPOL = 0
P71 ( VD )
VDPOL = 0
HDPOL = 1
P70 ( HD )
P71 ( VD )
VDPOL = 1
P70 ( HD )
HDPOL = 1
Figure 2.14.14 VD / HD input and VDPOL/HDPOL
(4) Y/BL signal select function
This function is used to select either Y or BL signal output from the Y/BL pin.
Y/BL signal select register (1 bit) … YBLCS (bit 7 in ORP6S)
“0”
“1”
Y signal output
BL signal output
…
…
Y signal … Output in all OSD areas (Logical OR for R, G, B,
Character data, Fringing data, area data, etc.)
BL signal … ·When EXBL is “0”:
Output in all display character areas
When EXBL is “1”:
Output in the whole page
(5) I signal function select
When PIDS (bit 3 in ORP6S) is set to “0”, Port 57 (I pin) can be used as Half
Transparency/Half Tone through an extra circuit.
The I-pin output is made high only for the area planes. If you want to make the
I-pin output high for area plane 1, set PISEL1 (bit 3 in the ORACL register) to “1”.
If you want to make the I-pin output high for area plane 2, set PISEL2 (bit 7 in the
ORACL register) to “1”.
(6) R, G, B, Y/BL Internal/external signal select.
Selects either R, G, B, and Y/BL signals from the internal OSD circuit, or RIN,
GIN, BIN, and Y/BLIN signals from external input.
R, G, B, Y/BL signal select registers (2 bits) … MPXS1/MPXS0
(Bits 1 and 0 in ORP6S)
“00”
… Simultaneous output (Signal from the OSD circuit has
higher priority.)
“01”
… Output of signal from internal OSD circuit
“10”
… Output of signal from external input
“11”
… Simultaneous output (External input signal has higher
priority.)
88CS34-153
2007-09-12
TMP88CS34/CP34
2.14.6.2 OSD data output format control
(1) Scan mode
The double scan mode is used to handle non-interlaced scanning TV. When
double scan mode is enabled, the vertical display counter increases every 2 scan
lines and a vertical size of a dot is double. This function is enabled by setting
VDSMD (bit 7 in ORETC) in the OSD control register to “1”.
Scan mode select register (1 bit) … VDSMD (bit 7 in ORETC)
“0”
“1”
…
…
Normal mode
Double scan mode
Note 1: The data written to those control register is transferred to the OSD circuit and
become valid when the data is written.
Note 2: When OSD circuit is used on an interlace scanning TV, a jitter elimination
circuit must be enabled and set AFLD to “1” in JECR.
Table 2.14.3 The Difference of 2 types of Scan Mode
Normal mode
Double scan mode
Specification Unit of vertical display
start position
One scanning line
Two scanning lines
1 dot height
−
Normal mode height × 2
Normal mode
Double scan mode
Normal mode
Interlace scanning
Double scan mode
Non-interlace scanning
Figure 2.14.15 Scan Mode
88CS34-154
2007-09-12
TMP88CS34/CP34
2.14.6.3 Display Position Control
(1) Code display position setting
1.
Horizontal display start position
The horizontal display start position can be set in 256 steps by writing to OSD
control registers HS17 to HS10 (bit 7 to 0 in ORHS1). The value is in common with
all lines.
Specification unit: 2 TOSC
Specification steps: 256
Specification horizontal display start position: Line 1 to 12: HS17 to HS10
(ORHS1)
HS1 = (HS17 to HS10) H × 2TOSC + 22TOSC (Line1 to 12)
Note 1: TOSC; One cycle of OSD oscillation.
Note 2: The data written to these control registers is transmitted to OSD circuit by
setting RGWR (bit 2 in ORDON) to “1”.
2.
Vertical display start position
The vertical display start position can be specified for each display line using
625 steps by writing to VSn9 to VSn0 (in ORVSn (n; 1 to 12)).
Specification unit: 1 scan line
Specification steps: 512
Specification vertical display start position:
Line1: VS19 to VS10 (ORVS 1)
Line2: VS29 to VS20 (ORVS 2)
..
.
Line12: VS129 to VS120 (ORVS 12)
Line n: VSn = (VSn9 to VSn0) H × 1THD (n; 1 to 12)
Note 1: THD; One cycle of HD signal.
Note 2: The data written to these control registers is transmitted to OSD circuit by setting RGWR
(bit 2 in ORDON) to “1”.
Note 3: If display lines are overlapped each other, previous display line is enabled and next line is disabled.
If vertical display start positions of two or more lines are set on same value, high priority line is
enabled. Lines of OSD (VS1 to VS12) are fixed priority levels as follows:
VS1 > VS2 > VS3 >……> VS12
Set the vertical display start position not to overlap display lines.
VS5 (display on, small character)
VS2 (display canceled, middle character)
VS3 (display on, small character)
Occasion of overlapping
Note 4: The line which is displayed off is managed as a small size character line.
Note 5: Transfer the contents of vertical display start position registers into OSD circuit before the position of
the scanning line coincides with their own vertical display start position.
88CS34-155
2007-09-12
TMP88CS34/CP34
(2)
Area display position setting
The planes have the priority such as Code plane > Area plane 1 > Area plane 2 >
Raster plane.
1.
Horizontal display start position
The horizontal display start position can be set in 512 steps by writing to OSD
control registers AHSn8 to AHSn0 (bit 8 to 0 in ORAHSn). And also display stop
position is correspond to AHEn8 to AHEn0 (bit 8 to 0 in ORAHEn). (n; 1 to 2)
Horizontal display start position
AHSn = (AHSn8 to AHSn0)H × 2TOSC
Horizontal display end position
AHEn = (AHEn8 to AHEn0)H × 2TOSC
Note 1: TOSC: One cycle of OSD oscillation.
Note 2: If the horizontal display start position for characters is the same as that for
areas, the two positions are not displayed at the same time. The horizontal
display start position for characters is displayed 16 TOSC (corresponding to a
register value of 8) later than that for areas.
Vertical display start position
2.
The vertical display start position can be set in 625 steps by writing to OSD
control registers AVSn9to AVSn0 (bit 9 to 0 ORAVSn). And also display stop
position is correspond to AVEn9 to AVEn0 (bit 9 to 0 in ORAVEn). (n; 1 to 2)
Vertical display start position
AVSn = (AVSn9 to AVSn0)H × THD
Vertical display end position
AVEn = (AVEn9 to AVEn0)H × THD
Note:
THD: One cycle of HD signal.
HD
VS1 VS2
AVS2 AVE2
AVS1 AVE1
HS1
34 5 6 7 8
910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Code plane 1
1 2 3 4 5 6 7 8
910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Code plane 2
1 2
AHS1
VD
Area plane 1
AHE1
Area plane 2
HS1
AHS2
AHE2
SS 1 2 3 4 5 6 7 8
910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS Code plane 9
SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS Code plane 10
SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS Code plane 11
SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS Code plane 12
Figure 2.14.16 TV Scan Image
88CS34-156
2007-09-12
TMP88CS34/CP34
2.14.6.4 Character Ornamentation Control
(1) Character sizes
Character size can be selected line by line from 4 sizes. And display on/off also
can be set line by line. Small, middle, large and double height character size and
display on/off can be set with OSD control registers CSn (n = 1 to 12, ORCS4,
ORCS8, ORCS12) in the OSD control registers.
Character sizes: 4 sizes (Small, middle, large and double height)
Character size and display on/off specification unit: Line
Character size select/display on/off register (2 bits × 12)
Line 1: CS1
Line 2: CS2
:
:
Line 12: CS12
Table 2.14.4 Character Size and Display On/Off Specifications (n = 1 to 12 and m = 1 to 12)
CSn
CSn
(high-order bit)
(low-order bit)
1
1
Small-size character
0
On
1
0
Medium-size character
0
On
0
1
Large-size character
0
On
1
0
Double-height character
1
On
0
0
−
0
Off
Character size
DCSCn
(double-height specification)
Display on/off
Note 1: To display a double-height character, write “10” and “1”, respectively, to CSn
(medium-size character specification) and DCSCm (double-height display
specification). If DCSCm and CSn are, respectively, “0” and “10”, medium-size
characters are displayed.
Note 2: If the character size specification (CSn) is “11” or “01”, no double-height character
can be displayed.
Note 3: Do not specify to modify double-height characters (such as fringing, smoothing,
and slanting) because such specifications hamper normal display.
Note 4: The display off line operates like the width of small character size line thought the
character is not displayed.
Note 5: The data written to these control registers is transmitted to OSD circuit by setting
RGWR (bit 2 in ORDON) to “1”.
Note 6: When OSD circuit is used on an interlace scanning TV, a jitter elimination circuit
must be enabled and set AFLD to “1” in JECR.
Note 7: When VDSMD and AFLD are “0”, only character of even display dot is displayed.
(refer to 2.16 a jitter elimination circuit)
88CS34-157
2007-09-12
TMP88CS34/CP34
Table 2.14.5 Dot Size and Character Size
VDSMD = 0
(normal mode)
Dot size
VDSMD = 1
(double-scan mode)
Character size
Dot size
Character size
EULAn = 0
Small-size character
1TOSC × 0.5THD
16TOSC × 9THD
1TOSC × 1THD
16TOSC × 18THD
(underline off)
Medium-size character
2TOSC × 1THD
32TOSC × 18THD
2TOSC × 2THD
32TOSC × 36THD
Large-size character
4TOSC × 2THD
64TOSC × 36THD
4TOSC × 4THD
64TOSC × 72THD
Double-height character
1TOSC × 1THD
16TOSC × 18THD
1TOSC × 2THD
16TOSC × 36THD
EULAn = 1
Small-size character
1TOSC × 0.5THD
16TOSC × 12THD
1TOSC × 1THD
16TOSC × 24THD
(underline on)
Medium-size character
2TOSC × 1THD
32TOSC × 24THD
2TOSC × 2THD
32TOSC × 48THD
Large-size character
4TOSC × 2THD
64TOSC × 48THD
4TOSC × 4THD
64TOSC × 72THD
Double-height character
1TOSC × 1THD
16TOSC × 24THD
1TOSC × 2THD
16TOSC × 48THD
Note: TOSC = one OSD oscillation cycle. THD = one HD signal cycle.
88CS34-158
2007-09-12
TMP88CS34/CP34
Small
Middle
Double height
Large
Figure 2.14.17 Character Size
(2) Smoothing function
The smoothing function is used to make characters look smooth. Enabling
smoothing displays 1/4 dot between two dots connecting corner to corner within a
character. Small size character and color font can not be enabled smoothing.
Smoothing is enabled by setting ESMZ (bit 4 in ORETC) in the OSD control
register to “1”.
Smoothing specification unit: Display page
Smoothing specification register (1 bit) … ESMZ (bit 4 in ORETC)
“0”
“1”
…
…
Disable smoothing
Enable smoothing
Note 1: Data of the register is transferred to the OSD circuit and become valid
when the data is written.
Note 2: The smoothing function is invalid for the color font.
Before
After
Before
After
Available form for Smoothing
Invalid form for Smoothing
Figure 2.14.18 Available Form and Invalid Form for Smoothing
88CS34-159
2007-09-12
TMP88CS34/CP34
Original character
Smoothing
Figure 2.14.19 Smoothing Example
(3) Fringing function
The fringing function is used to display a character with a fringe width is 1 dot
in a different color from that of the character. When a character is displayed with
the maximum of 18 vertical dots and 16 horizontal dots, the fringe exceeds right
and left of the character display area. No vertical fringing is displayed out of the
character display area. If there is an adjacent character that outer dot is active,
then this dot will overrule the fringe in the horizontal direction. Underlines are
not fringed.
Fringing is enabled for each line by setting EFR1 to EFR8 (OREFR8) and EFR9
to EFR12 (OREFR12) in the OSD control register to “1”.
A color for fringe is specified common to all lines using OSD control registers,
RFDT, GFDT, and BFDT (bit 2 to 0 in ORBK).
Fringing specification unit: Line
Fringing enable register (1 bit × 12) … EFRn (n; 1 to 8) (OREFR8), EFRn (n; 9
to 12) (OREFR12)
“0”
… Disable fringing
“1”
… Enable fringing
Fringe colors: 8 or 27
Fringe color specification unit: Display page
Fringe color register (3 bits) … RFDT, GFDT, BFDT (bit 2 to 0 in ORBK)
Note 1: The fringe of 1st column character does not exceed left, and the fringe of
32th character does not exceed right.
Note 2: Do not specify fringing for the color font.
Note 3: Do not specify fringing for characters for which double-height display is
specified.
88CS34-160
2007-09-12
TMP88CS34/CP34
Table 2.14.6 Fringe Color
GFDT
BFDT
Figure color
0
0
0
Setting color of ORCPT0
0
0
1
Setting color of ORCPT1
0
1
0
Setting color of ORCPT2
0
1
1
Setting color of ORCPT3
1
0
0
Setting color of ORCPT4
1
0
1
Setting color of ORCPT5
1
1
0
Setting color of ORCPT6
1
1
1
Setting color of ORCPT7
Vertical indicate area
18 dots
RFDT
Before Fringing
After Fringing
Vertical indicate area
24 dots
Disable underline
Before Fringing
After Fringing
Enable underline
a) Small character, Normal mode
Figure 2.14.20 (a) Fringing Example
88CS34-161
2007-09-12
Vertical indicate area
18 dots
TMP88CS34/CP34
Before Fringing
After Fringing
Vertical indicate area
24 dots
Disable underline
Before Fringing
After Fringing
Enable underline
b) Small character, Double scan mode
Figure 2.14.21 (ｂ) Fringing Example
88CS34-162
2007-09-12
Vertical indicate area
18 dots
TMP88CS34/CP34
Before Fringing
After Fringing
Vertical indicate area
24 dots
Disable underline
Before Fringing
After Fringing
Enable underline
c) Middle/Large character, Normal mode
Figure 2.14.22 (ｃ) Fringing Example
88CS34-163
2007-09-12
Vertical indicate area
18 dots
TMP88CS34/CP34
Before Fringing
After Fringing
Vertical indicate area
24 dots
Disable underline
Before Fringing
After Fringing
Enable underline
d) Middle/Large character, Double scan mode
Figure 2.14.23 (ｄ) Fringing Example
88CS34-164
2007-09-12
TMP88CS34/CP34
(4) Double-height display function
It is possible to display a character having the same horizontal size as for the
small-size character and the same vertical size as for the medium-size character.
This function can be realized by specifying medium-size character display for the
character size and setting up the double-height display setting register (ORDCSC).
Its specification unit is the row.
Double-height display enable unit: Row
Double-height display enable register (1 bit × 12): DCSCn (n = 1 to 12)
(ORDCSC register)
Character size specification: “10” is set in CSn (n = 1 to 12; ORCS4, ORCS8, and
ORCS12).
Small-size
character
Medium-size character
Double-height
character
Figure 2.14.24 Double-Height Character Display
Note:
Do not specify the fringing, smoothing, or slanting character modification
function for a row where double-height display is specified.
88CS34-165
2007-09-12
TMP88CS34/CP34
(5) Displaying a Small-Size Character Consisting of 26 Vertical and 18 Horizontal
Dots
It is possible to display small-size characters at vertical intervals of 26 scanning
lines. This function is realized by specifying small-size character display and
setting up the 26-dot vertical display setting register ORCCD. This specification
can be made in line units.
26-dot vertical display enable unit: Row
26-dot vertical display enable register (1 bit × 12): CCDn (n = 1 to 12) (ORCCD
register)
Character size specification: “11” is set in CSn (n = 1 to 12; ORCS4, ORCS8, and
ORCS12).
Small-size character
26-dot vertical display
Figure 2.14.25 26-dot Vertical Display
(6) Background function
The background color is the color of all backgrounds including the background
of the character area (see Table 2.14.5). The background function is specified in
screen units by setting the EBKGD OSD control register (bit 7 in the ORRCL
register) to “1”. Using the ECBKD OSD control register (bit 3 in the ORDSN
register) can enable/disable the character-specific background color.
The background color is specified, using the RBDT, GBDT, and BBDT OSD
control registers (bits 6 to 4 in the ORBK register). Setting the ECHDSN OSD
control register (bit 3 in the ORDON register) to “1” specifies SLNT (bit 6 in the
ORDSN register) and EUL (bit 5 in the ORDSN register), respectively, as RBDT
and GBDT. A background color different from that of the screen can be set up as a
character-specific background.
Background color enable units: Screen and character
Background enable register (2 bits)
Screen unit: EBKGD (bit 7 in the ORRCL register)
Character unit: ECBKD (bit 3 in the ORDSN register)
Background color specification units: Screen and character
Background color specification register
If ECHDSN = 0: RBDT, GBDT, and BBDT (bits 6 to 4 in the ORBK register)
If ECHDSN = 1: RBDT, GBDT (bits 6 to 4 in the ORBK register),
SLNT (corresponding to RBDT), and EUL (corresponding
to GBDT)
88CS34-166
2007-09-12
TMP88CS34/CP34
Table 2.14.7 Background Color Control
OSD control register
Display status
EBKGD
ECBKD
0
0
No background is displayed.
0
1
No background is displayed.
1
0
No background is displayed.
1
1
A background is displayed.
Table 2.14.8 Character-Specific Background Color Setting Function
Register
name
Function
0
1
Slanting
←
RBDT
(background color of red)
Underlining
←
GBDT
(background color of green)
BLF
Blanking
←
←
ECBKE
Character-specific
background enable
←
←
SLNT
Character
modification
specification
register
Character-specific background color
setting (ECHDSN)
EUL
Note1: When the ECHDSN is set to "1", the background color is specified by RBDT (red) and GBDT
(green) bits.In this case, ORCPT0,ORCPT2,ORCPT4 and ORCPT6 are available for color
pallet.
Note 2: OSD output isn't done, and a video signal is indicated in the background area in case of
EBKGD=0, ECBKD=0 and EBKGD=1, ECBKD=0.A background area becomes transparent
in case of EBKGD=0 and ECBKD=1. That color is indicated when it is piled up and indicated
with the area plane. The background color specified in case of EBKGD=1 and ECBKD=1 is
indicated.
Table 2.14.9 Background Color
RBDT
GBDT
BBDT
Background color
0
0
0
Setting color of ORCPT0
0
0
1
Setting color of ORCPT1
0
1
0
Setting color of ORCPT2
0
1
1
Setting color of ORCPT3
1
0
0
Setting color of ORCPT4
1
0
1
Setting color of ORCPT5
1
1
0
Setting color of ORCPT6
1
1
1
Setting color of ORCPT7
88CS34-167
2007-09-12
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Character color : Cyan
Background color : Yellow
Scanning line
Scanning line
R
R
G
G
B
B
Y
Y
BL
BL
1) Disable Background
2) Enable Background
Figure 2.14.26 Background Function
Note: When the background function is enabled, the line enable the fringing function should not start with
a blank character. If it starts with a blank character, a fringe is displayed to the left of the blank
character.
88CS34-168
2007-09-12
TMP88CS34/CP34
2.14
2.14.6.5 OSD Display Screen Control
(1) Display on/off
This function is used to display characters specified for on/off display.
Display on/off specification unit: Display page
Display on/off specification register (1 bit) ··· DON (bit 0 in ORDON)
“0”
···
Disable display
“1”
···
Enable display
Note: Do not start STOP mode during display is enable.
(2) Window function
This function is used to set upper and lower limit of display page. Window upper
limit is specified by WVSH (ORWVSH). Window lower limit is specified by WVSL
(ORWVSL). This function is enabled by setting EWDW (bit 1 in ORDON ) in the
OSD control register to 1.
Window specification unit: Display page
Window function enable specification register (1 bit) ··· EWDW (bit 1 in
ORDON)
“0”
···
Disable window function
“1”
···
Enable window function
Window upper limit specification register (10 bits) ··· WVSH9 to 0 (ORWVSH)
Window lower limit specification register (10 bits) ··· WVSL9 to 0 (ORWVSL)
Window upper and lower limit position ···
When VDSMD is “0” (Normal mode):
WVSH = (WVSH9 to WVSH0) H × THD
WVSL = (WVSL9 to WVSL0) H × THD
When VDSMD is “1” ( Double scan mode):
WVSH = (WVSH9 to WVSH0) H × 2THD
WVSL = (WVSL9 to WVSL0) H × 2THD
Note 1: THD; One cycle of HD signal
Note 2: WVSL > WVSH ≥ “1”
Note 3: Modify the value of window upper and lower limit register and the value of
EWDW during VD signal is low.
Note 4: It is recommendable that the window function is always enabled (EWDW = “1”)
and set WVSH to “01H”, WVSL to “1FEH”.
Note 5: Characters and symbols at scanning line specified by WVSL are not displayed.
88CS34-169
2007-09-12
TMP88CS34/CP34
HD
Background color
Area plane color
Picture
WVSH
Raster color
SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS
AHS1
SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS
VD
SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SS
WVSL
Picture
Note:
Window display: ON, Area plane display: ON, Background color display: ON, Raster plane display: ON
Figure 2.14.27 Display Example
Display off
WVSH
Display
Figure 2.14.28 If WVSH is on a Code Plane
88CS34-170
2007-09-12
TMP88CS34/CP34
(3) Full-raster blanking function
Full-raster blanking function is used to color the entire background for the
display area (TV screen). When using the full-raster blanking function, set
YBLCS (bit 2 in ORP6S) to “1”, output BL signal from Y/BL pin, because Y signal
cannot delete whole display page from video signal.
This function is specified for each display page by setting EXBL (bit 6 in
ORRCL) in the OSD register to “1”.
Full-raster blanking specification unit: Display page
Full-raster blanking enable register (1 bit) ··· EXBL (bit 6 in ORRCL)
“0”
···
Disable full-raster blanking
“1”
···
Enable full-raster blanking
Full-raster blanking color specification ···
registers (3 bits)
RCLR, RCLG, RCLB
(bit 2 to 0 in ORRCL)
Table 2.14.10 Raster Plane Color
RCLR
RCLG
RCLB
Raster plane color
0
0
0
Setting color or ORCPT0
0
0
1
Setting color or ORCPT1
0
1
0
Setting color or ORCPT2
0
1
1
Setting color or ORCPT3
1
0
0
Setting color or ORCPT4
1
0
1
Setting color or ORCPT5
1
1
0
Setting color or ORCPT6
1
1
1
Setting color or ORCPT7
88CS34-171
2007-09-12
TMP88CS34/CP34
(4) Area plane function
Area plane function is used to display square area to two points on a screen.
Two planes operate independently. They are displayed according to the priority
(area plane 1 > area plane 2).
See area plane display position setting in section 2.14.6.3 (2) how to set display
positions for each area.
Each area plane is set to ON or OFF by AON2 and AON1 (bit 5 and bit 4 in
ORRCL).
Area plane colors are set by ACLRx, ACLGx, ACLBx (bit 6 to bit 4 and bit 2 to
bit 0 in ORACL, x = 1, 2).
Area plane colors: 8 or 27
Area plane specification unit: plane
Area plane color specification register (6 bit)
Area plane 1: ACLR1/ACLG1/ACLB1 (bit 2 to 0 in ORACL)
Area plane 2: ACLR2/ACLG2/ACLB2 (bit 6 to 4 in ORACL)
Table 2.14.11 Area Plane Color
ACLRx
ACLGx
ACLBx
Area plane color
0
0
0
Setting color of ORCPT0
0
0
1
Setting color of ORCPT1
0
1
0
Setting color of ORCPT2
0
1
1
Setting color of ORCPT3
1
0
0
Setting color of ORCPT4
1
0
1
Setting color of ORCPT5
1
1
0
Setting color of ORCPT6
1
1
1
Setting color of ORCPT7
(x: 1, 2)
(5) I-pin function
The I-pin output becomes valid only for area planes. Resetting the PIDS OSD
control register (bit 3 in the ORP6S register) to “0” causes P57 to work for I-pin
output. If you want to produce an I-pin output for area plane 1, set the PISEL1
OSD control register (bit 3 in the ORACL register) to “1”. If you want to produce
an I-pin output for area plane 2, set the PISEL2 OSD control register (bit 7 in the
ORACL register) to “1”. The I-pin output depends on the display priority of the
area planes.
88CS34-172
2007-09-12
88CS34-173
D
C
B
A
BL
Y
I
BL
Y
I
BL
Y
I
BL
Y
I
B
C
D
A
dot
Area 1
Area 2 Halftone
PISEL1 = 0
PISEL2 = 1
B
C
D
A
D
C
B
A
BL
Y
I
BL
Y
I
BL
Y
I
BL
Y
I
dot
Area 1 Halftone
Area 2
• Example 2
<EXBL = 0, YBLCS = 0, 1>
Area where any of font colors R, G, and B is high
Character display area
• Example 1
<EXBL = 0, YBLCS = 0, 1>
PISEL1 = 1
PISEL2 = 0
D
C
B
A
BL
Y
I
BL
Y
I
BL
Y
I
BL
Y
I
B
C
D
A
dot
Area 1 Halftone
Area 2 Halftone
• Example 3
<EXBL = 0, YBLCS = 0, 1>
PISEL1 = 1
PISEL2 = 1
TMP88CS34/CP34
(6) Examples of OSD outputs
Figure 2.14.29 OSD Output Examples (a)
2007-09-12
Character display area
88CS34-174
BL
Y
B, C I
BL
I
BL
A, B,
C, D
dot
Area 1 Halftone
Raster
Area 2
Area where any of font colors R, G, and B is high
B
C
D
A
Y
dot
Area 1
PISEL1 = 1
PISEL2 = 0
PISEL1 = 0
PISEL2 = 1
• Example 5
<Full-raster display (EXBL = 0, YBLCS = 0, 1)>
Y
A, D I
B
C
D
A
Raster
Area 2 Halftone
• Example 4
<Full-raster display (EXBL = 0, YBLCS = 0, 1)>
BL
Y
B, C I
BL
Y
A, D I
B
C
D
A
dot
Area 1 Halftone
Raster
Area 2 Halftone
PISEL1 = 1
PISEL2 = 1
• Example 6
<Full-raster display (EXBL = 0, YBLCS = 0, 1)>
TMP88CS34/CP34
Figure 2.14.30 OSD Output Examples (b)
2007-09-12
A, B,
I
C, D,
E
BL
B
C
D
A
dot
Area 1
Area 2 Halftone
B
C
D
A
A, B,
I
C, D,
E
BL
dot
Area 1 Halftone
Area 2
A, B,
I
C, D,
E
BL
PISEL1 = 1
PISEL2 = 0
In patterns 1, 2 and 3, area plane 1, rather than
area plane 2, is displayed.
• Example 8
<EXBL = 1, YBLCS = 1>
Area where any of font colors R, G, and B is high
Character display area
PISEL1 = 0
PISEL2 = 1
In examples 7, 8 and 9, area plane 1, rather
than area plane 2, is displayed.
• Example 7
<EXBL = 1, YBLCS = 1>
B
C
D
A
dot
Area 1 Halftone
Area 2 Halftone
PISEL1 = 1
PISEL2 = 1
In patterns 1, 2 and 3, area plane 1, rather than
area plane 2, is displayed.
• Example 9
<EXBL = 1, YBLCS = 1>
TMP88CS34/CP34
Figure 2.14.31 OSD Output Examples (c)
88CS34-175
2007-09-12
A, B,
I
C, D,
E
BL
B
C
D
A
dot
Area 1
Raster
Area 2 Halftone
B
C
D
A
88CS34-176
A, B,
I
C, D,
E
BL
dot
Area 1 Halftone
Raster
Area 2
B
C
D
A
dot
Area 1 Halftone
Raster
Area 2 Halftone
PISEL1 = 1
PISEL2 = 1
• Example 12
<Full-raster display (EXBL = 1, YBLCS = 1)>
A, B,
I
C, D,
E
BL
PISEL1 = 1
PISEL2 = 0
• Example 11
<Full-raster display (EXBL = 1, YBLCS = 1)>
Area where any of font colors R, G, and B is high
Character display area
PISEL1 = 0
PISEL2 = 1
In patterns 1, 2 and 3, area plane 1, rather than
area plane 2, is displayed.
• Example 10
<Full-raster display (EXBL = 1, YBLCS = 1)>
TMP88CS34/CP34
Figure 2.14.32 OSD Output Examples (d)
2007-09-12
TMP88CS34/CP34
2.14.6.6 Interrupt Control
(1) Display line counter
The display line counter indicates number of display line (s) by OSD circuit on
the TV screen. The display line counter is a 4-bit counter which is initialized to “0”
by the falling edge of the VD signal and which increments when last scanning of
each display line is completed (falling edge of the HD signal). It is necessary to be
read out display line counter several times, because it does not synchronize CPU
clock.
Display line counter register (4 bits) ··· DCTR (bit 3 to 0 in ORIRC)
“0000” ··· No display line is completed.
“0001” ··· 1st display line is completed.
“0010” ··· 2nd display line is completed.
to
to
“1111” ··· 15th display line is completed.
Display line
counter
Display on
2nd Display Line
Display off
3rd Display Line
Display on
3
4th Display Line with all blank characters
Display on
:
:
10th Display Line
Display on
11th Display Line
Display on
12th Display Line
Display on
12
11
10
9
2
1
1st Display Line
4
0
m
VD signal
Note 1:
The display line counter also increments when a line with all blank characters or a line with display off is
specified.
Note 2:
When display lines are overlapped each other, previous display line is enabled and next line is disabled.
At this time, the display line counter does not increment for disabled line.
Figure 2.14.33 Display Line Counter
88CS34-177
2007-09-12
TMP88CS34/CP34
(2) Interrupt generator circuit
An interrupt request is generated when a falling edge of VD signal or when line
counter (DCTR) is counted to the certain value specified by ISDC.
Interrupt source select register (1 bit): SVD (bit 4 in ORIRC)
“0”
··· Interrupt request generated when the display line counter (DCTR)
is counted to the certain value which is specified by ISDC.
“1”
··· Interrupt request is generated when a falling edge of VD signal.
Interrupt generation line specification register (4 bits) ··· ISDC (bit 3 to 0 in ORIRC)
“0000”
··· Interrupt request generated when the display line counter is
cleared.
“0001”
··· Interrupt request generated at end points of the last scanning
line of the first display line
“0010”
··· Interrupt request generated at end points of the last scanning
line of the 2’nd display line
to
“1111”
··· Interrupt request generated at end points of the last scanning
line of the 15’th display line
2.14.6.7 Display Memory Access
(1) Display memory
The display memory is accessed for two purposes, one for writing data to the
display memory, and one for reading data from the display memory.
Display memory address specification registers ··· DMA8 to MDA0 (ORDMA)
(9 bits)
Display memory data write registers
Character code write register (9 bits)
··· CRA8 to CRA0 (ORCRA)
Character ornamentation data write
··· SLNT, EUL, BLF, RDT,
registers (6 bits)
GDT, and BDT (ORDSN)
Character-specific background on/off
··· ECBKD (ORDSN register)
specification register (1 bit)
Display memory bank select register MBK (bit 1 in ORETC)
“0”
··· When writing either character code or character ornamentation data
“1”
··· When writing both character code and character ornamentation data
Note 1: These control registers have a characteristic that immediately when a value is
written to the register, the content of the register is transferred as valid data to the
OSD circuit/display memory.
Note 2: The data written to the display memory takes effect at the same time it is written. When
character code or character ornamentation data is written to the display memory while
it is displaying some character, the character may not be displayed correctly. When
writing data to the display memory, make sure no character is being displayed in the
memory location where you are going to write data.
Note 3: When writing data to or reading data from the display memory, do not use two-byte
transfer instructions such as “LDW(HL),mn LD rr, (pp).” Otherwise, erroneous data
may be written to the display memory or data may be written to an incorrect
address.
Note 4: Allow for at least two instruction cycles between a display memory address write
instruction and a data write or read instruction. Also, when continuous writing data
to or reading data from the display memory, allow for at least two instruction cycles
between one write or read instruction and the next. Otherwise, erroneous data may
be written to the display memory or data may be written to an incorrect address.
Note 5: When setting display memory addresses, always be sure to write all of 9 address
bits sequentially in order of DMA8 and DMA7 to DMA0.
88CS34-178
2007-09-12
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1.
Normal mode
In normal mode, the display memory addresses are automatically incremented each time
data is read from or written to the memory. Because addresses are automatically incremented,
this mode may be used for reading from or writing data to multiple continuous addresses
simultaneously.
<Display memory write sequence in normal mode>
(a) When writing either character code or character ornamentation data
(1) Set MFYWR, MBK, and RDWRV all to 0.
(2) Write the most significant address bit of the display memory to DMA8. Go on and write
the 8 low-order address bits of the display memory to DMA7 to DMA0.
(3) Writing character code or character ornamentation data
•
Writing character code
Write the most significant bit of character code to CRA8. Go on and write the 8
low-order bits of character code to CRA7 through CRA0. At this point in time, the 9
bits of character code written are transferred to the display memory, and DMA8 to
DMA0 are automatically incremented.
•
Writing character ornamentation data
Write character ornamentation data to SLNT, EUL, BLF, ECBKD, RDT, GDT,
and BDT. At this point in time, the character ornamentation data written are
transferred to the display memory, and DMA8 to DMA0 are automatically
incremented.
(4) To write data (character code or character ornamentation data) to continuous
addresses, repeat step (3).
(b) When writing character code and character ornamentation data at a time
(1) Set MFYWR to 0, MBK to 1, and RDWRV to 0.
(2) Write the most significant address bit of the display memory to DMA8. Go on and write
the 8 low-order address bits of the display memory to DMA7 to DMA0.
(3) Write character ornamentation data to SLNT, EUL, BLF, ECBKD, RDT, GDT, and
BDT. At this point in time, the character ornamentation written are transferred to the
display memory.
(4) Write the most significant bit of character code to CRA8. Go on and write the 8
low-order bits of character code to CRA7 to CRA0. At this point in time, the 9 bits of
character code written and the character ornamentation data written in step (3) are
transferred to the display memory, and DMA8 to DMA0 are automatically
incremented.
(5) To write data to continuous addresses, repeat steps (3) and (4).
88CS34-179
2007-09-12
TMP88CS34/CP34
<Display memory read sequence in normal mode>
(a) When reading either character code or character ornamentation data
(1) Set MFYWR to 0, MBK to 0, and RDWRV to 1.
(2) Write the most significant address bit of the display memory to DMA8. Go on and write
the 8 low-order address bits of the display memory to DMA7 to DMA0.
(3) Reading character code or character ornamentation data
•
Reading character code
•
Read the most significant bit of character code to CRA8. Go on and read the 8
low-order bits of character code to CRA7 to CRA0. At this point in time, DMA8 to
DMA0 are automatically incremented.
Reading character ornamentation data
Read character ornamentation data SLNT, EUL, BLF, ECBKD, RDT, GDT, and
BDT. At this point in time, DMA8 through DMA0 are automatically incremented.
(4) To read data (character code or character ornamentation data) from continuous
addresses, repeat step (3).
(b) When reading character code and character ornamentation data at a time
(1) Set MFYWR to 0, MBK to 1, and RDWRV to 1.
(2) Write the most significant address bit of the display memory to DMA8. Go on and write
the 8 low-order address bits of the display memory to DMA7 to DMA0.
(3) Read character ornamentation data SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT.
(4) Read the most significant bit of character code to CRA8. Read the 8 low-order bits of
character code to CRA7 to CRA0. At this point in time, DMA8 to DMA0 are
automatically incremented.
(5) To read data from continuous addresses, repeat steps (3) and (4).
2.
Read-modify-write mode
When writing data in read-modify-write mode, the display memory addresses are
automatically incremented as in normal mode, but when reading data in this mode, the
memory addresses are not automatically incremented.
Therefore, immediately after executing a read from some display memory address, you can
execute a write to the same display memory address. After executing a write, the display
memory addresses are automatically incremented.
(a) Reading/writing either
read-modify-write mode
character
code
or
character
ornamentation
data
in
(1) Set MFYWR to 1 and MBK to 0, and RDWRV to 1.
(2) Write the most significant address bit of the display memory to DMA8. Go on and write
the 8 low-order address bits of the display memory to DMA7 to DMA0.
(3) Reading character code or character ornamentation data
•
Reading character code
•
Read the most significant bit of character code to CRA8. Read the 8 low-order
bits of character code to CRA7 to CRA0. DMA8 to DMA0 are not incremented.
Reading character ornamentation data
Read character ornamentation data SLNT, EUL, BLF, ECBKD, RDT, GDT, and
BDT. DMA8 to DMA0 are not incremented.
88CS34-180
2007-09-12
TMP88CS34/CP34
(4) Writing character code or character ornamentation data
•
Set RDWRV to “0”.
•
Writing character code
Write the most significant bit of character code to CRA8. Go on and write the 8
low-order bits of character code to CRA7 to CRA0. At this point in time, the 9 bits of
character code written are transferred to the display memory, and DMA8 to DMA0
are automatically incremented.
•
Writing character ornamentation data
Write character ornamentation data to SLNT, EUL, BLF, ECBKD, RDT, GDT,
and BDT. At this point in time, the character ornamentation data written are
transferred to the display memory, and DMA8 to DMA0 are automatically
incremented.
(5) To continue executing read-modify-write operations, repeat steps (1) to (4). To
read/write data (character code or character ornamentation data). To continue
executing read modify-write mode from continuous addresses, repeat steps (3) and (4).
(b) Reading/writing both character
read-modify-write mode
code
and
character
ornamentation
data
in
(1) Set MFYWR to 1, MBK to 1 and RDWRV to 1.
(2) Write the most significant address bit of the display memory to DMA8. Go on and write
the 8 low-order address bits of the display memory to DMA7 to DMA0.
(3) Read character ornamentation data SLNT, EUL, BLF, ECBKD, RDT, GDT, and BDT.
At this point in time, DMA8 to DMA0 are not incremented.
(4) Read the most significant bit of character code to CRA8. Read the 8 low-order bits of
character code to CRA7 to CRA0. At this point in time, DMA8 to DMA0 are not
incremented.
(5) Set RDWRV to “0”.
(6) Write character ornamentation data to SLNT, EUL, BLF, ECBKD, RDT, GDT, and
BDT. At this point in time, the character ornamentation data written is transferred to
the display memory.
(7) Write the most significant bit of character code to CRA8. Go on and write the 8
low-order bits of character code to CRA7 to CRA0. At this point in time, the 9 bits of
character code written and the character ornamentation data written in step (6) are
transferred to the display memory, and DMA8 to DMA0 are automatically
incremented.
(8) To continue executing read-modify-write operations, repeat steps (1) to (7). (To
read/write data to and from continuous addresses in read-modify-write mode, repeat
steps (3) to (7).)
88CS34-181
2007-09-12
TMP88CS34/CP34
Table 2.14.12 Address Increment
RD(RDWRV =1)
WR(RDWRV=0)
Character
Character
Character code
Character code
ornamentation
ornamentation
MFYWR = 0
MFYWR = 1
MBK = 0
INC
INC
INC
MBK = 1
−
INC
−
INC
MBK = 0
−
−
INC
INC
MBK = 1
−
−
−
INC
INC
INC: Automatic address increment at read or write.
−: No address change at data read or write.
Example: Setting a character code (020H) to the display memory (Address: 120H) and
setting a character ornamentation (001H) for character code 020H and display
memory address 120H.
1.
MBK = 0
; Set display memory address
LD
(0x25),
0x01
; ORDMA<DMA8>
LD
(0x24),
0x20
; ORDMA<DMA7:0>
; Set character code
LD
(0x1F),
0x00
; ORCRA<CRA8>
LD
(0x1E),
0x20
; ORCRA<CRA7:0>
; Set display memory address again
LD
(0x25),
0x01
LD
(0x24),
0x20
; Set character ornamentation
LD
(0x1D),
0X01
; ORDSN<SLNT, ..... BDT>
2.
MBK = 1
; Set display memory address
LD
(0x25),
0x01
LD
(0x24),
0x20
; Set character ornamentation
LD
(0x1D),
0X01
; Set character code
LD
(0x1F),
0x00
LD
(0x1E),
0x20
Note 1: To write character data into the display memory, first write into register CRA8 and then
write into registers CRA7 to CRA0. When data is written into registers CRA7 to CRA0,
DMA is incremented. It is impossible to write into the display memory for CRA7 to CRA0
alone. If no data is written into register CRA8 while data is written into registers CRA7 to
CRA0, the value previously written into register CRA8 is written into the associated
display memory.
Note 2: To read data from the display memory, first read from register CRA8, and then read from
registers CRA7 to CRA0. When data is read from registers CRA7 to CRA0, DMA8 to
DMA0 is incremented.
Note 3: There should be a time interval of at least two machine cycles between a DMA set
instruction and a data write/read instruction. There should be a time interval of at least
two machine cycles between a data write instruction and a data read instruction.
88CS34-182
2007-09-12
TMP88CS34/CP34
(2) Characters
•
If ROMACH (bit 5 in ORDON) = 0
Characters: 383 monochrome font characters and 96 color font characters
Character specification register (9 bits): CRA8 to CRA0 (bits 8 to 0 in the ORCRA
register)
Character codes: User-programmable in character ROM
Monochrome font codes “001H” to “17FH”
Color font codes “180H” to “1DFH”
•
If ROMACH (bit 5 in ORDON) = 1
Characters: 447 monochrome font characters and 64 color font characters
Character specification register (9 bits): CRA8 to CRA0 (bits 8 to 0 in the ORCRA
register)
Character codes: User-programmable in character ROM
Monochrome font codes “001H” to “17FH”, “1C0H” to “1DFH”, “1F0H” to “1FFH”
Color font codes “180H” to “1BFH”
(3) Character color
Character colors: 8 or 27
Character color specification unit: Character
Character color specification register (3 bits): RDT/GDT/BDT (bit2 to 0 in ORDSN)
Table 2.14.13 Character Color
RDT
GDT
BDT
Character color
0
0
0
Setting color of ORCPT0
0
0
1
Setting color of ORCPT1
0
1
0
Setting color of ORCPT2
0
1
1
Setting color of ORCPT3
1
0
0
Setting color of ORCPT4
1
0
1
Setting color of ORCPT5
1
1
0
Setting color of ORCPT6
1
1
1
Setting color of ORCPT7
(4) Blinking function
Blinking function is used to blink display characters.
When BKMF is “1”, characters specified for blinking by BLF are not displayed. (If the
background color function is used, the background color is not disappeared.)
Blinking specification unit: Character
Blinking specification register (1 bit) ··· BLF (bit 4 in ORDSN)
“0”
··· No blinking
“1”
··· Blinking
Blinking master specification register (1 bit) … BKMF (bit 5 in ORETC)
“0”
“1”
Note:
···
···
Disable blinking
Enable blinking (Characters whose BLF are set to “1” are not displayed.)
Regarding the extra dot of the left and/or right character by fringing function, it is not
enabled as blink.
88CS34-183
2007-09-12
TMP88CS34/CP34
(5) Underline function
Underline function is used to add a line under a display character. The underline is same
color as that of character.
Underline specification unit: Character/Line
Underline enable register (Character unit) (1 bit) ··· EUL (Bit 5 in ORDSN)
“0”
··· No underline
“1”
··· Underline
Underline enable register (Line unit) (1 bit × 12) ···EULAn (n: 1 to 8) (OREULA8),
EULAn (n: 9 to 12) (OREULA12)
Underline colors: 8 or 27
Underline color specification registers (3 bits) ··· RDT, GDT, BDT (Bit 2 to 0 in ORDSN)
(refer to Table 2.15.10)
Note 1: To use the underline function, set both the underline enable register for underlining text in
characters and that for underlining text in lines. If the former register (EUL) only is set, an
underline is not displayed.
Note 2: A color font underline can be displayed in colors set up using RDT, GDT, and RDT.
16
18
Character display area
6
Underline display area
24
EUL = 0
EUL = 1
Figure 2.14.34 Underline
88CS34-184
2007-09-12
TMP88CS34/CP34
(6) Solid space control
Solid space control is used to display one column of solid space to the left and right of 32
columns.
Solid space control is used to delete the Video signal in the areas where solid spaces are
located in the original display page, then add color (raster color) to them.
Solid space specification unit: line
Solid space specification register (24 bits)
For line 1
SOL11 and SOL10 (Bits 1 and 0 in ORSOL4)
For line 2
SOL21 and SOL20 (Bits 3 and 2 in ORSOL4)
..
..
.
.
For line 12
SOL121 and SOL120 (Bits 7 and 6 in ORSOL12)
Solid space specification
The solid space control functions as follows:
SOLx1/SOLx0 (x = 1 to 12)
“00” ···
No solid space display
“01” ···
Solid space display left for 32 columns
“10” ···
Solid space display right for 32 columns
“11” ···
Solid space display left and right for 32 columns
Solid space color specification registers (3 bits)
···
RBDT, GBDT, BBDT (Bits 2 to 0 in ORBK)
(Same color as that of background)
32 columns
Solid space
(Left)
Solid space
(Right)
Figure 2.14.35 Solid Space
88CS34-185
2007-09-12
TMP88CS34/CP34
(7) Slant function
Slant function is used to slant characters for italics.
Slant specification unit: Character
Slant enable register (1 bit) ··· SLNT (Bit 6 in ORDSN)
“0”
··· No slant
“1”
··· Slant
Note 1: SLANT function is enabled each characters, and therefore, in case of using background
function, this color of the Background is enable as slant. Regarding the extra dots of the
left and/or right character by fringing function, it is not enabled as slant.
Note 2: When a character is slanted in an area, which overlaps with the character field, the
overlap is also slanted.
Note 3: If slanting a character causes part of the character to get into the character field to the
immediate right of the character, then this part is not displayed.
Note 4: R, G, B, and Y are all slanted. Thus, if the Y signal is selected, a video signal is displayed
above and to the left of the slant character. If the specified background color is black,
setting YBLCS to“1”prevents the upper-left video signal for a slant character from being
displayed.
Note 5: When a character is slanted, the dot data to the immediate left of the character is also
slanted.
Note 6: Do not specify slanting for the color font.
The same color as that of the dot on the left is displayed.
When an entire character field (including its
background) contains dots:
When the character field on the right
does not contain a dot:
Figure 2.14.36 Slant
88CS34-186
2007-09-12
TMP88CS34/CP34
(8) Functions supporting PAL100/NTSC120
This LSI package supports the PAL (Phase Alternating Lines) 100 and NTSC (National
Television System Community) 120 broadcasting systems. Figure 2.14.35 schematically shows
the supported screen scanning method.
A
A
A
A
1st field 1
1st field 2
2nd field 1
2nd field 2
Figure 2.14.37 PAL100/NTSC120 Image Scanning Lines (Schematic Diagram)
PAL100 support enable unit: Screen
PAL100 support enable register (1 bit): EPAL100 (bit 5 in the ORDON register)
PAL100 screen display start enable register (1 bit): PALTRG (bit 0 in the ORSTRG register)
To support PAL100/NTSC120, follow this procedure.
(a) To use PAL100/NTSC120, set the EPAL100 OSD control register (bit 5 in the ORDON
register) to “1”.
(b) Read the phase detection results, PDF0 to PDF2, of the horizontal sync signal (HD)
and the vertical sync signal (VD) (bits 6, 5, and 0 in the JESR jitter elimination status
register) each time a VD interrupt occurs.
(c) By reading the phase detection results PDF0 to PDF2, the phase of screen scanning is
determined according to the detected field (1st or 2nd field).
(d) Write PALTRG (bit 0 in the ORSTRG register) during the second cycle of the 2nd field
(2nd field 2).
Once PALTRG has been written, it becomes possible to support PAL100/NTSC120 for OSD
display in the next field (1st field).
Note 1: Use software to determine the write timing for PALTRG.
Note 2: It is impossible to normally display the screen on the field of which PALTRG is written.
Note 3: To read the phase detection results PDF0 to PDF2, write “1” to the JEEN jitter elimination
control register (bit 2 in the JECR register) to enable the jitter elimination circuit.
88CS34-187
2007-09-12
TMP88CS34/CP34
2.14.6.8 OSD Control Registers
Can not access all OSD control registers in any of read-modify-write instructions
such as bit operation, etc.
0RHS1
7
6
5
4
3
2
1
0
(00F81H)
HS17
HS16
HS15
HS14
HS13
HS12
HS11
HS10
(Initial value: 0000 0000)
Write
only
Horizontal display start position specification
7
6
5
4
3
2
1
0
(00F82H)
VS17
VS16
VS15
VS14
VS13
VS12
VS11
VS10
(Initial value: 0000 0000)
(00F83H)
−
−
−
−
−
−
VS19
VS18
(Initial value: **** **00)
ORVS2
(00F84H)
VS27
VS26
VS25
VS24
VS23
VS22
VS21
VS20
(Initial value: 0000 0000)
(00F85H)
−
−
−
−
−
−
VS29
VS28
(Initial value: **** **00)
ORVS3
(00F86H)
VS37
VS36
VS35
VS34
VS33
VS32
VS31
VS30
(Initial value: 0000 0000)
(00F87H)
−
−
−
−
−
−
VS39
VS38
(Initial value: **** **00)
ORVS4
(00F88H)
VS47
VS46
VS45
VS44
VS43
VS42
VS41
VS40
(Initial value: 0000 0000)
(00F89H)
−
−
−
−
−
−
VS49
VS48
(Initial value: **** **00)
ORVS5
(00F8AH)
VS57
VS56
VS55
VS54
VS53
VS52
VS51
VS50
(Initial value: 0000 0000)
(00F8BH)
−
−
−
−
−
−
VS59
VS58
(Initial value: **** **00)
ORVS6
(00F8CH)
VS67
VS66
VS65
VS64
VS63
VS62
VS61
VS60
(Initial value: 0000 0000)
(00F8DH)
−
−
−
−
−
−
VS69
VS68
(Initial value: **** **00)
ORVS7
(00F8EH)
VS77
VS76
VS75
VS74
VS73
VS72
VS71
VS70
(Initial value: 0000 0000)
(00F8FH)
−
−
−
−
−
−
VS79
VS78
(Initial value: **** **00)
ORVS8
(00F90H)
VS87
VS86
VS85
VS84
VS83
VS82
VS81
VS80
(Initial value: 0000 0000)
(00F91H)
−
−
−
−
−
−
VS89
VS88
(Initial value: **** **00)
ORVS9
(00F92H)
VS97
VS96
VS95
VS94
VS93
VS92
VS91
VS90
(Initial value: 0000 0000)
(00F93H)
−
−
−
−
−
−
VS99
VS98
(Initial value: **** **00)
ORVS10
(00F94H)
VS107
VS106
VS105
VS104
VS103
VS102
VS101
VS100
(Initial value: 0000 0000)
(00F95H)
−
−
−
−
−
−
VS109
VS108
(Initial value: **** **00)
ORVS11
(00F96H)
VS117
VS116
VS115
VS114
VS113
VS112
VS111
VS110
(Initial value: 0000 0000)
(00F97H)
−
−
−
−
−
−
VS119
VS118
(Initial value: **** **00)
ORVS12
(00F98H)
VS127
VS126
VS125
VS124
VS123
VS122
VS121
VS120
(Initial value: 0000 0000)
(00F99H)
−
−
−
−
−
−
VS129
VS128
(Initial value: **** **00)
ORVS1
VSn8 to 0
Vertical display start position for line n
Write
only
(n: 1 to 12)
Note 1:
If display lines are overlapped each other, previous display line is enabled and next line is disabled. Set
the vertical display start position not to overlap display lines.
Note 2:
Transfer the contents of vertical display start position registers into OSD circuit before a position of the
scanning line coincides with their own vertical display start position.
88CS34-188
2007-09-12
TMP88CS34/CP34
ORCS4
(00F9AH)
7
6
5
4
3
2
1
0
CS4
CS3
CS2
CS1
(Initial value: 0000 0000)
ORCS8
(00F9BH)
CS8
CS7
CS6
CS5
(Initial value: 0000 0000)
ORCS12
(00F9CH)
CS12
CS11
CS10
CS9
(Initial value: 0000 0000)
00:
01:
10:
11:
Character size and display
on/off for line n
CSn
Display off
Large size
Middle size
Small size
Write
only
(n: 1 to 12)
OREULA8
(00F9DH)
OREULA12
(00F9EH)
EULA8
EULA7
EULA6
EULA5
−
−
−
−
EULA1
(Initial value: 0000 0000)
EULA12 EULA11 EULA10 EULA9
EULA4
(Initial value: **** 0000)
Underline for display line for
line n
EULAn
EULA3
0:
1:
EULA2
Display off
Display on
(n: 1 to 12)
OREFR8
(00F9FH)
OREFR12
(00FA0H)
7
6
5
4
EFR8
EFR7
EFR6
EFR5
EFR4
EFR3
EFR2
EFR1
(Initial value: 0000 0000)
−
−
−
−
EFR12
EFR11
EFR10
EFR9
(Initial value: **** 0000)
EFRn
3
Fringing enable specification
register for line n
2
0:
1:
1
0
Write
only
Disable fringing
Enable fringing
(n: 1 to 12)
ORSLO4
(00FA2H)
SLO4
SLO3
SLO2
SLO1
(Initial value: 0000 0000)
ORSLO8
(00FA3H)
SLO8
SLO7
SLO6
SLO5
(Initial value: 0000 0000)
ORSLO12
(00FA4H)
SLO12
SLO11
SLO10
SLO9
(Initial value: 0000 0000)
SLOn
Solid space for line n
00:
01:
10:
11:
No solid space display
Solid space display left
Solid space display right
Solid space display left and right
Write
only
(n: 0 to 12)
88CS34-189
2007-09-12
TMP88CS34/CP34
ORBK
7
6
5
4
3
2
1
0
(00FA5H)
−
RBDT
GBDT
BBDT
−
RFDT
GFDT
BFDT
(Initial value: 0000 0000)
000: Setting color of ORCPT0
001: Setting color of ORCPT1
010: Setting color of ORCPT2
RBDT/
GBDT/
BBDT
Background color select
011: Setting color of ORCPT3
000: Setting color of ORCPT4
101: Setting color of ORCPT5
110: Setting color of ORCPT6
111: Setting color of ORCPT7
000: Setting color of ORCPT0
Write
only
001: Setting color of ORCPT1
010: Setting color of ORCPT2
RFDT/
GFDT/
BFDT
Fringing color select
011: Setting color of ORCPT3
000: Setting color of ORCPT4
101: Setting color of ORCPT5
110: Setting color of ORCPT6
111: Setting color of ORCPT7
88CS34-190
2007-09-12
TMP88CS34/CP34
ORACL
(00FA6H)
7
6
PISEL2 ACLR2
5
ACLG2
4
3
2
ACLB2 PISEL1 ACLR1
1
0
ACLG1
ACLB1
(Initial value: 0000 0000)
000: Setting color of ORCPT0
001: Setting color of ORCPT1
010: Setting color of ORCPT2
ACLR2/
ACLG2/
ACLB2
Area 2 plane color select
011: Setting color of ORCPT3
000: Setting color of ORCPT4
101: Setting color of ORCPT5
110: Setting color of ORCPT6
111: Setting color of ORCPT7
000: Setting color of ORCPT0
001: Setting color of ORCPT1
010: Setting color of ORCPT2
ACLR1/
ACLG1/
ACLB1
Area 1 plane color select
Write
only
011: Setting color of ORCPT3
000: Setting color of ORCPT4
101: Setting color of ORCPT5
110: Setting color of ORCPT6
111: Setting color of ORCPT7
PISEL2
PISEL1
0: Not assign half transparency for area 2 plane
1: Assign half transparency for area 2 plane
0: Not assign half transparency for area 1 plane
1: Assign half transparency for area 1 plane
88CS34-191
2007-09-12
TMP88CS34/CP34
ORIV
(00FBBH)
7
6
VDPOL HDPOL
VDPOL
HDPOL
YBLII
RGBII
YIV
BLIV
RGBIV
IIV
5
4
3
2
1
0
YBLII
RGBII
YIV
BLIV
RGBIV
IIV
(Initial value: 0000 0000)
0: Non-invert input signal
1: Invert input signal
0: Non-invert input signal
HD input polarity select
1: Invert input signal
0: Active high
Y/BLIN input polarity select
1: Active low
0: Active high
RIN, GIN, BIN input polarity select
1: Active low
0: Active high
Y output polarity select
1: Active low
0: Active high
BL output polarity select
1: Active low
0: Active high
R, G, B output polarity select
1: Active low
0: Active high
I output polarity select
1: Active low
VD input polarity select
Write
only
ORDMA
7
6
5
4
3
2
1
(00024H)
DMA7
DMA6
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
(Initial value: 0000 0000)
(00025H)
−
−
−
−
−
−
−
DMA8
(Initial value: **** ***0)
DMAn
0
Write
only
Display memory address
(n: 0 to 8)
Note:
It is necessary to write all bits of display memory address, writng DMA7 to DMA0 after
DMA8, when writing display address.
ORDSN
7
6
5
4
3
2
1
0
(0001DH)
−
SLNT
EUL
BLF
ECBKD
RDT
GDT
BDT
SLNT
EUL
BLF
ECBKD
Slant enable specification
register
0: Disable slant
Underline enable specification
register
0: Disable underline
Blinking enable specification
register
0: Disable blinking
Character-specific background
on/off specification
0: Disable backgournd color display
(Initial value: **** ****)
1: Enable slant
1: Enable underline
1: Enable blinking
1: Enable backgournd color display
000: Setting color of ORCPT0
Read/
Write
001: Setting color of ORCPT1
010: Setting color of ORCPT2
RDT/
GDT/
BDT
Character color select
011: Setting color of ORCPT3
000: Setting color of ORCPT4
101: Setting color of ORCPT5
110: Setting color of ORCPT6
111: Setting color of ORCPT7
Note:
To display a background color, write "1" to EBKGD (bit 7 in the ORRCL register) to enable
the background function enable register for the entire screen.
88CS34-192
2007-09-12
TMP88CS34/CP34
7
6
5
4
3
2
1
(0001EH)
CRA7
CRA6
CRA5
CRA4
CRA3
CRA2
CRA1
CRA0
(Initial value: **** ****)
(0001FH)
−
−
−
−
−
−
−
CRA8
(Initial value: **** ****)
ORCRA
CRAn
0
Read/
Write
Character code
(n: 0 to 8)
Note: Write or read CRA7 to CRA0 after write or read CRA8.
ORWVSH
(00FBCH)
(00FBDH)
7
6
5
4
3
2
1
0
WVSH7 WVSH6 WVSH5 WVSH4 WVSH3 WVSH2 WVSH1 WVSH0
−
−
WVSLn
−
−
−
−
WVSH9 WVSH8
(Initial value: 0000 0000)
(Initial value: **** **00)
Write
only
Window upper limit position
(n: 0 to 9)
ORWVSL
(00FBEH)
(00FBFH)
7
6
5
4
3
2
1
0
WVSL7 WVSL6 WVSL5 WVSL4 WVSL3 WVSL2 WVSL1 WVSL0
−
−
WVSLn
−
−
−
−
WVSL9 WVSL8
(Initial value: 0000 0000)
(Initial value: **** **00)
Write
only
Window lower limit position
(n: 0 to 9)
ORDON
7
6
(00F80H)
−
−
EPAL100
5
4
3
2
EPAL100 ROMACH ECHDSN RGWR
PAL100 mode specification
register
Monochrome/color font area
ROMACH
switching register
1
0
EWDW
DON
(Initial value: **00 0000)
0:
PAL100 mode disable
1:
PAL100 mode enable
0:
383 monochrome font characters
96 color font characters
1:
447 monochrome font characters
64 color font characters
ECHDSN
RGWR
Character-specific background
color setting on/off specification
register
0:
Character-specific background color setting off
1:
Character-specific background color setting on
0:
Data transfer control OSD register 1:
Read/
Write
(Initial setting)
Written data is transferred to the OSD circuit
(cleared to "0" after the transfer).
EWDW
Window enable specification
register
0:
Window specification off
1:
Window specification on
DON
Display on/off specification
register
0:
Display off
1:
Display on
Note 1: *: Don’t care
Note 2: All OSD control registers cannot use the read-modify-write instructions. (Bit manipulation
instructions such as SET, CLR, etc. and logical operation such as AND, OR, etc.)
88CS34-193
2007-09-12
TMP88CS34/CP34
ORRCL
(00FA7H)
7
6
5
4
3
2
1
0
EBKGD
EXBL
AON2
AON1
−
RCLR
RCLG
RCLB
Background function enable
specification register
0: No background function
EXBL
Full-raster blanking enable
specification register
0: No Full-raster blanking
AON2
Area 2 plane display enable
specification register
0: No area 2 plane display
AON1
Area 1 plane display enable
specification register
0: No area 1 plane display
EBKGD
(Initial value: 0000 *000)
1: Background function enable
1: Full-raster blanking
1: Area 2 plane display enable
1: Area 1 plane display enable
000: Setting color of ORCPT0
Write
only
001: Setting color of ORCPT1
010: Setting color of ORCPT2
RCLR/
RCLG/
RCLB
Raster plane color select
011: Setting color of ORCPT3
000: Setting color of ORCPT4
101: Setting color of ORCPT5
110: Setting color of ORCPT6
111: Setting color of ORCPT7
88CS34-194
2007-09-12
TMP88CS34/CP34
ORAHS1
7
6
5
4
3
2
1
0
(00FA8H)
AHS17
AHS16
AHS15
AHS14
AHS13
AHS12
AHS11
AHS10
(Initial value: 0000 0000)
(00FA9H)
−
−
−
−
−
−
−
AHS18
(Initial value: **** ***0)
ORAHE1
(00FAAH)
AHE17
AHE16
AHE15
AHE14
AHE13
AHE12
AHE11
AHE10
(Initial value: 0000 0000)
(00FABH)
−
−
−
−
−
−
−
AHE18
(Initial value: **** ***0)
AHS1n
Horizontal start point for area 1 plane
AHE1n
Horizontal end point for area 1 plane
Write
only
(n: 0 to 8)
ORAVS1
(00FACH)
AVS17
AVS16
AVS15
AVS14
AVS13
AVS12
AVS11
AVS10
(Initial value: 0000 0000)
(00FADH)
−
−
−
−
−
−
AVS19
AVS18
(Initial value: **** **00)
ORAVE1
(00FAEH)
AVE17
AVE16
AVE15
AVE14
AVE13
AVE12
AVE11
AVE10
(Initial value: 0000 0000)
(00FAFH)
−
−
−
−
−
−
AVE19
AVE18
(Initial value: **** **00)
AVS1n
Vertical start point for area 1 plane
AVE1n
Vertical end point for area 1 plane
Write
only
(n: 0 to 9)
ORAHS2
(00FB0H)
AHS27
AHS26
AHS25
AHS24
AHS23
AHS22
AHS21
AHS20
(00FB1H)
−
−
−
−
−
−
−
AHS28
ORAHE2
(00FB2H)
AHE27
AHE26
AHE25
AHE24
AHE23
AHE22
AHE21
AHE20
(Initial value: 0000 0000)
(00FB3H)
−
−
−
−
−
−
−
AHE28
(Initial value: **** ***0)
AHS2n
Horizontal start point for area 2 plane
AHE2n
Horizontal end point for area 2 plane
Write
only
(n: 0 to 8)
ORAVS2
(00FB4H)
AVS27
AVS26
AVS25
AVS24
AVS23
AVS22
AVS21
AVS20
(Initial value: 0000 0000)
(00FB5H)
−
−
−
−
−
−
AVS29
AVS28
(Initial value: **** **00)
ORAVE2
(00FB6H)
AVE27
AVE26
AVE25
AVE24
AVE23
AVE22
AVE21
AVE20
(Initial value: 0000 0000)
(00FB7H)
−
−
−
−
−
−
AVE29
AVE28
(Initial value: **** **00)
AVS2n
Vertical start point for area 2 plane
AVE2n
Vertical end point for area 2 plane
Write
only
(n: 0 to 9)
88CS34-195
2007-09-12
TMP88CS34/CP34
ORP6S
(00FBAH)
7
6
5
4
3
2
P67S
P66S
P65S
P64S
PIDS
YBLCS
P67S to
P64S
ORETC
(00FB8H)
I pin output select
YBLCS
Y/BL signal select
MPXS
R, G, B, Y/BL signal select
0
MPXS
(Initial value: 0000 0000)
0: R, G, B, Y/BL signal output
1: Port contents output
0: I signal output
1: Port contents output
0: Y signal output
1: BL signal output
00: Simultaneous output (Signal from the OSD circuit has
higher priority.)
01: Output of signal from internal OSD circuit
10: Output of signal from externally input
11: Simultaneous output (Externally input signal has higher
priority.)
P6 port output select
PIDS
1
7
6
5
4
3
2
1
0
VDSMD
“0”
BKMF
ESMZ
“0”
MFYWR
MBK
RDWRV
VDSMD
Scan mode select
BKMF
Blinking master
ESMZ
Smoothing enable specification
register
MFYWR
Display memory bank
switching
MBK
RDWRV
Note:
Display memory read mode
select
Read/write mode select at
normal mode
Write
only
(Initial value: 0000 0000)
0: Normal mode
1: Double scan mode
0: Double blinking
1: Enable blinking
0: Disable smoothing
1: Enable smoothing
0: Normal mode
1: Read-modify-write-mode
0: Access to either character code or character display
options
1: Access both character code and character display
option
0: Data write mode for display memory
1: Data read mode for display memory
Write
only
Clear “0” to bit 6 and 3 in ORETC.
88CS34-196
2007-09-12
TMP88CS34/CP34
ORIRC
7
6
5
4
(00FB9H)
−
−
−
SDV
SVD
ISDC
ORIRC
(00FB9H)
−
DCTR
Note:
3
Interrupt source select
Interrupt generation line select
−
−
−
Display line counter
2
1
ISDC
0
(Initial value: ***0 0000)
0: Interrupt request by ISDC value
1: Interrupt request at falling edge of VD signal
When the line display of the ISDC value ends (with the
falling edge of HD signal)
while SVD = 0, interrupt request is generated.
0000: Request interrupt when display of low-order 4 bits
”0000” of DCTR ends.
0001: Low-order 4 bits ”0001” of DCTR
0010: Low-order 4 bits ”0010” of DCTR
0011: Low-order 4 bits ”0011” of DCTR
0100: Low-order 4 bits ”0100” of DCTR
0101: Low-order 4 bits ”0101” of DCTR
0110: Low-order 4 bits ”0110” of DCTR
0111: Low-order 4 bits ”0111” of DCTR
1000: Low-order 4 bits ”1000” of DCTR
1001: Low-order 4 bits ”1001” of DCTR
1010: Low-order 4 bits ”1010” of DCTR
1011: Low-order 4 bits ”1011” of DCTR
1100: Low-order 4 bits ”1100” of DCTR
1101: Low-order 4 bits ”1101” of DCTR
1110: Low-order 4 bits ”1110” of DCTR
1111: Low-order 4 bits ”1111” of DCTR
DCTR
Write
only
(Initial value: **** 0000)
0000: No line display or when the display of the 16th line
ends.
0001: 1st line display ends.
0010: 2nd line display ends.
0011: 3rd line display ends.
0100: 4th line display ends.
0101: 5th line display ends.
0110: 6th line display ends.
0111: 7th line display ends.
1000: 8th line display ends.
1001: 9th line display ends.
1010: 10th line display ends.
1011: 11th line display ends.
1100: 12th line display ends.
1101: 13th line display ends.
1110: 14th line display ends.
1111: 15th line display ends.
Read
only
The display line counter also increments when a line with all blank data or a line with
display off is specified.
If display lines are overlapped each other, previous display line is enabled and next line is
disabled. At this time, the display line counter also increments.
88CS34-197
2007-09-12
TMP88CS34/CP34
ORDCSC
(00FC4H)
(00FC5H)
7
6
5
4
3
DCSC8 DCSC7 DCSC6 DCSC5 DCSC4
−
−
−
−
n: 1 to 12
Note:
1
DCSC3
DCSC2
0
DCSC1 (Initial value: 0000 0000)
DCSC12 CDSC11 CDSC10 CDSC9 (Initial value: **** 0000)
n: Double-height specification for
row n
DCSCn
2
0: Display a medium-size character when medium-size
character display is specified.
1: Display a double-height character when medium-size
character display is specified.
Write
only
To display double-height characters, write “10” to CSn (n = 1 to 12) in the ORCSm (m = 4, 8, 12) register,
specify the medium character size, and write “1” to DCSCn (n = 1 to 12).
7
6
CPT0MD1
Fixed
at 0
ORCPT1
7
6
(00FC7H)
−
−
ORCPT2
7
6
(00FC8H)
−
−
ORCPT3
7
6
(00FC9H)
−
−
ORCPT4
7
6
(00FCAH)
−
−
ORCPT5
7
6
(00FCBH)
−
−
ORCPT6
7
6
(00FCCH)
−
−
ORCPT7
7
6
(00FCDH)
−
−
ORCPT0
(00FC6H)
CPT0MD1
CPTxR0
CPTxR1
CPTxG0
CPTxG1
CPTxB0
CPTxB1
5
4
3
2
1
0
CPT0R1 CPT0R0 CPT0G1 CPT0G0 CPT0B1 CPT0B0
5
4
3
2
1
0
CPT1R1 CPT1R0 CPT1G1 CPT1G0 CPT1B1 CPT1B0
5
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
(Initial value: **00 0000)
0: 8-color mode
Write
only
1: 27-color mode
CPTOMD1 = 0
CPTOMD1 = 1
R luminance
specification
register
CRTxR1 = 0, CRTxR0 = 0: No output
CRTxR1 = 0, CRTxR0 = 1: Light red
CRTxR1 = 1, CRTxR0 = 0: Light red
CRTxR1 = 1, CRTxR0 = 1: Light red
CRTxR1 = 0, CRTxR0 = 0: No output
CRTxR1 = 0, CRTxR0 = 1: Dark red
CRTxR1 = 1, CRTxR0 = 0: Dark red
CRTxR1 = 1, CRTxR0 = 1: Light red
G luminance
specification
register
CRTxG1 = 0, CRTxG0 = 0: No output
CRTxG1 = 0, CRTxG0 = 1: Light green
CRTxG1 = 1, CRTxG0 = 0: Light green
CRTxG1 = 1, CRTxG0 = 1: Light green
CRTxG1 = 0, CRTxG0 = 0: No output
CRTxG1 = 0, CRTxG0 = 1: Dark green
CRTxG1 = 1, CRTxG0 = 0: Dark green
CRTxG1 = 1, CRTxG0 = 1: Light green
B luminance
specification
register
CRTxB1 = 0, CRTxB0 = 0: No output
CRTxB1 = 0, CRTxB0 = 1: Light blue
CRTxB1 = 1, CRTxB0 = 0: Light blue
CRTxB1 = 1, CRTxB0 = 1: Light blue
CRTxB1 = 0, CRTxB0 = 0: No output
CRTxB1 = 0, CRTxB0 = 1: Dark blue
CRTxB1 = 1, CRTxB0 = 0: Dark blue
CRTxB1 = 1, CRTxB0 = 1: Light blue
ORSTRG1
7
6
5
4
3
2
1
0
(00FCEH)
−
−
−
−
−
−
−
PALTRG
PALRG
(Initial value: **00 0000)
0
CPT7R1 CPT7R0 CPT7G1 CPT7G0 CPT7B1 CPT7B0
27-color mode
specification
register
(Initial value: **00 0000)
0
CPT6R1 CPT6R0 CPT6G1 CPT6G0 CPT6B1 CPT6B0
5
(Initial value: **00 0000)
0
CPT5R1 CPT5R0 CPT5G1 CPT5G0 CPT5B1 CPT5B0
5
(Initial value: **00 0000)
0
CPT4R1 CPT4R0 CPT4G1 CPT4G0 CPT4B1 CPT4B0
5
(Initial value: **00 0000)
0
CPT3R1 CPT3R0 CPT3G1 CPT3G0 CPT3B1 CPT3B0
5
(Initial value: **00 0000)
0
CPT2R1 CPT2R0 CPT2G1 CPT2G0 CPT2B1 CPT2B0
5
(Initial value: 0000 0000)
PAL100 mode
trigger start
register
0: PAL trigger stop
1: PAL trigger start
88CS34-198
Write
only
(Initial value: **** ***0)
Write
only
2007-09-12
TMP88CS34/CP34
OSD Control Register List (1/3)
Register
Register
Address
Name
Register bit configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit contents
Bit 3
Bit 2
Bit 1
R/W
Bit 0
When ECHDSN = 0
SLNT = 1: Slant enable, 0: Slant disable
EUL = 1: Underline display on, 0: Underline display off
When ECHDSN = 1
0001D
ORDSN
−
SLNT
EUL
BLF
ECBKD
RDT
GDT
BDT
R/W
SLNT: Background color red
EUL: Background color green
BLF = 1: Blinking enable, 0: Blinking disable
ECBKD = 1:Character background color display
enable, Character background color display disable
0001E
ORCRA
0001F
00024
ORDMA
00025
CRA7
CRA6
CRA5
CRA4
CRA3
CRA2
CRA1
CRA0
−
−
−
−
−
−
−
CRA8
DMA7
DMA6
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
−
−
−
−
−
−
−
DMA8
CRAx: Character code (x: 0 to 8)
R/W
DMAx: Display memory address setting (x: 0 to 8)
W
EPAL100 = 1: PAL100/NTSC120 select, 0: Other
ROMACH: Select font number (mono font/color font)
1: 447 mono font character/64 color font character,
0: 383 mono font character/96 color font character
00F80
ORDON
−
−
EPAL100 ROMACH
ECHDSN
RGWR
EWDW
DON
ECHDSN = 1: Bit 6 and 5 in ORDSN is changed to
character background color, 0: Bit 6 and 5 in ORDSN
is character ornamentation
R/W
RGWR: Writing data transfer control bit
EWDW = 1: Window function enable, 0: Window
function disable
DON = 1: OSD display ON, 0: OSD display OFF
00F81
ORHS1
HS17
HS16
HS15
HS14
HS13
HS12
HS11
HS10
00F82
ORVS1
VS17
VS16
VS15
VS14
VS13
VS12
VS11
VS10
−
−
−
−
−
−
VS19
VS18
VS27
VS26
VS25
VS24
VS23
VS22
VS21
VS20
−
−
−
−
−
−
VS29
VS28
VS37
VS36
VS35
VS34
VS33
VS32
VS31
VS30
−
−
−
−
−
−
VS39
VS38
VS47
VS46
VS45
VS44
VS43
VS42
VS41
VS40
−
−
−
−
−
−
VS49
VS48
VS57
VS56
VS55
VS54
VS53
VS52
VS51
VS50
−
−
−
−
−
−
VS59
VS58
VS67
VS66
VS65
VS64
VS63
VS62
VS61
VS60
−
−
−
−
−
−
VS69
VS68
VS77
VS76
VS75
VS74
VS73
VS72
VS71
VS70
−
−
−
−
−
−
VS79
VS78
VS87
VS86
VS58
VS84
VS83
VS82
VS81
VS80
−
−
−
−
−
−
VS89
VS88
VS97
VS96
VS95
VS94
VS93
VS92
VS91
VS90
−
−
−
−
−
−
VS99
VS98
VS107
VS106
VS105
VS104
VS103
VS102
VS101
VS100
−
−
−
−
−
−
VS109
VS108
VS117
VS116
VS115
VS114
VS113
VS112
VS111
VS100
−
−
−
−
−
−
VS119
VS118
VS127
VS126
VS125
VS124
VS123
VS122
VS121
VS120
−
−
−
−
−
−
VS129
VS128
00F83
00F84
ORVS2
00F85
00F86
ORVS3
00F87
00F88
ORVS4
00F89
00F8A
ORVS5
00F8B
00F8C
ORVS6
00F8D
00F8E
ORVS7
00F8F
00F90
ORVS8
00F91
00F92
ORVS9
00F93
00F94
ORVS10
00F95
00F96
ORVS11
00F97
00F98
ORVS12
00F99
HS17 to HS10: Code horizontal display base position
setting
W
VS19 to VS10: Code vertical display potision setting
W
VS29 to VS20: Code vertical display potision setting
W
VS39 to VS30: Code vertical display potision setting
W
VS49 to VS40: Code vertical display potision setting
W
VS59 to VS50: Code vertical display potision setting
W
VS69 to VS60: Code vertical display potision setting
W
VS79 to VS70: Code vertical display potision setting
W
VS89 to VS80: Code vertical display potision setting
W
VS99 to VS90: Code vertical display potision setting
W
VS100 to VS109:Code vertical display potision setting
W
VS110 to VS119:Code vertical display potision setting
W
VS120 to VS129:Code vertical display potision setting
W
00F9A
ORCS4
CS4
CS3
CS2
CS1
CSn: Character size (n: 1 to 12)
00F9B
ORCS8
CS8
CS7
CS6
CS5
00: Display off 10: Middle size
00F9C
ORCS12
CS12
CS11
CS10
CS9
01: Large size 11: Small size
00F9D
OREULA8
EULA8
EULA7
EULA6
EULA5
EULA4
EULA3
EULA2
EULA1
00F9E
OREULA12
−
−
−
−
EULA12
EULA11 EULA10
EULA9
00F9F
OREFR8
EFR8
EFR7
EFR6
EFR5
EFR4
EFR3
EFR2
EFR1
00FA0
OREFR12
−
−
−
−
EFR12
EFR11
EFR10
EFR9
88CS34-199
W
EULAn: Underline display setting for line n (n: 0 to 12)
W
EFRn: Fringing setting for line n (n: 0 to 12)
W
2007-09-12
TMP88CS34/CP34
OSD Control Register List (2/3)
Register
Register
Register bit configuration
Address
Name
00FA2
ORSOL4
SOL4
SOL3
SOL2
SOL1
00FA3
ORSOL8
SOL8
SOL7
SOL6
SOL5
00FA4
ORSOL12
00FA5
ORBK
Bit 7
Bit 6
Bit 5
SOL12
−
Bit 4
SOL11
RBDT
GBDT
Bit contents
Bit 3
Bit 2
Bit 1
SOL10
BBDT
−
SOLn: Solid space display setting for line n
(n; 0 to 12)
SOL9
RFDT
R/W
Bit 0
GFDT
BFDT
W
00: No solid space
10: Right
01: Left
11: Left and right
RBDT, GBDT, BBDT: Background color setting
W
ACLR2/ACLG2/ACLB2: Area 2 plane color
00FA6
ORACL
PISEL2
ACLR2
ACLG2
ACLB2
PISEL1
ACLR1
ACLG1
ACLB1
ACLR1/ACLG1/ACLB1: Area 1 plane color
PISEL2: Set half transparency for area 2 plane
W
PISEL1: Set half transparency for area 1 plane
EBKGD: Background function
EXBL: Full-rasterblanking
00FA7
ORRCL
EBKGD
EXBL
AON2
AON1
−
RCLR
RCLG
RCLB
Ｗ
AON2: Area 2 plane display
AON1: Area 1 plane display
RCLR/RCLG/RCLB:Raster plane color
00FA8
ORAHS1
00FA9
00FAA
ORAHE1
00FAB
00FAC
ORAVS1
00FAD
00FAE
ORAVE1
00FAF
00FB0
ORAHS2
00FB1
00FB2
ORAHE2
00FB3
00FB4
ORAVS2
00FB5
00FB6
ORAVE2
00FB7
AHS17
AHS16
AHS15
AHS14
AHS13
AHS12
AHS11
AHS10
AHS1x: Area 1 plane horizonatal start position
−
−
−
−
−
−
−
AHS18
(x: 0 to 8)
AHE17
AHE16
AHE15
AHE14
AHE13
AHE12
AHE11
AHE10
AHE1x: Area 1 plane horizonatal end position
−
−
−
−
−
−
−
AHE18
(x: 0 to 8)
AVS17
AVS16
AVS15
AVS14
AVS13
AVS12
AVS11
AVS10
−
−
−
−
−
−
AVS19
AVS18
AVE17
AVE16
AVE15
AVE14
AVE13
AVE12
AVE11
AVE10
−
−
−
−
−
−
AVE19
AVE18
AHS27
AHS26
AHS25
AHS24
AHS23
AHS22
AHS21
AHS20
AHS2x: Area 2 plane horizonatal start position
−
−
−
−
−
−
−
AHS28
(x: 0 to 8)
AHE27
AHE26
AHE25
AHE24
AHE23
AHE22
AHE21
AHE20
AHE2x: Area 2 plane horizonatal end position
−
−
−
−
−
−
−
AHE28
(x: 0 to 8)
AVS27
AVS26
AVS25
AVS24
AVS23
AVS22
AVS21
AVS20
AVS2x: Area 2 plane vertical start position
−
−
−
−
−
−
AVS29
AVS28
(x: 0 to 8)
AVE27
AVE26
AVE25
AVE24
AVE23
AVE22
AVE21
AVE20
AVE2x: Area 2 plane vertical end position
−
−
−
−
−
−
AVE29
AVE28
(x: 0 to 8)
Ｗ
Ｗ
AVS1x: Area 1 plane vertical start position (x: 0 to 8)
Ｗ
AVE1x: Area 1 plane vertical end position (x: 0 to 8)
Ｗ
Ｗ
Ｗ
Ｗ
Ｗ
VDSMD: Scan mode select
BKMF: Blinking master
00FB8
ORETC
VDSMD
“0”
BKMF
ESMZ
“0”
MFYWR
MBK
RDWRV
ESMZ: Smoothing
MFYWR: Display memory read mode select
W
MBK: Display memory bank switching select
RDWRV: Read/write mode select normal mode
SVD: Interrupt source select
00FB9
ORIRC
−
−
−
SVD
ISDC
00FB9
ORIRC
−
−
−
−
DCTR
W
ISDC: Interrupt generation line select
DCTR:Display line counter
R
P6xS: P6 port output select (x:4 to 7)
00FBA
ORP6S
P67S
P66S
P65S
P64S
PIDS
YBLCS
PIDS: I pin output select
MPXS
W
YBLCS: Y/BL signal select
MPXS: R, G, B, Y/BL signal select
HDPOL: VD input polarity select
HDPOL: HD input polarity select
YBLII: Y/BLIN input polarity select
00FBB
ORIV
VDPOL
HDPOL
YBLII
RGBII
YIV
BLIV
RGBIV
IIV
RGBII: RIN, GIN, BIN input polarity select
Y/V: Y Output polarity select
W
BLIV: BL output polarity select
RGBIV: R, G, B output polarity select
IIV: I pin output polarity select
00FBC
ORWVSH
00FBD
00FBE
ORWVSL
00FBF
00FC2
ORCCD
00FC3
00FC4
00FC5
ORDCSC
WVSH7
WVSH6
WVSH5
WVSH4
WVSH3
WVSH2
WVSH1
WVSH0
−
−
−
−
−
−
WVSH9
WVSH8
WVSL7
WVSL6
WVSL5
WVSL4
WVSL3
WVSL2
WVSL1
WVSL0
−
−
−
−
−
−
WVSL9
WVSL8
CCD8
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
−
−
−
−
CCD12
CCD11
CCD10
CCD9
DCSC8
DCSC7
DCSC6
DCSC5
DCSC4
DCSC3
DCSC2
DCSC1
−
−
−
−
DCSC12
DCSC11
DCSC10 DCSC9
88CS34-200
WVSHx: Window upper limit position (x: 0 to 9)
W
WVSLx: Window lower limit position (x: 0 to 9)
W
CCDx: Horizontal 16 dot and vertical 26 dot display
at small size character (x: 0 to 12)
W
DCSCx: Double height display (x: 0 to 12)
W
2007-09-12
TMP88CS34/CP34
OSD Control Register List (3/3)
Register
Register
Address
Name
Register bit configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit contents
Bit 2
Bit 1
R/W
Bit 0
Color palette composition register 0
CPT1MD1: OSD color select register (x: 1, 2)
00FC6
ORCPT0
CPT0MD1
“0”
CPT0R1
CPT0R0
CPT0G1
CPT0G0 CPT0B1
CPT0B0
00FC7
ORCPT1
−
−
CPT1R1
CPT1R0
CPT1G1
CPT1G0 CPT1B1
CPT1B0 Color palette composition register 1
W
00FC8
ORCPT2
−
−
CPT2R1
CPT2R0
CPT2G1
CPT2G0 CPT2B1
CPT2B0 Color palette composition register 2
W
CPT1MD1 = 0: 27-color select mode
W
CPT1MD1 = 1: 8-color select mode
00FC9
ORCPT3
−
−
CPT3R1
CPT3R0
CPT3G1
CPT3G0 CPT3B1
CPT3B0 Color palette composition register 3
W
00FCA
ORCPT4
−
−
CPT4R1
CPT4R0
CPT4G1
CPT4G0 CPT4B1
CPT4B0 Color palette composition register 4
W
00FCB
ORCPT5
−
−
CPT5R1
CPT5R0
CPT5G1
CPT5G0 CPT5B1
CPT5B0 Color palette composition register 5
W
00FCC
ORCPT6
−
−
CPT6R1
CPT6R0
CPT6G1
CPT6G0 CPT6B1
CPT6B0 Color palette composition register 6
W
00FCD
ORCPT7
−
−
CPT7R1
CPT7R0
CPT7G1
CPT7G0 CPT7B1
CPT7B0 Color palette composition register 7
W
00FCE
ORSTRG
−
−
−
−
−
PALTRG PAL100/NTSC120 start trigger
W
−
−
Note 1: Except the meshed registers are changed by RGWR.
Note 2: Only lower 2 bits of the register in address 00F80H are changed by RGWR (The register in address
00F80H must not be used with any of the read-modify-write instructions as SET, CLR, etc.).
88CS34-201
2007-09-12
TMP88CS34/CP34
2.15 Jitter Elimination Circuit
The TMP88CS34/CP34 has a built-in jitter elimination circuit which maintains the vertical
stability of the OSD even when input of the vertical signal fluctuates.
And the field decision information for the OSD circuit is detected by using jitter elimination
circuit.
2.15.1
Configuration
Jitter removal status register
Phase detect signal PDF [2:0]
JRMSR
Field decision
circuit
HD (P70)
Previous field
decision signal
A Y
B
S
VD (P71)
HD / VD
Edge detect circuit
Internal VD signal
output control
circuit
Delay value
setting circuit
A
B
Y
VD
(To OSD circuit)
VDSEL
VD signal delay value
measuring circuit
fc/2
AFLD
JEEN
JECR
Jitter elimination control register
Figure 2.15.1 Jitter Elimination Circuit
88CS34-202
2007-09-12
TMP88CS34/CP34
2.15.2 Control
Jitter elimination circuit is controlled by the jitter elimination control register (JECR).
Jitter elimination control register
JECR
7
6
5
4
3
2
1
0
(00FE4H)
−
−
−
VDSEL
AFLD
JEEN
“0”
“0”
VDSEL
0:
1:
0:
1:
0:
1:
VD select
AFLD
Automatic field decision
JEEN
Jitter elimination enable specification
VD from P71
VD from jitter elimination circuit
Automatic field decision disabled
Automatic field decision enabled
Jitter elimination disabled
Jitter elimination enabled
Note 1:
Clear the AFLD to “0” to disable jitter elimination circuit.
Note 2:
Always clear “0” to bit 1 and 0 of JECR.
Note 3:
(Initial value: ***0 0000)
Write
only
Clear “0” to AFLD and VDSEL if there is no phase shift in the vertical and horizontal sync. signals every
other time, such as with non-interlaced TV.
Note 4:
*: Don’t care
Note 5:
Setting JEEN to “0”, OSD display is only 2nd field.
Note 6:
Setting AFLD to “0”, OSD display is only 2nd field.
Jitter elimination status register
JESR
(00FE5H)
7
6
5
4
3
2
1
0
FDSF
PDF1
PDF0
−
−
−
−
PDF2
(Initial value: 0*** ****)
0:
FDSF
Field detect status flag
PDF2, 1, 0 Phase detect flag between HD and VD
A position of a scanning line exists in the field
which has a second display dot of character on
an interlace TV screen.
1: A position of a scanning line exists in the field
which has a first display dot of character on an
interlace TV screen.
Read
000: Phase 0
only
001: Phase 1
010: Phase 2
011: Phase 3
100: Phase 4
101: Phase 5
110: Phase 6
111: Phase 7
Note 1:
FDSF is different from the 1st and the 2nd field. It is a unique field decided for OSD display.
Note 2:
*: Don’t care
Note 3:
HD
VD
Phase 7
Phase 0
Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
Phase 7
Phase 0
Figure 2.15.2 Jitter Elimination Control Register and Jitter Elimination Status Register
2.15.3 Jitter Elimination Mode
The jitter elimination circuit is to identify the phase of the falling edges of the external
VD signal and HD signal. When VD signal is falling within HD signal falling +/−1/4HD,
the jitter is automatically eliminated and internal VD signal is set to the stable location.
This function is enabled by setting JEEN (bit2 in JECR) in the jitter elimination control
register to “1”.
88CS34-203
2007-09-12
TMP88CS34/CP34
2.15.4 Auto Field Line Decision
The internal vertical and horizontal sync. signals corrected by the jitter elimination
circuit generate the field line decision signals used in the OSD.
The OSD display in normal mode
Type A)
When the OSD circuit is used on the TV system which has a phase shift in the
vertical and horizontal sync. Signals every other filed such as the interlace
TV, enable jitter elimination circuit and set “1” to AFLD and VDSEL. At this
time, the field lines which have first and second display dot of character are
displayed.
Type B)
When the OSD circuit is used on the TV system which has no phase shift in
the vertical and horizontal sync. Signals every other filed such as the
non-interlace TV, enable jitter elimination circuit and clear “0” to AFLD and
VDSEL. At this time, the field line which has a second display dot of
character is only displayed.
The OSD display in double scan mode
Type C)
Disable jitter elimination circuit and clear “0” to AFLD and VDSEL. At this
time, the field lines which have first and second display dot of character are
displayed.
(2) The field line which has a
second display dot of
character
(1) The field line which has a
first display dot of character
Scanning system
Register
Display
Type A
VDSEL = 1, AFLD = 1
(1) and (2)
Type B
VDSEL = 0, AFLD = 0
(2)
Type C
VDSEL = 0, AFLD = 0
(1) and (2)
Figure 2.15.3 Relation with Field Line and VDSEL, AFLD
88CS34-204
2007-09-12
TMP88CS34/CP34
Input/Output Circuit
(1) Control pins
The input/output circuitries of the TMP88CS34/CP34 control pins are shown below.
Control Pin
I/O
Input/Output Circuitry
Remarks
Osc. enable
XIN
XOUT
I/O
fc
VDD
Rf
XIN
VDD
RO
XOUT
RIN
R
I/O
Address-trap-reset
Watchdog-timer-reset
System-clock-reset
(P20)
Sink open drain output
Hysteresis input
Pull-up register
RIN = 220 MΩ (typ.)
R = 1 kΩ (typ.)
Hysteresis input
VDD
STOP / INT5
Rf = 1.2 MΩ (typ.)
RO = 0.5 kΩ (typ.)
VDD
RESET
Resonator connecting pins
(high-frequency)
R = 1 kΩ (typ.)
Input
R
P20/ STOP / INT5
Pull-down register
VDD
RIN = 70 kΩ (typ.)
R
TEST
R = 1 kΩ (typ.)
Input
RIN
Osc. enable
OSC1
OSC2
fc
VDD
Rf
I/O
OSC1
RO
VDD
Pin for connecting a resonator
for on-screen display
Rf = 1.2 MΩ (typ.)
RO = 0.5 kΩ (typ.)
OSC2
88CS34-205
2007-09-12
TMP88CS34/CP34
(2) Input/Output ports
Port
I/O
Input/Output Circuitry
VDD
Initial “High-Z”
P20
Remarks
Sink open drain output
Hysteresis input
R = 1 kΩ (typ.)
I/O
R
P30
to
P33
P50,
P57
Tri-state I/O
Hysteresis input
VDD
Initial “High-Z”
R = 1 kΩ (typ.)
I/O
R
Disable
P70,
P71
P34,
P35,
P51,
P52
Tri-state I/O or Open drain
output programmable
Hysteresis input
VDD
Initial “High-Z”
Open drain
output enable
I/O
R
Disable
Tri-state I/O
VDD
Initial “High-Z”
R = 1 kΩ (typ.)
P40
to
I/O
R
Disable
P47
P53
I/O
Tri-state I/O
Hysteresis input
Key-on wake-up input
(VIL4 = 0.65 × VDD)
VDD
Initial “High-Z”
to
R = 1 kΩ (typ.)
R
Disable
R = 1 kΩ (typ.)
RA = 5 kΩ (typ.)
P56
CA = 22 pF (typ.)
CA
RA
Key-on
Wake-up
88CS34-206
2007-09-12
TMP88CS34/CP34
Port
I/O
Input/Output Circuitry
Remarks
Sink open drain input/output
High-current output
IOL = 20 mA (typ.)
VDD
Initial “High-Z”
P60
I/O
R = 1 kΩ (typ.)
R
Disable
RA = 5 kΩ (typ.)
CA = 22 pF (typ.)
CA
RA
Key-on
Wake-up
Key-on wake-up input
(VIL4 = 0.65 × VDD)
Tri-state input/output
VDD
Initial “High-Z”
R = 1 kΩ (typ.)
RA = 5 kΩ (typ.)
P61
I/O
R
Disable
CA
Initial “High-Z”
Key-on wake-up input
(VIL4 = 0.65 × VDD)
RA
Key-on
Wake-up
VDD
Tri-state input/output
R = 1 kΩ (typ.)
P62
to
P67
CA = 22 pF (typ.)
I/O
R
Disable
88CS34-207
2007-09-12
TMP88CS34/CP34
Electrical Characteristics
Absolute maximum ratings
Parameter
(VSS = 0 V)
Symbol
Pins
Supply Voltage
VDD
−
−0.3 to 6.5
Input Voltage
VIN
−
−0.3 to VDD + 0.3
Output Voltage
VOUT1
−
−0.3 to VDD + 0.3
Output Current (Per 1 pin)
Output Current (Total)
Ratings
IOUT1
Ports P2, P3, P4, P5, P61 to P67, P7
IOUT2
Ports P60
30
Σ IOUT1
Ports P2, P3, P4, P5, P64 to P67, P7
30
Σ IOUT2
Ports P60
30
Unit
V
3.2
mA
400
Power Dissipation [Topr = 70 °C]
PD
−
Soldering Temperature (time)
Tsld
−
Storage Temperature
Tstg
−
−55 to 125
Operating Temperature
Topr
−
−30 to 70
mW
260 (10 s)
°C
Note: The absolute maximum ratings are rated values which must not be exceeded during operation,
even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is
exceeded, a device may break down or its performance may be degraded, causing it to catch fire or
explode resulting in injury to the user. Thus, when designing products which include this device,
ensure that no absolute maximum rating value will ever be exceeded.
Recommended operating conditions
Parameter
Symbol
(VSS = 0 V, Topr = −30 to 70 °C)
Pins
Conditions
Min
Max
4.5
5.5
Unit
fc = 16 MHz NORMAL mode
Supply Voltage
fc = 16 MHz IDLE mode
VDD
STOP mode
Input High Voltage
Input Low Voltage
Clock Frequency
VIH1
Except hysteresis input
VIH2
Hysteresis input
VDD × 0.70
VDD = 4.5 to 5.5V
VDD × 0.75
VDD
V
VDD × 0.90
VIH3
Key-on Wake-up input
VIL1
Except hysteresis input
VIL2
Hysteresis input
VIL3
Key-on Wake-up input
VDD = 4.5 to 5.5V
fc
XIN, XOUT
VDD = 4.5 to 5.5V
fOSC
Internal clock
VDD = 4.5 to 5.5V
VDD × 0.30
VDD = 4.5 to 5.5V
0
VDD × 0.25
VDD × 0.65
8.0
16.0
fc = 8 MHz
8.0
12.0
fc = 16 MHz
16.0
24.0
MHz
Note 1: The recommended operating conditions for a device are operating conditions under which it can be
guaranteed that the device will operate as specified. If the device is used under operating conditions
other than the recommended operating conditions (supply voltage, operating temperature range,
specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include
this device, ensure that the recommended operating conditions for the device are always adhered
to.
Note 2: Clock frequency fc: Supply voltage range is specified in NORMAL mode and IDLE mode.
Note 3: Smaller value is alternatively specified as the maximum value.
88CS34-208
2007-09-12
TMP88CS34/CP34
DC Characteristics
Parameter
(VSS = 0 V, Topr = −30 to 70 °C)
Symbol
Hysteresis voltage
Input current
Pins
Conditions
Typ.
Max
Unit
−
0.9
−
V
VHS
Hysteresis inputs
IIN1
TEST
VDD = 5.5 V, VIN = 5.5 V/0 V
−
−
±2
IIN2
Open drain ports
VDD = 5.5 V, VIN = 5.5 V/0 V
−
−
±2
IIN3
Tri-state ports
VDD = 5.5 V, VIN = 5.5 V/0 V
−
−
±2
IIN4
RESET , STOP
VDD = 5.5 V, VIN = 5.5 V/0 V
Input resistance
RIN2
RESET
VDD = 5.5 V, VIN = 0 V
Output leakage
current
ILO1
Sink open drain ports
ILO2
Output high voltage
VOH2
Output low voltage
Output low current
−
−
±2
100
220
450
VDD = 5.5 V, VOUT = 5.5 V
−
−
2
Tri-state ports
VDD = 5.5 V, VOUT = 5.5 V/0 V
−
−
±2
Tri-state ports
VDD = 4.5 V, IOH = −0.7 mA
4.1
−
−
VOL
Except XOUT and
ports P60
VDD = 4.5 V, IOL = 1.6 mA
−
−
0.4
IOL3
Port P60
VDD = 4.5 V, IOL = 1.0 V
−
20
−
VDD = 5.5 V
fc = 16 MHz
VIN = 5.3 V/0.2 V
−
25
30
−
20
25
−
0.5
10
Supply current in
NORMAL mode
Supply current in
IDLE mode
Min
−
IDD
(Note3)
VDD = 5.5 V
VIN = 5.3 V/0.2 V
Supply current in
STOP mode
μA
kΩ
μA
V
mA
μA
Note 1: Typical values show those at Topr = 25 °C, VDD = 5 V.
Note 2: Input Current IIN3; The current through resistor is not included.
Note 3: Supply Current IDD; The current (Typ. 0.5 mA) through ladder resistors of ADC is included in
NORMAL mode and IDLE mode.
AD Conversion Characteristics
Parameter
Analog reference voltage
Analog reference voltage range
Analog input voltage
Symbol
(VSS = 0 V, VDD = 4.5 V to 5.5 V, Topr = −30 to 70 °C)
Conditions
Full scale error
Typ.
Max
VAREF
supplied from VDD pin.
−
VDD
−
VASS
supplied from VSS pin.
−
0
−
= VDD − VSS
−
VDD
−
VSS
−
VDD
−
−
±1
−
−
±2
−
−
±2
−
−
±3
ΔVAREF
VAIN
Nonlinearity error
Zero point error
Min
VDD = 5.0 V
Total error
Unit
V
LSB
Note: The total error means all error except quanting error.
88CS34-209
2007-09-12
TMP88CS34/CP34
AC characteristics
Parameter
(VSS = 0 V, VDD = 4.5 V to 5.5 V, Topr = −30 to 70 °C)
Symbol
Machine cycle time
tcy
Conditions
In NORMAL mode
tWCH
For external clock operation
Low level clock pulse width
tWCL
(XIN input), fc = 16 MHz
Recommended oscillating conditions
High-frequency
oscillation
Oscillator
Typ.
Max
Unit
0.5
−
1.0
μs
31.25
−
−
ns
In IDLE mode
High level clock pulse width
Parameter
Min
(VSS = 0 V, VDD = 4.5 V to 5.5 V, Topr = −30 to 70 °C)
Oscillation
Frequency
Ceramic resonator
Recommended Oscillator
Recommended Constant
C1
C2
8 MHz
Murata
CSA 8.00MTZ
30 pF
30 pF
16 MHz
Murata
CSA 16.00MXZ040
5 pF
5 pF
XIN
XOUT
C1
C2
High-frequency Oscillation
Note 1: To keep reliable operation, shield the device electrically with the metal plate on its package mold
surface against the high electric field, for example, by CRT (Cathode Ray Tube) .
Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are
subject to change. For up-to-date information, please refer to the following URL;
http://www.murata.co.jp/search/index.html
88CS34-210
2007-09-12
TMP88CS34/CP34
Recommended oscillating conditions
Item
(VSS = 0 V, VDD = 4.5 V to 5.5 V, Topr = −30 to 70 °C)
Oscillation
Resonator
Oscillation for OSD
Recommended parameter value
Frequency
LC resonator
L (μH)
C1 (pF)
C2 (pF)
8 MHz
33
5 to 30
10
12 MHz
15
5 to 30
10
16 MHz
10
5 to 30
10
20 MHz
6.8
5 to 25
10
24 MHz
4.7
5 to 25
10
OSC1
OSC2
L
C2
C1
Oscillation for OSD
The frequency generated in LC oscillation can be obtained using the following equations.
f =
1
C ･C
,C = 1 2
2π LC
C1 + C2
C1 is not fixed at a constant value. It can be changed to tune into the desired frequency.
Note 1: Toshiba’s OSD circuit determines a horizontal display start position by counting clock pulses
generated in LC oscillation. For this reason, the OSD circuit may fail to detect clock pulses normally,
resulting in the horizontal start position becoming unstable, at the beginning of oscillation, if the
oscillation amplitude is low.
Changing L and C2 from the values recommended for a specific frequency may hamper a stable
OSD display.
If the LC oscillation frequency is the same as a high-frequency clock value, the oscillation of the
high-frequency oscillator may cause the LC oscillation frequency to fluctuate, thus making OSD
displays flicker.
When determining these parameters, please check the oscillation frequency and the stability of
oscillation on your TV sets.
Also check the determined parameters on your final products, because the optimum parameter
values may vary from one product to another.
Note 2: When using the LSI package in a strong electric field, such as near a CRT, electrically shield the
package so that its normal operation can be maintained.
88CS34-211
2007-09-12
TMP88CS34/CP34
Notice of ROM Entry
When you make a ROM data entry for TMP88CS34/CP34,
Please transfer one file including program area, vector table area and OSD font area.
The ROM area must be transferred is as follows.
4000H
TMP88CS34
4000H
TMP88CP34
Program area
Program area
FEFFH
13EFFH
20000H
20000H
OSD font area
2A7FFH
2A7FFH
FFF00H
FFFFFH
OSD font area
FFF00H
Vector table
area
FFFFFH
Vector table
area
Flow of ROM data entry
After evaluation finished
Program and vector table
Program
vector table
OSD font
OSD font
Two files are merged into one file.
ROM data entry
88CS34-212
2007-09-12
TMP88CS34/CP34
Package
P-SDIP42-600-1.78
Unit: mm
88CS34-213
2007-09-12
TMP88CS34/CP34
P-QFP44-1414-0.80D
Unit: mm
88CS34-214
2007-09-12
TMP88CS34/CP34
88CS34-215
2007-09-12