TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93CW46A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93CW46A Low Voltage/Low Power CMOS 16-Bit Microcontroller TMP93CW46AF 1. Outline and Device Characteristics The TMP93CW46AF is high-speed advanced 16-bit microcontroller to enable low voltage and low power consumption operation. The TMP93CW46AF is housed in 100-pin mini flat package. The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) • TLCS-90 instruction mnemonic upward compatible • 16-Mbyte linear address space • General-purpose registers and register bank system • 16-bit multiplication/division and bit transfer/arithmetic instructions • Micro DMA: 4 channels (1.6 µs/2 bytes at 20 MHz) (2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal RAM: 4 Kbytes Internal ROM: 128 Kbytes (4) External memory expansion • Can be expanded up to 16 Mbytes (for both programs and data). • Can mix 8- and 16-bit external data buses. …Dynamic data bus sizing (5) 8-bit timer: 2 channels (6) 8-bit PWM timer: 2 channels (7) 16-bit timer: 2 channels (8) Serial interface: 5 channels • UART/synchronous modes: 4 channels • UART mode: 1 channel (9) 10-bit AD converter: 8 channels 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 93CW46A-1 2004-02-10 TMP93CW46A (10) Watchdog timer (11) Chip select/wait controller: 3 blocks (12) Interrupt functions: 35 • 9 CPU interrupts … SWI instruction, and Illegal instruction • 20 internal interrupts • 6 external interrupts 7-level priority can be set. (13) I/O ports: 79 • Large current output: 6 pins, LED direct drive (14) Standby function 4 HALT modes (RUN, IDLE2, IDLE1, STOP) (15) Clock gear function • High-frequency clock can be changed fc to fc/16. • Dual clock operation (16) Operating voltage • VCC = 2.7 to 5.5 V (17) Package: P-LQFP100-1414-0.50F Note: Note that TMP93CW46A is different from OTP type TMP93PW46A in the electrical characteristics as follows. See the respective electrical characteristics for details. • Power supply current ICC • Large current port IOLA 93CW46A-2 2004-02-10 TMP93CW46A PA0 to PA6 PA7 (SCOUT) Port A VCC [3] VSS [3] CPU P50 to P57 (AN0 to AN7) AVCC AVSS VREFH VREFL (TXD0) P90 (RXD0) P91 (SCLK0/ CTS0 ) P92 (TXD1) P93 (RXD1) P94 (SCLK1) P95 (TXD2) P60 (RXD2) P61 (SCLK2/ CTS2 ) P62 (TXD3) P63 (RXD3) P64 (SCLK3/ CTS3 ) P65 (TXD4) P66 (RXD4) P67 (TI0) P70 (TO1) P71 (TO2) P72 (TO3) P73 10-bit 8-ch AD converter Serial I/O (Channel 0) XWA XBC XDE XHL XIX XIY XIZ XSP W A B C D E H L IX IY IZ SP 32 bits SR Highfrequency OSC CLK Lowfrequency OSC RESET ALE TEST2, TEST1 P C Serial I/O (Channel 1) Serial I/O (Channel 3) Serial I/O (Channel 4) Interrupt controller P87 (INT0) Watchdog timer WDTOUT 4-Kbyte RAM 8-bit timer (Timer 0) 8-bit timer (Timer 1) NMI Port 0 P00 to P07 (AD0 to AD7) Port 1 P10 to P17 (AD8 to AD15/ A8 to A15) Port 2 P20 to P27 (A0 to A7/A16 to A23) P30 ( RD ) 8-bit PWM (Timer 2) 8-bit PWM (Timer 3) XT1 XT2 AM8/ AM16 EA F Serial I/O (Channel 2) X1 X2 P31 ( WR ) P32 ( HWR ) Port 3 128-Kbyte ROM P33 ( WAIT ) P34 ( BUSRQ ) P35 ( BUSAK ) (INT4/TI4) P80 (INT5/TI5) P81 (TO4) P82 (TO5) P83 16-bit timer (Timer 4) (INT6/TI6) P84 (INT7/TI7) P85 (TO6) P86 16-bit timer (Timer 5) P36 (R/ W ) P37 ( RAS ) CS/WAIT controller (3 blocks) P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) P42 ( CS2 / CAS2 ) Figure 1.1 TMP93CW46A Block Diagram 93CW46A-3 2004-02-10 TMP93CW46A 2. Pin Assignment and Functions The assignment of input/output pins for the TMP93CW46AF, their names and outline functions are described below. ○ ○ Timer ADC Clock, Mode SIO ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ TMP93CW46A Pin no. Pin no. TMP93CW46A ○ ○ ○ ○ ○ ○ 88 P65/ CTS3 /SCLK3 P66/TXD4 89 P67/RXD4 90 VSS 91 P50/AN0 92 P51/AN1 93 P52/AN2 94 P53/AN3 95 81 P41/ CS1 / CAS1 P54/AN4 96 80 P40/ CS 0 / CAS 0 P55/AN5 97 79 P37/ RAS P56/AN6 98 78 P36/ R / W P57/AN7 99 77 P35/ BUSAK VREFH 100 76 P34/ BUSRQ VREFL AVSS AVCC 1 2 3 75 P33/ WAIT NMI 4 P70/TI0 5 P71/TO1 P72/TO2 6 7 P73/TO3 P80/INT4/TI4 P81/INT5/TI5 8 9 10 P82/TO4 P83/TO5 11 12 P84/INT6/TI6 P85/INT7/TI7 13 14 72 71 70 69 68 67 66 65 64 63 62 P86/TO6 P87/INT0 15 16 P90/TXD0 P91/RXD0 17 18 87 P64/RXD3 86 P63/TXD3 85 P62/ CTS2 /SCLK2 84 P61/RXD2 83 P60/TXD2 82 P42/ CS2 / CAS2 ○ ○ ○ ○ ○ ○ ○ ○ 73 P31/ WR Top view LQFP100 P30/ RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 P21/A1/A17 P20/A0/A16 VCC VSS SIO ○ 74 P32/ HWR ○ ○ ○ ○ ○ ○ ○ ○ 61 WDTOUT P95/SCLK1 22 AM8/ AM16 23 CLK VCC 24 25 60 59 58 57 56 55 54 53 52 51 VSS 26 50 P05/AD5 X1 27 49 P04/AD4 X2 28 48 P03/AD3 EA 29 47 P02/AD2 RESET 30 46 P01/AD1 P96/XT1 31 45 P00/AD0 P97/XT2 32 44 VCC TEST1 33 43 ALE TEST2 34 42 PA7/SCOUT PA0 35 41 PA6 PA1 36 40 PA5 PA2 37 39 PA4 P92/ CTS 0 /SCLK0 19 P93/TXD1 P94/RXD1 Programmable Pull Pull down up Memory interface Programmable Pull Pull up down 20 21 P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 P06/AD6 38 PA3 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of the TMP93CW46AF. Figure 2.1.1 Pin Assignment (100-Pin LQFP) 93CW46A-4 2004-02-10 TMP93CW46A 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 to Table 2.2.4 show pin names and functions. Table 2.2.1 Pin Names and Functions (1/4) Pin Names Number of Pins I/O Functions P00 to P07 AD0 to AD7 8 I/O 3 states Port 0: I/O port that allows selection of I/O on a bit basis Address/Data (Lower): Bits 0 to 7 of address/data bus P10 to P17 AD8 to AD15 A8 to A15 8 I/O 3 states Output Port 1: I/O port that allows selection of I/O on a bit basis Address data (Upper): Bits 8 to 15 of address/data bus Address: 8 to 15 of address bus P20 to P27 8 I/O Output Output Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor) Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus 1 Output Output Port 30: Output port Read: Strobe signal for reading external memory 1 Output Output Port 31: Output port Write: Strobe signal for writing data on pins AD0 to AD7 1 I/O Output Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to AD15 1 I/O Input Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait 1 I/O Input Port34: I/O port (with pull-up resistor) Bus request: Signal used to request high impedance for AD0 to AD15, A0 to A23, RD , WR , HWR , R/ W , RAS , CS0 , CS1 , and CS2 pins. 1 I/O Output Port 35: I/O port (with pull-up resistor) Bus acknowledge: Signal indicating that AD0 to AD15, A0 to A23, RD , WR , HWR , R/ W , RAS , CS0 , CS1 , and CS2 pins are at high impedance after receiving BUSRQ. P36 R/ W 1 I/O Output Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents read or dummy cycle. 0 represents write cycle. P37 1 I/O Output Port 37: I/O port (with pull-up resistor) Row address strobe: Outputs RAS strobe for DRAM. 1 I/O Output Output Port 40: I/O port (with pull-up resistor) Chip select 0: Outputs 0 when address is within specified address area. Column address strobe 0: Outputs CAS strobe for DRAM when address is within A0 to A7 A16 to A23 P30 RD P31 WR P32 HWR P33 WAIT P34 BUSRQ (For external DMAC) P35 BUSAK (For external DMAC) RAS P40 CS0 CAS0 specified address area. Note: This device’s built-in memory or built-in I/O cannot be accessed with the external DMA controller, using the BUSRQ and BUSAK signals. 93CW46A-5 2004-02-10 TMP93CW46A Table 2.2.2 Pin Names and Functions (2/4) Pin Names P41 Number of Pins I/O Functions 1 I/O Output Output Port 41: I/O port (with pull-up resistor) Chip select 1: Outputs 0 if address is within specified address area. Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified 1 I/O Output Output Port 42: I/O port (with pull-down resistor) Chip select 2: Outputs 0 if address is within specified address area. Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified P50 to P57 AN0 to AN7 8 Input Input Port 5: Input port Analog input: Analog signal input for AD converter VREFH 1 Input Pin for high level reference voltage input to AD converter VREFL 1 Input P60 TXD2 1 I/O Output Port 60: I/O port (with pull-up resistor) Serial send data 2 P61 RXD2 1 I/O Input Port 61: I/O port (with pull-up resistor) Serial receive data 2 P62 1 I/O Input I/O Port 62: I/O port (with pull-up resistor) Serial data send enable 2 (Clear to send) Serial Clock I/O 2 P63 TXD3 1 I/O Output Port 63: I/O port (with pull-up resistor) Serial receive data 3 P64 RXD3 1 I/O Input Port 64: I/O port (with pull-up resistor) Serial receive data 3 P65 1 I/O Input I/O Port 65: I/O port (with pull-up resistor) Serial data send enable 3 (Clear to send) Serial Clock I/O 3 P66 TXD4 1 I/O Output Port 66: I/O port (with pull-up resistor) Serial send data 4 P67 RXD4 1 I/O Input Port 67: I/O port (with pull-up resistor) Serial receive data 4 P70 TI0 1 I/O Input Port 70: I/O port (with pull-up resistor) Timer input 0: Timer 0 input P71 TO1 1 I/O Output Port 71: I/O port (with pull-up resistor) Timer output 1: Timer 0 or 1 output P72 TO2 1 I/O Output Port 72: I/O port (with pull-up resistor) PWM output 2: 8-bit PWM timer 2 output P73 TO3 1 I/O Output Port 73: I/O port (with pull-up resistor) PWM output 3: 8-bit PWM timer 3 output CS1 CAS1 address area. P42 CS2 CAS2 address area. CTS2 SCLK2 CTS3 SCLK3 Pin for low level reference voltage input to AD converter 93CW46A-6 2004-02-10 TMP93CW46A Table 2.2.3 Pin Names and Functions (3/4) Pin Names Number of Pins I/O Functions P80 TI4 INT4 1 I/O Input Input Port 80: I/O port (with pull-up resistor) Timer input 4: Timer 4 count/capture trigger signal input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge P81 TI5 INT5 1 I/O Input Input Port 81: I/O port (with pull-up resistor) Timer input 5: Timer 4 count/capture trigger signal input Interrupt request pin 5: Interrupt request pin with rising edge P82 TO4 1 I/O Output Port 82: I/O port (with pull-up resistor) Timer output 4: Timer 4 output pin P83 TO5 1 I/O Output Port 83: I/O port (with pull-up resistor) Timer output 5: Timer 4 output pin P84 TI6 INT6 1 I/O Input Input Port 84: I/O port (with pull-up resistor) Timer input 6: Timer 5 count/capture trigger signal input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge P85 TI7 INT7 1 I/O Input Input Port 85: I/O port (with pull-up resistor) Timer input 7: Timer 5 count/capture trigger signal input Interrupt request pin 7: Interrupt request pin with rising edge P86 TO6 1 I/O Output P87 INT0 1 I/O Input P90 TXD0 1 I/O Output Port 90: I/O port (with pull-up resistor) Serial send data 0 P91 RXD0 1 I/O Input Port 91: I/O port (with pull-up resistor) Serial receive data 0 P92 1 I/O Input I/O Port 92: I/O port (with pull-up resistor) Serial data send enable 0 (Clear to send) Serial Clock I/O 0 P93 TXD1 1 I/O Output Port 93: I/O port (with pull-up resistor) Serial send data 1 P94 RXD1 1 I/O Input Port 94: I/O port (with pull-up resistor) Serial receive data 1 P95 SCLK1 1 I/O I/O Port 95: I/O port (with pull-up resistor) Serial clock I/O 1 PA0 to PA5 6 I/O Port A0 to A5: I/O ports (large current output) PA6 1 I/O Port A6: I/O port CTS0 SCLK0 Port 86: I/O port (with pull-up resistor) Timer output 6: Timer 5 output pin Port 87: I/O port (with pull-up resistor) Interrupt request pin 0: Interrupt request pin with programmable level/rising edge 93CW46A-7 2004-02-10 TMP93CW46A Table 2.2.4 Pin Names and Functions (4/4) Pin Names Number of Pins I/O Functions PA7 SCOUT 1 I/O Output Port A7: I/O port System clock output: Outputs system clock or 2 times oscillation clock for synchronizing to external circuit. Watchdog timer output pin WDTOUT 1 Output NMI 1 Input CLK 1 Output Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at rising edge by program. Clock output: Outputs “System clock ÷ 2” clock. Pulled-up during reset. Can be disabled for reducing noise. EA 1 Input Fixed to “1”. AM8/ AM16 1 Input Fixed to “1”. ALE 1 Output RESET 1 Input X1/X2 2 I/O High-frequency oscillator connecting pin XT1 P96 1 Input I/O Low-frequency oscillator connecting pin Port 96: I/O port (Open-drain output) XT2 P97 1 Output I/O Low-frequency oscillator connecting pin Port 97: I/O port (Open-drain output) TEST1/TEST2 2 Output/Input VCC 3 Address latch enable (Can be disabled for reducing noise.) Reset: Initializes LSI (with pull-up resistor). TEST1 should be connected with TEST2 pin. Do not connect to any other pins. Power supply pin (All VCC pins are connected to the power supply source.) VSS 3 GND pin (All VSS pins are connected to the GND (0 V).) AVCC 1 Power supply pin for AD converter AVSS 1 GND pin for AD converter (0 V) Note: Built-in pull-up/pull-down resistors can be released from the pins other than the RESET pin by software. 93CW46A-8 2004-02-10 TMP93CW46A 3. Operation This section describes the functions and basic operational blocks of the TMP93CW46A devices. See the 7. “Points of Note and Restrictions” for the using notice and restrictions for each block. 3.1 CPU The TMP93CW46A device has a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous chapter.) This section describes CPU functions unique to the TMP93CW46A that are not described in the previous chapter. 3.1.1 Reset When resetting the TMP93CW46A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (16 µs at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 × 1/2). When reset is accepted, the CPU sets as follows: • Program counter (PC) according to reset vector that is stored 8000H to 8002H. PC<7:0> ← Data located at 8000H PC<15:8> ← Data located at 8001H PC<23:16> ← Data located at 8002H Note: The address in which the reset vector is stored depends on the respective derivative products. Stack pointer (XSP) for system mode to 100H. • • Status register <IFF2:0> to 111. (Sets mask register to interrupt level 7.) • Status register <MAX> to 1. (Sets to maximum mode.) • Status register <REP2:0> to 000. (Sets register banks to 0.) When reset is released, instruction execution starts from PC (Reset vector). CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins are as follows. • Initializes built-in I/O registers as per specifications. • Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode. • Sets WDTOUT pin to “0”. (Resetting enables the watchdog timer.) • Pulls up the CLK pin to 1. • Sets the ALE pin to high impedance (High-Z). Note 1: By resetting, register in the CPU except program counter (PC), status register (SR) and stack pointer (XSP) and the data in internal RAM are not changed. Note 2: The CLK pin is pulled up during reset. When the voltage is put down externally, there is possible to cause malfunctions. Figure 3.1.1 shows the reset timing chart of TMP93CW46A. 93CW46A-9 2004-02-10 Address Data output 93CW46A-10 P96 to P97 (Output mode: open drain output) (Input mode) (Input mode) P50 to P57, A0 to A7 (Input mode) P20 to P27, P42 (P42 input mode) P32 to P37, P40 to P41 P60 to P67, P70 to P73 P80 to P87, P90 to P95 CAS2 (P40 to P41 input mode) (P37 input mode) RAS CAS0 to CAS1 (P32 input mode) Internal pull up or pull down High impedance Address HWR WR AD0 to AD15 RD AD0 to AD15 Address (P36 input mode) R/W ALE (P42 input mode) CS2 Address (P40 to P41 input mode) CS0 to CS1 Sampling (P20 to P27 input mode) Sampling A16 to A23 RESET CLK X1 Omitted 45 times of X1 (Starts read cycle of 0 waits after reset release) Omitted 220 times of X1 Write Read TMP93CW46A Figure 3.1.1 TMP93CW46A Reset Timing Chart 2004-02-10 TMP93CW46A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP93CW46A. 000000H 000080H Internal I/O (128 bytes) 256-byte direct area (n) 000100H Internal RAM (4 Kbytes) 001080H 64-Kbyte area (nn) External memory 008000H 008100H Interrupt vector table area (64 entries × 4 bytes) 010000H 128-Kbyte internal ROM 028000H 16-MByte area (R) (−R) (R +) (R + R8/16) (R + d8/16) (nnn) External memory FFFF00H FFFFFFH Reserved (256 bytes) ( Note: = Internal area) The 256-byte area from FFFF00H to FFFFFFH can not be used. Figure 3.2.1 Memory Map 93CW46A-11 2004-02-10 TMP93CW46A 3.3 Standby Function Standby control circuits consist of (1) System clock controller, (2) Prescaler clock controller, and (3) Standby controller. The Oscillator operating mode is classified to (a) Single clock mode (Only X1, X2 pin), and (b) Dual clock mode (X1, X2, XT1, XT2 pin). Figure 3.3.1 shows a transition figure. Figure 3.3.2 shows the block diagram. Reset RUN mode (Stops only CPU) Instruction Instruction IDLE2 mode (Stops CPU and AD) Release reset Interrupt NORMAL mode (fc/gear_value/2) Interrupt Instruction Interrupt STOP mode (Stops all circuits) Instruction Interrupt IDLE1 mode (Operates only oscillator) (a) Signal Clock Mode Transition Figure Reset RUN mode (Stops only CPU) Instruction Instruction IDLE2 mode (Stops CPU and AD) Release reset Interrupt NORMAL mode (fc/gear_value/2) Interrupt Instruction Instruction IDLE1 mode (Operates only oscillator) Interrupt Interrupt Instruction RUN mode (Stops only CPU) Instruction Instruction Interrupt Instruction IDLE2 mode (Stops CPU and AD) Interrupt STOP mode (Stops all circuits) SLOW mode (fs/2) Instruction IDLE1 mode (Operates only oscillator) Interrupt (b) Dual Clock Mode Transition Figure Figure 3.3.1 Transition Figure The clock frequency input from X1, X2 pin is called fc, and the clock frequency selected by SYSCR1<SYSCK>, <GEAR2:0> is called system clock fFPH. The devided clock of fFPH is called system clock fSYS, and the 1 cycle of fSYS is called 1 state. 93CW46A-12 2004-02-10 TMP93CW46A Table 3.3.1 Internal Operation and System Clock Operating Mode Oscillator High Frequency (fc) Low Frequency (fs) Single clock RESET NORMAL RUN Oscillation Dual clock RUN IDLE2 IDLE1 STOP Reset Reset fc/32 Operate Programmable (fc/2, fc/4, fc/8, fc/16, fc/32) Stop Stop only AD Stop Stop RESET SLOW System Clock fSYS Stop IDLE1 NORMAL Internal I/O Operate IDLE2 STOP CPU Stop Oscillation Programmable Programmable Reset Stop Operate Stop only AD Stop Stop 93CW46A-13 Stop fc/32 Programmable Operate Oscillation Oscillator using as system clock: Oscillation Other oscillator: Programmable Reset (fc/2, fc/4, fc/8, fc/16, fc/32) fs/2 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32, fs/2) Stop 2004-02-10 93CW46A-14 Low-frequency oscillator X1 X2 High-frequency oscillator SYSCR0<XEN><RXEN> WDMOD<HALTM1:0> XT1 XT2 SYSCR0<XTEN> <RXTEN> fs fc fc ÷2 ÷4 ÷8 ÷16 fc/2 fc/4 fc/8 fc/16 fs Selector SYSCR1<SYSCK> SYSCR0<RSYSCK> SYSCR0 <PRCK1:0> SYSCR1<GEAR2:0> Selector Selector fFPH fc/16 fs • Watchdog timer ....................................... fSYS • Warm up (Releasing STOP mode) .......... fFPH • Warm up (Changing clocks) .................... fc or fs. ÷2 fSYS System clock ÷2 ÷4 Run & stop TRUN <PRRUN> ÷2 CKOCR <SCOSEL> Selector CPU Internal I/O ROM, RAM 9-bit prescaler 5-bit prescaler Watchdog timer/ Warm-up timer SYSCR0<WUEF> SCOUT/PA7 CLK 8-bit timers 0 and 1 16-bit timers 4 and 5 Serial interfaces 0 to 4 8-bit PWMs 0 and 1 TMP93CW46A Figure 3.3.2 Block Diagram of Dual Clock, Standby Circuits 2004-02-10 TMP93CW46A SYSCR0 (006EH) SYSCR1 (006FH) WDMOD (005CH) 7 Bit symbol XEN Read/Write After reset 1 Function High- 6 XTEN 5 RXEN 4 RXTEN 0 1 0 0 0 frequency oscillator (fc) 0: Stop 1: Oscillation Lowfrequency oscillator (fs) 0: Stop 1: Oscillation Highfrequency oscillator (fc) after released STOP mode 0: Stop 1: Oscillation Lowfrequency oscillator (fs) after released STOP mode 0: Stop 1: Oscillation Slect clock after released STOP mode 0: fc 1: fs Warm-up timer (Write) 0: Don’t care 1: Start timer (Read) 0: End warm-up 1: Not end warm-up 7 6 5 4 3 SYSCK 2 GEAR2 0 Select system clock 0: fc 1: fs 7 6 5 Bit symbol WDTE WDTP1 WDTP0 Read/Write After reset 1 0 0 Function WDT control WDT detection time 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS 7 6 4 WARM 0 PRCK0 Warm-up timer 0: 214/ inputted frequency 1: 216/ inputted frequency 5 0 0 Select prescaler clock 00: fFPH 01: fs 10: fc/16 11: (Reserved) 1 GEAR1 0 GEAR0 2 HALTM0 1 RESCR 0 DRVE 0 0 0 R/W 0 4 0 Standby mode 00: 01: 10: 11: RUN mode STOP mode IDLE1 mode IDLE2 mode 3 SCOSEL 0 SCOUT select 0: fFPH 1: fSYS Note 2: 1 PRCK1 R/W 1 0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 3 HALTM0 Bit symbol Read/Write After reset Function Note 1: 2 WUEF R/W Bit symbol Read/Write After reset Function 1: Enable CKOCR (006DH) 3 RSYSCK 1: Connects 1: Drives WDT pin even output to in STOP mode RESET pin internally. 2 SCOEN 1 ALEEN 0 CLKEN R/W 1 0/1(Note 2) ALE pin SCOUT output output control control 0: I/O ports 0: High-Z output 1: SCOUT 1: ALE output output 0/1(Note 2) CLK pin output control 0: High-Z output 1: CLK output SYSCR1<bit7:4> and CKOCR<bit7:4> are read as “1”. After reset, <ALEEN> and <CLKEN> bits are “0”. (ALE and CLK is high impedance.) During reset, CLK pin is internally pulled up regardless of the products. Note 3: Writing “0” to SYSCR1<SYSCK> enables the low frequency oscillation circuit regardless of the value of SYSCR0<XTEN>. Additionally, writing “1” to <SYSCK> register enables low frequency oscillation circuit regardless of the value of SYSCR0<XTEN>. Figure 3.3.3 I/O Register about Dual Clock and Standby 93CW46A-15 2004-02-10 TMP93CW46A 3.3.1 System Clock Controller The system clock controller generates system clock (fSYS) for CPU core and internal I/O. It contains two oscillation circuits and clock gear circuit for high frequency (fc). The register SYSCR1<SYSCK> changes system clock to either fc or fs, SYSCR0<XEN>, <XTEN> controls enable/disable each oscillator, SYSCR1<GEAR2:0> changes high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16), and these functions can reduce the power consumption. The system clock (fSYS) is set to fc/32 (fc/16 × 1/2) because of <XEN> = “1”, <XTEN> = “0”, <SYSCK> = “0”, <GEAR2:0> = “100” by resetting. For example, fSYS is set to 0.5 MHz by resetting the case of 16 MHz oscillator is connected to X1, X2 pins. The high-frequency (fc) and low-frequency (fs) clocks can be easily obtained by connecting a resonator to the X1/X2, XT1/XT2 pins, respectively. Clock input from an external oscillator is also possible. The XT1, XT2 pins have also Port 96, 97 function. Therefore the case of single clock mode, the XT1, XT2 pins can be used as I/O port pins. High-frequency Clock X1 X2 X1 Low-frequency Clock X2 XT1 XT2 XT1 XT2 (Open) 74HCU04 * See application circuit in chapter 5 (a) Crystal/ceramic resonator (b) External oscillator (c) Crystal resonator (d) External oscillator Figure 3.3.4 Examples of Resonator Connection Note 1: Note on using low-frequency oscillation circuit To connect the low-frequency resonator to port 96, 97, it is necessary to set the following to reduce the power consumption. (Connecting with resonators) P9CR<P96C, P97C> = “11”, P9<P96:97> = “00” (Connecting with oscillators) P9CR<P96C, P97C> = “11”, P9<P96:97> = “10” Note 2: Accurate adjustment of the oscillation frequency The CLK pin outputs 1/2 system clock frequency (fSYS/2) to monitor the oscillation clock. With a system requiring adjustment of the oscillation frequency, the adjusting program must be created beforehand. 93CW46A-16 2004-02-10 TMP93CW46A (1) Switching NORMAL to SLOW mode When the resonator is connected to X1, X2, or XT1, XT2 pin, the warm-up timer is used to change the operation frequency after getting stabilized oscillation. The warm-up time can be selected by WDMOD<WARM>. This starting and ending of warm-up timer are performed like the following example 1, 2 by program. Note 1: The warm-up timer is also used as a watchdog timer. So, when it is used as a warm-up timer, the watchdog timer must be disabled. Note 2: The case of using oscillator (Not resonator) with stabilized oscillation, a warm-up timer is not need. Note 3: The warm-up timer is operated by a oscillation clock. Therefore, warm-up time has an error. Table 3.3.2 Warm-up Time Warm-up Time WDMOD<WARM> Change to NORMAL Change to SLOW 0 (214/frequency) 0.8192 (ms) 500 (ms) 3.2768 (ms) 2000 (ms) 16 1 (2 /frequency) 93CW46A-17 at fc = 20 MHz, fs = 32.768 kHz 2004-02-10 TMP93CW46A Setting example 1 The case of changing from high frequency (fc) to low frequency (fs). SYSCR0 SYSCR1 WDCR WDMOD WUP: EQU EQU EQU EQU RES LD SET SET SET BIT JR SET RES SET 006EH 006FH 005DH 005CH 7, (WDMOD) (WDCR), B1H 4, (WDMOD) 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) 7, (WDMOD) ; Disables watchdog timer. ; ; Sets warm-up time to 216/fs. ; Enables low-frequency oscillation ; Clears and starts warm-up timer. ; Detects end of warm-up timer. ; ; Changes fSYS from fc to fs. ; Disables high-frequency oscillation. ; Enables watchdog timer. <XEN> X1, X2 pins <XTEN> XT1, XT2 pins Warm-up timer Counts up by fSYS Counts up by fs End of warm-up timer <SYSCK> fc fs System clock fSYS Enables Clears and starts low frequency warm-up timer Changes fSYS Disables high frequency from fc to fs End of warm-up timer 93CW46A-18 2004-02-10 TMP93CW46A Setting example 2 The case of changing from low frequency (fs) to high frequency (fc). SYSCR0 SYSCR1 WDCR WDMOD WUP: EQU EQU EQU EQU RES LD RES SET SET BIT JR RES 006EH 006FH 005DH 005CH 7, (WDMOD) (WDCR), B1H 4, (WDMOD) 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) ; ; Disables watchdog timer. ; Sets warm-up time to 214/fc. ; Enables high frequency (fc). ; Clears and starts warm-up timer. ; Detects end of warm-up timer. ; ; Changes fSYS from fs to fc. RES SET 6, (SYSCR0) 7, (WDMOD) ; Disables low-frequency oscillation. ; Enable watchdog timer <XEN> X1, X2 pins <XTEN> XT1, XT2 pins Warm-up timer Counts up by fSYS Counts up by fc End of warm-up timer <SYSCK> fs fc System clock fSYS Enables high frequency Clears and starts warm-up timer Changes fSYS from fs to fc End of warm-up timer Disables low frequency 93CW46A-19 2004-02-10 TMP93CW46A (2) Clock gear controller When the high-frequency clock fc is selected at SYSCR1<SYSCK> = “0”, the clock gear select register SYSCR1<GEAR2:0> sets fFPH to either fc, fc/2, fc/4, fc/8, fc/16. Switching fFPH with the clock gear reduces the power consumption. Setting Example 3 The case of changing gear value of high frequency SYSCR1 EQU LD 006FH (SYSCR1), XXXX0000B ; Changes fSYS to fc/2 LD (SYSCR1), XXXX0100B ; Changes fSYS to fc/32 X: Don’t care (High-speed clock gear changing) To change the clock gear, write the register value to SYSCR1<GEAR2:0> register. It is necessary the warm-up time until changing after writing the register value. There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing. To execute the instruction next to the clock gear switching instruction by the clock gear after changing, input the dummy instruction as follows (Instruction to execute the write cycle). (Example) SYSCR1 EQU LD 006FH (SYSCR1), XXXX0001B ; Changes fSYS to fc/4. LD (DUMMY), 00H ; Dummy instruction Instruction to be executed by the clock gear after changing 3.3.2 Prescaler Clock Controller The 9-bit prescaler provides a clock to 8-bit timers 0 and 1, 16-bit timers 4 and 5, and serial interfaces 0 to 4. And the 5-bit prescaler provides a clock to 8-bit PWMs 0 and 1. The clock input to the 5-bit prescaler is a clock divided by 2 which is selected by fFPH, fc/16 or fs by SYSCR0<PRCK1:0> register. The clock input to the 9-bit prescaler is a clock divided by 4 which is selected either fFPH or fc/16 by SYSCR0<PRCK1:0> register. <PRCK1:0> register is initialized to “00” by resetting. The clock selected by <SYSCK> is input. When the IDLE 1 mode (Operates only oscillator) is used, set TRUN<PRRUN> to “0” to reduce the power consumption of 9, 5-bit prescaler before “HALT” instruction is executed. 93CW46A-20 2004-02-10 TMP93CW46A 3.3.3 Internal Clock Pin Output Function (1) PA7/SCOUT pin PA7/SCOUT pin outputs the internal clocks fFPH or fSYS. The port A control register PACR<PA7C> and the clock output control register CKOCR<SCOEN, SCOSEL> specifies the clock and the pins. PA7/SCOUT pin is used as the input port by reset. Table 3.3.3 shows pin states in the respective operation modes which is under condition that PA7/SCOUT pin is specified as SCOUT output. Table 3.3.3 SCOUT Pin States in the Operation Modes Operation Mode HALT Mode NORMAL, SLOW RUN, IDLE2, IDLE1 Output Clock fFPH Outputs fFPH clock. fSYS Outputs fSYS clock. STOP Fixed to “0” or “1”. (2) CLK pin CLK pin outputs fSYS divided by 2 internal clock. Outputs are specified by the clock output control register CKOCR<CLKEN>. Writing “1” sets clock output, and writing “0” sets high impedance. After reset, CKOCR<CLKEN> is depended on each product types. It is necessary to set for each usage. Table 3.3.4 shows the value and operation after reset. During reset, CLK pin is internally pulled up regardless of the value of <CLKEN> register. Table 3.3.4 <CLKEN> and CLK Pin Operation after Reset Type Number CKOCR<CLKEN> CLK Pin Operation TMP93CW46A 0 High impedance Note: To set <CLKEN> = “0” and set CLK pin to high impedance, pull up externally to prevent through current which follows to the input buffer of CLK pin. 93CW46A-21 2004-02-10 TMP93CW46A 3.3.4 Standby Controller (1) HALT mode When the HALT instruction is executed, the operating mode changes RUN, IDLE2, IDLE1 or STOP mode depending on the contents of the HALT mode setting register WDMOD<HALTM1:0>. Figure 3.3.5 shows the watchdog timer mode registers. Watchdog Timer Mode Register WDMOD Bit symbol (005CH) Read/Write After reset Function 7 6 5 4 WDTE WDTP1 WDTP0 WARM 3 2 1 0 HALTM1 HALTM0 RESCR DRVE R/W 1 Watchdog timer control 0: Disable 1: Enable 0 0 0 Watchdog timer detect time selection 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS Warm-up timer 0: 214/ select clock frequency 1: 216/ select clock frequency 0 0 HALT mode selection 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 0 Runaway detect internal reset control 1: Executes internal reset by runaway detect 0 STOP mode pin control 1: Drive pins in STOP mode Pin state control in STOP mode 0 I/O off 1 Retains the state before halt HALT mode setting 00 RUN mode (Only CPU stop) 01 STOP mode (All circuits stop) 10 IDLE1 mode (Only oscillator operating) 11 IDLE2 mode (A part I/O operating) Warm-up time selection at returning from the stop mode (see Table 3.3.7) 0 214/select clock frequency 1 216/select clock frequency Figure 3.3.5 Watchdog Timer Mode Register The futures of RUN, IDLE2, IDLE1 and STOP modes are as follows. 1. RUN: Only the CPU halts 2. IDLE2: The built-in oscillator and the specified I/O operates. 3. IDLE1: Only the built-in oscillator operates, while all other built-in circuits stop. 4. STOP: All internal circuits including the built-in oscillator stop. This greatly reduces power consumption. The operations in the halt state is described in Table 3.3.5. 93CW46A-22 2004-02-10 TMP93CW46A Table 3.3.5 I/O Operation during HALT Mode HALT Mode RUN IDLE2 WDMOD<HALTM1:0> 00 11 CPU IDLE1 STOP 10 01 Stop I/O port Keep the state when the “HALT” instruction was executed. See Table 3.3.8 Block 8-bit timer 8-bit PWM timer 16-bit timer Operate Serial channel Stop AD converter Watchdog timer Interrupt controller (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combinations between the states of interrupt mask register <IFF2:0> and the HALT modes. The details for releasing the halt status are shown in Table 3.3.6. • Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of the interrupt mask register, the interrupt due to the source is processed after releasing the HALT mode, and CPU starts executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not executed. (In non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is executed. In this case, interrupt processing is not processed, and CPU starts executing the instruction next to the HALT instruction, but the interrupt request flag is held at “1”. • Note: Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. Release by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessary enough resetting time (3 ms or more) to set the operation of the oscillator to be stable. When releasing the halt mode by resetting, the internal RAM data keeps the state before the “HALT” instruction is executed. However the other setting contents are initialized. (Releasing due to interrupts keep the state before the “HALT” instruction is executed.) 93CW46A-23 2004-02-10 TMP93CW46A Table 3.3.6 Halt Releasing Source and Halt Releasing Operation Interrupt Receiving Status HALT mode (Interrupt level) ≥ (Interrupt mask) (Interrupt level) < (Interrupt mask) IDLE2 IDLE1 STOP RUN IDLE2 IDLE1 STOP ♦ ♦ ♦ − − − − × × × − − − − ♦ ♦ ♦ ♦ ♦ ♦ ♦ ○ ○ ○ ○ × × × × × × × × × × × × × × × × × × × × × × × × × × × × × INTAD ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ × × RESET ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ INTWDT Interrupt Interrupt Disable RUN NMI Halt releasing source Interrupt Enable INT0 INT4 to 7 INTT0 to 3 INTTR4 to 7 INTRX0 to 4, TX0 to 4 *1 *1 *1 ♦: After releasing the HALT mode, CPU starts interrupt processing. (RESET initializes LSI.) ○: After releasing the HALT mode, CPU starts executing an instruction that follows the HALT instruction. ×: It can not be used to release the HALT mode. −: The priority level (Interrupt request level) of non-maskable interrupts is fixed to highest priority level “7”. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note: When releasing the HALT mode is executed by INT0 interrupt of the level mode in the interrupt enabled status, hold level “H” until starting interrupt processing. If level “L” is set before holding level “L”, interrupt processing is correctly started. (Example releasing “RUN” mode) INT0 interrupt releases halt state when the RUN mode is on. Address 8203H 8206H 8209H 820BH 820EH LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (WDMOD), 00H INT0 Interrupt routine INT0 820FH ; Selects INT0 interrupt rising edge. ; Sets interrupt level to “6” for INT0. ; Sets interrupt level to “5” for CPU. ; Sets HALT mode to “RUN”. ; Halts CPU. LD XX, XX 93CW46A-24 RETI 2004-02-10 TMP93CW46A (3) Operation 1. RUN mode In the RUN mode, the system clock continues to operate even after a HALT instruction is executed. Only the CPU stops executing the instruction. In the halt state, an interrupt request is sampled with the falling edge of the “CLK” signal. Releasing the RUN mode is executed by the external/internal interrupts. (See Table 3.3.6 “Halt Releasing Source and Halt Releasing Operation”.) Figure 3.3.6 shows the interrupt timing for releasing the halt state by interrupts in the RUN/IDLE2 mode. X1 CLK A0 to A23 Address Address + 2 ALE AD0 to AD15 Address Data Address Address Data RD WR NMI INT0 (Level) INT4 to INT7 (Rising edge) INT4, INT6 (Falling edge) Internal INT RUN/IDLE2 mode Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2 Modes 2. IDLE2 mode In the IDLE2 mode, the system clock is supplied to only specific internal I/O devices, and the CPU stops executing the current instruction. In the IDLE2 mode, the halt state is released by an interrupt with the same timing as in the RUN mode. The IDLE2 mode is released by external/internal interrupt, except INTWDT/INTAD interrupts. (See Table 3.3.6 “Halt Releasing Source and Halt Releasing Operation”.) In the IDLE2 mode, the watchdog timer should be disabled before entering the halt status to prevent the watchdog timer interrupt occurring just after releasing the HALT mode. 93CW46A-25 2004-02-10 TMP93CW46A 3. IDLE1 mode In the IDLE1 mode, only the internal oscillator operates. The system clock in the MCU stops, the CLK pin is fixed at the level “H” in the output enable (CKOCR<CLKEN> = “1”). In the halt state, and interrupt request is sampled asynchronously with the system clock, however the halt release (Restart of operation) is performed synchronously with it. IDLE1 mode is released by external interrupts (NMI, INT0). (See Table 3.3.6 “Halt Releasing Source and Halt Releasing Operation”.) When the IDLE1 mode is used, setting TRUN<PRRUN> to “0” to stop 9, 5-bit prescaler before “HALT” instruction reduces the power consumption. Figure 3.3.7 illustrates the timing for releasing the halt state by interrupts in the IDLE1 mode. X1 CLK A0 to A23 Address + 2 Address ALE AD0 to AD15 Address Data Address Data RD WR NMI INT0 (Level) INT0 (Rising edge) IDEL1 mode Figure 3.3.7 Timing Chart of Halt Released by Interrupts in IDLE1 Mode 93CW46A-26 2004-02-10 TMP93CW46A 4. STOP mode The STOP mode is selected to stop all internal circuits including the internal oscillator. The pin status in the STOP mode is depended on setting the watchdog timer mode register WDMOD<DRVE>. (See Figure 3.3.5 for setting WDMOD<DRVE>.) Table 3.3.8 summarizes the state of these pins in the STOP mode. The STOP mode is released by external interrupts (NMI, INT0). When the STOP mode is released, the system clock is started outputting after warm-up timer to get the stabilized oscillation. A warm-up time can be set using WDMOD<WARM>. See the example of warm-up time in Table 3.3.7. In the system which supplies stable clock generated by an external oscillator, the warm-up time can be reduced using T45CR<QCU>. Figure 3.3.8 illustrates the timing for releasing the halt state by interrupts in the STOP mode. Warm-up time X1 CLK A0 to A23 Address + 2 Address ALE AD0 to AD15 Address Data Address Data RD WR NMI INT0 (Level) INT0 (Rising edge) STOP mode Figure 3.3.8 Timing Chart of Halt Released by Interrupt in STOP Mode 93CW46A-27 2004-02-10 TMP93CW46A Table 3.3.7 The Example of Warm-up Time after Releasing the STOP Mode Operation Clock after the STOP Mode Warm-up Time [ms] WDMOD<WARM> = 0 WDMOD<WARM> = 1 fc fc/2 fc/4 fc/8 fc/16 0.8192 1.6384 3.2768 6.5536 13.1072 fs 500 3.2768 6.5536 13.1072 26.2144 52.4288 Clock fc = 20 MHz fs = 32.768 kHz 2000 How to calculate the warm-up time WDMOD<WARM> = “0”: Operation clock after the 214/STOP mode WDMOD<WARM> = “1”: Operation clock after the 216/STOP mode The NORMAL/SLOW mode selection is possible after releasing STOP mode. This is selected by SYSCR0<RSYSCK> register. Therefore, setting to <RSYSCK>, <RXEN>, <RXTEN> is necessary before “HALT” instruction is executed. (Setting example) The STOP mode is entered when the low frequency operates, and high frequency operates after releasing due to NMI. Address SYSCR0 SYSCR1 WDMOD 8FFDH 9000H 9002H EQU EQU EQU LD RES LD 006EH 006FH 005CH (SYSCR1), 08H 4, (WDMOD) (SYSCR0), −11000 − − B ; fSYS = fs/2 ; Sets warm-up time to 214/fc ; Operates high frequency after released. HALT 9005H Clears and starts warm-up timer (High-frequency clock) NMI End NMI interrupt routine 9006H LD XX, XX RETI −: No change Note: When different modes are used before and after STOP mode as the above mentioned, there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of “HALT” instruction (during 8 states). In the system which accepts the interrupts during execution “HALT” instruction, set the same operation mode before and after the STOP mode. 93CW46A-28 2004-02-10 TMP93CW46A Table 3.3.8 Pin States in STOP Mode Pin Name P00 to P07 P10 to P17 P20 to P27 P30 ( RD ), P31 ( WR ) P32 to P37 P40, P41 P42 ( CS2 / CAS2 ) P5 P6 P7 P80 to P86 P87 (INT0) P90 to P95 PA0 to PA6 PA7 NMI WDTOUT ALE CLK RESET EA AM8/ AM16 X1 X2 P96 P97 I/O TMP93CW46A <DRVE> = 0 <DRVE> = 1 ▲ ▲ − − Output − Input mode Output mode AD8 to AD15 Input mode Output mode AD0 to AD7 Input mode Output mode A0 to A7/A16 to A23 Output pin Input mode Output mode Input mode Output mode Input mode Output mode Input mode Input mode Output mode Input mode Output mode Input mode Output mode Input mode Output mode Input mode (INT0) Input mode Output mode Input mode Output mode Input mode Output mode, SCOUT Input pin Output pin ▲ ▲ PU* PU* PU* PU* PU* PU* PU PU Input PU* PU* − − − − Input Output Input Output Input Output Input Output Input Output Input Input Output Input Output Input Output Input Output Output (<ALEEN> = 1) Output (<CLKEN> = 1) Input “L” level output − Input “L” level output “H” level output Input Input Input Input Input − “H” level output − − − − − − − “H” level output Input Output* − Input Output* − Input Input Input Output Input mode Output mode XT1 Input mode Output mode XT2 ▲ ▲ − − Output − ▲ ▲ Output − PU* PU* PU* PU* PD* PD* Output Input Output Input Output Input Output ▲ −: Input: Output: Output*: PU: PU*: PD*: ▲: ×: Note: Input for input mode/input pin is invalid; output mode/output pin is at high impedance. Input gate in operation. Fix input voltage to “L” or “H” so that input pin stays constant. Output state Open-drain output state. Input gate in operation. Set output to “L” or attach pull-up pin so that the input gate stays constant. Programmable pull-up pin. Fix the pin to avoid through current since the input gate operates when a pull-up pin resistor is not set Programmable pull-up pin. Input gate disable state. No through current even if the pin is set t high impedance. Programmable pull-down pin. Input gate disable state. No through current even if the pin is set t high impedance. When HALT instruction is executed and CPU stops at the address of the port register, input gate in operation. Fix the pin to avoid through current and change the program. In the other cases, input for input mode is invalid, output mode is at high impedance. Cannot set. Port registers are used for controlling programmable pull up/pull down. If a pin is also used for an output function (e.g., TO1) and the output function is specified, whether pull up or pull down is selected depends on the output function data. If a pin is also used for an input function, whether pull up or pull down is selected depends on the port register setting value only. 93CW46A-29 2004-02-10 TMP93CW46A 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and the built-in interrupt controller. TMP93CW46A has altogether the following 35 interrupt sources: • Interrupts from the CPU … 9 (Software interrupts, and Illegal (Undefined) instruction execution) • Interrupts from external pins ( NMI , INT0 and INT4 to INT7) … 6 • Interrupts from built-in I/Os … 20 A fixed individual interrupt vector number is assigned to each interrupt source; six levels of priority (Variable) can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority of 7. When an interrupt is generated, the interrupt controller sends the value of the priority of the interrupt source to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the highest) to the CPU. The CPU compares the value of the priority sent with the value in the CPU interrupt mask register <IFF2:0>. If the value is greater than that the CPU interrupt mask register, the interrupt is accepted. However software interrupts and illegal instruction execution interrupts are not compared with <IFF2:0>, the interrupt is processed. The value in the CPU interrupt mask register <IFF2:0> can be changed using the EI instruction. Executing EI n changes the contents of <IFF2:0> to n. For example, programming EI 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and non-maskable interrupts which are set in the interrupt controller. The DI instruction operates in the same way as the EI 7 instruction, setting <IFF2:0> = 7. Since the priority values for maskable interrupts are 0 to 6, the DI instruction is used to disable maskable interrupts to be accepted. The EI instruction becomes effective immediately after execution. In addition to the general-purpose interrupt processing mode described above, there is also a micro DMA processing mode. Micro DMA is a mode used by the CPU to automatically transfer byte or word data. It enables the CPU to process interrupts such as data saves to built-in I/Os at high speed. Figure 3.4.1 is a flowchart showing overall interrupt processing. 93CW46A-30 2004-02-10 TMP93CW46A Interrupt processing Read interrupt vector V. Clear interrupt request F/F. Vector V and high-speed micro DMA start vector match Yes Data transfer by high-speed micro DMA No COUNT ← COUNT − 1 General-purpose interrupt processing PUSH PC PUSH SR SR<IFF2:0> ← Accepted interrupt level + 1 INTNEST ← INTNEST + 1 Micro DMA processing (Note) Yes COUNT = 0 No PC ← (8000H + V) Interrupt processing program Note: In read-only mode, always branches to NO without conditional branch. RETI instruction POP SR POP PC INTNEST ← INTNEST − 1 End Figure 3.4.1 Interrupt Processing Flowchart 93CW46A-31 2004-02-10 TMP93CW46A 3.4.1 General-purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows. In the software interrupts or the illegal instruction execution interrupts from CPU, the following (1) and (3) are not executed. (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority, then clears the interrupt request. The default priority is fixed as follows: The smaller the vector value, the higher the priority. (2) The CPU pushes the program counter and the status register to the system stack area (Area indicated by the system mode stack pointer (XSP)). (3) The CPU sets a value in the CPU interrupt mask register <IFF2:0> that is higher by 1 than the value of the accepted interrupt level. However, if the value is 7, 7 is set without an increment. (4) The CPU increments the INTNEST (Interrupt nesting counter). (5) The CPU jumps to address stored at 8000H + interrupt vector, then starts the interrupt processing routine. The following diagram shows all the above processing state number. Bus Width of Stack Area 8-bit 16-bit Bus Width of Interrupt Vector Area Interrupt Processing State Number MAX Mode MIN Mode 8 bits 35 31 16 bits 31 27 8 bits 29 27 16 bits 25 23 To complete the interrupt processing, the RETI instruction is usually used. Executing this instruction restores the contents of the program counter and the status registers and decrements INTNEST (Interrupt nesting counter). Though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register <IFF2:0>. The CPU mask register <IFF2:0> is set to a value higher by 1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest. The interrupt request with a priority higher than the accepted now interrupt during the CPU is processing above (1) to (5) is accepted before the 1st instruction in the interrupt processing routine, causing interrupt processing to nest. The CPU does not accept an interrupt request of the same level as that of the interrupt being processed. (Non-maskable interrupts can be accepted, causing interrupt processing to nest.) Resetting initializes the CPU mask registers <IFF2:0> to 7; therefore, maskable interrupts are disabled. The following (1) to (5) show a flowchart of interrupt processing. 93CW46A-32 2004-02-10 TMP93CW46A (1) Maskable interrupt (2) Non-maskable interrupt (NMI interrupt routine) (INTT0 interrupt routine) (main) EI 1 (main) DI IFF←2 [2] [1] INTT0 (Level 1) NMI (Level 7) [3] [4] [5] [4] IFF←7 RETI During execution of the main program, the CPU accepts an interrupt request. The CPU increments the IFF so that the interrupts of level 1 are not accepted during processing the interrupt routine. RETI DI instruction is executed in the main program, so that the interrupts of only level 7 are accepted. The CPU does not increment the IFF even if the CPU accepts an interrupt request of level 7. (3) Interrupt nesting (4) Software interrupt (INTT0 interrupt routine) (INTT1 interrupt routine) (main) EI 3 (SWI3 routine) (main) DI IFF←4 [2] IFF←5 [4] [3] INTT0 (Level 3) [9] [3] [5] IFF←1 [1] IFF←7 [2] [1] [1] INTT1 (Level 4) [8] [5] [7] [5] IFF←4 RETI RETI During processing the interrupts of level 3, the IFF is set to 4. When an interrupt with a level higher than level 4 is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest. [3] SWI 3 [6] IFF←3 [2] [4] RETI The CPU accepts the software interrupt request during DI status (IFF = 7) because of the level 7. The IFF is not changed by the software interrupts. (5) Interrupt sampling timing (INTT0 interrupt routine) [3] (main) EI 3 [1] INTT1 (Level 4) [2] XXX INTT0 (Level 3) [8] [5] [7] [4] Example: [6] (Underline): Instruction [1], [2] … : Execution flow RETI RETI If an interrupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level. The program counter which returns at [5] is the start address of INTT0 interrupt routine. 93CW46A-33 2004-02-10 TMP93CW46A The addresses 008000H to 0080FFH (256 bytes) of the TMP93CW46A are assigned for interrupt vector area. Table 3.4.1 TMP93CW46A Interrupt Table Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 − 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 − to − Type Nonmaskable Interrupt Source Reset, or SW10 instruction SWI 1 instruction Illegal instruction, or SWI2 SWI 3 instruction SWI 4 instruction SWI 5 instruction SWI 6 instruction SWI 7 instruction NMI: NMI pin INTWD: Watchdog timer Maskable INT0: INT0 pin INT4: INT4 pin INT5: INT5 pin INT6: INT6 pin INT7: INT7 pin (Reserved) INTT0: 8-bit timer0 INTT1: 8-bit timer1 INTT2: 8-bit timer2/PWM0 INTT3: 8-bit timer3/PWM1 INTTR4: 16-bit timer4 (TREG4) INTTR5: 16-bit timer4 (TREG5) INTTR6: 16-bit timer5 (TREG6) INTTR7: 16-bit timer5 (TREG7) INTRX0: Serial receive (Channel 0) INTTX0: Serial send (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial send (Channel 1) INTAD: AD conversion completion INTRX2: Serial receive (Channel 2) INTTX2: Serial send (Channel 2) INTRX3: Serial receive (Channel 3) INTTX3: Serial send (Channel 3) INTRX4: Serial receive (Channel 4) INTTX4: Serial send (Channel 4) (Reserved) to (Reserved) Vector Value “V” Address Refer to Vector 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2 2 0 4 8 C 0 4 8 C 0 4 H H H H H H H H H H 8 8 8 8 8 8 8 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2 2 0 4 8 C 0 4 8 C 0 4 H H H H H H H H H H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C H H H H H H H H H H H H H H H H H H H H H H H H H H 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H H H H H H H H H H H H H H H H H H H H H H H H 0 C H 8 0 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 to F 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 to F C H 93CW46A-34 Micro DMA Start Vector − − − − − − − − 08H 09H 0AH 0BH 0CH 0DH 0EH − 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H − to − 2004-02-10 TMP93CW46A Setting to reset/interrupt vector 1. Reset vector 8000H 8001H 8002H 8003H 2. PC<7:0> PC<15:8> PC<23:16> XX Interrupt vector (except reset vector) Address refer to vector +0 +1 +2 +3 PC<7:0> PC<15:8> PC<23:16> XX XX: Don’t care (Setting example) Reset vector: 8100H, NMI Vector: 9ABCH, INTAD Vector: 123456H. ORG DL 8000H 008100H ; Reset = 8100H ORG DL 8020H 009ABCH ; NMI = 9ABCH ORG DL 8070H 123456H ; INTAD = 123456H ORG LD 8100H A, B (cf) ORG LD 9ABCH B, C ORG LD 123456H C, A ORG, DL are the assembler directive. ORG: Control location counter DL: Define the long word (32 bits) data 93CW46A-35 2004-02-10 TMP93CW46A 3.4.2 Micro DMA In addition to the conventional interrupt processing, the TMP93CW46A also has a micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether processing is micro DMA mode or general-purpose interrupt. If micro DMA mode is requested, the CPU performs micro DMA processing. The micro DMA can process at very high speed compared with the TLCS-90 micro DMA because it has transfer parameters in dedicated registers in the CPU. Since those dedicated registers are assigned as CPU control registers, they can only be accessed by the LDC instruction. (1) Micro DMA operation Micro DMA operation starts when the accepted interrupt vector value matches the micro DMA start vector value set in the interrupt controller. The micro DMA has four channels so that it can be set for up to four types of interrupt source. When a micro DMA interrupt is accepted, data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. If the value in the counter after decrementing is other than 0, micro DMA processing is completed; if the value in the counter after decrementing is 0, general-purpose interrupt processing is performed. In read-only mode, which is provided for DRAM refresh, the value in the counter is ignored and dummy read is repeated. 32-bit control registers are used for setting transfer source/destination addresses. However, the TMP93CW46A has only 24 address pins for output. A 16-Mbyte space is available for the micro DMA. There are two data transfer modes: One-byte mode and one-word mode. Incrementing, decrementing, and fixing the transfer source/destination address after transfer can be done in both modes. Therefore data can easily be transferred between I/O and memory and between I/Os. For details of transfer modes, see the description of transfer mode registers. The transfer counter has 16 bits, so up to 65536 transfers (The maximum when the initial value of the transfer counter is 0000H.) can be performed for one interrupt source by micro DMA processing. When the transfer counter is decremented to “0” after data is transferred with micro DMA, general-purpose interrupt processing is performed. After processing the general-purpose interrupt, starting the interrupts of the same channel restarts the transfer counter from 65536. If necessary, reset the transfer counter. Interrupt sources processed by micro DMA processing are 26 sources with the micro DMA start vectors listed in Table 3.4.1. 93CW46A-36 2004-02-10 93CW46A-37 WR, HWR RD A16 to A23 AD0 to AD15 ALE X1 Dummy DM2 DM3 Dummy DM4 D0 to D15 DM6 D0 to D15 DM8 Destination address A0 to A15 DM7 (Note 2) DM9 Dummy DM10 High-speed micro DMA cycle (COUNT ≠ 0) Source address A0 to A15 DM5 (Note 1) Note 1: This is added 2 states the case of the bus width of source address area is 8 bits. Note 2: This added 2 states the case of the bus width of destination address area is 8 bits. Note 3: This may be a dummy cycle with instruction queue buffer. Note 4: In the case of the word transfer mode. DM1 1 state D0 to D15 DM12 Address A0 to A15 DM11 (Note 3) D0 to D15 DM14 Address + 2 A0 to A15 DM13 (Note 3) D0 to D15 DM16 Address + 4 A0 to A15 DM15 (Note 3) TMP93CW46A Figure 3.4.2 Micro DMA Cycle (COUNT ≠ 0) 2004-02-10 93CW46A-38 WR, HWR DM2 DM20 DM35 D0 to D15 DM6 DM22 DM37 XSP − 4 DM21 (Note 4) Source address A0 to A15 DM5 Address + 2 DM36 XSP − 6 DM19 Address DM34 Dummy DM4 (Note 4) DM3 D0 to D15 DM8 DM24 XSP − 2 DM23 (Note 4) Destination address A0 to A15 DM7 (Note 2) This is added 2 states the case of the bus width of source address area is 8 bits. This added 2 states the case of the bus width of destination address area is 8 bits. This be a dummy cycle with instruction queue buffer. This is added 2 states the case of the bus width of stack address area is 8 bits. Dummy DM33 Dummy DM18 Dummy DM17 DM1 Note 1: Note 2: Note 3: Note 4: RD AD0 to AD15 ALE X1 WR, HWR RD AD0 to AD15 ALE X1 WR, HWR RD A16 to A23 AD0 to AD15 ALE X1 (Note 1) DM10 Dummy DM26 Dummy DM25 DM9 D0 to D15 DM12 DM27 D0 to D15 DM29 DM16 DM31 Dummy DM32 Dummy DM15 8002H + V DM30 Address + 2 A0 to A15 DM14 (Note 3) DM13 8000H + V DM28 Address A0 to A15 DM11 (Note 3) TMP93CW46A Figure 3.4.3 Micro DMA Cycle (COUNT=0) 2004-02-10 TMP93CW46A Timing chart in the previous page is a micro DMA cycle of the transfer address increment mode. (The other mode except the read-only mode is the same as this.) (Condition: MAX mode, 16-bit bus width for 16 Mbytes, 0 waits) (2) Register configuration (CPU control register) Channel 0 DMAS0 Transfer source address register 0 DMAD0 Transfer destination address register 0 DMAC0 Transfer counter register 0 DMAM0 (Use only lower 24 bits.) (1 to 65536) Transfer mode register 0 Channel 1 DMAS1 Transfer source address register 1 DMAD1 Transfer destination address register 1 DMAC1 Transfer counter register 1 DMAM1 Transfer mode register 1 Channel 2 DMAS2 Transfer source address register 2 DMAD2 Transfer destination address register 2 DMAC2 Transfer counter register 2 DMAM2 Transfer mode register 2 Channel 3 DMAS3 Transfer source address register 3 DMAD3 Transfer destination address register 3 DMAC3 Transfer counter register 3 DMAM3 Transfer mode register 3 8 bits 16 bits 32 bits These control registers can be set only with “LDC cr, r” instruction. (e.g.) LD LDC LD LDC LD LDC LD LDC XWA, 100H DMAS0, XWA XWA, 50H DMAD0, XWA WA, 40H DMAC0, WA A, 05H DMAM0, A 93CW46A-39 2004-02-10 TMP93CW46A (3) Transfer mode register: DMAM0 to DMAM3 (DMAM0 to DMAM3) 0 0 0 0 Mode Note: When setting values for this register, set the upper 4 bits to 0. Z: 0 = Byte transfer, 1 = Word transfer 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 Z Z Z Z Z 0 1 Execution time (Min) at 20 MHz Transfer destination address INC mode ........................ I/O to memory (DMADn+) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INT. 16 states Transfer destination address DEC mode .......................... I/O to memory (DMADn−) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INT. 16 states Transfer source address INC mode ................................. memory to I/O (DMADn) ← (DMASn+) DMACn ← DMACn − 1 if DMACn = 0 then INT. 16 states Transfer source address DEC mode ................................ memory to I/O (DMADn) ← (DMASn−) DMACn ← DMACn − 1 if DMACn = 0 then INT. 16 states Fixed address mode .................................................................... I/O to I/O (DMADn) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INT. 16 states Read-only mode ............................................................. for DRAM refresh Dummy ← (DMASn); Reads 4 bytes. DMASn ← DMASn + 4; Increments lower word only. DMACn ← DMACn − 1 14 states Counter mode ............................................................. for interrupt counter DMASn ← DMASn + 1 DMACn ← DMACn − 1 if DMACn = 0 then INT. 11 states (1.6 µs) (1.6 µs) (1.6 µs) (1.6 µs) (1.6 µs) (1.4 µs) (1.1 µs) Note 1: n: Corresponds to micro DMA channels 0 to 3. DMADn+/DMASn+: Post-increment (Increments register value after transfer.) DMADn−/DMASn−: Post-decrement (Decrement register value after transfer.) Note 2: Execution time: When setting source address/destination address area to 16-bit bus, 0 waits. Clock condition: fc = 20 MHz, Clock gear: 1 (fc) Note 3: Do not use the codes other than the above mentioned codes for transfer mode register. 93CW46A-40 2004-02-10 TMP93CW46A <Example for usage of read only mode (DRAM refresh)> * Clock condition System clock: High speed (fc) Clock gear: 1 (fc) When the hardware configuration is as follows: DRAM mapping size: 1 Mbyte DRAM data bus size: 8 bits DRAM mapping address range: 100000H to 1FFFFFH Set the following registers first; refresh is performed automatically. 1. 2. Register initial value setting LD XIX, 100000H LDC DMAS0, XIX LD A, LDC DMAM0, A … Mapping start address 00001010B … Read only mode (for DRAM refresh) Timer setting Set the timers so that interrupts are generated at intervals of 62.5 µs or less. 3. Interrupt controller setting Set the timer interrupt mask higher than the other interrupts mask. Write the above timer interrupt vector value in the micro DMA start vector register, DMA0V. (Operation description) The DRAM data bus is an 8-bit bus and the micro DMA is in read-only mode (4 bytes), so refresh is performed for four times per interrupt. When a 512 refresh/8 ms DRAM is connected, DRAM refresh is performed sufficiently if the micro DMA is started every 15.625 µs × 4 = 62.5 µs or less, since the timing is 15.625 µs/refresh. (Overhead) Each processing time by the micro DMA is 1.8 µs (18 states) at 20 MHz with an 8-bit data bus. In the above example, the high-speed micro DMA is started every 62.5 µs, 1.8 µs/62.5 µs = 0.0288; thus, the overhead is 2.88%. (Note) When the bus is released which must wait to accept the interrupt, DRAM refresh is not performed because of the micro DMA is generated by an interrupt. 93CW46A-41 2004-02-10 TMP93CW46A 3.4.3 Interrupt Controller Figure 3.4.4 is a block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the halt release signal circuit. Each interrupt channel (Total of 26 channels) in the interrupt controller has an interrupt request flag, interrupt priority setting register, and a register for storing the micro DMA start vector. The interrupt request flag is used to latch interrupt requests from peripheral devices. The flag is cleared to 0 at the following conditions. • At reset • When the CPU reads the interrupt vector after acceptance of interrupt • When the CPU executes an instruction that clears the interrupt of that channel (Writes 0 in <IxxC> of the interrupt priority setting register). For example, to clear the INT0 interrupt request, set the register after the DI instruction as follows. INTE0AD ← − − − −0− − − Zero-clears the INT0 flip-flop. The status of the interrupt request flag is detected by reading the clear bit. Detects whether there is an interrupt request for an interrupt channel. The interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., INTE0AD, INTE45, etc.) provided for each interrupt source. Interrupt levels to be set are from 1 to 6. Writing 0 or 7 as the interrupt priority disables the corresponding interrupt request. The priority of the non-maskable interrupt ( NMI pin, watchdog timer, etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance with the default priority. The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value <IFF2:0> set in the status register by the interrupt request signal with the priority value sent; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1 in the CPU SR<IFF2:0>. Interrupt requests where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. When interrupt processing is completed (After execution of the RETI instruction), the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR<IFF2:0>. The interrupt controller also has four registers used to store the micro DMA start vector. These are I/O registers. Writing the start vector of the interrupt source for the micro DMA processing (See Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD) prior to the micro DMA processing. 93CW46A-42 2004-02-10 INT4 INT5 INT6 INT7 INTT0 INTT1 INTT2 INTT3 INTTR4 INTTR5 INTTR6 INTTR7 INTRX0 INTTX0 INTRX1 INTTX1 INTAD INTRX2 INTTX2 INTRX3 INTTX3 INTRX4 INTTX4 INT0 INTWD NMI R R 93CW46A-43 RESET D5 D4 D3 D2 D1 D0 Q CLR D Dn + 3 Y1 Y2 Y3 Y4 Y5 Y6 6 V = 20H V = 24H 6 6 detect Match DMA0V DMA1V DMA2V DMA3V V = 2CH V = 30H V = 34H V = 38H V = 40H V = 44H V = 48H V = 4CH V = 50H V = 54H V = 58H V = 5CH V = 60H V = 64H V = 68H V = 6CH V = 70H V = 74H V = 78H V = 7CH V = 80H V = 84H V = 88H Interrupt request flip flop read Interrupt request clear Dn + 3 Interrupt request V read V = 28H Q Micro DMA start vector setting register RESET S Interrupt request F/F C B Dn + 1 Dn + 2 D Q CLR A Decoder Dn Priority setting register RESET Interrupt vecror V read Interrupt request flip flop S Q 4 1 6 1 26 Interrupt vector generation (Highest priority = 7) 1 2 Highest A priority 3 B interrupt 4 level select C 5 6 7 0 1 2 3 B A 4 input OR 7 Priority encoder Micro DMA channel priority encoder Interrupt controller 2 6 D2 D3 D4 D5 D6 D7 D0 D1 Interrupt vector read 3 INTRQ2 to 0 Interrupt request signal to CPU NMI Interrupt level detect RESET INT0 RESET 2 if INTRQ2 to 0 ≥ IFF2 to 0 then 1. 3 3 IFF2 to 0 Interrupt enable flag on CPU side CPU Micro DMA channel specification Micro DMA request Halt release During IDLE1 During STOP Interrupt request signal EI1 to EI7 DI TMP93CW46A Figure 3.4.4 Block Diagram of Interrupt Controller 2004-02-10 TMP93CW46A (1) Interrupt priority setting register Symbol Address INTE0AD 7 6 5 4 3 2 1 0 IADC IADM2 IADM1 IADM0 I0C I0M2 I0M1 I0M0 R/W 0070H W 0 0 R/W 0 0 0 0 I5C INTE45 I5M2 I5M1 R/W 0071H I5M0 W 0 0 I4C R/W 0 I7C I7M2 0 I7M1 I7M0 W 0 IT1C 0 0 I6C I6M2 R/W 0 IT1M2 0 IT1M1 IT1M0 W 0 0 0 0 INTEPW10 IT0C 0 IPW1M0 W 0 IT0M2 0 INTET54 0 0 IPW0M2 IT7C IT5M0 IT7M2 0 0 IT4C 0 IT7M1 0 IT7M0 INTES0 ITX0M2 0077H 0 IT6C INTES1 ITX1M2 0078H ITX0M0 0 IRX0C ITX2C ITX2M2 ITX1M0 0 IRX1C IRX1M2 ITX3C ITX3M2 ITX2M0 0 IRX2M2 INTES4 ITX4M2 005BH ITX3M0 0 IRX3M2 IxxC 0 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 0 0 IRX3M1 IRX3M0 W 0 0 ITX4M0 0 IRX4C 0 0 IRX4M2 IRX4M1 IRX4M0 R/W 0 W 0 0 INTTX4 IxxM2 0 0 0 0 1 1 1 1 IRX2M0 INTRX3 ITX4M1 0 IRX2M1 0 IRX3C 0 W 0 0 R/W 0 R/W 0 W INTTX3 ITX4C IRX1M0 INTRX2 ITX3M1 0 IRX1M1 0 IRX2C 0 W 0 0 R/W 0 R/W 005AH 0 W INTTX2 INTES3 IRX0M0 INTRX1 ITX2M1 0 0 W 0 0 W 0 IRX0M1 R/W 0 R/W 0059H 0 IRX0M2 INTTX1 INTES2 IT6M0 INTRX0 ITX1M1 0 0 W 0 0 W 0 IT6M1 R/W 0 R/W 0 IT6M2 INTTX0 ITX1C IT4M0 INTTR6 (TREG6) ITX0M1 0 0 W 0 0 W 0 IT4M1 R/W 0 R/W 0 IT4M2 INTTR7 (TREG7) ITX0C IPW0M0 INTTR4 (TREG4) W 0 IPW0M1 R/W 0 R/W 0076H 0 W INTTR5 (TREG5) INTET76 0 INTT2 (Timer 2/PWM0) W 0 IT0M0 0 IPW0C 0 IT5M1 R/W 0075H IT0M1 R/W 0 IT5M2 0 W INTT3 (Timer 3/PWM1) IT5C I6M0 INTT0 (Timer 0) IPW1M1 R/W 0074H I6M1 0 R/W 0 IPW1M2 0 W INTT1 (Timer 1) IPW1C 0 INT6 R/W 0073H I4M0 W 0 INT7 INTET10 I4M1 ←After reset INT4 R/W 0072H 0 ←Interrupt source I4M2 INT5 INTE67 0 INT0 INTAD ←Bit symbol ←Read/Write W 0 0 INTRX4 Function (Write) Prohibits interrupt request. Sets interrupt request level to “1”. Sets interrupt request level to “2”. Sets interrupt request level to “3”. Sets interrupt request level to “4”. Sets interrupt request level to “5”. Sets interrupt request level to “6”. Prohibits interrupt request. Function (Read) Indicates no interrupt request. Indicates interrupt request. Function (Write) Clears interrupt request flag. − − − − − Don’t care − − − − − Note 1: Read-modify-write is prohibited. Note 2: Note about clearing interrupt request flag The interrupt request flag of INTAD, INTRX0 to INTRX4 are not cleared by writing “0” to IxxC because of they are level interrupts. They can be cleared only by resetting or reading the conversion value or the receive buffer. 93CW46A-44 2004-02-10 TMP93CW46A (2) External interrupt control Interrupt Input Mode Control Register 7 6 5 4 3 2 1 0 IIMC Bit symbol I0IE I0LE NMIREE (007BH) Read/Write W W W After reset 0 1: INT0 input enable Function INT0 input enable (Note 1) 0 INT0 disable (P87 function only) 1 Input enable 0 0: INT0 edge mode 1: INT0 level mode 0 1: Can be accepted in NMI rising edge. NMI rising edge enable 0 1 Interrupt request generation at falling edge Interrupt request generation at rising/falling edge INT0 level enable (Note 2) 0 Rising edge detect interrupt 1 High level interrupt Note 1: The INT0 pin can also be used for standby release as described later. Even if the pin is not used for standby release, setting this register to “0” maintains the port function during standby mode. Note 2: Case of changing from level to edge for INT0 pin mode execution example: LD (INTE0AD), XXXX0000B ; INT0 disable, clean the request flag LD (IIMC), XXXXX10XB ; Change from level to edge LD (INTE0AD), XXXX0nnnB ; Set interrupt level “n” for INT0, clear the request flag Note 3: Read-modify-write is prohibited. Note 4: IIMC<Bit7:3> is always read as “1”. Note 5: See electrical characteristics in section 4 for external interrupt input pulse. Figure 3.4.5 Interrupt Input Mode Control Register Table 3.4.2 Setting of External Interrupt Pin Functions Interrupt Pin Name NMI − INT0 INT4 Setting Method Falling edge IIMC<NMIREE> = 0 Falling and rising edges IIMC<NMIREE> = 1 Rising edge IIMC<I0LE> = 0, <I0lE> = 1 High level IIMC<I0LE> = 1, <I0lE> = 1 Rising edge T4MOD<CAP12M1:0> = 0, 0 or 0, 1 or 1, 1 Falling edge T4MOD<CAP12M1:0> = 1, 0 P87 P80 INT5 P81 INT6 P84 INT7 Mode P85 Rising edge − Rising edge T5MOD<CAP34M1:0> = 0, 0 or 0, 1 or 1, 1 Falling edge T5MOD<CAP34M1:0> = 1, 0 Rising edge 93CW46A-45 − 2004-02-10 TMP93CW46A (3) Micro DMA start vector When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the bits 2 to 7 of the interrupt vector with each channel’s micro DMA start vector. When both match, the interrupt is processed in micro DMA mode for the channel whose value matched. If the interrupt vector matches more than two channel, the channel with the lower channel number has a higher priority. Micro DMA 0 Start Vector 7 DMA0V Bit symbol (007CH) Read/Write 6 5 4 3 DMA0V5 DMA0V4 DMA0V3 2 1 0 DMA0V2 DMA0V1 DMA0V0 0 0 0 W After reset 0 Function 0 0 Micro DMA channel 0 processed by matching bits 2 to 7 of the interrupt vector. Micro DMA 1 Start Vector 7 DMA1V Bit symbol (007DH) Read/Write 6 5 4 3 DMA1V5 DMA1V4 DMA1V3 2 1 0 DMA1V2 DMA1V1 DMA1V0 0 0 0 W After reset 0 Function 0 0 Micro DMA channel 1 processed by matching bits 2 to 7 of the interrupt vector. Micro DMA 2 Start Vector 7 DMA2V Bit symbol (007EH) Read/Write 6 5 4 3 2 1 0 DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 0 0 0 0 0 0 W After reset Function Micro DMA channel 2 processed by matching bits 2 to 7 of the interrupt vector. Micro DMA 3 Start Vector 7 DMA3V Bit symbol (007FH) Read/Write After reset Function Note: 6 5 4 3 DMA3V5 DMA3V4 DMA3V3 2 1 0 DMA3V2 DMA3V1 DMA3V0 0 0 0 W 0 0 0 Micro DMA channel 3 processed by matching bits 2 to 7 of the interrupt vector. Read-modify-write is not possible for DMA0V to DMA3V. Figure 3.4.6 Micro DMA Start Vector Register 93CW46A-46 2004-02-10 TMP93CW46A (4) Notes The instruction execution unit and the bus interface unit of this CPU operate independently of each other. Therefore, if the instruction used to clear an interrupt request flag of an interrupt is fetched before the interrupt is generated, it is possible that the CPU might execute the fetched instruction to clear the interrupt request flag while reading the interrupt vector after accepting the interrupt. To avoid the above occurring, clear the interrupt request flag by entering the instruction to clear the flag after the DI instruction. In the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing instruction and following more than one instruction are executed. When EI instruction is placed immediately after clearing instruction, an interrupt becomes enable before interrupt request flags are cleared. In the case of changing the value of the interrupt mask register <IFF2:0> by execution of POR SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. 93CW46A-47 2004-02-10 TMP93CW46A 3.5 Functions of Ports The TMP93CW46A has 79 bits for I/O ports. These port pins have I/O functions for the built-in CPU and internal I/Os as well as general-purpose I/O port functions. Table 3.5.1 lists the function of each port pin. Table 3.5.2 lists I/O registers and specification. Table 3.5.1 Functions of Ports (R: ↑ = with programmable pull-up resistor ↓ = with programmable pull-down resistor) Port Name Pin Name Number of Pins Direction R Direction Setting Unit Pin Name for Built-in Function Port 0 P00 to P07 8 I/O − Bit AD0 to AD7 Port 1 P10 to P17 8 I/O − Bit AD8 to AD15/A8 to A15 Port 2 P20 to P27 8 I/O ↓ Bit A0 to A7/A16 to A23 Port 3 P30 P31 P32 P33 P34 P35 P36 P37 1 1 1 1 1 1 1 1 Output Output I/O I/O I/O I/O I/O I/O − − ↑ ↑ ↑ ↑ ↑ ↑ (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit P40 P41 P42 1 1 1 I/O I/O I/O ↑ ↑ ↓ Bit Bit Bit CS0 / CAS0 Port 5 P50 to P57 8 Input − (Fixed) AN0 to AN7 Port 6 P60 1 I/O ↑ Bit TXD2 P61 P62 P63 P64 P65 P66 P67 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O ↑ ↑ ↑ ↑ ↑ ↑ ↑ Bit Bit Bit Bit Bit Bit Bit RXD2 Port 7 P70 P71 P72 P73 1 1 1 1 I/O I/O I/O I/O ↑ ↑ ↑ ↑ Bit Bit Bit Bit TI0 TO1 TO2 TO3 Port 8 P80 P81 P82 P83 P84 P85 P86 P87 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ Bit Bit Bit Bit Bit Bit Bit Bit TI4/INT4 TI5/INT5 TO4 TO5 TI6/INT6 TI7/INT7 TO6 INT0 Port 9 P90 P91 P92 P93 P94 P95 P96 P97 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O ↑ ↑ ↑ ↑ ↑ ↑ − − Bit Bit Bit Bit Bit Bit Bit Bit TXD0 RXD0 PA0 to PA6 7 I/O − Bit PA7 1 I/O − Bit Port 4 Port A 93CW46A-48 RD WR HWR WAIT BUSRQ BUSAK R/ W RAS CS1 / CAS1 CS2 / CAS2 CTS2 /SCLK2 TXD3 RXD3 CTS3 /SCLK3 TXD4 RXD4 CTS0 /SCLK0 TXD1 RXD1 SCLK1 XT1 XT2 SCOUT 2004-02-10 TMP93CW46A Table 3.5.2 I/O Registers and Specification (1/2) Port Port 0 Name I/O Register Pn PnCR Input port Output port AD0 to AD7 bus Input port Output port AD8 to AD15 bus A8 to A15 output Input port (without PD) Input port (with PD) Output port A0 to A7 output A16 to A23 output Output port Outputs RD only when accessing external space Always outputs RD Output port Outputs WR only when accessing external space Input port (without PU) Input port (with PU) Output port HWR output WAIT input (without PU) WAIT input (with PU) BUSRQ input (without PU) × × × × × × × 1 0 × 1 1 × 1 0 × × 0 1 × × 0 1 0 0 1 × 0 1 0 1 0 0 1 0 1 BUSRQ input (with PU) 1 0 1 P35 BUSAK output × 1 1 P36 P37 R/ W output RAS output × × 1 1 1 1 P40 to P41 P40 Input port (without PU) Input port (with PU) Output port Input port (without PD) Input port (with PD) Output port (Note 1) CS0 output 0 1 × 1 0 × × 0 0 1 0 0 1 1 0 0 0 0 0 0 1 P00 to P07 Port 1 P10 to P17 Port 2 P20 to P27 Port 3 P30 P31 P32 to P37 P32 P33 P34 Port 4 Specification P42 PnFC None 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 None None 0 0 1 1 0 0 0 None 1 P41 CS1 output (Note 1) × 1 1 P42 CS2 output (Note 1) × 1 1 Port 5 P50 to P57 Port 6 P60 to P67 Input port AN0 to AN7 input (Note 2) Input port (without PU) Input port (with PU) Output port TXD2 output TXD3 output TXD4 output RXD2 input (without PU) RXD2 input (with PU) RXD3 input (without PU) RXD3 input (with PU) × × 0 1 × × × × 0 1 0 1 P60 P63 P66 P61 P64 None 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 None None X: Don’t care Note 1: CS/WAIT control registers BnCH<BnCAS> selects the wave form output from P40 to P42 pin, CS0 to CS2 or CAS0 to CAS2 . Note 2: The channel for AD converter input is selected by ADMOD2<ADCHn>. 93CW46A-49 2004-02-10 TMP93CW46A Table 3.5.3 I/O Registers and Specification (2/2) Port Port 6 Name P67 P62 P65 Port 7 P70 to P73 P70 Port 8 P71 P72 P73 P80 to P87 P80 P81 P84 P85 Port 9 P82 P83 P86 P87 (Note 3) P90 to P95 P90 P93 P91 P94 P92 P95 P96 to P97 Port A PA0 to PA7 PA7 Specification I/O Register Pn PnCR RXD4 input (without PU) RXD4 input (with PU) SCLK2 output CTS2 /SCLK2 input (without PU) 0 1 × 0 0 0 1 0 CTS2 /SCLK2 input (with PU) SCLK3 output CTS3 /SCLK3 input (without PU) 1 0 × 0 1 0 CTS3 /SCLK3 input (with PU) Input port (without PU) Input port (with PU) Output port TI0 input (without PU) TI0 input (with PU) TO1 output port TO2 output port TO3 output port Input port (without PU) Input port (with PU) Output port TI4/INT4 input (without PU) TI4/INT4 input (with PU) TI5/INT5 input (without PU) TI5/INT5 input (with PU) TI6/INT6 input (without PU) TI6/INT6 input (with PU) TI7/INT7 input (without PU) TI7/INT7 input (with PU) TO4 output TO5 output TO6 output INT0 input (without PU) INT0 input (with PU) Input port (without PU) Input port (with PU) Output port TXD0 output TXD1 output RXD0 input (without PU) RXD0 input (with PU) RXD1 input (without PU) RXD1 input (with PU) SCLK0 output CTS0 /SCLK0 input (without PU) CTS0 /SCLK0 input (with PU) SCLK1 output SCLK1 input (without PU) SCLK1 input (with PU) Input port Output port (Note 4) XT1/2 (Note 5) Input port Output port SCOUT output port (Note 6) 1 0 0 1 × 0 1 × × × 0 1 × 0 1 0 1 0 1 0 1 × × × 0 1 0 1 × × × 0 1 0 1 × 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 × 0 1 × × × × × × 1 0 0 0 1 0 0 1 1 PnFC None 1 0 0 1 0 0 0 0 0 None 1 1 1 0 0 0 None None None None 1 1 1 None 0 0 0 1 1 None None 1 0 0 1 0 0 None None Note 3: Using P87 pin as INT0, IIMC register has to be set enable interrupt. Note 4: Using P96/P97 as output port, output is through the open-drain buffer. Note 5: Using P96/P97 as XT1 to XT2, SYSCR0 register has to be set enable oscillation. Note 6: Using PA7 as SCOUT, PAFC register has to be written suitable value. 93CW46A-50 2004-02-10 TMP93CW46A Resetting makes the port pins listed below function as general-purpose I/O ports. I/O pins programmable for input or output are set to input ports except P96/XT1, P97/XT2. To set port pins for built-in functions, a program is required. Note about the Bus Release and programmable pull-up/pull-down I/O ports. When the bus is released ( BUSAK = “0”), the output buffer of AD0 to AD15, A0 to A23, control signal ( RD , WR , HWR , R/ W , RAS , CS0 / CAS0 to CS2 / CAS2 ) is off and their state become high impedance. However, the output of built-in programmable pull-up/pull-down resistors are kept before the bus is released. These programmable pull-up/pull-down resistors can be selected ON/OFF by programmable when they are used as the input ports. The case of they are used as the output ports, they can not be selected ON/OFF by programmable. Table 3.5.4 shows the pin state when the bus is released. Table 3.5.4 The Pin State (when the Bus is Released) The Pin State (when the Bus is Released) Pin Name Used as the Port Used as the Function P00 to P07 (AD0 to AD7) P10 to P17 (AD8 to AD15/A8 to A15) The state is not changed. (Do not become to high impedance (High-Z).) Become high impedance (High-Z). P30 ( RD ) P31 ( WR ) Becomes high impedance (High-Z). Becomes high impedance (High-Z). P32 ( HWR ) P37 ( RAS ) The output buffer is OFF. The programmable pull-up resistor is ON the case of only the output latch is equal to “1”. The output buffer is OFF. The programmable pull-up resistor is ON irrespective of the output latch. P36 (R/ W ) P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) The output buffer is OFF. The programmable pull-up resistor is ON the case of only the output latch is equal to “1”. The output buffer is OFF. There is a possibility that the programmable pull-up resistor is ON or OFF due to the bus releasing timing irrespective of the output latch. P42 ( CS2 / CAS2 ) The output buffer is OFF. The programmable pull-down resistor is ON the case of only the output latch is equal to “0”. The output buffer is OFF. There is a possibility that the programmable pull-down resistor is ON or OFF due to the bus releasing timing irrespective of the output latch. The state is not changed. (Do not become to high impedance (High-Z).) The output buffer is OFF. The programmable pull-down resistor is ON the case of only the output latch is equal to “0”. P20 to P27 (A16 to A23) 93CW46A-51 2004-02-10 TMP93CW46A Figure 3.5.1 shows the example of the external interface circuit the case of the bus releasing function is used. When the bus is released, both internal memory and internal I/O can not be accessed. But the internal I/O continues to operate. So, the watchdog timer also continues to run. Therefore, be careful about bus releasing time and setting the detection time of the WDT. P35 ( BUSAK ) About 3 to 5 kΩ P42 ( CS2 ) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P36 ( R / W ) P37 ( RAS ) P40 ( CS0 ) P41 ( CS1 ) System control bus P20 (A16) to P27 (A23) Address bus (A23 to A16) Figure 3.5.1 Example of the Interface Circuit (The case of using bus releasing function) The above circuit is necessary to fix the signal level in the case of the bus is released. Resetting sets P30 ( RD ), P31 ( WR ) to output, P40 ( CS0 ), P41 ( CS1 ), P32 ( HWR ), P36 ( R / W ), P37 ( RAS ), and P35 ( BUSAK ) to input with pull-up resistor, P42 ( CS2 ) and P20 to P27 (A16 to A23) to input with pull-down resistor. The above circuit is necessary to fix the signal level after reset because of the external pull-up resistor collisions with the internal pull-down resistor. The value of this external pull-up resistor must be 3 to 5 kΩ. (The value of the internal pull-down resistor is about 50 to 150 kΩ.) P20 to P27 (A16 to A23) also needs circuit like P42 ( CS2 ) to fix the signal level. But for the P20 to P27 (A16 to A23) which does not have means “L” is active, add pull-down directly like above circuit. 93CW46A-52 2004-02-10 TMP93CW46A 3.5.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P0CR. Resetting resets all bits of P0CR to 0 and sets port 0 to input mode. In addition to functioning as a general-purpose I/O port, port 0 also functions as an address data bus (AD0 to AD7). To access external memory, port 0 functions as an address data bus (AD0 to AD7) and all bits of the control register P0CR are cleared to 0. Reset Direction control (on bit basis) Internal data bus P0CR write Output latch Port 0 P00 to P07 (AD0 to AD7) Output buffer S P0 write S B Selector A A P0 read B Selector Figure 3.5.2 Port 0 93CW46A-53 2004-02-10 TMP93CW46A 3.5.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P1CR and function register P1FC. Reset all bits of output latch P1, control register P1CR, and function register P1FC to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 also functions as an address data bus (AD8 to AD15) or an address bus (A8 to A15). Reset Direction control (on bit basis) P1CR write Function control (on bit basis) Internal data bus P1FC write Output latch Port 1 Output buffer P1 write S P10 to P17 (AD8 to AD15/A8 to A15) B Selector A P1 read Figure 3.5.3 Port 1 93CW46A-54 2004-02-10 TMP93CW46A Port 0 Register 4 7 6 5 P07 P06 P05 2 1 0 P03 P02 P01 P00 P0 Bit symbol (0000H) Read/Write R/W After reset Input mode (Output latch register becomes undefined.) P0CR Bit symbol (0002H) Read/Write After reset Function P04 3 Port 0 Control Register 5 4 3 7 6 P07C P06C P05C P04C 0 0 0 0 2 1 0 P03C P02C P01C P00C 0 0 0 0 R/W 0: Input 1: Output (At external access, Port 0 becomes AD7 to AD0 and P0CR is cleared to 0.) Port 0 I/O setting Port 1 Register 4 7 6 5 P17 P16 P15 Input Output 3 2 1 0 P13 P12 P11 P10 P1 Bit symbol (0001H) Read/Write R/W After reset Input mode (Output latch register is cleared to “0”.) P1CR Bit symbol (0004H) Read/Write After reset Port 1 Control Register 5 4 3 7 6 P17C P16C P15C P14C 0 0 0 0 Bit symbol (0005H) Read/Write After reset Function 2 1 0 P13C P12C P11C P10C 0 0 0 0 2 1 0 P13F P12F P11F P10F 0 0 0 0 R/W Function P1FC P14 0 1 <<See P1FC below.>> 7 6 P17F P16F Port 1 Function Register 5 4 3 P15F P14F R/W 0 0 0 0 P1FC/P1CR = 00: Input 01: Output 10: AD15 to AD8 11: A15 to A8 Port 1 function setting Read-modify-write is prohibited for registers P0CR, P1CR, and P1FC. P1FC<P1XF> 0 1 0 Input port Address data bus (AD15 to AD8) 1 Output port Address bus (A15 to A8) P1CR <P1XC> Note: <P1XF> is bit X in register P1FC; <P1XC>, in register P1CR. Figure 3.5.4 Registers for Ports 0 and 1 93CW46A-55 2004-02-10 TMP93CW46A 3.5.3 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register P2CR and function register P2FC. Resetting resets all bits of output latch P2, control register P2CR and function register P2FC to 0. It also sets port 2 to input mode and connects a pull-down resistor. In addition to functioning as a general-purpose I/O port, port 2 also functions as an address data bus (A0 to A7) and an address bus (A16 to A23). Using port 2 as address bus (A0 to A7 or A16 to A23), write “1” to output latches and be off the programmable pull-down resistors. A16 to A23 B Selector A0 to A7 A S Reset Direction control (on bit basis) P2CR write Internal data bus Function control (on bit basis) S P2FC write B Selector Output latch Port 2 P20 to P27 (A0 to A7/ A16 to A23) A Output buffer P2 write N-ch Programmable S B pull down Selector A P2 read Figure 3.5.5 Port 2 93CW46A-56 2004-02-10 TMP93CW46A Port 2 Register 4 7 6 5 P27 P26 P25 2 1 0 P23 P22 P21 P20 P2 Bit symbol (0006H) Read/Write R/W After reset Input mode (Output latch register is cleared to “0”.) P2CR Bit symbol (0008H) Read/Write After reset Port 2 Control Register 5 4 3 7 6 P27C P26C P25C P24C 0 0 0 0 Bit symbol (0009H) Read/Write After reset Function 2 1 0 P23C P22C P21C P20C 0 0 0 0 W Function P2FC P24 3 <<See P2FC below.>> Port 2 Function Register 5 4 3 7 6 P27F P26F P25F P24F 0 0 0 0 2 1 0 P23F P22F P21F P20F 0 0 0 0 W P2FC/P2CR = 00: Input 01: Output 10: A7 to A0 11: A23 to A16 Port 2 function setting P2FC<P2XF> 0 1 0 Input port Address data bus (A7 to A0) 1 Output port Address bus (A23 to A16) P2CR <P2XC> Note: <P2XF> is bit X in register P2FC; <P2XC>; in register P2CR. To set as an address bus A23 to A16, set P2FC after setting P2CR. Note 1: Read-modify-write is prohibited for registers P2CR and P2FC. Note 2: When port P2 is used in the input mode, P2 register controls the built-in pull-down resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-down resistor may be depended on the states of the input pin. Figure 3.5.6 Registers for Port 2 93CW46A-57 2004-02-10 TMP93CW46A 3.5.4 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR and function register P3FC. Resetting resets all bits of output latch P3, control register P3CR (Bits 0 and 1 are unused), and function register P3FC to 0. Resetting also outputs 1 from P30 and P31, sets P32 to P37 to input mode, and connects a pull-up resistor. In addition to functioning as a general-purpose I/O port, port 3 also functions as an I/O for the CPU’s control/status signal. When P30 pin is defined as RD signal output mode (<P30F> = 1), clearing the output latch register <P30> to 0 outputs the RD strobe (Used for the pseudo static RAM) from the P30 pin even when the internal address area is accessed. If the output latch register <P30> remains 1, the RD strobe signal is output only when the external address area is accessed. 93CW46A-58 2004-02-10 TMP93CW46A Reset Function control (on bit basis) Internal data bus P3FC write S Output latch S A Output buffer P30 ( RD ) P31 ( WR ) Selector P3 write B RD , WR P3 read Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P-ch Programmable pull up Internal data bus P3FC write S Output latch A P32 ( HWR ) S Output buffer Selector P3 write P35 ( BUSAK ) P36 (R/ W ) P37 ( RAS ) B HWR , BUSAK S , R/ W , RAS B Selector A P3 read Figure 3.5.7 Port 3 (P30, P31, P32, P35, P36, P37) 93CW46A-59 2004-02-10 TMP93CW46A Reset Direction control (on bit basis) P3CR write P-ch Internal data bus S Output latch Programmable pull up P33 ( WAIT ) Output buffer P3 write S B Selector A P3 read Internal WAIT Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P-ch Internal data bus P3FC write S Output latch Programmable pull up P34 ( BUSRQ ) P3 write S B Selector A P3 read Internal BUSRQ Figure 3.5.8 Port3 (P33, P34) 93CW46A-60 2004-02-10 TMP93CW46A P3 Bit symbol (0007H) Read/Write After reset Port 3 Register 4 7 6 5 P37 P36 P35 P34 3 2 1 0 P33 P32 P31 P30 1 1 1 1 R/W 1 1 1 1 Input mode (pulled up) P3CR Bit symbol (000AH) Read/Write After reset Output mode Port 3 Control Register 5 4 3 7 6 P37C P36C P35C 0 0 0 2 1 P34C P33C P32C 0 0 0 0 W 0: Input 1: Output I/O setting Output mode 0 Input 1 Output P3FC Bit symbol (000BH) Read/Write After reset Function Port 3 Function Register 5 4 3 7 6 P37F P36F P35F P34F 0 0 0 0 0: Port 1: BUSAK 0: Port 1: BUSRQ 2 1 0 P32F P31F P30F W 0: Port 1: RAS 0: Port 1: R/ W 0 0: Port 1: HWR 0 0 0: Port 1: WR 0: Port 1: RD P30 ( RD ) function setting <P30> BUSRQ setting 0 1 “0” output Always RD output (for pseudo SRAM) “1” output RD output only for external access <P30F> P3FC<P34F> 1 P3CR<P34C> 0 0 1 BUSAK setting P3FC<P35F> 1 P3CR<P35C> 1 P31 ( WR ) function setting <P31> 0 <P31F> R/ W setting 0 P3FC<P36F> 1 P3CR<P36C> 1 RAS setting 1 1 “0” output “1” output WR output only for external access HWR setting P3FC<P37F> 1 P3FC<P32F> 1 P3CR<P37C> 1 P3CR<P32C> 1 Note 1: Read-modify-write is prohibited for registers P3CR and P3FC. Note 2: When port P3 is used in the input mode, P3 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: When P33/ WAIT pin is used as a WAIT pin, set P3CR<P33C> to “0” and chip select/wait control register<BnW1:0> to “10”. Figure 3.5.9 Registers for Port 3 93CW46A-61 2004-02-10 TMP93CW46A 3.5.5 Port 4 (P40 to P42) Port 4 is a 3-bit general-purpose I/O port. I/O can be set on a bit basis using control register P4CR and function register P4FC. Resetting does the following: • Sets the P40 and P42 output latch registers to 1. • Resets all bits of the P42 output latch register, the control register P4CR, and the function register P4FC to 0. • Sets P40 and P41 to input mode and connects a pull-up resistor. • Sets P42 to input mode and connects a pull-down resistor. In addition to functioning as a general-purpose I/O port, port 4 also functions as a chip select output signal ( CS0 to CS2 or CAS0 to CAS2 ). 93CW46A-62 2004-02-10 TMP93CW46A Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P-ch Programmable pull up Internal data bus P4FC write S Output latch P40 ( CS0 / CAS0 ), S A Output buffer P41 ( CS1 / CAS1 ) Selector P4 write B CS0 / CAS0 S , CS1 / CAS1 B Selector A P4 read Reset Direction control (on bit basis) P4CR write Function control (on bit basis) Internal data bus P4FC write R Output latch S A P42 ( CS2 / CAS2 ) Output buffer Selector P4 write N-ch B CS2 / CAS2 S Programmable pull down B Selector A P4 read Figure 3.5.10 Port 4 93CW46A-63 2004-02-10 TMP93CW46A 7 P4 Bit symbol (000CH) Read/Write 6 5 Port 4 Register 4 3 2 P42 After reset 0 (Pull down) (000EH) Read/Write P41 P40 1 (Pull up) 1 (Pull up) Input mode 7 Bit symbol 0 R/W Function P4CR 1 6 Port 4 Control Register 5 4 3 2 1 0 P42C P41C P40C W After reset 0 0 0 0: Input 1: Output Function I/O setting 7 P4FC Bit symbol (0010H) Read/Write 6 Port 4 Function Register 5 4 3 0 Input 1 Output 2 1 0 P42F P41F P40F W After reset 0 0 0: Port Function 0 1 0 1 0 1 0 1: CS / CAS Port (P40) CS0 / CAS0 Port (P41) CS1 / CAS1 Port (P42) CS2 / CAS2 Note 1: Read-modify-write is prohibited for registers P4CR and P4FC. Note 2: When port P4 is used in the input mode, P4 register controls the built-in pull-up/pull-down resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up/pull-down resistor may be depended on the states of the input pin. Note 3: To output chip select signal ( CS0 / CAS0 to CS2 / CAS2 ), set the corresponding bits of the control register P4CR and the function register P4FC to “1”. Chip select/wait controller (B0CS, B1CS, B2CS) registers select the function of CS / CAS . Note 4: P4<Bit7:3> is always read as “1”. Figure 3.5.11 Registers for Port 4 93CW46A-64 2004-02-10 TMP93CW46A 3.5.6 Port 5 (P50 to P57) Port 5 is an 8-bit input port, also used as an analog input pin for the internal AD Converter. Internal data bus Port 5 P50 to P57 (AN0 to AN7) Port 5 read Conversion result register AD converter Channel selector AD read Figure 3.5.12 Port 5 Port 5 Register 4 7 6 5 P57 P56 P55 3 2 1 0 P52 P51 P50 Bit symbol (000DH) Read/Write R After reset Input mode Note: P54 P53 P5 The input channel selection of AD converter is set by AD converter mode register ADMOD2. Figure 3.5.13 Register for Port 5 93CW46A-65 2004-02-10 TMP93CW46A 3.5.7 Port 6 (P60 to P67) Port 60 to 67 are 8-bit general-purpose I/O ports. I/O can be set on bit basis. Resetting sets port 6 as an input port and connects a pull-up resistor. It also sets all bits of the output latch to 1. In addition to functioning as a general-purpose I/O port, port 60 to 67 also function as serial channels 2, 3, 4 I/O functions. Writing 1 in the corresponding bit of the port 6 function register (P6FC) enables the respective functions. Resetting resets the function register P6FC to 0, and sets all bits to ports. (1) Port 60, 63, 66 (TXD2, TXD3, TXD4) In addition to functioning as a general-purpose I/O port, port 60, 63, 66 also function as serial channel TXD output pins. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P-ch Internal data bus P6FC write S Output latch Programmable pull up A S P60 (TXD2) P63 (TXD3) Selector P6 write TXD2, TXD3, TXD4 P66 (TXD4) B S B Selector A P6 read Figure 3.5.14 Port 60, 63, 66 93CW46A-66 2004-02-10 TMP93CW46A (2) Port 61, 64, 67 (RXD2, RXD3, RXD4) In addition to functioning as a general-purpose I/O port, port 61, 64, 67 also function as serial channel RXD input pins. Reset Direction control (on bit basis) P-ch Programmable pull up Internal data bus P6CR write S Output latch P61 (RXD2) P64 (RXD3) P67 (RXD4) S P6 write B Selector P6 read A RXD2, RXD3, RXD4 Figure 3.5.15 Port 61, 64, 67 (3) Port 62, 65 ( CTS2 /SCLK2, CTS3 /SCLK3) In addition to functioning as a general-purpose I/O port, port 62, 65 also function as serial channel 2, 3 CTS input pins or SCLK input/output pins. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) Internal data bus P6FC write S Output latch A P-ch Programmable pull up S Selector P6 write SCLK2, SCLK3 B P62 (SCLK2/ CTS2 ) P65 (SCLK3/ CTS3 ) S B Selector P6 read A CTS2 , CTS3 SCLK2, SCLK3 Figure 3.5.16 Port 62, 65 93CW46A-67 2004-02-10 TMP93CW46A P6 Bit symbol (0012H) Read/Write After reset P6CR Bit symbol (0014H) Read/Write After reset Port 6 Register 4 7 6 5 P67 P66 P65 P64 3 2 1 0 P63 P62 P61 P60 1 1 1 R/W 1 1 1 1 1 Input mode (Pull up) Port 6 Control Register 5 4 3 7 6 P67C P66C P65C 0 0 0 P64C P63C 2 1 0 P62C P61C P60C 0 0 0 W Function 0 0 0: Input 1: Output Port 6 I/O setting 7 P6FC Bit symbol (0016H) Read/Write After reset Function Port 6 Function Register 5 4 3 6 P66F P65F P63F 0 0 W 0 0: Port 1: TXD4 2 P62F 0 Input 1 Output 1 0 P60F W 0: Port 1: SCLK3 0: Port 1: TXD3 W 0 0: Port 1: SCLK2 0 0: Port 1: TXD2 P60 TXD2 output setting P6FC<P60F> 1 P6CR<P60C> 1 P62 SCLK2 output setting P6FC<P62F> 1 P6CR<P62C> 1 P63 TXD3 output setting P6FC<P63F> 1 P6CR<P63C> 1 P65 SCLK2 output setting P6FC<P65F> 1 P6CR<P65C> 1 P66 TXD4 output setting P6FC<P66F> 1 P6CR<P66C> 1 Note 1: Read-modify-write is prohibited for registers P6CR and P6FC. Note 2: When port P6 is used in the input mode, P6 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: P61/RXD2, P64/RXD3, P67/RXD4 pins have no port/function switch registers. When using as input ports, the serial receive data is input to SIO. Figure 3.5.17 Registers for Port 6 93CW46A-68 2004-02-10 TMP93CW46A Port 7 (P70 to P73) Port 7 is a 4-bit general-purpose I/O port. I/O can be set on bit basis. Resetting sets port 7 as an input port and connects a pull-up resistor. In addition to functioning as a general-purpose I/O port, port 70 also functions as an input clock pin TI0 of an 8-bit timer 0, port 71 as an 8-bit timer output (TO1), port 72 as a PWM0 output (TO2), and port 73 as a PWM1 output (TO3) pin. Writing 1 in the corresponding bit of the port 7 function register (P7FC) enables output of the timer. Resetting resets the function register P7CR, P7FC to 0, and sets all bits to ports. Reset Direction control (on bit basis) P7CR write P-ch S Output latch Programmable pull up P70 (TI0) P7 write S B Selector P7 read A TI0 Reset Internal data bus 3.5.8 Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write S Output latch P-ch A Programmable pull up S P71 to P73 Selector (TO1 to TO3) P7 write B Timer F/F OUT TO1: Timer 1 TO2: Timer 2 TO3: Timer 3 B Selector P7 read S A Figure 3.5.18 Port 7 93CW46A-69 2004-02-10 TMP93CW46A 7 P7 Bit symbol (0013H) Read/Write 6 5 Port 7 Register 4 3 2 P73 P72 1 After reset (0015H) Read/Write P71 P70 1 1 1 Input mode (Pull up) 7 Bit symbol 0 R/W Function P7CR 1 6 Port 7 Control Register 5 4 3 2 1 0 P73C P72C P71C P70C 0 0 0 0 W After reset Function 0: Input 1: Output Port 7 I/O setting 7 P7FC Bit symbol (0017H) Read/Write 6 Port 7 Function Register 5 4 3 P73F 0 Input 1 Output 2 1 P72F P71F 0 W After reset 0 Function 0: Port 1: TO3 0 0 0: Port 1: TO2 0: Port 1: TO1 Setting P71 as TO1 P7FC<P71F> 1 P7CR<P71C> 1 Setting P72 as TO2 P7FC<P72F> 1 P7CR<P72C> 1 Setting P73 as TO3 P7FC<P73F> 1 P7CR<P73C> 1 Note 1: Read-modify-write is prohibited for registers P7CR and P7FC. Note 2: When port P7 is used in the input mode, P7 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: P70/TI0 pin does not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted to 8-bit timer 0 as a timer input 0 (T10). Note 4: P4<Bit7:4> is always read as “1”. Figure 3.5.19 Registers for Port 7 93CW46A-70 2004-02-10 TMP93CW46A 3.5.9 Port 8 (P80 to P87) Port 8 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port 8 as an input port and connects a pull-up resistor. It also sets all bits of the output latch register P8 to 1. In addition to functioning as a general-purpose I/O port, port 8 also functions as an input for 16-bit timer 4 and 5 clocks, an output for 16-bit timer F/F 4, 5, and 6 output, and an input for INT0. Writing “1” in the corresponding bit of the port 8 function register (P8FC) enables those functions. Resetting resets the function register P8CR, P8FC to “0” and sets all bits to ports. (1) P80 to P86 Reset Direction control (on bit basis) P-ch Programmable pull up P8CR write S Output latch S P8 write P80 (TI4/INT4) P81 (TI5/INT5) P84 (TI6/INT6) P85 (TI7/INT7) B Selector TI4, TI5 TI6, TI7 A P8 read Reset Internal data bus Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch P8 write P-ch A S Selector Timer F/F OUT TO4: Timer 4 TO5: Timer 4 TO6: Timer 5 Programmable pull up B P82 (TO4) P83 (TO5) P86 (TO6) B Selector P8 read S A Figure 3.5.20 Port 8 (P80 to P86) 93CW46A-71 2004-02-10 TMP93CW46A (2) P87 (INT0) Port 87 is a general-purpose I/O port, and also used as an INT0 pin for external interrupt request input. Reset Internal data bus Direction control (on bit basis) P-ch Programmable pull up P8CR write S Output latch P8 write P87 (INT0) S B Selector P8 read A Level/edge detect INT0 interrupt IIMC<I0IE> IIMC<I0LE> Figure 3.5.21 Port 87 93CW46A-72 2004-02-10 TMP93CW46A P8 Bit symbol (0018H) Read/Write After reset Port 8 Register 4 7 6 5 P87 P86 P85 P84 3 2 1 0 P83 P82 P81 P80 1 1 1 1 R/W 1 1 1 1 Input mode (Pull up) P8CR Bit symbol (001AH) Read/Write After reset Port 8 Control Register 5 4 3 7 6 P87C P86C P85C P84C 0 0 0 0 2 1 0 P83C P82C P81C P80C 0 0 0 0 W Function 0: Input 1: Output Port 8 I/O setting 7 6 Port 8 Function Register 5 4 3 2 P8FC Bit symbol P86F P83F P82F (001CH) Read/Write W W W After reset 0 0 Function 0: Port 1: TO6 0: Port 1: TO5 0 Input 1 Output 1 0 0 0: Port 1: TO4 Setting P82 as TO4 P8FC<P82F> 1 P8CR<P82C> 1 Setting P83 as TO5 P8FC<P83F> 1 P8CR<P83C> 1 Setting P84 as TO6 P8FC<P86F> 1 P8CR<P86C> 1 Note 1: Read-modify-write is prohibited for registers P8CR and P8FC. Note 2: When port P8 is used in the input mode, P8 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: P80/T14, P81/T15, P84/T16, P85/T17 pins do not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted to 16-bit timer as a time input. When P87/INT0 pin is used as an INT0 pin, set P8CR<P87C> to “0” and IIMC<I0IE> to “1”. Figure 3.5.22 Registers for Port 8 93CW46A-73 2004-02-10 TMP93CW46A Port 9 (P90 to P97) • Port 90 to 95 Port 90 to 95 is a 6-bit general-purpose I/O port. I/Os can be set on a bit basis. Resetting sets P90 to P95 to an input port and connects a pull-up resistor. It also sets all bits of the output latch register to 1. In addition to functioning as a general-purpose I/O port, P90 to P95 can also function as an I/O for serial channels 0 and 1. Writing “1” in the corresponding bit of the port 9 function register (P9FC) enables those functions. Resetting resets the function register P9CR, P9FC to “0” and sets all bits to ports. • Port 96 to 97 Port 96 to 97 is a 2-bit general-purpose I/O port. I/Os can be set on a bit basis. The output buffer for P96 to P97 is an open drain type buffer. Resetting sets output latch and control registers to “1” and outputs high-impedance (High-Z). In addition to functioning as a general-purpose I/O port, P96 to P97 can also function as a low-frequency oscillator connecting pin (XT1, XT2) for dual clock mode. The dual clock function can be set by programming system clock control register SYSCR0, 1. (1) Port 90, 93 (TXD0/TXD1) Ports 90 and 93 also function as serial channel TXD output pins in addition to I/O ports. They have a programmable open-drain function. Reset Direction control (on bit basis) P9CR write Internal data bus 3.5.10 Function control (on bit basis) P9FC write S Output latch P-ch A Programmable pull up S P90 (TXD0) P93 (TXD1) Selector TXD0, TXD1 P9 write Open drain possible B S B ODE<ODE1:0> Selector P9 read A Figure 3.5.23 Ports 90 and 93 93CW46A-74 2004-02-10 TMP93CW46A (2) Port 91, 94 (RXD0, RXD1) Port 91and 94 are I/O ports, and also used as RXD input pins for serial channels. Reset Direction control (on bit basis) P-ch Internal data bus P9CR write S Output latch Programmable pull up P91 (RXD0) P94 (RXD1) S B P9 write Selector P9 read A RXD0, RXD1 Figure 3.5.24 Ports 91 and 94 (3) Port 92 ( CTS0 /SCLK0) Port 92 is an I/O port, and also used as a CTS0 input pin and as a SCLK0 I/O pin for serial channel 0. Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P-ch Programmable pull up P9FC write S Output latch A S P92 (SCLK0/ CTS0 ) Selector SCLK0 OUT P9 write B S B Selector P9 read A CTS0 SCLK0 Figure 3.5.25 Ports 92 93CW46A-75 2004-02-10 TMP93CW46A (4) Port 95 (SCLK1) Port 95 is a general-purpose I/O port. It is also used as a SCLK1 I/O pin for serial channel 1. Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P-ch Programmable pull up P9FC write S Output latch A S P95 (SCLK1) Selector SCLK1 OUT P9 write B S B Selector P9 read A SCLK1 Figure 3.5.26 Port 95 93CW46A-76 2004-02-10 TMP93CW46A (5) Port 96 (XT1), 97(XT2) Port 96, 97 is general purpose I/O ports. It is also used as a low-frequency oscillator connecting pin. Reset Bus6 S Direction control (on bit basis) Low-frequency oscillation enable P9CR write S Output latch Bus6 P96 (XT1) Output buffer (Open-drain output) P9 write Internal data bus S B Bus6 Selector A P9 read (ON at “1”) Bus7 S Direction control (on bit basis) P9CR write Bus7 S Output latch P97 (XT2) Output buffer (Open-drain output) P9 write Low-frequency clock (fs) S Bus7 B Selector A P9 read Figure 3.5.27 Port 96 to 97 93CW46A-77 2004-02-10 TMP93CW46A P9 Bit symbol (0019H) Read/Write After reset Port 9 Register 4 7 6 5 P97 P96 P95 P94 3 2 1 0 P93 P92 P91 P90 1 1 1 1 R/W 1 1 1 1 Output mode P9CR Bit symbol (001BH) Read/Write After reset Input mode Port 9 Control Register 5 4 3 7 6 P97C P96C P95C P94C 1 1 0 0 2 1 0 P93C P92C P91C P90C 0 0 0 0 W Function 0: Input 1: Output Port 9 I/O setting Note: Port 96, 97’s output buffer is an open drain output type. 7 6 Port 9 Function Register 5 4 3 2 0 Input 1 Output 1 0 P9FC Bit symbol P95F P93F P92F P90F (001DH) Read/Write W W W W After reset 0 0 0 Function 0: Port 1: SCLK1 0: Port 1: TXD1 0 0: Port 1: SCLK0 0: Port 1: TXD0 P90 TXD0 output setting (Note) P9FC<P90F> 1 P9CR<P90C> 1 P92 SCLK0 output setting P9FC<P92F> 1 P9CR<P92C> 1 P93 TXD1 output setting (Note) P9FC<P93F> 1 P9CR<P93C> 1 P95 SCLK1 output setting P9FC<P95F> 1 P9CR<P95C> 1 Note 1: Read-modify-write is prohibited for registers P9CR and P9FC. Note 2: When port P9 is used in the input mode, P9 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Port 96 and 97 have no built-in pull-up resistors. Note 3:To set the TXD pin to open drain, write “1” in bit 0 (for TXD0 pin) or 1 (for TXD1) pin of the ODE register. P91/RXD0, P94/RXD1 pins have no port/function switch registers. When using as input port, serial receive data is input to SIO. Note 4 Notes on using low-frequency oscillation circuit To connect a low-frequency resonator to port 96, 97, it is necessary to set the following procedures to reduce the consumption power supply. (connecting to a resonator) Set P9CR<P96C, P97C> = “11”, P9<P96, P97> = “00”. (connection to an oscillator) Set P9CR<P96C, P97C> = “11”, P9<P96, P97> = “10”. Note 5: When ports 96 and 97 is used in the output mode, input gate in operation. Set output to “L” or attach pull-up on pin to reduce the consumption of power, before the HALT instruction is executed. Figure 3.5.28 Register for Port 9 93CW46A-78 2004-02-10 TMP93CW46A Port A (PA0 to PA7) Port A is an 8-bit general-purpose I/O port. Port A0 to A5 is possible to output large current and drive LED directly. I/Os can be set on a bit basis by control register PACR. After reset, PACR is reset to “0” and port A is set to an input port. In addition to functioning as a general-purpose I/O port (only PA7), PA7 can also functions as a clock output pin. The output clock is fFPH or fSYS that is selected by the CKOCR<SCOSEL>. This function is enabled by setting PACR<PA7C> and CKOCR<SCOEN> to “1”. Reset R Direction Control (on bit basis) PACR write Internal data bus 3.5.11 S Output latch PA0 to PA6 PA write S B Selector A PA read Figure 3.5.29 Port A0 to A6 93CW46A-79 2004-02-10 TMP93CW46A Reset R Direction control (on bit basis) Bus 7 PACR write R Function control (on bit basis) Internal data bus Bus 2 CKOCR write S Output latch Bus 7 S A Selector PA7 (SCOUT) B PA write S B Bus 7 Selector A PA read fFPH A fSYS B Selector S CKOCR<SCOSEL> Figure 3.5.30 Port A7 93CW46A-80 2004-02-10 TMP93CW46A PA Bit symbol (001EH) Read/Write Port A Register 4 7 6 5 PA7 PA6 PA5 PA4 (001FH) Read/Write After reset 1 1 (006DH) Read/Write PA3 PA2 PA1 PA0 1 1 1 1 1 7 6 PA7C PA6C PA5C PA4C 0 0 0 0 2 1 0 PA3C PA2C PA1C PA0C 0 0 0 0 W 0: Input 7 Bit symbol 0 Port A Control Register 5 4 3 Function CKOCR 1 Input mode 1 Bit symbol 2 R/W After reset PACR 3 6 1: Output Clock Output Control Register 5 4 3 2 1 0 SCOSEL SCOEN ALEEN CLKEN 0 0 R/W After reset Function Clock select Clock enable 0/1 0/1 ALE enable CLK enable CLK pin output control (Note 2) 0 “High-Z” output 1 CLK output ALE pin output control (Note 2) 0 “High-Z” output 1 ALE output SCOUT/PA7 pin control PACR<PA7C> <SCOEN> <SCOSEL> 0 0 1 0 1 0 1 1 Output mode Input Port fFPH clock output fSYS clock output (Note 3) Note 1: Read-modify-write is prohibited for registers PACR. Note 2: The value after reset of <CLKEN>, <ALLEN> is “0” (High-impedance output). The CLK pin is pulled up internally during reset. Note 3: The output clock from SCOUT pin is fFPH or fSYS clock. e.g.) The case of connected 20 MHz oscillator to X1, X2 pin. <SCOSEL> = “0” → 20 MHz clock <SCOSEL> = “1” → 10 MHz clock Figure 3.5.31 Registers for Port A 93CW46A-81 2004-02-10 TMP93CW46A 3.6 Chip Select/Wait Controller, AM8/ AM16 Pin TMP93CW46A has a built-in chip select/wait controller used to control chip select ( CS0 to CS2 pins), wait ( WAIT pin), and data bus size (8 or 16 bits) for any of the three block address areas. And AM8/ AM16 pin selects external data bus width for TMP93CW46A. 3.6.1 AM8/ AM16 Pin Set this pin to “1”. After reset, the CPU accesses the internal ROM with 16-bit bus width. The bus width when the CPU accesses an external area is set by chip select/wait control register (Described at 3.6.3.) and the registers of port 1. 3.6.2 Address/Data Bus Pins Port 0/AD0 to AD7, Port 1/AD8 to AD15 and Port 2/AD16 to AD23/A0 to A7 function as address/data bus for connecting the external memories. a. b. c. d. Number of address bus pins Max 24 (to 16 Mbytes) Max 24 (to 16 Mbytes) Max 16 (to 64 Kbytes) Max 8 (to 256 bytes) Number of data bus pins 8 16 8 16 Number of multiplexed pins 8 16 0 0 Port 0 AD0 to AD7 AD0 to AD7 AD0 to AD7 AD0 to AD7 Port 1 A8 to A15 AD8 to AD15 A8 to A15 AD8 to AD15 Port 2 A16 to A23 A16 to A23 A0 to A7 A0 to A7 Port function A23 to 8 AD7 to 0 A23 to 8 A7 to 0 D7 to 0 A23 to 16 AD15 to 0 A23 to 16 A15 to 0 D15 to 0 A15 to 0 A15 to 0 A7 to 0 AD7 to 0 (Note 1) A7 D7 to 0 to 0 AD15 to 0 A7 to 0 (Note 1) A15 D15 to 0 to 0 Timing chart ALE ALE ALE ALE RD RD RD RD Note 1: In case of c. and d., the data bus signals output the addresses since the signals are also used as the address bus. Writing “0” to bit CKOCR<ALEEN>, ALE signal can be stopped outputting. Note 2: After reset operation, Port 0, Port 1 and Port 2 function as input ports. Note 3: All the options a. to d. can be made available using the P1CR, P1FC, P2CR and P2FC registers. ( EA = VIH, AM8/ AM16 = VIH) 93CW46A-82 2004-02-10 TMP93CW46A 3.6.3 Chip Select/Wait Control Registers Table 3.6.1 shows control registers. One block address areas are controlled by 1-byte CS/WAIT control registers (B0CS, B1CS, and B2CS). (1) Enable Control register bit7 (B0E, B1E, and B2E) is a master bit used to specify enabling (“1”)/disabling (“0”) of the setting. Resetting sets B0E and B1E to disable (“0”) and B2E to enable (“1”). (2) CS/CAS Waveform select Control register bit5 (B0CAS, B1CAS, and B2CAS) is used to specify waveform mode output from the chip select pin ( CS0 / CAS0 to CS2 / CAS2 ). Setting this bit to 0 specifies CS0 to CS2 waveforms; setting it to 1 specifies CAS0 to CAS2 waveforms. Resetting clears bit5 to 0. (3) Data bus size select Bit4 (B0BUS, B1BUS, and B2BUS) of the control register is used to specify data bus size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to 1 accesses the memory in 8-bit data bus mode. Changing data bus size depending on the access address is called dynamic bus sizing. Table 3.6.2 shows the details of the bus operation. (4) Wait control Control register bits 3 and 2 (B0W1 to B0W0, B1W1 to B1W0, B2W1 to B2W0) are used to specify the number of waits. Setting these bits to 00 inserts a 2 states wait regardless of the WAIT pin status. Setting them to 01 inserts a 1-state wait regardless of the WAIT status. Setting them to 10 inserts a 1-state wait and samples the WAIT pin status. If the pin is low, inserting the wait maintains the bus cycle until the pin goes high. Setting them to 11 completes the bus cycle without a wait regardless of the WAIT pin status. Resetting sets these bits to 00 (2-state wait mode). (5) Address area specification Control register bits 1 and 0 (B0C1 to B0C0, B1C1 to B1C0, B2C1 to B2C0) are used to specify the target address area. Setting these bits to 00 enables settings (CS output, Wait state, Bus size, etc.) as follows: * CS0 setting enabled when 7F00H to 7FFFH is accessed. * CS1 setting enabled when 1080H to 7FFFH is accessed. * CS2 setting enabled when 28000H to 3FFFFH is accessed. Setting bits to 01 enables setting for all CS’s blocks and outputs a low strobe signal ( CS0 / CAS0 to CS2 / CAS2 ) from chip select pins when 400000H to 7FFFFFH is accessed. Setting bits to 10 enables them 800000H to BFFFFFH is accessed. Setting bits to 11 enables them when C00000H to FFFFFFH is accessed. 93CW46A-83 2004-02-10 TMP93CW46A Table 3.6.1 Chip Select/Wait Control Register Code B0CS Name Block0 CS/WAIT control register Address 0068H 7 6 5 4 3 2 1 0 B0E B0CAS B0BUS B0W1 B0W0 B0C1 B0C0 W W W W W W W 0 1: Master bit of bit 0 to 6 0 0 0 0 0 0: CS0 1: CAS0 0 0: 16-bit bus 1: 8-bit bus 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits B1CS Block1 CS/WAIT control register 0069H B1E B1CAS B1BUS B1W1 B1W0 B1C1 B1C0 W W W W W W W 0 1: Master bit of bit 0 to 6 0 0 0 0 0 0: CS1 1: CAS1 0 0: 16-bit bus 1: 8-bit bus 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits B2CS Block2 CS/WAIT control register 006AH 00: 7F00H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to 00: 1080H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B2E B2CAS B2BUS B2W1 B2W0 B2C1 B2C0 W W W W W W W 1 1: Master bit of bit 0 to 6 0 0 0 0 0 0: CS2 1: CAS2 0 0: 16-bit bus 1: 8-bit bus 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits 00: 28000H to 01: 400000H to 10: 800000H to 11: C00000H to Table 3.6.2 Dynamic Bus Sizing Operand Data Size 8 bits 16 bits Operand Start Memory Data Address Size CPU Data D15 to D8 D7 to D0 2n + 0 8 bits 2n + 0 xxxxx b7 to b0 (Even number) 16 bits 2n + 0 xxxxx b7 to b0 b7 to b0 2n + 1 8 bits 2n + 1 xxxxx (Odd number) 16 bits 2n + 1 b7 to b0 xxxxx 2n + 0 8 bits 2n + 0 2n + 1 xxxxx xxxxx b7 to b0 b15 to b8 16 bits 2n + 0 b15 to b8 b7 to b0 8 bits 2n + 1 2n + 2 xxxxx xxxxx b7 to b0 b15 to b8 16 bits 2n + 1 2n + 2 b7 to b0 xxxxx xxxxx b15 to b8 8 bits 2n + 0 2n + 1 2n + 2 2n + 3 xxxxx xxxxx xxxxx xxxxx b7 to b0 b15 to b8 b23 to b16 b31 to b24 16 bits 2n + 0 2n + 2 b15 to b8 b31 to b24 b7 to b0 b23 to b16 8 bits 2n + 1 2n + 2 2n + 3 2n + 4 xxxxx xxxxx xxxxx xxxxx b7 to b0 b15 to b8 b23 to b16 b31 to b24 16 bits 2n + 1 2n + 2 2n + 4 b7 to b0 b23 to b16 xxxxx xxxxx b15 to b8 b31 to b24 (Even number) 2n + 1 (Odd number) 32 bits CPU Address 2n + 0 (Even number) 2n + 1 (Odd number) xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the wirte strobe signal remains non active. 93CW46A-84 2004-02-10 TMP93CW46A 3.6.4 Chip Select Image An image of the actual chip select is shown below. Out of the whole memory area, address areas that can be specified are divided into four parts. Addresses from 000000H to 3FFFFFH are divided differently: 7F00H to 7FFFH is specified for CS0; 1080H to 7FFFH, for CS1; and 28000H to 3FFFFFH, for CS2. The reason is that a device other than ROM (e.g., RAM or I/O) might be connected externally. 7F00H to 7FFFH (256 bytes) for CS0 are mapped mainly for possible expansions to external I/O. 1080H to 7FFFH (Approx. 31 Kbytes) for CS1 are mapped there mainly for possible extensions to external RAM. 28000H to 3FFFFFH (Approx. 4 Mbytes) for CS2 are mapped mainly for possible extensions to external ROM. With the TMP93CW46A which has a built-in ROM, addresses from 8000H to 27FFFH are used as the internal ROM area. After reset, the CPU reads the program from the built-in ROM in 16-bit bus, 0-wait mode. CS0 CS1 CS2 000000H 7F00H B0C1, 0 = “00” B1C1, 0 = “00” 8000H 28000H B2C1, 0 = “00” 400000H B0C1, 0 = “01” B1C1, 0 = “01” B2C1, 0 = “01” B0C1, 0 = “10” B1C1, 0 = “10” B2C1, 0 = “10” B0C1, 0 = “11” B1C1, 0 = “11” B2C1, 0 = “11” (Mainly for I/O) (Mainly for RAM) (Mainly for ROM) 800000H C00000H FFFFFFH Note 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the chip select/wait controller. Note 2: External areas other than CS0 to CS2 are accessed in 16-bit data bus (0 waits) mode. When using the chip select/wait controller, do not specify the same address area more than once. (However, when addresses 7F00H to 7FFFH for CS0 and 1080H to 7FFFH for CS1 are specified, in other words, specifications overlap, only the CS0 setting/pin is active.) Note 3: When the bus is released ( BUSAK = “0”), CS0 to CS2 pins are also released (the output buffer is OFF). Refer to note about the bus release in 3.5 “Functions of Ports” about the state of pins. 93CW46A-85 2004-02-10 TMP93CW46A 3.6.5 Example of Usage Figure 3.6.1 is an example in which an external memory is connected to the TMP93CW46A. In this example, a ROM 128 Kbytes is connected using 16-bit bus, and RAM 256 Kbytes using 16-bit bus. TMP93CW46A A16 to A17 Latch × 16 ROM (128 Kbits × 16) A16 A1 to A15 AD8 to AD15 D AD0 to AD7 Q A15 A0 to A14 D8 to D15 D0 to D7 OE LE CE ALE RAM (128 Kbits × 8) CS2 A16 to A17 A1 to A15 RD A15 to A16 A0 to A14 I/O1 to I/O8 OE R/ W HWR Upper byte CE1 CS1 RAM (128 Kbits × 8) A16 to A17 A15 to A16 WR A1 to A15 A0 to A14 I/O1 to I/O8 OE AM8/ AM16 R/ W CE1 EA Lower byte Figure 3.6.1 Example of External Memory Connection (ROM and RAM = 16 bits) TMP93CW46A has built-in ROM and RAM. When ROM and RAM have insufficient capacity, it is possible to connect an external memory as the example of the external memory connection. In this example, the memory configuration is as follows. Memory ROM SRAM Memory Size Address CS Pin Data Bus Internal 128 Kbytes 008000H to 027FFFH − 16 bits External 128 Kbytes 400000H to 41FFFFH CS2 16 bits Internal 4 Kbytes 000080H to 00107FH − 16 bits External 256 Kbytes 800000H to 83FFFFH CS1 16 bits 93CW46A-86 2004-02-10 TMP93CW46A 3.7 8-Bit Timers The TMP93CW46A contains two 8-bit timers (Timers 0 and 1), each of which can be operated independently. The cascade connection allows these timers to be used as 16-bit timer. The following four operating modes are provided for the 8-bit timers. • 8-bit interval timer mode (2 timers) • 16-bit interval timer mode (1 timer) • 8-bit programmable square wave pulse generation (PPG: Variable duty with variable cycle) output mode (1 timer) • 8-bit pulse width modulation (PWM: variable duty with constant cycle) output mode (1 timer) Figure 3.7.1 shows the block diagram of 8-bit timer (Timer 0 and timer 1). Each timer consists of an 8-bit up counter, 8-bit comparator, and 8-bit timer register. Besides, one timer flip-flop (TFF1) is provided for pair of timer 0 and timer 1. Among the input clock sources for the timers, the internal clocks of φT1, φT4, φT16, and φT256 are obtained from the 9-bit prescaler shown in Figure 3.7.2. The operation modes and timer flip-flops of the 8-bit timer are controlled by three control registers TMOD, TFFCR, and TRUN. 93CW46A-87 2004-02-10 93CW46A-88 Selector TFFCR<DBEN> Select TMOD<T0CLK1:0> PPGTRG PWMTRG TREG0-WR TI0 pin φT1 φT4 φT16 2n − 1 Over flow Clear φT1 φT16 φT256 Register buffer 8-bit timer register (TREG0) 8-bit comparator (CP0) INTT0 Clear 8-bit up counter (UC1) RUN TRUN<T1RUN> 8-bit timer register (TREG1) 8-bit comparator (CP1) TMOD<T1CLK1:0> Selector Internal data bus TO0TRG (to serial channel) Match detect TMOD<T10M1:0, PWMM1:0> 8-bit up counter (UC0) RUN TRUN<T0RUN> INTT1 Selector Match detect TFF1 TMOD<T10M1:0> TFFCR, TMOD Timer F/F control TO1 (P71) TMP93CW46A Figure 3.7.1 Block Diagram of 8-Bit Timers (Timers 0 and 1) 2004-02-10 TMP93CW46A 1. Prescaler, Prescaler clock select There are 9 bit prescaler and prescaler clock selection register to generate input clock for 8-bit timers 0 and 1, 16-bit timers 4 and 5 and serial interfaces 0 to 4. Figure 3.7.2 shows the block diagram. Table 3.7.1 shows prescaler clock resolution into 8, 16-bit timer. To CPU System clock (fSYS) 2 To 8-bit PWM prescaler fFPH Selector Selector 9-bit prescaler fs Selector XT1 fc fc/2 fc/4 fc/8 fc/16 2 4 8 16 32 64 128 256 512 2 4 φT1 φT4 φT16 φT256 SYSCR0 <PRCK1:0> Run/stop & clear φT1 φT4 φT16 TRUN<PRRUN> SYSCR1<SYSCK> φ1 φT0 φT2 φT8 φT32 2 To 8-bit timers 0 and 1 To 16-bit timers 4 and 5 To serial interfaces 0 to 4 SYSCR1<GEAR2:0> ÷2 ÷4 ÷8 ÷16 X1 Figure 3.7.2 The Block Diagram of Prescaler Table 3.7.1 Prescaler Clock Resolution to 8-/16-Bit Timer at fc = 20 MHz, fs = 32.768 kHz Select System Clock <SYSCK> Select Prescaler Clock <PRCK1:0> 1 (fs) 00 0 (fc) (fFPH) φT4 φT16 φT256 fs/23 (244 µs) fs/25 (977 µs) fs/27 (3.9 ms) fs/211 (62.5 ms) 000 (fc) fc/23 (0.4 µs) fc/25 (1.6 µs) fc/27 (6.4 µs) fc/211 (102.4 µs) 001 (fc/2) 010 (fc/4) 100 (fc/16) XXX φT1 XXX 011 (fc/8) XXX Prescaler Clock Resolution Gear Value <GEAR2:0> 4 (0.8 µs) 5 (1.6 µs) 6 (3.2 µs) 7 (6.4 µs) fc/2 fc/2 fc/2 fc/2 6 (3.2 µs) 7 (6.4 µs) 8 (12.8 µs) 9 (25.6 µs) fc/2 fc/2 fc/2 fc/2 8 (12.8 µs) fc/212 (204.8 µs) 9 (25.6 µs) fc/213 (409.6 µs) 10 (51.2 µs) fc/214 (819.2 µs) 11 (102.4 µs) fc/215 (1.638 ms) fc/2 fc/2 fc/2 fc/2 01 (Low-frequency clock) XXX fs/23 (244 µs) fs/25 (977 ms) fs/27 (3.9 ms) fs/211 (62.5 ms) 10 (Note) (fc/16 clock) XXX fc/27 (6.4 µs) fc/29 (25.6 µs) fc/211 (102.4 µs) fc/215 (1.638 ms) 16-bit timer XXX: Don’t care 8-bit timer Note: The fc/16 clock as a prescaler clock can not be used when the fs is used as a system clock. 93CW46A-89 2004-02-10 TMP93CW46A The clock selected among fFPH clock, fc/16 clock and fs is divided by 4 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to “00”, selecting the fFPH clock input divided by 4. The 8-bit timer 0, 1 selects between 4 clock inputs: φT1, φT4, φT16, and φT256 among the prescaler output. This prescaler can be run or stopped by the timer control register TRUN<PRRUN>. Counting starts when <PRRUN> is set to “1”. The prescaler is cleared to zero and stops operation when <PRRUN> is set to “0”. Resetting clear <PRRUN> to “0” and stops the prescaler. When the IDLE1 mode (Only the oscillator operates) is used, set TRUN<PRRUN> to “0” to reduce the power consumption of the prescaler before the “HALT” instruction is executed. 2. Up counter This is an 8-bit binary counter which counts up by the input clock pulse specified by TMOD. The input clock of timer 0 is selected from the external clock from TI0 pin and the three internal clocks φT1, φT4, and φT16, according to the set value of TMOD register. The input clock of timer 1 depends on the operation modes. When set to 16-bit timer mode, the overflow output of timer 0 is used as the input clock. When set to any other mode than 16-bit timer mode, the input clock is selected from the internal clocks φT1, φT16, and φT256 as well as the comparator output (Match detection signal) of timer 0 according to the set value of TMOD register. Example: When TMOD<T10M1:0> = 01, the overflow output of timer 0 becomes the input clock of timer 1 (16-bit timer mode). When TMOD<T10M1:0> = 00 and TMOD<T1CLK1:0> = 01, φT1 becomes the input of timer 1 (8-bit timer mode). Operation mode is also set by TMOD register. When reset, it is initialized to TMOD<T10M1:0> = 00 whereby the up counter is placed in the 8-bit timer mode. The counting and stop and clear of up counter can be controlled for each interval timer by the timer operation control register TRUN. When reset, all up counters will be cleared to stop the timers. 93CW46A-90 2004-02-10 TMP93CW46A 3. Timer register This is an 8-bit register for setting an interval time. When the set value of timer registers TREG0, TREG1, matches the value of up counter, the comparator match detect signal becomes active. If the set value is 00H, this signal becomes active when the up counter overflows. Timer register TREG0 is a double buffer structure, each of which makes a pair with register buffer. The timer flip-flop control register TFFCR<DBEN> bit controls whether the double buffer structure should be enabled or disabled. It is disabled when <DBEN> = 0 and enabled when they are set to 1. In the condition of double buffer enable state, the data is transferred from the register buffer to the timer register when the 2n − 1 overflow occurs in PWM mode, or at the PPG cycle in PPG mode. Therefore, during timer mode, the double buffer can not be used. When reset, it will be initialized to <DBEN> = 0 to disable the double buffer. To use the double buffer, write data in the timer register, set <DBEN> to 1, and write the following data in the register buffer. Up counter Comparator (CP0) Timer registers 0 (TREG0) Shift trigger Selector Matching detection of PPG cycle 2n − 1 overflow of PWM TREG0 WR Register buffers 0 Write Internal data bus TFFCR<DBEN> Figure 3.7.3 Configuration of Timer Register 0 Note: Timer register and the register buffer are allocated to the same memory address. When <DBEN> = 0, the same value is written in the register buffer as well as the timer register, while when <DBEN> = 1 only the register buffer is written. The memory address of each timer register is as follows. TREG0: 000022H TREG1: 000023H All the registers are write-only and cannot be read. 93CW46A-91 2004-02-10 TMP93CW46A 4. Comparator A comparator compares the value in the up counter with the values to which the timer register is set. When they match, the up counter is cleared to zero and an interrupt signal (INTT0, INTT1) is generated. If the timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. 5. Timer flip-flop The timer flip-flop (TFF1) is a flip-flop inverted by the match detect signal (8-bit comparator output). Inverting is disabled or enabled by the timer flip-flop control register TFFCR<TFF1IE>. After reset operation, the value of TFF1 is undefined. Writing “01” or “10” to TFFCR<TFF1C1:0> sets “0” or “1” to TFF1. Additionally, writing “00” to this bit inverts the value of TFF1. (Software inversion) TFF1 is output to TO1 pin (Also used as P71). When using as the timer output, the timer flip-flop should be set by port 7 function register P7FC beforehand. 93CW46A-92 2004-02-10 TMP93CW46A 7 TRUN (0020H) Bit symbol PRRUN Read/Write R/W After reset 0 6 5 4 3 T5RUN T4RUN P1RUN 2 1 0 P0RUN T1RUN T0RUN 0 0 0 R/W 0 Function 0 0 Prescaler and timer run/stop control 0: Stop and clear 1: Run (Count up) Count operation 0 Stop and clear 1 Count PRRUN: Operation of prescaler T5RUN: Operation of 16-bit timer (Timer 5) T4RUN: Operation of 16-bit timer (Timer 4) P1RUN: Operation of PWM timer (PWM1/Timer 3) P0RUN: Operation of PWM timer (PWM0/Timer 2) T1RUN: Operation of 8-bit timer (Timer 1) T0RUN: Operation of 8-bit timer (Timer 0) SYSCR0 Bit symbol (006EH) Read/Write After reset Function 7 6 5 4 XEN XTEN RXEN RXTEN 3 2 1 0 RSYSCK WUEF PRCK1 PRCK0 0 0 R/W 1 Highfrequency oscillator (fc) 0 Lowfrequency oscillator (fs) 1 Highfrequency oscillator (fc) after released 0: Stop 0: Stop 1: Oscillator 1: Oscillator STOP mode 0: Stop 1: Oscillator 0 0 Lowfrequency oscillator (fs) after released STOP mode Select clock after released STOP mode 0: Stop 1: Oscillator 0: fc 1: fs 0 Warm-up timer Select prescaler clock 00: fFPH (Write) 01: fs 0: Don’t care 10: fc/16 1: Start 11: (Reserved) timer (Read) 0: End warm up 1: Not end warm up Figure 3.7.4 Timer Operation Control Register/System Clock Control Register 93CW46A-93 2004-02-10 TMP93CW46A TMOD (0024H) Bit symbol 7 6 5 4 T10M1 T10M0 PWMM1 PWMM0 Read/Write After reset Function 3 2 1 0 T1CLK1 T1CLK0 T0CLK1 T0CLK0 0 0 0 0 W 0 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM cycle 00: − 01: 26 − 1 10: 27 − 1 11: 28 − 1 Source clock of timer 1 00: TO0TRG 01: φT1 10: φT16 11: φT256 Source clock of timer 0 00: TI0 01: φT1 10: φT4 11: φT16 Input clock of timer 0 00 External input (TI0) 01 φT1 (Prescaler) 10 φT4 (Prescaler) 11 φT16 (Prescaler) Input clock of timer 1 TMOD<T10M1:0> ≠ 01 TMOD <T10M1:0> = 01 00 Comparator output of timer 0 Overflow output of timer 0 01 Internal clock φT1 10 Internal clock φT16 11 Internal clock φT256 (16-bit timer mode) Select PWM cycle 00 − 01 26 − 1 10 27 − 1 11 28 − 1 Set the operation mode of timers 0 and 1 00 Note: Two 8-bit timers (Timer 0 and timer 1) 01 16-bit timer 10 8-bit PPG output 11 8-bit PWM output (Timer 0) 8-bit timer (Timer 1) Prohibit read-modify-write Figure 3.7.5 Timer Mode Control Register (TMOD) 93CW46A-94 2004-02-10 TMP93CW46A 7 TFFCR (0025H) 6 5 4 3 Bit symbol DBEN TFF1C1 Read/Write R/W After reset Double buffer 0: Disable 1: Enable 1 TFF1C0 TFF1IE W 0 Function 2 1 0 TFF1IS R/W 1 00: Invert TFF1 01: Set TFF1 10: Clear TFF1 11: Don’t care * Always read as “11” 0 0 TFF1 Inversion trigger 0: Disable 1: Enable TFF1 Inversion source 0: Timer 0 1: Timer 1 Select inverse signal of timer F/F1 (“Don’t care” except in 8-bit timer mode) TMOD<T10M1:0 > = 00 0 1 01 10 11 Inversion by timer 0 16-bit timer mode PPG mode PWM mode match signal Inversion by Inversion by Inversion by Inversion by timer 1 match signal match signal of match and match signal each timer 0 and overflow signal timer 1 of timer 0 Inversion of timer F/F1 (TFF1) 0 Disable invert 1 Enable invert Control of timer F/F1 (TFF1) 00 Invert the value of TFF1 (software inversion) 01 Set TFF1 to “1”. 10 Clear TFF1 to “0”. 11 Don’t care Double buffer control of TREG0 0 Disable double buffer 1 Enable double buffer Note: TFFCR<bit7:5>, <bit3:2> are always read as “1”. Figure 3.7.6 Timer Flip-Flop Control Register (TFFCR) 93CW46A-95 2004-02-10 TMP93CW46A The operation of 8-bit timers will be described below: (1) 8-bit timer mode Two interval timers 0, 1, can be used independently as 8-bit interval timer. All interval timers operate in the same manner, and thus only the operation of timer 1 will be explained below. 1. Generating interrupts in a fixed cycle To generate timer 1 interrupt at constant intervals using timer 1 (INTT1), first stop timer 1 then set the operation mode, input clock, and a cycle to TMOD and TREG1 register, respectively. Then, enable interrupt INTT1 and start the counting of timer 1. Example: To generate timer 1 interrupt every 1 s at fs = 32.768 MHz, set each register in the following manner. * Clock condition MSB System clock: Clock gear: Prescaler clock: Low frequency (fs) xxx Low frequency (fs) LSB TRUN TMOD 7 ← − ← 0 6 X 0 5 − 4 − 3 − 2 − X X 1 0 TREG1 INTET10 TRUN ← 0 ← 1 ← 1 0 1 X 0 0 − 0 1 − 0 − − 0 − − 1 0 − 0 − − 0 − 0 − − 1 Stop timer 1, and clear it to “0”. Set the 8-bit timer mode, and select φT16 (3.9 ms at fs = 32.768 kHz) as the input clock. Set the timer register 1 s ÷ φT16 = 256 (00H). Enable INTT1, and set it to level 5. Start timer 1 counting. X: Don’t care, −: No change Use the Table 3.7.1 for selecting the input clock. Note: The input clock of timer 0 and timer 1 are different from as follows. Timer 0: TI0 input, φT1, φT4, φT16 Timer 1: Match output of timer 0, φT1, φT16, φT256 93CW46A-96 2004-02-10 TMP93CW46A 2. Generating a 50% duty square wave pulse The timer flip-flop (TFF1) is inverted at constant intervals, and its status is output to timer output pin (TO1). Example: To output a 4.0 µs square wave pulse from TO1 pin at fc = 20 MHz, set each register in the following procedures. Either timer 0 or timer 1 may be used, but this example uses timer 1. * Clock condition TRUN TMOD 7 ← − ← 0 6 − 5 − 4 − 3 − 2 − 1 1 1 − 0 − − 0 X X 0 TREG1 TFFCR ← 0 ← − 0 − 0 − 0 − 0 1 1 0 0 1 1 1 P7CR P7FC TRUN ← X ← X ← 1 X X X X X − X X − − − − − − − 1 1 1 X − System clock: Clock gear: Prescaler clock: − High frequency (fc) 1 (fc) fFPH Stop timer 1, and clear it to “0”. Set the 8-bit timer mode, and select φT1 (0.4 µs at fc = 20 MHz) as the input clock. Set the timer register 4.0 µs ÷ φT1 ÷ 2 = 5. Clear TFF1 to “0”, and set to invert by the match detect signal from timer 1. Select P71 as TO1 pin. Start timer 1 counting. X: Don’t care, −: No change φ T1 TRUN <T1RUN> Bit7 to bit2 Up counter Bit1 Bit0 0 1 2 3 0 1 2 3 0 1 2 3 0 Comparator timing Comparator output (matching detect) INTT1 UC clear TFF1 TO1 2.0 µs at fc = 20 MHz Figure 3.7.7 Square Wave (50% Duty) Output Timing Chart 93CW46A-97 2004-02-10 TMP93CW46A 3. Making timer 1 count up by match signal from timer 0 comparator Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1. Comparator output (Timer 0 match) Timer 0 up counter (when TREG0 = 5) Timer 1 up counter (when TREG1 = 2) 1 2 3 4 5 1 1 2 3 2 4 5 1 2 3 1 Timer 1 match output Figure 3.7.8 Timer 1 Count Up by Timer 0 (2) 16-bit timer mode A 16-bit interval timer is configured by using the pair of timer 0 and timer 1. To make a 16-bit timer mode, set timer 0/timer 1 mode register TMOD<T10M1:0> to “01”. When set in 16-bit timer mode, the overflow output of timer 0 will become the input clock of timer 1, regardless of the set value of TMOD<T1CLK1:0>. Table 3.7.1 shows the relation between the cycle of timer (Interrupt) and the selection of input clock. The lower 8 bits of the timer (Interrupt) cycle are set by the timer register TREG0, and the upper 8 bits are set by TREG1. Note that TREG0 always must be set first. (Writing data into TREG0 disables the comparator temporarily, and the comparator is restarted by writing data into TREG1.) Setting example: To generate an interrupt INTT1 every 0.4 seconds at fc = 20 MHz, set the following values for timer registers TREG0 and TREG1. * Clock condition System clock: High frequency (fc) High frequency clock gear: 1 (fc) Prescaler clock: fFPH When counting with input clock of φT16 (6.4 µs at 20 MHz) 0.4 s ÷ 6.4 µs = 62500 = F424H Therefore, set TREG1 = F4H and TREG0 = 24H, respectively. 93CW46A-98 2004-02-10 TMP93CW46A The comparator match signal is output from timer 0 each time the up counter UC0 matches TREG0, where the up counter UC0 is not be cleared. With the timer 1 comparator, the match detect signal is output at each comparator timing when up counter UC1 and TREG1 values match. When the match detect signal is output simultaneously from both comparators of timer 0 and timer 1, the up counters UC0 and UC1 are cleared to “0”, and the interrupt INTT1 is generated. If inversion is enabled, the value of the timer flip-flop TFF1 is inverted. Example: When TREG1 = 04H and TREG0 = 80H Value of up counter (UC1, UC0) 0000H 0080H 0180H 0280H 0380H 0480H Timer 0 comparator match detect signal Interrupt INTT1 Timer output TO1 Inversion Figure 3.7.9 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulse can be generated at any frequency and duty by timer 0. The output pulse may be either low-active or high-active. In this mode, timer 1 cannot be used. Timer 0 outputs pulse to TO1 pin (Also used as P71). tH tL t TREG0 and UC0 match (Interrupt INTT0) TREG1 and UC0 match (Interrupt INTT1) TO1 TREG0 TREG1 Figure 3.7.10 8-Bit PPG Output Waveforms 93CW46A-99 2004-02-10 TMP93CW46A In this mode, a programmable square wave is generated by inverting timer output each time the 8-bit up counter (UC0) matches the timer registers TREG0 and TREG1. However, it is required that the set value of TREG0 is smaller than that of TREG1. Though the up counter (UC1) of timer 1 is not used in this mode, UC1 should be set for counting by setting TRUN<T1RUN> to 1. Figure 3.7.11 shows the block diagram for this mode. TO1 TRUN<T0RUN> TI0 pin φT1 φT4 φT16 Selector 8-bit up counter (UC 0) TFF1 TFFCR <TFF1C1:0, TFF1IE> Inversion TMOD<T0CLK1:0> INTT0 Comparator Comparator INTT1 TREG 0 TREG0-WR Selector Shift trigger Register buffer TREG 1 TFFCR<DBEN> Internal data bus Figure 3.7.11 Block Diagram of 8-Bit PPG Output Mode When the double buffer of TREG0 is enabled in this mode, the value of register buffer will be shifted in TREG0 each time TREG1 matches UC0. Use of the double buffer makes the handling of low duty waves easily (when duty is varied). Match with TREG0 and up counter (Up counter = Q2) (Up counter = Q1) Match with TREG 1 TREG 0 (Value to be compared) Register buffer Shift from register buffer Q2 Q1 Q2 Q3 TREG 0 (Register buffer) write Figure 3.7.12 Operation of Register Buffer 93CW46A-100 2004-02-10 TMP93CW46A Example: Generating 1/5 duty 50 kHz pulse (at fc = 20 MHz) 20 µs * Clock condition System clock: Clock gear: Prescaler clock: High frequency (fc) 1 (fc) fFPH Calculate the value to be set for timer register. To obtain the frequency 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 µs. Given φT1 = 0.4 µs (at 20 MHz), 20 µs ÷ 0.4 µs = 50 Consequently, to set the timer register 1 (TREG1) to TREG1 = 50 = 32H and then duty to 1/5, t × 1/5 = 20 µs × 1/5 = 4 µs 4 µs ÷ 0.4 µs = 10 Therefore, set timer register 0 to TREG0 = 10 = 0AH. TRUN TMOD TREG0 TREG1 TFFCR ← ← ← ← ← 7 − 1 0 0 − 6 X 0 0 0 − 5 − X 0 1 − 4 − X 0 1 1 3 − X 1 0 0 2 − X 0 0 1 1 0 0 1 1 1 0 0 1 0 0 X P7CR P7FC TRUN ← X ← X ← 1 X X X X X − X X − − − − − − − 1 1 1 − X 1 Stop timer 0, and clear it to “0”. Set the 8-bit PPG mode, and select φT1 as input clock. Write “0AH”. Write “32H”. Sets TFF1 and enable the inversion and double buffer enable. Writing “10” provides negative logic pulse. Set P71 as the TO1 pin. Start timer 0 and timer 1 counting. X: Don’t care, −: No change 93CW46A-101 2004-02-10 TMP93CW46A (4) 8-bit PWM output mode This mode is valid only for timer 0. In this mode, maximum 8-bit resolution of PWM pulse can be output. PWM pulse is output to TO1 pin (also used as P71) when using timer 0. Timer 1 can also be used as 8-bit timer. Timer output is inverted when up counter (UC0) matches the set value of timer register TREG0 or when 2n − 1 (n = 6, 7, or 8; specified by TMOD<PWMM1:0>) counter overflow occurs. Up counter UC0 is cleared when 2n − 1 counter overflow occurs. To use this PWM mode, the following conditions must be satisfied. (Set value of timer register) < (Set value of 2n − 1 counter overflow) (Set value of timer register) ≠ 0 TREG0 and UC0 match 2n − 1 overflow (interrupt INTT0) TO1 tPWM (PWM cycle) Figure 3.7.13 8-Bit PWM Waveforms Figure 3.7.14 shows the block diagram of this mode. TO1 TRUN<T0RUN> TI0 φT1 φT4 φT16 Selector 8-bit up counter (UC 0) TFF1 Clear 2n − 1 TMOD<T0CLK1:0> overflow control TMOD <T10M1:0> = 11 TMOD <PWMM1:0> TFFCR <TFF1C1:0, TFF1IE> Invert Overflow Comparator INTT 0 TREG0 Selector TREG0-WR Shift trigger Register buffer TFFCR<DBEN> Internal data bus Figure 3.7.14 Block Diagram of 8-Bit PWM Mode 93CW46A-102 2004-02-10 TMP93CW46A In this mode, the value of register buffer will be shifted in TREG0 if 2n − 1 overflow is detected when the double buffer of TREG0 is enabled. Use of the double buffer makes easy the handling of small duty waves. Match with TREG0 Up counter = Q1 Up counter = Q2 2n − 1 overflow Shift into TREG0 TREG 0 (Value to be compared) Q1 Register buffer Q2 Q2 Q3 TREG0 (Register buffer) write Figure 3.7.15 Operation of Register Buffer Example: To output the following PWM waves to TO1 pin at fc = 20 MHz. 68 µs 102 µs * Clock condition System clock: Clock gear: Prescaler clock: High frequency (fc) 1 (fc) fFPH To realize 102 µs of PWM cycle by φT1 = 0.4 µs (at fc = 20 MHz), 102 µs ÷ 0.4 µs = 255 = 2n − 1 Consequently, n should be set to 8. As the period of low level is 68 µs, for φT1 = 0.4 µs, set the following value for TREG0. 68 µs ÷ 0.4 µs = 170 = AAH TRUN TMOD MSB 7 ← − ← 1 6 X 1 5 − 4 − 1 TREG0 TFFCR P7CR P7FC TRUN ← ← ← ← ← 0 X X X X 1 X X X − 1 X X X 1 2 − − 1 − 0 3 − − 0 X X X − 1 1 − − − 0 0 − − − 1 1 1 1 − 0 LSB 0 0 1 0 X − X 1 Stop timer 0, and clear it to “0”. Set 8-bit PWM mode (cycle: 28 − 1) and select φT1 as the input clock. Writes “AAH”. Clears TFF1, enable the inversion and double buffer. Set P71 as the TO1 pin. Start timer 0 counting. X: Don’t care, −: No change 93CW46A-103 2004-02-10 TMP93CW46A Table 3.7.2 PWM Cycle at fc = 20 MHz, fs = 32.768 kHz Select Prescaler Clock <SYSCK> Select Gear Value System <GEAR2:0> Clock <PRCK1:0> 1 (fs) 00 (fFPH) 0 (fc) PWM Cycle 2 −1 2 −1 6 φT1 2 −1 7 φT4 φT16 φT1 246 ms 31.0 ms 8 φT4 φT16 φT1 φT4 124 ms 496 ms 62.3 ms 249 ms XXX 15.4 ms 61.5 ms 000 (fc) 25.2 µs 100.8 µs 403.2 µs 001 (fc/2) 50.4 µs 201.6 µs 806.4 µs 101.6 µs 406.4 µs 010 (fc/4) 100.8 µs 403.2 µs 011 (fc/8) 50.8 µs φT16 203.2 µs 812.8 µs 102.0 µs 408.0 µs 1.61 ms 203.2 µs 812.8 µs 996 ms 1.63 ms 1.63 ms 204.0 µs 816.0 µs 3.26 ms 3.26 ms 408.0 µs 1.63 ms 6.53 ms 201.6 µs 806.4 µs 3.23 ms 406.4 µs 1.63 ms 6.52 ms 816.0 µs 3.26 ms 13.06 ms 100 (fc/16) 403.2 µs 1.61 ms 6.45 ms 812.8 µs 3.25 ms 13.04 ms 1.63 ms 6.53 ms 26.11 ms XXX 01 (Low-frequency clock) XXX 15.4 ms 61.5 ms 246 ms 31.0 ms 124 ms 496 ms 62.3 ms 249 ms 996 ms XXX 10 (fc/16 clock) XXX 403.2 µs 1.61 ms 6.45 ms 812.8 µs 3.25 ms 13.04 ms 1.63 ms 6.53 ms 26.11 ms XXX: Don’t care (5) Table 3.7.3 shows the list of 8-bit timer modes. Table 3.7.3 Timer Mode Setting Registers Register Name TMOD TFFCR Name of Function in Register T10M PWMM T1CLK T0CLK TFF1IS Function Timer Mode PWM0 Cycle Upper Timer Input Clock Lower Timer Input Clock Timer F/F Invert Signal Select 01 − − External clock, φT1, φT4, φT16 (00, 01, 10, 11) − Lower timer match: φT1, φT16, φT256 External clock, φT1, φT4, φT16 16-bit timer mode 8-bit timer × 2 channels 00 − (00, 01, 10, 11) 8-bit PPG × 1 channel 10 8-bit PWM × 1 channel 11 8-bit timer × 1 channel 11 − − 26 − 1, 27 − 1, 28 − 1 − (01, 10, 11) − (00, 01, 10, 11) External clock, φT1, φT4, φT16 (00, 01, 10, 11) External clock, φT1, φT4, φT16 0: Lower timer output 1: Upper timer output − − (00, 01, 10, 11) φT1, φT16, φT256 (01, 10, 11) − Output disabled −: Don’t care 93CW46A-104 2004-02-10 TMP93CW46A 3.8 8-Bit PWM Timers The TMP93CW46A has two built-in 8-bit PWM timers (Timers 2 and 3). They have two operating modes. • 8-bit PWM (Pulse width modulation: variable duty at fixed interval) output mode • 8-bit interval timer mode Figure 3.8.1, 3.8.2 are block diagram of 8-bit PWM timer (Timers 2 and 3). PWM timers consist of an 8-bit up counter, 8-bit comparator, and 8-bit timer register. Two timer flip-flops (TFF2 for timer 2 and TFF3 for timer 3) are provided. Input clocks φP1, φP4, and φP16 for the PWM timers can be obtained using the built-in prescaler. PWM timer operating mode and timer flip-flops are controlled by four control registers (P0MOD, P1MOD, PFFCR, and TRUN). PWM timer 0 and 1 can be used independently. All PWM timers operate in the same manner, and thus only the operation of PWM timer 0 will be explained below. F/F2 (TFF2) P0MOD<PWM0M> TRUN<P0RUN> Selector Set φP1 φP4 φP16 Run Clock control PWM2-OUT (TO2) Clear F/F control Clear PFFCR<FF2C1:0> PFFCR<FF2TRG1:0> 8-bit up counter (UC2) 2n − 1 Overflow P0MOD<T2CLK1:0> P0MOD<PWM0S1:0> Interrupt Match detect control 8-bit comparator (CP2) INTT2 P0MOD<PWM0INT> 8-bit timer register TREG2 Shift trigger B Selector Register buffer S A TREG-WR Register write P0MOD<DB2EN> Internal data bus Figure 3.8.1 Block Diagram of 8-Bit PWM Timer 0 (Timer 2) 93CW46A-105 2004-02-10 TMP93CW46A F/F3 (TFF3) P1MOD<PWM1M> TRUN<P1RUN> Selector Set φP1 φP4 φP16 Run Clock control PWM3-OUT (TO3) Clear F/F control Clear PFFCR<FF3C1:0> PFFCR<FF3TRG1:0> 8-bit up counter (UC3) 2n − 1 Overflow P1MOD<T3CLK1:0> P1MOD<PWM1S1:0> Interrupt Match detect control 8-bit comparator INTT3 (CP3) P1MOD<PWM1INT> 8-bit timer register TREG3 Shift trigger B Selector Register buffer S A TREG-WR Register write P1MOD<DB3EN> Internal data bus Figure 3.8.2 Block Diagram of 8-Bit PWM Timer 1 (Timer 3) 93CW46A-106 2004-02-10 TMP93CW46A 1. Prescaler, prescaler clock select There are 5-bit prescaler and prescaler clock selection register to generate input clock for 8-bit PWM Timers 0 and 1. Figure 3.8.3 shows the block diagram. Table 3.8.1 shows prescaler clock resolution into 8-bit PWM timers 0 and 1. To CPU 2 fFPH 5-bit prescaler Selector 2 2 4 8 16 32 φP16 φP4 φP1 4 To 8-bit PWM timers 0 and 1 Selector To 9-bit prescaler for 8-bit timers 0 and 1, fs XT1 SYSCR0 <PRCK1:0> Run/stop & clear 16-bit timers 4 and 5, serial interfaces 0 to 4. Selector TRUN<PRRUN> fc fc/2 SYSCR1<SYSCK> fc/4 fc/8 fc/16 SYSCR1<GEAR2:0> ÷2 ÷4 ÷8 ÷16 X1 Figure 3.8.3 The Block Diagram of Prescaler Table 3.8.1 Prescaler Clock Resolution to 8-Bit PWM Timers 0 and 1 at fc = 20 MHz, fs = 32.768 kHz Select System Clock <SYSCK> Select Prescaler Clock <PRCK1:0> φP1 φP4 φP16 XXX fs/2 (122 µs) fs/2 (488 µs) fs/2 (1.95 ms) 000 (fc) fc/22 (0.2 µs) fc/24 (0.8 µs) fc/26 (3.2 µs) 00 001 (fc/2) fc/23 (0.4 µs) fc/25 (1.6 µs) fc/27 (6.4 µs) (fFPH) 010 (fc/4) fc/24 (0.8 µs) fc/26 (3.2 µs) fc/28 (12.8 µs) 011 (fc/8) fc/25 (1.6 µs) fc/27 (6.4 µs) fc/29 (25.6 µs) 100 (fc/16) fc/26 (3.2 µs) fc/28 (12.8 µs) fc/210 (51.2 µs) 1 (fs) 0 (fc) Prescaler Clock Resolution Gear Value <GEAR2:0> 2 4 6 XXX 01 (Low-frequency clock) XXX fs/22 (122 µs) fs/24 (488 µs) fs/26 (1.95 ms) XXX 10 (fc/16 clock) XXX fc/26 (3.2 µs) fc/28 (12.8 µs) fc/210 (51.2 µs) XXX: Don’t care Note: The fc/16 clock as a prescaler clock can not be used when the fs is used as a system clock. 93CW46A-107 2004-02-10 TMP93CW46A The clock selected among fFPH clock, fc/16 clock and fs is divided by 2 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to “00” selects the fFPH clock input divided by 2. The register TRUN<PRRUN> which controls this prescaler is also used as the other timers. So, this prescaler can not be operated independently. The 8-bit PWM timer0, 1 selects between 3 clock inputs, φP1, φP4, and φP16 among the prescaler outputs. This prescaler also can be run or stopped by TRUN<PRRUN> described of the 8-bit timer. Counting starts when <PRRUN> is set to “1”. The prescaler is cleared zero and stops operation when <PRRUN> is set to “0”. Resetting clear <PRRUN> to “0” and stops the prescaler. When the IDLE1 mode (Only the oscillator operates) is used, set TRUN<PRRUN> to “0” to reduce the power consumption of the prescaler before the “HALT” instruction is executed. 2. Up counter The up counter is an 8-bit binary counter which counts up according to the input clock specified by PWM mode register P0MOD<T2CLK1:0>. The input clock for the up counter is selected from the internal clocks φP1, φP4, and φP16 (PWM dedicated prescaler output) depending on the <T2CLK1:0>. Operating mode is set by P0MOD<PWM0M>. At reset, it is initialized to “0”, thus, the up counter is placed in PWM mode. In PWM mode, the up counter is cleared when a 2n − 1 overflow occurs; in timer mode, the up counter is cleared at compare and match. Count/stop and clear of the up counter can be controlled for each PWM timer using the timer operation control register TRUN. Resetting clears all up counters and stops timers. 3. Timer register The 8-bit register is used for setting an interval time. When the value set in the timer register (TREG2) matches the value in the up counter, the match detect signal of the comparator becomes active. Timer register TREG2 is each paired with register buffer to make a double buffer structure. TREG2 controls double buffer enable/disable by P0MOD<DB2EN>: Disabled when <DB2EN> = 0, enabled when <DB2EN> = 1. Data is transferred from register buffer to timer register when a 2n − 1 overflow occurs in PWM mode, or when compare and match occur in 8-bit timer mode. That is, with a PWM timer, the timer mode can be operated in double buffer enable state, unlike PWM mode and timer mode for timers 0 and 1. At reset, <DB2EN> is initialized to 0 to disable double buffer. The same data value is written to both the register buffer and the timing register. To use double buffer, write the data in the timer register at first, then set <DB2EN> to 1, and write the following data in the register buffer. 93CW46A-108 2004-02-10 TMP93CW46A Up counter Comparator Timer register (TREG2) Shift trigger Selector Register buffer 8-bit match detect PWM2n − 1 overflow TREG2 WR Write Internal data bus <DB2EN> Figure 3.8.4 Structure of Timer Registers 2 Memory addresses of the timer registers are as follows: TREG2: 000026H (for PWM0) TREG3: 000027H (for PWM1) The timer register and the register buffer are allocated to the same memory address. When <DB2EN> = “0”, the same value is written to both register buffer and timer register. When <DB2EN> = “1”, the value is written to the register buffer only. Register buffer values can be read when reading the above addresses. The timer register is only writing, and it can not read. 4. Comparator Compares the value in the up counter with the value in the timer register (TREG2). When they match, the comparator outputs the match detect signal. In timer mode, the comparator clears the up counter to 0 at compare and match. It also inverts the value of the timer flip-flop if timer flip-flop invert is enabled. 5. Timer flip-flop The value of the timer flip-flop is inverted by the match detect signal (Comparator output) of each interval timer or 2n − 1 overflow. The value can be output to the timer output pin TO2 (Also used as P72). 93CW46A-109 2004-02-10 TMP93CW46A P0MOD (0028H) 7 6 5 4 3 2 1 0 Bit symbol FF2RD DB2EN PWM0INT PWM0M T2CLK1 T2CLK0 PWM0S1 PWM0S0 Read/Write R 0 0 After reset Function − Flip-flop (F/F2) output data W 0 0 1: Double buffer 2 enable 0: 2 − 1 overflow interrupt 1: Compare and match interrupt n 0 0: PWM mode 1: Timer mode 0 0 00: φP1 00: 2 − 1 01: φP4 01: 2 − 1 10: φP16 10: 2 − 1 11: Don’t care 11: Don’t care 6 7 8 Select PWM0 cycle 00 26 − 1 01 27 − 1 10 28 − 1 11 Don’t care Select PWM0 input clock 00 φP1 01 φP4 10 φP16 11 Don’t care Select PWM0 mode 0 PWM mode 1 8-bit timer mode Select PWM0 interrupt 0 Overflow interrupt 1 Compare and match interrupt Control double buffer 0 Disable 1 Enable PWM timer flip-flop2 (TFF2) output value (TO2) Note: Read-modify-write is prohibited. Figure 3.8.5 8-Bit PWM0 Mode Control Register 93CW46A-110 2004-02-10 TMP93CW46A P1MOD (0029H) 7 6 5 4 3 2 1 0 Bit symbol FF3RD DB3EN PWM1INT PWM1M T3CLK1 T3CLK0 PWM1S1 PWM1S0 Read/Write R 0 0 After reset Function − Flip-flop (F/F3) output data W 0 0 1: Double buffer 3 enable 0: 2 − 1 overflow interrupt 1: Compare and match interrupt n 0 0: PWM mode 1: Timer mode 0 0 00: φP1 00: 2 − 1 01: φP4 01: 2 − 1 10: φP16 10: 2 − 1 11: Don’t care 11: Don’t care 6 7 8 Select PWM1 cycle 00 26 − 1 01 27 − 1 10 28 − 1 11 Don’t care Select PWM1 input clock 00 φP1 01 φP4 10 φP16 11 Don’t care Select PWM1 mode 0 PWM mode 1 8-bit timer mode Select PWM1 interrupt 0 Overflow interrupt 1 Compare and match interrupt Control double buffer 0 Disable 1 Enable PWM timer flip-flop3 (TFF3) output value (TO3) Note: Read-modify-write is prohibited. Figure 3.8.6 8-Bit PWM1 Mode Control Register 93CW46A-111 2004-02-10 TMP93CW46A 7 PFFCR (002AH) Bit symbol FF3C1 Read/Write After reset Function 00: 01: 10: 11: 6 5 FF3C0 FF3TRG1 4 3 FF3TRG0 FF2C1 W R/W 1 1 Don’t care Set TFF3 Clear TFF3 Don’t care 0 0 00: Disable TFF3 inverted. 01: Invert by match. 10: Set by match; clear by overflow. 11: Clear by match; set by overflow. 00: 01: 10: 11: 2 1 0 FF2C0 FF2TRG1 FF2TRG0 W R/W 1 1 Don’t care Set TFF2 Clear TFF2 Don’t care 0 0 00: Disable TFF2 inverted. 01: Invert by match. 10: Set by match; clear by overflow. 11: Clear by match; set by overflow. Select PWM timer F/F2 (TFF2) trigger 00 Disable TFF2 trigger. 01 Invert by compare and match. 10 Set by compare and match. Clear by 2n − 1 overflow. 11 Clear by compare and match. Set by 2n − 1 overflow. Control PWM timer F/F2 (TFF2) 00 Don’t care 01 Set TFF2 to “1”. 10 Clear TFF2 to “0”. 11 Don’t care Select PWM timer F/F3 (TFF3) trigger 00 Disable TFF3 trigger. 01 Invert by compare and match. 10 Set by compare and match. Clear by 2n − 1 overflow. 11 Clear by compare and match. Set by 2n − 1 overflow. Control PWM timer F/F3 (TFF3) 00 Don’t care 01 Set TFF3 to “1”. 10 Clear TFF3 to “0”. 11 Don’t care Figure 3.8.7 8-Bit PWM F/F Control Register 93CW46A-112 2004-02-10 TMP93CW46A 7 TRUN (0020H) Bit symbol PRRUN Read/Write R/W After reset 0 6 5 4 3 T5RUN T4RUN P1RUN 2 1 0 P0RUN T1RUN T0RUN 0 0 0 R/W 0 Function 0 0 Prescaler and timer run/stop control 0: Stop and clear 1: Run (Count up) Count operation 0 Stop and clear 1 Count PRRUN: Operation of prescaler T5RUN: Operation of 16-bit timer (Timer 5) T4RUN: Operation of 16-bit timer (Timer 4) P1RUN: Operation of PWM timer (PWM1/timer 3) P0RUN: Operation of PWM timer (PWM0/timer 2) T1RUN: Operation of 8-bit timer (Timer 1) T0RUN: Operation of 8-bit timer (Timer 0) SYSCR0 Bit symbol (006EH) Read/Write After reset Function 7 6 5 4 3 2 1 0 XEN XTEN RXEN RXTEN RSYSCK WUEF PRCK1 PRCK0 1 0 1 0 0 0 R/W Highfrequency oscillator (fc) Lowfrequency oscillator (fs) Highfrequency oscillator (fc) after released 0: Stop 0: Stop 1: Oscillator 1: Oscillator STOP mode 0: Stop 1: Oscillator Lowfrequency oscillator (fs) after released STOP mode 0 0 Select clock Warm-up after timer released (Write) STOP mode 0: Don’t care 0: fc 1: Start timer 1: fs (Read) 0: Stop 1: Oscillator Select prescaler clock 00: fFPH 01: fs 10: fc/16 11: (Reserved) 0: End warm up 1: Not end warm up Figure 3.8.8 Timer Operation Control Register/System Clock Control Register 93CW46A-113 2004-02-10 TMP93CW46A The following explains PWM timer operations. (1) PWM timer mode PWM output changes under the following two conditions. Condition 1: • TFF2 is cleared to 0 when the value in the up counter (UC2) and the value set in the TREG2 match. • TFF2 is set to 1 when a 2n − 1 counter overflow (n = 6, 7, or 8) occurs. Condition 2: • TFF2 is set to 1 when the value in the up counter (UC2) and the value set in TREG2 match. • TFF2 is cleared to 0 when a 2n − 1 counter overflow (n = 6, 7, or 8) occurs. The up counter (UC2) is cleared by a 2n − 1 counter overflow. The PWM timer can output 0% to 100% duty pulses because a 2n − 1 counter overflow has a higher priority. That is, to obtain 0% output (Always low), the mode used to set TFF2 to TFF0 due to overflow (PFFCR<FF2TRG1:0> = 1, 0) must be set and 2n − 1 (Value for overflow) must be set in TREG2. To obtain 100% output (Always high), the mode must be changed: PFFCR<FF2TRG1:0> = 1, 1 then the same operation is required. PWM timing 2 −1 n PWM counter Timing in detail m−1 m m+1 2 −3 n 2 −2 n 0 01 Match detect 2n − 1 overflow counter clear Match detect Overall timing (Note) 2n − 1 overflow Timer F/F output (TO2/TO3) Figure 3.8.9 Output Waves in PWM Timer Mode Note: The above waves are obtained in a mode where the F/F is set by a match with the timer register (TREG) and reset by an overflow. 93CW46A-114 2004-02-10 TMP93CW46A Figure 3.8.10 is a block diagram of this mode. φP1 φP4 φP16 8-bit up counter (UC2) Clock control Clear P0MOD <PWM0S1:0> P0MOD<T2CLK1:0> 2n − 1 overflow Overflow control 8-bit comparator (CP2) Selector A PFFCR<FF2TRG1:0> PFFCR<FF2C1:0> Timer F/F control 8-bit timer register (TREG2) B TREG2 WR Match TO2 Shift trigger S Interrupt INTT2 Register buffer control P0MOD<DB2EN> Internal data bus P0MOD<PWM0INT> Figure 3.8.10 Block Diagram of PWM Timer Mode (PWM0) In this mode, enabling double buffer is very useful. The register buffer value shifts into TREG2 when a 2n − 1 overflow is detected, when double buffer is enabled. Using double buffer makes handling small duty waves easily. Match with TREG 2 2n − 1 overflow (Up counter = Q1) (Up counter = Q2) Shift from register buffer TREG 2 (Compared value) Register buffer Q1 Q2 Q2 Q3 Register buffer write Figure 3.8.11 Register Buffer Operation 93CW46A-115 2004-02-10 TMP93CW46A Example: To output the following PWM waves to TO2 pin using PWM0 at fc = 20 MHz System clock: High frequency (fc) High frequency clock gear: 1 (fc) Prescaler clock: System clock * Clock condition 12 µs 25.4 µs To implement 25.4 µs PWM cycle by φP1 = 0.2 µs (at fc = 20 MHz) 25.4 µs ÷ 0.2 µs = 127 = 27 − 1. Consequently, set n to 7. Since the low level cycle = 12 µs; for φP1 = 0.2 µs 12 µs ÷ 0.2 = 60 = 3CH set the 3CH in TREG2. TRUN P0MOD 7 ← − ← − 6 X 0 5 − 4 − 3 − 1 − 0 − 0 2 0 0 0 0 0 1 TREG2 P0MOD PFFCR ← 0 ← − ← − 0 1 − 1 0 − 1 0 − 1 0 0 1 0 1 0 0 1 0 1 0 P7CR P7FC TRUN ← X ← X ← 1 X X X X X − X X − − − − 1 1 1 − − − X − Stops PWM0 and clears it to 0. Sets PWM (27 − 1) mode, input clock φP1, overflow interrupt, and disables double buffer. Writes 3CH. Enables double buffer. Sets TFF2 and a mode where TFF2 is set by compare and match, and cleared by overflow. − Sets P72 as TO2 pin Starts PWM0 counting. X: Don’t care, −: No change Table 3.8.2 PWM Cycle at fc = 20 MHz, fs = 32.768 kHz Select System Clock <SYSCK> Select Prescaler Clock <PRCK1:0> 1 (fs) PWM Cycle Gear Value <GEAR2:0> XXX 0 (fc) 2 −1 7 2 −1 6 φP1 φP16 φP1 φP4 φP16 φP1 φP4 φP16 30.8 ms 123 ms 15.5 ms 62.0 ms 248 ms 31.1 ms 125 ms 498 ms 000 (fc) 12.6 µs 50.4 µs 201.6 µs 25.4 µs 101.6 µs 406.4 µs 51.0 µs 204.0 µs 816.0 µs 00 001 (fc/2) 25.2 µs 100.8 µs 403.2 µs 50.8 µs 203.2 µs 812.8 µs 102.0 µs 408.0 µs (fFPH) 010 (fc/4) 50.4 µs 201.6 µs 806.4 µs 101.6 µs 406.4 µs 1.63 ms 204.0 µs 816.0 µs 011 (fc/8) 100.8 µs 403.2 µs 1.61 ms 203.2 µs 812.8 µs 3.25 ms 408.0 µs 1.63 ms 6.53 ms 100 (fc/16) 201.6 µs 806.4 µs 3.23 ms 406.4 µs 6.50 ms 816.0 µs 3.26 ms 13.06 ms XXX 01 (Low frequency) XXX XXX 10 (fc/16 clock) XXX 7.69 ms φP4 8 2 −1 7.69 ms 201.6 µs 30.8 ms 806.4 µs 123 ms 3.23 ms 15.5 ms 406.4 µs 1.63 ms 62.0 ms 1.63 ms 248 ms 6.50 ms 31.1 ms 816.0 µs 125 ms 3.26 ms 1.63 ms 3.26 ms 498 ms 13.06 ms XXX: Don’t care 93CW46A-116 2004-02-10 TMP93CW46A (2) 8-bit timer mode Both PWM timers can be used independently as 8-bit interval timers. Since both timers operate in exactly the same way, PWM0 (Timer 2) is used for the purposes of explanation. 1. Generating interrupts at a fixed interval To generate timer 2 interrupts (INTT2) at a fixed interval using PWM0 timer, first stop PWM0, then set the operating mode, input clock, and interval in the P0MOD and TREG2 registers. Next, enable INTT2 and start counting PWM0. Example: To generate a timer 2 interrupt every 40 µs at fc = 20 MHz, set registers as follows: System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock * Clock condition TRUN P0MOD 7 ← − ← X 6 X 0 5 − 1 4 − 1 3 − 0 2 0 0 1 − X 0 − X Stops PWM timer 0 and clears it to 0. Sets 8-bit timer mode and selects φP1 (0.2 µs) and TREG2 INTEPW10 TRUN ← 1 ← − ← 1 1 − X 0 − − 0 − − 1 1 − 0 1 1 0 0 − 0 0 − compare interrupt. Sets 40 µs ÷ 0.2 µs = C8H in timer register. Enables INTT2 and sets interrupt level 4. Starts counting PWM0. X: Don’t care, −: No change Select an input clock using the Table 3.8.1. Note: To generate interrupts in 8-bit timer mode, P0MOD<PWM0INT> must be set to 1. 93CW46A-117 2004-02-10 TMP93CW46A 2. Generating a 50% square wave To generate a 50% square wave, invert the timer flip-flop at a fixed interval and output the timer flip-flop value to the timer output pin (TO2). Example: To output a 2.0 µs square wave at fc = 20 MHz from TO2 pin, set registers as follows. System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock * Clock condition TRUN P0MOD 7 ← − ← X 6 X 0 5 − 1 4 − 1 3 − 0 2 0 0 1 − X 0 − X TREG2 PFFCR P7CR P7FC TRUN ← ← ← ← ← 0 − X X X 0 − X X − 0 − X X − 0 1 − − − 1 0 1 1 1 0 0 − − − 1 1 − X − 0 − X X 1 Stops PWM0 and clears it to 0. Sets 8-bit timer mode and selects φP1 (0.2 µs) as the input clock. Sets 2.0 µs ÷ 0.2 µs ÷ 2 = 5 in the timer register. Clears TFF2 to TFF0 and inverts using comparator output. Sets P72 as TO2 pin. Starts counting PWM0. X: Don’t care, −: No change φP1 TRUN Up counter 01 02 03 04 05 06 01 02 04 05 06 01 02 Comparator timing Match detect UC clear TFF2 TO2 1.0 µs (at fc = 20 MHz) Figure 3.8.12 Square Wave (50% duty) Output Timing Chart 93CW46A-118 2004-02-10 TMP93CW46A This mode is as shown in Figure 3.8.13 below. φP1 φP4 φP16 8-bit up counter (UC2) Clock control Clear P0MOD<T2CLK1:0> 8-bit comparator (CP2) Match 8-bit timer register (TREG2) B Selector Timer F/F control TO2 PFFCR<FF2C1:0> PFFCR<FF2TRG1:0> Shift trigger Interrupt TREG2 WR A S INTT2 Register buffer control P0MOD<DB2EN> P0MOD<PWM0INT> Register write Internal data bus Figure 3.8.13 Block Diagram of 8-Bit Timer Mode 93CW46A-119 2004-02-10 TMP93CW46A 3.9 16-Bit Timers The TMP93CW46A contains two (Timer 4 and timer 5) multifunctional 16-bit timer/event counters with the following operation modes. • 16-bit interval timer mode • 16-bit event counter mode • 16-bit programmable pulse generation (PPG) mode • Frequency measurement mode • Pulse width measurement mode • Time differential measurement mode Timer/event counter consists of 16-bit up counter, two 16-bit timer registers (One of them applies double buffer), two 16-bit capture registers, two comparators, capture input controller, and timer flip-flop and the control circuit. Timer/event counter is controlled by 4 control registers: T4MOD/T5MOD, T4FFCR/T5FFCR, TRUN and T45CR. Figure 3.9.1, 3.9.2 show the block diagram of 16-bit timer/event counter (Timer 4 and timer 5). Timer 4 and 5 can be used independently. All timer operate in the same manner except the following points, and thus only the operation of timer 4 will be explained below. (Different points between timer 4 and 5) Timer out pin Different phased pulse output mode Timer 4 Timer 5 TO4 pin (TFF4) TO5 pin (TFF5) TO6 pin (TFF6) no TO7 pin (TFF7) Yes No (no TO7 pin) 93CW46A-120 2004-02-10 TFF1 TI4 TI5 T4MOD <CAP12M1:0> TI4 Capture control 93CW46A-121 Selector Trigger Capture register 1 CAP1 Register buffer 4 TREG4 Comparator CP4 T4MOD<T4CLK1:0> Upper byte φT1 φT4 φT16 Software capture T4MOD<CAP1IN> Upper byte Internal data bus T45CR<DB4EN> Lower byte Selector Match detection Capture register 2 CAP2 TREG5 Comparator CP5 T4MOD<CLE> TRUN<T4RUN> Upper byte Clear Trigger Upper byte TREG4-WR 16-bit up counter UC4 TRUN<T4RUN> Lower byte Internal data bus Lower byte Match detection Timer F/F control TO4 TO5 TFF4 TFF5 T4MOD<CAP2T5, EQ5T5> T4FFCR Lower byte TMP93CW46A INTTR5 INTTR4 INT4 INT5 Figure 3.9.1 Block Diagram of 16-Bit Timer (Timer 4) 2004-02-10 TFF1 TI6 TI7 INT6 INT7 93CW46A-122 Note: Selector Register buffer 6 TREG6 Comparator CP6 T5MOD<T6CLK1:0> Upper byte φT1 φT4 φT16 Trigger Capture register 3 CAP3 Only one timer output pin for the timer 5. T5MOD <CAP34M1:0> TI6 Capture control T5MOD<CAP3IN> Software capture Upper byte Internal data bus T45CR<DB6EN> Lower byte Selector Match detection Capture register 4 CAP4 TREG7 Comparator CP7 T5MOD<CLE> Upper byte Clear TRUN<T5RUN> Trigger Upper byte TREG6-WR 16-bit up counter UC5 TRUN<T5RUN> Lower byte Internal datda bus Lower byte Match detection Timer F/F control T5FFCR Lower byte TFF6 TO6 TMP93CW46A INTTR7 INTTR6 Figure 3.9.2 Block Diagram of 16-Bit Timer (Timer 5) 2004-02-10 TMP93CW46A 7 T4MOD (0038H) Bit symbol CAP2T5 Read/Write After reset Function 6 5 EQ5T5 CAP1IN W R/W 0 0 TFF5 invert trigger 0: Disable trigger 1: Enable trigger Invert Invert when the when the UC value is up counter loaded to matches CAP2 TREG5 1 0: Software capture 1: Don’t care 4 3 2 1 CAP12M1 CAP12M0 CLE T4CLK1 R/W R/W 0 0 Capture timing 0 1: UC4 clear enable 00: Disable INT4 occurs at rise edge. 01: TI4↑ TI5↑ INT4 occurs at rise edge. 10: TI4↑ 0 T4CLK0 R/W 0 0 Timer 4 source clock 00: TI4 01: φT1 10: φT4 11: φT16 TI4↓ INT4 occurs at fall edge. 11: TFF1↑ TFF1↓ INT4 occurs at rise edge. Timer 4 input clock 00 External clock (TI4) 01 φT1 10 φT4 11 φT16 Clearing the up counter UC4 0 Clear disable 1 Clear by match with TREG5. Figure 3.9.3 16-Bit Timer Mode Controller Register (T4MOD) (1/2) 93CW46A-123 2004-02-10 TMP93CW46A 7 T4MOD (0038H) Bit symbol CAP2T5 Read/Write After reset Function 6 5 EQ5T5 CAP1IN W R/W 0 0 TFF5 invert trigger 0: Disable trigger 1: Enable trigger Invert Invert when the when the UC value is up counter loaded to matches CAP2 TREG5 1 0: Software capture 1: Don’t care 4 3 2 1 CAP12M1 CAP12M0 CLE T4CLK1 R/W R/W 0 0 1: UC4 clear enable 00: Disable INT4 occurs at rise edge. 01: TI4↑ 0 0 Timer 4 source clock 00: TI4 01: φT1 10: φT4 TI5↑ INT4 occurs at rise edge. 10: TI4↑ T4CLK0 R/W 0 Capture timing 0 11: φT16 TI4↓ INT4 occurs at fall edge. 11: TFF1↑ TFF1↓ INT4 occurs at rise edge. Capture timing of timer 4 Capture control 00 01 Capture disable CAP1 at TI4 rise CAP2 at TI5 rise CAP1 at TI4 rise 10 CAP2 at TI4 fall CAP1 at TFF1 rise 11 CAP2 at TFF1 fall INT4 control Interrupt occurs at the rise edge of TI4 (INT4) input. Interrupt occurs at the fall edge of TI4 (INT4) input. Interrupt occurs at the rise edge of TI4 (INT4) input. Software capture 0 The up counter 4 value is loaded to CAP1 (Software capture). 1 Always read as “1”. Timer flip-flop 5 (TFF5) invert trigger 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission) CAP2T5: Invert when the up counter value is loaded to CAP2 EQ5T5: Invert when the up counter matches TREG5 Figure 3.9.4 16-Bit Timer Controller Register (T4MOD) (2/2) 93CW46A-124 2004-02-10 TMP93CW46A 7 T4FFCR Bit symbol (0039H) Read/Write After reset Function TFF5C1 6 5 4 3 2 1 TFF5C0 CAP2T4 CAP1T4 EQ5T4 EQ4T4 TFF4C1 R/W R/W R/W R/W 0 0 0 0 W 1 00: Invert 1 0 TFF4C0 W 1 1 TFF5 TFF4 invert trigger 00: Invert 01: Set TFF5 0: Disable trigger 01: Set TFF4 10: Clear TFF5 1: Enable trigger 10: Clear TFF4 TFF4 11: Don’t care Invert when Invert when Invert when Invert when 11: Don’t care Always read as “11”. the UC value the UC value the UC the UC Always read as “11” is loaded to is loaded to matches matches CAP2 CAP1 TREG5 TREG4 Timer flip-flop 4 (TFF4) control 00 Inverts the TFF4 value (Software inversion). 01 Sets TFF4 to “1”. 10 Clear TFF4 to “0”. 11 Don’t care (Always read as “11”). Timer flip-flop 4 (TFF4) invert trigger 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission) CAP2T4: Invert when the up counter value is loaded to CAP2 CAP1T4: Invert when the up counter value is loaded to CAP1 EQ5T4: Invert when up counter matches TREG5 EQ4T4: Invert when up counter matches TREG4 Timer flip-flop 5 (TFF5) control 00 Inverts the TFF5 value (Software inversion). 01 Sets TFF5 to “1”. 10 Clear TFF5 to “0”. 11 Don’t care (Always read as “11”.) Figure 3.9.5 16-Bit Timer 4 F/F Control (T4FFCR) 93CW46A-125 2004-02-10 TMP93CW46A 7 T5MOD (0048H) 6 5 4 3 2 1 T5CLK1 Bit symbol CAP3IN CAP34M1 CAP34M0 CLE Read/Write W R/W R/W After reset Function 1 0: Software capture 1: Don’t care 0 0 0 1: UC5 clear enable Capture timing 00: Disable INT6 occurs at rise edge. 01: TI6↑ TI7↑ INT6 occurs at rise edge. 10: TI6↑ 0 T5CLK0 R/W 0 0 Timer 5 source clock 00: TI6 01: φT1 10: φT4 11: φT16 TI6↓ INT6 occurs at fall edge. 11: TFF1↑ TFF1↓ INT6 occurs at rise edge. Timer 5 input clock 00 External clock (TI6) 01 φT1 10 φT4 11 φT16 Clearing the up counter UC5 0 Clear disable 1 Clear by match with TREG7 Figure 3.9.6 16-Bit Timer Mode Control Register (T5MOD) (1/2) 93CW46A-126 2004-02-10 TMP93CW46A 7 T5MOD (0048H) 6 5 4 3 2 1 T5CLK1 Bit symbol CAP3IN CAP34M1 CAP34M0 CLE Read/Write W R/W R/W After reset Function 1 0: Software capture 1: Don’t care 0 0 00: Disable INT6 occurs at rise edge. 01: TI6↑ 0 0 Timer 5 source clock 00: TI6 01: φT1 10: φT4 TI7↑ INT6 occurs at rise edge. 10: TI6↑ T5CLK0 R/W 0 1: UC5 clear enable Capture timing 0 11: φT16 TI6↓ INT6 occurs at fall edge. 11: TFF1↑ TFF1↓ INT6 occurs at rise edge. Timer 5 capture timing Capture control 00 01 Capture disable CAP3 at TI6 rise CAP4 at TI7 rise CAP3 at TI6 rise 10 CAP4 at TI6 fall CAP3 at TFF1 rise 11 CAP4 at TFF1 fall INT6 control Interrupt occurs at the rise edge of TI6 (INT6) input. Interrupt occurs at the fall edge of TI6 (INT6) input. Interrupt occurs at the rise edge of TI6 (INT6) input. Software capture 0 The up counter 5 value is loaded to CAP3. 1 Don’t care. (Always read as “1”.) Figure 3.9.7 16-Bit Timer Control Register (T5MOD) (2/2) 93CW46A-127 2004-02-10 TMP93CW46A 7 T5FFCR (0049H) 6 5 4 3 2 1 Bit symbol CAP4T6 CAP3T6 EQ7T6 EQ6T6 TFF6C1 Read/Write R/W R/W R/W R/W 0 0 0 0 After reset Function 0 TFF6C0 W 1 1 TFF6 invert trigger 00: Invert 0: Disable trigger 01: Set TFF6 1: Enable trigger 10: Clear TFF6 TFF6 Invert when Invert when Invert when Invert when 11: Don’t care the UC value the UC value the UC the UC Always read as “11” is loaded to is loaded to matches matches CAP4 CAP3 TREG7 TREG6 Timer flip-flop 6 (TFF6) control 00 Inverts the TFF6 value (Software inversion). 01 Sets TFF6 to “1”. 10 Clear TFF6 to “0”. 11 Don’t care. (Always read as “11”.) Timer flip-flop 6 (TFF6) invert trigger 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission) CAP4T6: Invert when the up counter value is loaded to CAP4 CAP3T6: Invert when the up counter value is loaded to CAP3 EQ7T6: Invert when up counter matches TREG7 EQ6T6: Invert when up counter matches TREG6 Figure 3.9.8 16-Bit Timer 5 F/F Control (T5FFCR) 93CW46A-128 2004-02-10 TMP93CW46A 7 T45CR (003AH) Bit symbol QCU Read/Write R/W After reset Function 6 5 4 3 2 1 0 DB6EN DB4EN R/W 0 0 Warm-up Double buffer timer 0: Disable control 1: Enable 0 Double Double buffer of buffer of TREG6 TREG4 Double buffer control 0 Disable 1 Enable DB6EN: Double buffer to TREG6 DB4EN: Double buffer to TREG4 Warm-up timer input control Note 1: 0 Use 7-stage binary counter 1 Not Use 7-stage binary counter (Note) In case of unused the 7-stage binary counter as a warm-up timer, the stable clock must be input from external circuit. Note 2: T45CR<bit6:2> is always read as “1”. Figure 3.9.9 16-Bit Timer Trigger Control Register (T45CR) 93CW46A-129 2004-02-10 TMP93CW46A 7 TRUN (0020H) Bit symbol PRRUN Read/Write R/W After reset 0 6 5 4 3 T5RUN T4RUN P1RUN 2 1 0 P0RUN T1RUN T0RUN 0 0 0 R/W 0 Function 0 0 Prescaler and timer run/stop control 0: Stop and clear 1: Run (Count up) Count operation 0 Stop and clear 1 Count PRRUN: Operation of prescaler T5RUN: Operation of 16-bit timer (Timer 5) T4RUN: Operation of 16-bit timer (Timer 4) P1RUN: Operation of PWM timer (PWM1/timer 3) P0RUN: Operation of PWM timer (PWM0/timer 2) T1RUN: Operation of 8-bit timer (Timer 1) T0RUN: Operation of 8-bit timer (Timer 0) Note: TRUN<bit6> is always read as “1”. SYSCR0 Bit symbol (006EH) Read/Write After reset Function 7 6 5 4 3 2 1 0 XEN XTEN RXEN RXTEN RSYSCK WUEF PRCK1 PRCK0 1 0 1 0 0 0 0 Lowfrequency oscillator (fs) after released STOP mode Select clock after released STOP mode R/W Highfrequency oscillator (fc) Lowfrequency oscillator (fs) Highfrequency oscillator (fc) after released 0: Stop 0: Stop 1: Oscillation 1: Oscillation STOP mode 0: Stop 1: Oscillation 0: Stop 1: Oscillation 0: fc 1: fs 0 Warm-up timer (Write) 0: Don’t care 1: Start timer (Read) 0: End warm up 1: Not end warm up Select prescaler clock 00: fFPH 01: fs 10: fc/16 11: (Reserved) Figure 3.9.10 Timer Operation Control Register/System Clock Control Register 93CW46A-130 2004-02-10 TMP93CW46A 1. Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock for 8-bit timers 0 and 1, 16-bit timers 4 and 5 and serial interfaces 0 to 4. Figure 3.9.11 shows the block diagram. Table 3.9.1 shows prescaler clock resolution into 8-/16-bit timer. To CPU 2 fFPH …… To 8-bit PWM prescaler 9-bit prescaler fs Selector XT1 Selector Selector 2 4 8 16 32 64 128 256 512 fc fc/2 2 4 SYSCR0 <PRCK1:0> Run/stop & clear TRUN<PRRUN> φT1 φT4 φT16 φT256 To 8-bit timers 0 and 1 φT1 φT4 φT16 To 16-bit timers 4 and 5 φ1 φT0 φT2 φT8 φT32 SYSCR1<SYSCK> 2 To serial interfaces 0 to 4 fc/4 fc/8 fc/16 SYSCR1<GEAR2:0> X1 ÷2 ÷4 ÷8 ÷16 Figure 3.9.11 The Block Diagram of Prescaler Table 3.9.1 Prescaler Clock Resolution to 8-/16-Bit Timer at fc = 20 MHz, fs = 32.768 kHz System Clock Selection <SYSCK> Prescaler Clock Selection <PRCK1:0> 1 (fs) Clock Gear fs/2 (244 µs) fc/2 3 (0.4 µs) fc/2 4 (0.8 µs) 010 (fc/4) fc/2 5 011 (fc/8) 000 (fc) 0 (fc) XXX XXX (fFPH) 01 (Low-frequency clock) 10 (fc/16 clock) φT1 3 XXX 00 Prescaler Clock Resolution Value <GEAR2:0> 001 (fc/2) φT4 φT16 φT256 fs/2 5 (977 µs) fs/2 (3.9 ms) fs/211 (62.5 ms) fc/2 5 (1.6 µs) fc/2 (6.4 µs) fc/211 (102.4 µs) fc/2 6 (3.2 µs) fc/2 (12.8 µs) fc/2 (1.6 µs) fc/2 7 (6.4 µs) fc/2 (25.6 µs) fc/213 (409.6 µs) fc/26 (3.2 µs) fc/2 8 (12.8 µs) fc/210 (51.2 µs) fc/214 (819.2 µs) 7 (6.4 µs) fc/2 9 (25.6 µs) fc/2 (102.4 µs) fc/2 (244 µs) fs/2 5 (977 µs) fs/27 (3.9 ms) fs/211 (62.5 ms) (6.4 µs) fc/2 (25.6 µs) fc/2 (102.4 µs) fc/2 100 (fc/16) fc/2 XXX fs/23 XXX fs/2 7 XXX: Don’t care 9 7 7 8 9 11 11 12 15 15 (204.8 µs) (1.64 ms) (1.64 ms) 16-bit timer 8-bit timer Note: The fc/16 clock as a prescaler clock can not be usedwhen the fs is used as a system clock. 93CW46A-131 2004-02-10 TMP93CW46A The clock selected among fFPH clock, fc/16 clock and fs is divided by 4 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to “00” selects the fFPH clock input divided by 2. The 16-bit timer selects between 3 clock inputs: φT1, φT4, and φT16 among the prescaler outputs. This prescaler can be run or stopped by the timer operation control register TRUN<PRRUN>. Counting starts when <PRRUN> is set to “1”. The prescaler is cleared zero and stops operation when <PRRUN> is set to “0”. Resetting clear <PRRUN> to “0” and stops the prescaler. When the IDLE1 mode (Only the oscillator operates) is used, set TRUN<PRRUN> to “0” to stop this prescaler before the “HALT” instruction is executed. 2. Up counter The up counter is a 16-bit binary counter which counts up according to the input clock specified by T4MOD<T4CLK1:0> register. As the input clock, one of the internal clocks φT1, φT4, and φT16 from 9-bit prescaler (also used for 8-bit timer), and external clock from TI4 pin (also used as P80/INT4 pin) can be selected. When reset, it will be initialized to <T4CLK1:0> = 00 to select TI4 input mode. Counting or stop and clear of the counter is controlled by timer operation control register TRUN<T4RUN>. When clearing is enabled, up counter UC will be cleared to zero each timer it coincides matches the timer register TREG5. The “clear enable/disable” is set by T4MOD<CLE>. If clearing is disabled, the counter operates as a free-running counter. 3. Timer register These two 16-bit registers are used to set the counter value. When the value of up counter UC4 matches the set value of this timer register, the comparator match detect signal will be active. Setting data for timer both registers (TREG4 and TREG5) is always needed. For example, either using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8-bits in order. TREG 4 TREG 5 Upper 8 bits Lower 8 bits Upper 8 bits Lower 8 bits 000031H 000030H 000033H 000032H TREG 6 Timer 4 TREG 7 Upper 8 bits Lower 8 bits Upper 8 bits Lower 8 bits 000041H 000040H 000043H 000042H Timer 5 TREG4 timer register is a double buffer structure, which is paired with register buffer. The timer control register T45CR<DB4EN> controls whether the double buffer structure should be enabled or disable d.: disabled when <DB4EN> = 0, while enabled when <DB4EN> = 1. When the double buffer is enabled, the timing to transfer data from the register buffer to the timer register is at the match between the up counter (UC4) and timer register TREG5. When reset, it will be initialized to <DB4EN> = 0, whereby the double buffer is disabled. To use the double buffer, write data in the timer register, set <DB4EN> = 1, and then write the following data in the register buffer. 93CW46A-132 2004-02-10 TMP93CW46A TREG4 and register buffer are allocated to the same memory addresses 000030H/000031H. When <DB4EN> = 0, the same value will be written in both TREG4 and register buffer. When <DB4EN> = 1, the value is written into only the register buffer. 4. Capture register These 16-bit registers are used to hold the values of the up counter. Data in the capture registers should be read all 16 bits. For example, using a 2-byte data load instruction or two 1-byte data load instruction, from the lower 8 bits followed by the upper 8 bits. CAP 1 CAP 2 Upper 8 bits Lower 8 bits Upper 8 bits Lower 8 bits 000035H 000034H 000037H 000036H CAP 3 5. 16-bit timer 4 CAP 4 Upper 8 bits Lower 8 bits Upper 8 bits Lower 8 bits 000045H 000044H 000047H 000046H 16-bit timer 5 Capture input control This circuit controls the timing to latch the value of up counter UC4 into the capture register (CAP1, CAP2). The latch timing of capture register is controlled by register T4MOD<CAP12M1:0>. • When T4MOD<CAP12M1:0> = 00 Capture function is disabled. Disable is the default on reset. • When T4MOD<CAP12M1:0> = 01 Data is loaded to CAP1 at the rising edge of TI4 pin (also used as P80/INT4) input, while data is loaded to CAP2 at the rising edge of TI5 pin (also used as P81/INT5) input. (Time difference measurement) • When T4MOD<CAP12M1:0> = 10 Data is loaded to CAP1 at the rising edge of TI4 pin input, while to CAP2 at the falling edge. Only in this setting, interrupt INT4 occurs at falling edge. (Pulse width measurement) • When T4MOD<CAP12M1:0> = 11 Data is loaded to CAP1 at the rising edge of timer flip-flop TFF1, while to CAP2 at the falling edge. Besides, the value of up counter can be loaded to capture registers by software. Whenever “0” is written in T4MOD<CAPIN> the current value of up counter will be loaded to capture register CAP1. It is necessary to keep the prescaler in RUN mode (TRUN<PRRUN> to be “1”). 6. Comparator These are 16-bit comparators which compare the up counter UC4 value with the set value of (TREG4, TREG5) to detect the match. When a match is detected, the comparators generate an interrupt (INTTR4, INTTR5) respectively. The up counter UC4 is cleared only when UC4 matches TREG5. (The clearing of up counter UC4 can be disabled by setting T4MOD<CLE> = 0.) 93CW46A-133 2004-02-10 TMP93CW46A 7. Timer flip-flop (TFF4) This flip-flop is inverted by the match detect signal from the comparators and the latch signals to the capture registers. Disable/enable of inversion can be set for each element by T4FFCR<CAP2T4, CAP1T4, EQ5T4, EQ4T4>. TFF4 will be inverted when “00” is written in T4FFCR<TFF4C1:0>. Also it is set to “1” when “01” is written, and cleared to “0” when “10” is written. The value of TFF4 can be output to the timer output pin TO4 (also used as P82). TFF4 is undefined on reset. 8. Timer flip-flop (TFF5) This flip-flop is inverted by the match detect signal between the up counter (UC4) and the timer register TREG5 and the latch signal to the capture register CAP2. Disable/enable of inversion can be set for each element by T4MOD<CAP2T5, EQ5T5>. TFF5 will be inverted when “00” is written in T4FFCR<TFF5C1:0>. Also it is set to “1” when “01” is written, and cleared to “0” when “10” is written. The value of TFF5 can be output to the timer output pin TO5 (also used as P83). TFF5 is undefined on reset. Note: This flip-flop (TFF5) is contained only in the 16-bit timer 4. 93CW46A-134 2004-02-10 TMP93CW46A (1) 16-bit timer mode Generating interrupts at fixed intervals. In this example, the interval time is set in the timer register TREG5 to generate the interrupt INTTR5. TRUN INTET54 7 ← − ← 1 6 X 1 5 − 0 4 0 0 3 − 1 T4FFCR T4MOD ← 1 ← 0 1 0 0 1 TREG5 ← * * * * * * 0 0 0 1 1 0 0 1 * * (** = 01, 10, 11) * * * * * * * * * * TRUN ← 1 X − 1 − 2 − 0 − 1 − 0 − 0 − 0 − Stop timer 4. Enable INTTR5 and sets interrupt level 4. Disable INTTR4. Disable trigger. Select internal clock for input and disable the capture function. Set the interval time (16 bits). Start timer 4. X: Don’t care, −: No change (2) 16-bit event counter mode In 16-bit timer mode as described in above, the timer can be used as an event counter by selecting the external clock (TI4 pin input) as the input clock. To read the value of the counter, first perform “software capture” once and read the captured value. The counter counts at the rising edge of TI4 pin input. TI4 pin can also be used as P80/INT4. TRUN P8CR INTET54 7 ← − ← − ← 1 6 X − 1 5 − − 0 4 0 − 0 3 − − 1 2 − − 0 1 − − 0 0 − 0 0 T4FFCR T4MOD TREG5 ← 1 ← 0 ← * 1 0 * 0 1 * 0 0 * 0 0 * 0 1 * 1 0 * 1 0 * * * * ← 1 X * − * − * − * − * − TRUN Note: 1 Stop timer 4. Set P80 to input mode. Enable INTTR5 and sets interrupt level 4, while disables INTTR4. Disable trigger. Select TI4 as the input clock. Set the number of counts (16 bits). Start timer 4. When used as an event counter, set the prescaler in RUN mode. 93CW46A-135 2004-02-10 TMP93CW46A (3) 16-bit programmable pulse generation (PPG) output mode The PPG mode is obtained by inversion of the timer flip-flop TFF4 that is to be enabled by the match of the up counter UC4 with the timer register TREG4 or 5 and to be output to TO4 (also used as P82). In this mode, the following conditions must be satisfied. (Set value of TREG4) < (Set value of TREG5) T45CR TRUN TREG4 7 ← 0 ← − ← * * 6 X X * * TREG5 ← * * * * * * * * * * T45CR ← 0 X X X * − * − 1 T4FFCR ← 1 1 0 0 1 1 1 0 T4MOD ← 0 0 1 P8CR P8FC TRUN ← − ← X ← 1 − − − 0 0 1 * * (** = 01, 10, 11) − − 1 − − X − 1 X X 1 − − − − X 5 X − * * X − 4 X 0 * * 3 − − * * 2 − − * * 1 − − * * 0 0 − * * Double buffer of TREG4 disable. Stop timer 4. Set the duty. (16 bits) * * Set the cycle. (16 bits) * − * Double Buffer of TREG4 enable. (Change the duty and cycle at the interrupt INTTR5) Set the mode to invert TFF4 at the match with TREG4/TREG5, and also set the TFF4 to “0”. Select the internal clock for the input, and disable the capture function. Assign P82 as TO4. Start timer 4. X: Don’t care, −: No change Match with TREG4 (Interrupt INTTR4) Match with TREG5 (Interrupt INTTR5) TO4 pin Figure 3.9.12 Programmable Pulse Generation (PPG) Output Waveforms 93CW46A-136 2004-02-10 TMP93CW46A When the double buffer of TREG4 is enabled in this mode, the value of register buffer 4 will be shifted in TREG4 at match with TREG5. This feature makes easy the handling of low duty waves. Match with TREG4 Up counter = Q2 Up counter = Q1 Match with TREG5 Shift into the TREG5 TREG4 (Value to be compared) Q1 Q2 Register buffer Q3 Q2 Write into the TREG4 Figure 3.9.13 Operation of Register Buffer Shows the block diagram of this mode. TRUN<T4RUN> TI4 φT1 φT4 φT16 16-bit up counter UC4 Selector 16-bit comparator Match Clear 16-bit comparator TO4 (PPG output) F/F (TFF4) TO5 F/F (TFF5) Match TREG4 Selector TREG4-WR Register buffer 4 TREG5 T45CR<DB4EN> Internal data bus Figure 3.9.14 Block Diagram of 16-Bit PPG Mode 93CW46A-137 2004-02-10 TMP93CW46A (4) Application examples of capture function The loading of up counter (UC4) values into the capture registers CAP1 and CAP2, the timer flip-flop TFF4 inversion due to the match detection by comparators CP4 and CP5, and the output of the TFF4 status to TO4 pin can be enabled or disabled. Combined with interrupt function, they can be applied in many ways, for example: 1. 1. One-shot pulse output from external trigger pulse 2. Frequency measurement 3. Pulse width measurement 4. Time difference measurement One-shot pulse output from external trigger pulse Set the up counter UC4 in free-running mode with the internal input clock, input the external trigger pulse from TI4 pin, and load the value of up counter into capture register CAP1 at the rising edge of the TI4 pin. Then set to T4MOD<CAP12M1:0> = 01. When the interrupt INT4 is generated at the rising edge of TI4 input, set the CAP1 value (c) plus a delay time (d) to TREG4 ( = c + d), and set the above set value (c + d) plus a one-shot pulse width (p) to TREG5 ( = c + d + p). When the interrupt INT4 occurs the T4FFCR<EQ5T4, EQ4T4> register should be set that the TFF4 inversion is enabled only when the up counter value matches TREG4 or TREG5. When interrupt INTTR5 occurs, this inversion will be disabled. Set the counter in free-running mode. Count clock (Internal clock) TI4 pin input (External trigger pulse) c+d c c+d+p Load the up counter value into capture register 1 (CAP1). INT4 occurred Match with TREG4 INTTR5 occurred Inversion enable Match with TREG5 Timer output pin TO4 Disables inversion caused by loading of the up counter value into CAP1. Inversion enable Delay time Pulse width (d) (p) Figure 3.9.15 One-shot Pulse Output (with delay) 93CW46A-138 2004-02-10 TMP93CW46A Setting example: To output 2 ms one-shot pulse with 3 ms delay to the external trigger pulse to TI4 pin System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH * Clock condition Main setting Keep counting (Free running). Count with φT1. T4MOD ← − − 1 0 1 0 0 1 T4FFCR ← 1 1 0 0 0 0 1 0 P8CR P8FC ← − ← X − − − − 1 1 − X − − − X X X INTE45 INTET54 TRUN ← − ← 1 ← 1 − − − 0 X 0 − 0 1 1 1 − 1 0 − 0 0 − 0 0 − ← CAP1 + 3 ms/φT1 ← TREG4 + 2 ms/φT1 ← − − − − 1 1 − − Load the up counter value into CAP1 at the rise edge of TI4 pin input. Clear TFF4 to zero. Disable TFF4 inversion. Select P82 as the TO4 pin. Enable INT4, and disable INTTR4 and INTTR5. Start timer 4. Setting of INT4 TREG4 TREG5 T4FFCR INTET54 ← 1 1 0 0 − − − − − − − 0 0 − − Enable TFF4 inversion when the up counter value matches TREG4 or 5. Enable INTTR5. Setting of INTTR5 T4FFCR INTET54 ← − ← 1 0 0 0 − − − − Disable TFF4 inversion when the up counter value matches TREG4 or 5. Disable INTTR5. X: Don’t care, −: No change When delay time is unnecessary, invert timer flip-flop TFF4 when the up counter value is loaded into capture register 1 (CAP1), and set the CAP1 value (c) plus and the one-shot pulse width (p) to TREG5 when the interrupt INT4 occurs. The TFF4 inversion should be enabled when the up counter (UC4) value matches TREG5, and disabled when generating the interrupt INTTR5. 93CW46A-139 2004-02-10 TMP93CW46A Count clock (Internal clock) c+p c TI4 pin input (External trigger pulse) Load the up counter value into capture register 1 (CAP1). INT4 occurred INTTR5 occurred Match with TREG5 Load the up counter value into capture register 2 (CAP2). Inversion enable Timer output pin TO4 Pulse width Enables inversion caused by Disables inversion caused by loading of (p) loading of the up counter value the up counter value into CAP2. into CAP1. Figure 3.9.16 One-shot Pulse Output (without Delay) 2. Frequency measurement The frequency of the external clock can be measured in this mode. The clock is input through the TI4 pin, and its frequency is measured by the 8-bit timers (Timer 0 and timer 1) and the 16-bit timer/event counter (Timer 4). The TI4 pin input should be selected for the input clock of timer 4. The value of the up counter is loaded into the capture register CAP1 at the rising edge of the timer flip-flop TFF1 of 8-bit timers (Timer 0 and timer 1), and into CAP2 at its falling edge. The frequency is calculated by the difference between the loaded values in CAP1 and CAP2 when the interrupt (INTT0 or INTT1) is generated by either 8-bit timer. Count clock (Internal clock) C1 C2 TFF1 Loading UC4 into CAP1 Loading UC4 into CAP2 C1 C1 C2 C2 INTT0/INTT1 Figure 3.9.17 Frequency Measurement For example, if the value for the level “1” width of TFF1 of the 8-bit timer is set to 0.5 [s], and the difference between CAP1 and CAP2 is 100, the frequency will be 100 ÷ 0.5 [s] = 200 [Hz]. 93CW46A-140 2004-02-10 TMP93CW46A 3. Pulse width measurement This mode allows to measure the “H” level width of an external pulse. While keeping the 16-bit timer/event counter counting (Free running) with the internal clock input, the external pulse is input through the TI4 pin. Then the capture function is used to load the UC4 values into CAP1 and CAP2 at the rising edge and falling edge of the external trigger pulse respectively. The interrupt INT4 occurs at the falling edge of TI4. The pulse width is obtained from the difference between the values of CAP1 and CAP2 and the internal clock cycle. For example, if the internal clock is 0.8 microseconds and the difference between CAP1 and CAP2 is 100, the pulse width will be 100 × 0.8 µs = 80 µs. Count clock (Internal clock) C2 C1 TI4 pin (External pulse) Loading UC4 into CAP1 Loading UC4 into CAP2 C1 C1 C2 C2 INT4 Figure 3.9.18 Pulse Width Measurement Note: Only in this pulse width measuring mode (T4MOD<CAP12M1:0> = 10), external interrupt INT4 occurs at the falling edge of TI4 pin input. In other modes, it occurs at the rising edge. The width of “L” level can be measured from the difference between the first C2 and the second C1 at the second INT4 interrupt. 93CW46A-141 2004-02-10 TMP93CW46A 4. Time difference measurement This mode is used to measure the difference in time between the rising edges of external pulses input through TI4 and TI5. Keep the 16-bit timer/event counter (Timer 4) counting (Free running) with the internal clock, and load the UC4 value into CAP1 at the rising edge of the input pulse to TI4. Then the interrupt INT4 is generated. Similarly, the UC4 value is loaded into CAP2 at the rising edge of the input pulse to TI5, generating the interrupt INT5. The time difference between these pulses can be obtained from the difference between the time counts at which loading the up counter value into CAP1 and CAP2 has been done. Count clock (Internal clock) C1 C2 TI4 pin input TI5 pin input Loading UC4 into CAP1 Loading UC4 into CAP2 INT4 INT5 Time difference Figure 3.9.19 Time Difference Measurement 93CW46A-142 2004-02-10 TMP93CW46A (5) Different phased pulses output mode (This mode can be used only timer 4.) In this mode, signals with any different phase can be outputted by free-running up counter UC4. When the value in up counter UC4 and the value in TREG4 (TREG5) match, the value in TFF4 (TFF5) is inverted and output to TO4 (TO5). Counter (Free running) Match with TREG4 Match with TREG5 TO4 TO5 Figure 3.9.20 Phase Output Cycles (Counter overflow time) of the above output waves are listed on Table 3.9.2. Table 3.9.2 Timer Output Cycle on the Different Phased Pulse Output Mode at fc = 20 MHz, fs = 32.768 kHz Select System Select Prescaler Clock Clock <SYSCK> <PRCK1:0> 1 (fs) XXX Counter Overflow Time φT1 15.999 s φT4 φT16 64.000 s 256.000 s 000 (fc) 26.214 ms 104.858 ms 419.430 ms 00 001 (fc/2) 52.429 ms 209.715 ms 838.861 ms (fFPH) 010 (fc/4) 104.858 ms 419.430 ms 1.678 s 011 (fc/8) 209.715 ms 838.861 ms 3.355 s 100 (fc/16) 419.430 ms 1.678 s 6.711 s XXX 01 (Low-frequency clock) XXX 15.999 s 64.000 s 256.000 s XXX 10 (fc/16 clock) XXX 419.430 ms 1.678 s 6.711 s 0 (fc) XXX: Gear Value <GEAR2:0> Don’t care 93CW46A-143 2004-02-10 TMP93CW46A 3.10 Serial Channel TMP93CW46A contains 5 serial I/O channels. Channels 0 to 3 select UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission). Channel 4 is used only in UART mode. The serial channel has the following operation modes. Mode 0: To transmit and receive I/O data using the synchronizing signal SCLK for extending I/O. • I/O interface mode (Channel 0 to 3) Mode 1: 7-bit data Mode 2: 8-bit data Mode 3: 9-bit data • UART mode (Channel 0 to 4) In mode 1 and mode 2, a parity bit can be added. Mode 3 has a wake-up function for making the master controller start slave controllers in a serial link system. Figure 3.10.1 shows the data format in each mode. Serial channels 0 to 4 can be used independently. All channels have the same operations except the following points, thus only the operation of channel 0 will be explained below. Different points among Channels 0 to 4 Channel 0 Pin name TXD0 (P90) RXD0 (P91) CTS0 /SCLK0 Channel 1 TXD1 (P93) RXD1 (P94) SCLK1 (P95) (P92) Channel 2 Channel 3 TXD2 (P60) RXD2 (P61) CTS2 /SCLK2 TXD3 (P63) RXD3 (P64) CTS3 /SCLK3 (P62) (P65) Channel 4 TXD4 (P66) RXD4 (P67) UART mode Yes Yes Yes Yes Yes I/O interface mode Yes Yes Yes Yes No Handshake function Yes No (No CTS1 pin) Yes Yes No (No CTS4 pin) Note: Using the handshake function can transmit in units of one data format. Thus over run error is prevented. See “Handshake function” for details. 93CW46A-144 2004-02-10 TMP93CW46A • Mode 0 (I/O interface mode) Bit0 1 2 3 4 5 6 7 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 Stop Parity Start Bit0 1 2 3 4 5 6 Parity Stop • Mode 2 (8-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 7 Stop Parity Start Bit0 1 2 3 4 5 6 7 Parity Stop Start Bit0 1 2 3 4 5 6 7 8 Stop Start Bit0 1 2 3 4 5 6 7 Bit8 • Mode 3 (9-bit UART mode) Stop (Wakeup) When bit8 = 1, address (Select code) is denoted. When bit8 = 0, data is denoted. Figure 3.10.1 Data Formats 93CW46A-145 2004-02-10 TMP93CW46A The serial channel has buffer registers for transmitting and receiving operations in order to temporarily store transmitted or received data. This is done so that transmitting and receiving operations can be done independently (Full duplex). However, in I/O interface mode, the SCLK (Serial clock) pin is used for both transmitting and receiving, the channel becomes half duplex. The receiving data register is a double buffer structure to prevent the occurrence of an overrun error and it provides one data format of margin before the CPU reads the received data. The receiving data register stores the previously received data while the buffer register receives the next frame data. By using CTS and RTS (There is no RTS pin, so any single port must be controlled by software) it is possible to halt data send until the CPU finishes reading receive data every time a frame is received. (Handshake function) In the UART mode, a check function is added to not start the receiving operation by erroneous start bits due to noise. The channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings of the start bit. When the transmission buffer becomes empty and requests the CPU to send the next transmission data, or when data is stored in the receiving data register and the CPU is requested to read the data, INTTX (Transmit interrupt) or INTRX (Receive interrupt) interrupt occurs. If an overrun error, parity error, or framing error occurs during receiving operation, flag SC0CR<OERR, PERR, FERR> will be set. The serial channels 0 to 4 include a special baud rate generator, which can set to any baud rate by dividing the frequency of 4 clocks (φT0, φT2, φT8, and φT32 from the 9-bit prescaler shared by the 8-bit/16-bit timers by the value 1, 2 + n/16 to 15 + n/16, 16n = 0 to 15). In I/O interface mode, it is possible to input synchronous signals as well as to transmit or receive data by using an external clock. 3.10.1 Control Registers The serial channels are controlled by 4 control registers SC0CR, SC0MOD, BR0CR and BRADD0. Transmitted and received data are stored in register SC0BUF. Note: The number of the control register name is equaled to the channel number. 93CW46A-146 2004-02-10 TMP93CW46A SC0MOD (0052H) Bit symbol 7 6 5 4 TB8 CTSE RXE WU Read/Write 3 2 1 0 SM1 SM0 SC1 SC0 0 0 0 0 R/W After reset Undefined Function Transfer data bit8 0 0 0 Wakeup function Hand shake Receiving function 0: CTS disable 1: CTS enable 0: Receive disable 0: Disable 1: Receive 1: Enable enable Serial transmission mode Serial transmission clock (UART) 00: I/O interface mode 01: 7-bit UART 10: 8-bit UART 11: 9-bit UART 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 11: External clock (SLCK0 input) Serial transmission clock source (UART) 00 Timer 0 match detect signal 01 Baud rate generator 10 Internal clock φ1 11 External clock (SLCK0 input) Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC0CR). Serial transmission mode 00 I/O interface mode 01 10 7-bit length UART 11 8-bit length 9-bit length Wakeup function 9-bit UART 0 Interrupt when data is received 1 Interrupt only when RB8 = 1 Other mode Don’t care Receiving function 0 Receive disable 1 Receive enable Hand shake function ( CTS pin) 0 Disable (Always transferable) 1 Enable Transmission data bit8 Figure 3.10.2 Serial Mode Control Register (Channel 0, SC0MOD) 93CW46A-147 2004-02-10 TMP93CW46A SC0CR (0051H) 7 6 5 4 3 2 1 Bit symbol RB8 EVEN Read/Write R PE OERR PERR FERR SCLKS After reset Undefined Function Received Parity Parity data bit8 0: Odd 1: Even addition 0: Disable 1: Enable R/W 0 R (Cleared to 0 when read) 0 0 Overrun 0 1: Error Framing IOC R/W 0 Parity 0 0 0 0: SCLK0 0: Baud rate generator 1: SCLK0 pin input 1: SCLK0 Select I/O interface Input clock 0 Baud rate generator 1 SCLK0 pin input Edge selection for SCLK pin (Input mode only) 0 Transmits and receives ( data at rise edge of SCLK0 ) 1 Transmits and receives ( data at fall edge of SCLK0 ) Framing error flag Parity error flag Overrun error flag Cleared to 0 when read. Enable parity addition 0 Disable 1 Enable Addition/check of even parity 0 Odd parity 1 Even parity Receiving data bit8 Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing instruction. Figure 3.10.3 Serial Control Register (Channel 0, SC0CR) 93CW46A-148 2004-02-10 TMP93CW46A BR0CR (0053H) Bit symbol 7 6 5 4 − BR0ADD BR0CK1 BR0CK0 Read/Write 0 0 0 (Note) + (16 − K)/16 Always division fixed to “0”. 0: Disable 1 0 BR0S3 BR0S2 BR0S1 BR0S0 0 0 0 0 + (16 − K)/16 division enable 0 00: φT0 01: φT2 Setting of the divided frequency 10: φT8 11: φT32 1: Enable Selecting the input clock of baud rate generator 0 Disable 00 Internal clock φT0 1 Enable 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 7 BRADD0 (006BH) 2 R/W After reset Function 3 6 5 4 Bit symbol 3 2 BR0K3 BR0K2 Read/Write 1 0 BR0K1 BR0K0 0 0 R/W After reset 0 0 Function Sets frequency divisor “K” (divided by N + (16 − K)/16) Sets baud rate generator frequency divisor BR0CR<BR0ADD> = 1 BRADD0 <BR0K3:0> BR0CR 0000 (N = 16) <BR0S3:0> or 0001 (N = 1) 0000 to 1111 (N = 15) Disable Disable Disable Divided by N + (16 − K)/16 0001 (K = 1) to 1111 (K = 15) 0010 (N = 2) BR0CR<BR0ADD> = 0 0001 (N = 1) to 1111 (N = 15) 0000 (N = 16) Divided by N Note 1: Set TRUN<PRRUN> to “1” when the baud rate generator is used. Note 2: Set BR0CE<BR0ADD> to “1” after setting K (K = 1 to 15) to BRADD0<BR0K3:0> when + (16 − K)/16 division function is used. Note 3: + (16 − K)/16 division function is possible to use in only UART mode. Set BR0CR<BR0ADD> to “0” and disable + (16 − K)/16 division function in I/O interface mode. Note 4: BRADD0<bit7:4> is always read as “1”. Note 5: Don’t read from or write to BR0CR register during sending or receiving. Figure 3.10.4 Baud Rate Generator Control (Channel 0, BR0CR, BRADD0) 93CW46A-149 2004-02-10 TMP93CW46A 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Transmission) SC0BUF (0050H) Note: (Receiving) Prohibit read-modify-write for SC0BUF. Figure 3.10.5 Serial Transmission/Receiving Buffer Registers (Channel 0, BR0CR) 93CW46A-150 2004-02-10 TMP93CW46A SC1MOD (0056H) Bit symbol 7 6 5 4 TB8 − RXE WU Read/Write After reset Function 3 2 1 0 SM1 SM0 SC1 SC0 0 0 0 0 R/W Undefined Transferred data bit8 0 0 Fix at “0”. Receiving function 0: Receive disable 1: Receive enable 0 Wakeup function 0: Disable 1: Enable Serial transmission Serial transmission mode clock (UART) 00: I/O interface mode 00: TO0 trigger 01: 7-bit UART 01: Baud rate 10: 8-bit UART generator 11: 9-bit UART 10: Internal clock φ1 11: External clock (SCLK1 input) Serial transmission clock source (for UART) 00 Timer 0 match detect signal 01 Baud rate generator 10 Internal clock φ1 11 External clock (SCLK1 input) Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC1CR). Serial transmission mode 00 I/O interface mode 01 10 7-bit length UART mode 11 8-bit length 9-bit length Wakeup function 9-bit UART 0 Interrupt when data is received 1 Interrupt only when RB8 = 1 Other mode Don’t care Receiving control 0 Receive disable 1 Receive enable Transmission data bit8 Figure 3.10.6 Serial Mode Control Register (Channel 1, SC1MOD) 93CW46A-151 2004-02-10 TMP93CW46A SC1CR (0055H) 7 6 Bit symbol RB8 EVEN Read/Write R After reset Undefined Function Received data bit8 5 4 3 2 1 PE OERR PERR FERR SCLKS R/W 0 Parity R (clear to 0 when read) 0 0: Odd Parity addition 1: Even 0: Disable 1: Enable 0 0 Overrun IOC R/W 0 1: Error 0 0 0 0: SCLK1 0: Baud rate generator Parity Framing 1: SCLK1 1: SCLK1 pin input Select I/O interface input clock 0 Baud rate generate 1 SCLK1 pin input Edge selection for SCLK pin (Input mode only) 0 Transmits and receives ( data at rise edge of SCLK1 ) 1 Transmits and receives ( data at fall edge of SCLK 1 ) Framing error flag Parity error flag Overrun error flag Cleared to 0 when read Enable parity addition 0 Disable 1 Enable Addition/check of even parity 0 Odd parity 1 Even parity Receiving data bit8 Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.10.7 Serial Control Register (Channel 1, SC1CR) 93CW46A-152 2004-02-10 TMP93CW46A BR1CR (0057H) Bit symbol 7 6 5 4 − BR1ADD BR1CK1 BR1CK0 Read/Write 0 0 0 Always + (16 − K)/16 fixed to “0”. division 1 0 BR1S3 BR1S2 BR1S1 BR1S0 0 0 0 0 0 00: φT0 01: φT2 0: Disable 10: φT8 1: Enable 11: φT32 + (16 − K)/16 division enable Setting of the divided frequency Selecting the input clock of baud rate generator 0 Disable 00 Internal clock φT0 1 Enable 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 7 BRADD1 (006CH) 2 R/W After reset Function 3 6 5 4 Bit symbol 3 2 BR1K3 BR1K2 Read/Write 1 0 BR1K1 BR1K0 0 0 R/W After reset 0 0 Function Sets frequency divisor “K” (divided by N + (16 − K)/16) Sets baud rate generator frequency divisor BR1CR<BR1ADD> = 1 BRADD0 <BR1K3:0> BR1CR 0000 (N = 16) <BR1S3:0> or 0001 (N = 1) 0000 to 1111 (N = 15) Disable Disable Disable Divided by N + (16 − K)/16 0001 (K = 1) to 1111 (K = 15) 0010 (N = 2) BR1CR<BR1ADD> = 0 0001 (N = 1) to 1111 (N = 15) 0000 (N = 16) Divided by N Note 1: Set TRUN<PRRUN> to “1” when the baud rate generator is used. Note 2: Set BR1CR<BR1ADD> to “1” after setting K (K = 1 to 15) to BRADD1<BR1K3:0> when + (16 − K)/16 division function is used. Note 3: + (16 − K)/16 division function is possible to use in only UART mode. Set BR1CR<BR1ADD> to “0” and disable + (16 − K)/16 division function in I/O interface mode. Note 4: BRADD1<bit7:4> is always read as “1”. Note 5: Don’t read from or write to BR1CR register during sending or receiving. Figure 3.10.8 Baud Rate Generator Control (Channel 1, BR1CR, BRADD1) 93CW46A-153 2004-02-10 TMP93CW46A 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Transmission) SC1BUF (0054H) Note: (Receiving) Prohibit read-modify-write for SC1BUF. Figure 3.10.9 Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF) 93CW46A-154 2004-02-10 TMP93CW46A SC2MOD (002EH) Bit symbol 7 6 5 4 TB8 CTSE RXE WU Read/Write 3 2 1 0 SM1 SM0 SC1 SC0 0 0 0 0 R/W After reset Undefined 0 Function Transferred Hand shake data bit8 0: CTS disable 1: CTS enable 0 0 Receiving function Wakeup function 0: Receive 0: Disable disable 1: Enable Serial transmission mode 00: I/O interface mode 01: 7-bit UART 10: 8-bit UART 11: 9-bit UART 1: Receive enable Serial transmission clock (UART) 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 11: External clock (SCLK2 input) Serial transmission clock source (for UART) 00 Timer 0 match detect signal 01 Baud rate generator 10 Internal clock φ1 11 External clock (SCLK2 input) Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC2CR). Serial transmission mode 00 I/O interface mode 01 10 7-bit length UART mode 11 8-bit length 9-bit length Wakeup function 9-bit UART 0 Interrupt when data is received 1 Interrupt only when RB8 = 1 Other mode Don’t care Receiving control 0 Receive disable 1 Receive enable Hand shake function ( CTS pin) 0 Disable (Always transferable) 1 Enable Transmission data bit8 Figure 3.10.10 Serial Mode Control Register (Channel 2, SC2MOD) 93CW46A-155 2004-02-10 TMP93CW46A SC2CR (002DH) 7 6 Bit symbol RB8 EVEN Read/Write R After reset Undefined Function Received data bit8 5 4 3 2 1 PE OERR PERR FERR SCLKS R/W 0 R (clear to 0 when read) 0 Parity Parity 0: Odd 1: Even addition 0: Disable 1: Enable 0 0 Overrun IOC R/W 0 1: Error 0 0 0 0: SCLK2 0: Baud rate generator Parity Framing 1: SCLK2 1: SCLK2 pin input Select I/O interface input clock 0 Baud rate generate 1 SCLK2 pin input Edge selection for SCLK pin (Input mode only) 0 Transmits and receives ( data at rise edge of SCLK2 ) 1 Transmits and receives ( data at fall edge of SCLK2 ) Framing error flag Parity error flag Overrun error flag Cleared to 0 when read Enable parity addition 0 Disable 1 Enable Addition/check of even parity 0 Odd parity 1 Even parity Receiving data bit8 Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.10.11 Serial Control Register (Channel 2, SC2CR) 93CW46A-156 2004-02-10 TMP93CW46A BR2CR (002FH) Bit symbol 7 6 5 4 − BR2ADD BR2CK1 BR2CK0 Read/Write 0 0 0 Always + (16 − K)/16 fixed to “0”. division 1 0 BR2S3 BR2S2 BR2S1 BR2S0 0 0 0 0 0 00: φT0 01: φT2 0: Disable 10: φT8 1: Enable 11: φT32 + (16 − K)/16 division enable Setting of the divided frequency Selecting the input clock of baud rate generator 0 Disable 00 Internal clock φT0 1 Enable 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 7 BRADD2 (002BH) 2 R/W After reset Function 3 6 5 4 Bit symbol 3 2 BR2K3 BR2K2 Read/Write 1 0 BR2K1 BR2K0 0 0 R/W After reset 0 0 Function Sets frequency divisor “K” (divided by N + (16 − K)/16) Sets baud rate generator frequency divisor BR2CR<BR2ADD> = 1 BRADD2 <BR2K3:0> BR2CR 0000 (N = 16) <BR2S3:0> or 0001 (N = 1) 0000 to 1111 (N = 15) Disable Disable Disable Divided by N + (16 − K)/16 0001 (K = 1) to 1111 (K = 15) 0010 (N = 2) BR2CR<BR2ADD> = 0 0001 (N = 1) to 1111 (N = 15) 0000 (N = 16) Divided by N Note 1: Set TRUN<PRRUN> to “1” when the baud rate generator is used. Note 2: Set BR2CR<BR2ADD> to “1” after setting K (K = 1 to 15) to BRADD2<BR2K3:0> when + (16 − K)/16 division function is used. Note 3: + (16 − K)/16 division function is possible to use in only UART mode. Set BR2CR<BR2ADD> to “0” and disable + (16 − K)/16 division function in I/O interface mode. Note 4: BRADD2<bit7:4> is always read as “1”. Note 5: Don’t read from or write to BR2CR register during sending or receiving. Figure 3.10.12 Baud Rate Generator Control (Channel 2, BR2CR, BRADD2) 93CW46A-157 2004-02-10 TMP93CW46A 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Transmission) SC2BUF (002CH) Note: (Receiving) Prohibit read-modify-write for SC2BUF. Figure 3.10.13 Serial Transmission/Receiving Buffer Registers (Channel 2, SC2BUF) 93CW46A-158 2004-02-10 TMP93CW46A SC3MOD (003EH) Bit symbol 7 6 5 4 TB8 CTSE RXE WU Read/Write 3 2 1 0 SM1 SM0 SC1 SC0 0 0 0 0 R/W After reset Undefined 0 Function Transferred data bit8 Hand shake 0: CTS disable 1: CTS enable 0 0 Receiving function Wakeup function Serial transmission mode 0: Receive 0: Disable disable 1: Enable 00: I/O interface mode 01: 7-bit UART 10: 8-bit UART 11: 9-bit UART 1: Receive enable Serial transmission clock (UART) 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 11: External clock (SCLK3 input) Serial transmission clock source (for UART) 00 Timer 0 match detect signal 01 Baud rate generator 10 Internal clock φ1 11 External clock (SCLK3 input) Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC3CR). Serial transmission mode 00 I/O interface mode 01 10 7-bit length UART mode 11 8-bit length 9-bit length Wakeup function 9-bit UART 0 Interrupt when data is received 1 Interrupt only when RB8 = 1 Other mode Don’t care Receiving control 0 Receive disable 1 Receive enable Hand shake function ( CTS pin) 0 Disable (always transferable) 1 Enable Transmission data bit8 Figure 3.10.14 Serial Mode Control Register (Channel 3, SC3MOD) 93CW46A-159 2004-02-10 TMP93CW46A SC3CR (003DH) 7 6 Bit symbol RB8 EVEN Read/Write R 5 4 3 2 1 PE OERR PERR FERR SCLKS R/W 0 R (clear to 0 when read) After reset Undefined Function Received Parity data bit8 0: Odd Parity addition 0 1: Even 0: Disable 1: Enable 0 0 Overrun IOC R/W 0 1: Error 0 0 0 0: SCLK3 0: Baud rate generator Parity Framing 1: SCLK3 1: SCLK3 pin input Select I/O interface input clock 0 Baud rate generate 1 SCLK3 pin input Edge selection for SCLK pin (Input mode only) 0 Transmits and receives ( data at rise edge of SCLK3 ) 1 Transmits and receives ( data at fall edge of SCLK3 ) Framing error flag Parity error flag Overrun error flag Cleared to 0 when read Enable parity addition 0 Disable 1 Enable Addition/check of even parity 0 Odd parity 1 Even parity Receiving data bit8 Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.10.15 Serial Control Register (Channel 3, SC3CR) 93CW46A-160 2004-02-10 TMP93CW46A BR3CR (003FH) Bit symbol 7 6 5 4 − BR3ADD BR3CK1 BR3CK0 Read/Write 0 0 0 Always + (16 − K)/16 fixed to “0”. division 1 0 BR3S3 BR3S2 BR3S1 BR3S0 0 0 0 0 0 00: φT0 01: φT2 0: Disable 10: φT8 1: Enable 11: φT32 + (16 − K)/16 division enable Setting of the divided frequency Selecting the input clock of baud rate generator 0 Disable 00 Internal clock φT0 1 Enable 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 7 BRADD3 (003BH) 2 R/W After reset Function 3 6 5 4 Bit symbol 3 2 BR3K3 BR3K2 Read/Write 1 0 BR3K1 BR3K0 0 0 R/W After reset 0 0 Function Sets frequency divisor “K” (divided by N + (16 − K)/16) Sets baud rate generator frequency divisor BR3CR<BR3ADD> = 1 BRADD3 <BR3K3:0> BR3CR 0000 (N = 16) <BR3S3:0> or 0001 (N = 1) 0000 to 1111 (N = 15) Disable Disable Disable Divided by N + (16 − K)/16 0001 (K = 1) to 1111 (K = 15) 0010 (N = 2) BR3CR<BR3ADD> = 0 0001 (N = 1) to 1111 (N = 15) 0000 (N = 16) Divided by N Note 1: Set TRUN<PRRUN> to “1” when the baud rate generator is used. Note 2: Set BR3CR<BR3ADD> to “1” after setting K (K = 1 to 15) to BRADD3<BR2K3:0> when + (16 − K)/16 division function is used. Note 3: + (16 − K)/16 division function is possible to use in only UART mode. Set BR3CR<BR3ADD> to “0” and disable + (16 − K)/16 division function in I/O interface mode. Note 4: BRADD3<bit7:4> is always read as “1”. Note 5: Don’t read from or write to BR3CR register during sending or receiving. Figure 3.10.16 Baud Rate Generator Control (Channel 3, BR3CR, BRADD3) 93CW46A-161 2004-02-10 TMP93CW46A 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Transmission) SC3BUF (003CH) Note: (Receiving) Prohibit read-modify-write for SC3BUF. Figure 3.10.17 Serial Transmission/Receiving Buffer Registers (Channel 3, SC3BUF) 93CW46A-162 2004-02-10 TMP93CW46A SC4MOD (004EH) Bit symbol 7 6 5 4 TB8 − RXE WU Read/Write 3 2 1 0 SM1 SM0 SC1 SC0 0 0 0 0 R/W After reset Undefined 0 Function Transferred Fix at “0”. data bit8 0 0 Receiving Wakeup function function 0: Receive 0: Disable disable 1: Enable 1: Receive enable Serial transmission mode Serial transmission 00: Reserved clock (UART) 00: TO0 trigger 01: 7-bit UART 01: Baud rate 10: 8-bit UART 11: 9-bit UART generator 10: Internal clock φ1 11: Don’t care Serial transmission clock source (for UART) 00 Timer 0 match detect signal 01 Baud rate generator 10 Internal clock φ1 11 Don’t care Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC4CR). Serial transmission mode 00 Reserved 01 10 7-bit length UART mode 11 8-bit length 9-bit length Wakeup function 9-bit UART 0 Interrupt when data is received 1 Interrupt only when RB8 = 1 Other mode Don’t care Receiving control 0 Receive disable 1 Receive enable Transmission data bit8 Figure 3.10.18 Serial Mode Control Register (Channel 4, SC4MOD) 93CW46A-163 2004-02-10 TMP93CW46A SC4CR (004DH) 7 6 Bit symbol RB8 EVEN Read/Write R 5 4 3 2 1 PE OERR PERR FERR − R/W 0 R (cleared to 0 when read) After reset Undefined Function Received Parity data bit8 0: Odd Parity addition 0 1: Even 0: Disable 0 0 Parity − R/W 0 0 0 Always fixed to “0”. 1: Error Overrun 0 Framing 1: Enable Framing error flag Parity error flag Overrun error flag Cleared to 0 when read. Enable parity addition 0 Disable 1 Enable Addition/check of even parity 0 Odd parity 1 Even parity Receiving data bit8 Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.10.19 Serial Control Register (Channel 4, SC4CR) 93CW46A-164 2004-02-10 TMP93CW46A BR4CR (004FH) Bit symbol 7 6 5 4 − BR4ADD BR4CK1 BR4CK0 Read/Write 0 0 0 Always + (16 − K)/16 fixed to “0”. division 1 0 BR4S3 BR4S2 BR4S1 BR4S0 0 0 0 0 0 00: φT0 01: φT2 0: Disable 10: φT8 1: Enable 11: φT32 + (16 − K)/16 division enable Setting of the divided frequency Selecting the input clock of baud rate generator 0 Disable 00 Internal clock φT0 1 Enable 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 7 BRADD4 (004BH) 2 R/W After reset Function 3 6 5 4 Bit symbol 3 2 BR4K3 BR4K2 Read/Write 1 0 BR4K1 BR4K0 0 0 R/W After reset 0 0 Function Sets frequency divisor “K” (divided by N + (16 − K)/16) Sets baud rate generator frequency divisor BR4CR<BR4ADD> = 1 BR4CR <BR4S3:0> BRADD4 <BR4K3:0> 0000 0000 (N = 16) 0010 (N = 2) or 0001 (N = 1) to 1111 (N = 15) Disable Disable Disable Divided by N + (16 − K)/16 0001 (K = 1) to 1111 (K = 15) BR4CR<BR4ADD> = 0 0001 (N = 1) to 1111 (N = 15) 0000 (N = 16) Divided by N Note 1: Set TRUN<PRRUN> to “1” when the baud rate generator is used. Note 2: Set BR4CR<BR4ADD> to “1” after setting K (K = 1 to 15) to BRADD4<BR4K3:0> when + (16 − K)/16 division function is used. Note 3: BRADD4<bit7:4> is always read as “1”. Note 4: Don’t read from or write to BR4CR register during sending or receiving. Figure 3.10.20 Baud Rate Generator Control (Channel 4, BR4CR, BRADD4) 93CW46A-165 2004-02-10 TMP93CW46A 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Transmission) SC4BUF (004CH) Note: (Receiving) Prohibit read-modify-write for SC4BUF. Figure 3.10.21 Serial Transmission/Receiving Buffer Registers (Channel 4, SC4BUF) 7 P9FC (001DH) 6 5 4 3 2 1 0 Bit symbol P95F P93F P92F P90F Read/Write W W W W After reset 0 0 0 Function 0: Port 1: SCLK1 0: Port 1: TXD1 0 0: Port 1: SCLK0 0: Port 1: TXD0 Setting TXD0 output 0 Port 1 TXD0 output Setting SCLK0 output 0 Port 1 SCLK0 output Setting TXD1 output 0 Port 1 TXD1 output Setting SCLK1 output 0 Port 1 SCLK1 output Note: Prohibit read-modify-write. Figure 3.10.22 Port 9 Function Register (P9FC) 93CW46A-166 2004-02-10 TMP93CW46A 7 ODE (0058H) 6 5 4 3 2 1 Bit symbol 0 ODE1 Read/Write ODE0 R/W After reset 0 Function P93 0: CMOS 1: Open drain 0 P90 0: CMOS 1: Open drain Setting P90 as open-drain output 0 CMOS output 1 Open-drain output Setting P93 as open-drain output Note: ODE<bit7:2> is read as “1”. 0 CMOS output 1 Open-drain output Figure 3.10.23 Port 9 Open-drain Enable Register (ODE) 7 P6FC (0016H) 6 5 Bit symbol P65F Read/Write W After reset 0 Function 0: Port 1: TXD4 3 2 P65F P63F P62F P60F W W W W 0 0 0 0: Port 1: SCLK3 4 0: Port 1: TXD3 1 0 0 0: Port 1: SCLK2 0: Port 1: TXD2 Setting TXD2 output 0 Port 1 TXD2 output Setting SCLK2 output 0 Port 1 SCLK2 output Setting TXD3 output 1 Port TXD3 output Setting SCLK3 output Setting TXD4 output 0 0 1 Port 0 Port TXD4 output 1 SCLK3 output Note: Prohibit read-modify-write. Figure 3.10.24 Port 6 Function Register (P6FC) 93CW46A-167 2004-02-10 TMP93CW46A 3.10.2 Configuration Figure 3.10.25 shows the block diagram of the serial channel 0. Serial clock generation circuit TO0TRG (Timer 0 comparator output) BR0CR <BR0CK1:0> BR0CR <BR0ADD> Baud rate generator UART mode SC0MOD <SC1:0> Selector System clock fSYS (φ1) ÷2 SCLK0 (Shared by P92) Selector Selector Selector φT0 φT2 φT8 φT32 BRADD0 <BR0K3:0> Prescaler BR0CR <BR0S3:0> SIOCLK SC0MOD <SM1:0> I/O interface mode SC0CR <IOC> SCLK0 (Shared by P92) I/O interface mode INTRX0 INTTX0 Receive counter (÷16 at UART mode) SC0MOD <WU> Serial channel interrupt control RXDCLK SC0MOD <RXE> Transmission counter (÷ 16 at UART mode) TXDCLK Receive control Transmission control CTS0 (Shared by P92) SC0CR <PE> <EVEN> SC0MOD<CTSE> Parity control RXD0 (Shared by P91) Receive buffer 1(Shift register) RB8 Receive buffer 2 (SC0BUF) Error flag TB8 Transmission buffer (SC0BUF) SC0CR <OERR> <PERR> <FERR> TXD0 (Shared by P90) Internal data bus Figure 3.10.25 Block Diagram of the Serial Channel 0 93CW46A-168 2004-02-10 TMP93CW46A Figure 3.10.26 shows the block diagram of the serial channel 1. Serial clock generation circuit TO0TRG (Timer 0 comparator output) BR1CR <BR1CK1:0> BR1CR <BR1ADD> Baud rate generator UART mode SC1MOD <SC1:0> Selector Selector Selector φT0 φT2 φT8 φT32 BRADD1 <BR1K3:0> Prescaler BR1CR <BR1S3:0> SIOCLK SC1MOD <SM1:0> Selector System clock fSYS (φ1) ÷2 SCLK1 (Shared by P95) SCLK1 (Shared by P95) I/O interface mode SC1CR <IOC> I/O interface mode INTRX1 INTTX1 Receive counter (÷16 at UART mode) SC1MOD <WU> Serial channel interrupt control RXDCLK SC1MOD Receive <RXE> control Transmission counter (÷ 16 at UART mode) TXDCLK Transmission control SC1CR <PE> <EVEN> Parity control RXD1 (Shared by P94) Receive buffer 1(Shift register) RB8 Receive buffer 2 (SC1BUF) Error flag TB8 Transmission buffer (SC1BUF) SC1CR <OERR> <PERR> <FERR> TXD1 (Shared by P93) Internal data bus Note: No handshake function in channel 1. Figure 3.10.26 Block Diagram of the Serial Channel 1 93CW46A-169 2004-02-10 TMP93CW46A Figure 3.10.27 shows the block diagram of the serial channel 2. Serial clock generation circuit TO0TRG (Timer 0 comparator output) BR2CR <BR2CK1:0> BR2CR <BR2ADD> Baud rate generator SC2MOD <SC1:0> Selector UART mode Selector Selector φT0 φT2 φT8 φT32 BRADD2 <BR2K3:0> Prescaler BR2CR <BR2S3:0> SIOCLK SC2MOD <SM1:0> Selector System clock fSYS (φ1) ÷2 SCLK2 (Shared by P62) I/O interface mode SC2CR <IOC> SCLK2 (Shared by P62) I/O interface mode INTRX2 INTTX2 Receive counter (÷16 at UART mode) SC2MOD <WU> Serial channel interrupt control RXDCLK SC2MOD Receive <RXE> control Transmission counter (÷ 16 at UART mode) TXDCLK Transmission control CTS2 (Shared by P62) SC2CR <PE> <EVEN> SC2MOD<CTSE> Parity control RXD2 (Shared by P61) Receive buffer 1(Shift register) RB8 Receive buffer 2 (SC2BUF) Error flag TB8 Transmission buffer (SC2BUF) SC2CR <OERR> <PERR> <FERR> TXD2 (Shared by P60) Internal data bus Figure 3.10.27 Block Diagram of the Serial Channel 2 93CW46A-170 2004-02-10 TMP93CW46A Figure 3.10.28 shows the block diagram of the serial channel 3. Serial clock generation circuit TO0TRG (Timer 0 comparator output) BR3CR <BR3CK1:0> BR3CR <BR3ADD> Baud rate generator UART mode SC3MOD <SC1:0> Selector System clock fSYS (φ1) ÷2 SCLK3 (Shared by P65) Selector Selector Selector φT0 φT2 φT8 φT32 BRADD3 <BR3K3:0> Prescaler BR3CR <BR3S3:0> SIOCLK SC3MOD <SM1:0> I/O interface mode SC3CR <IOC> SCLK3 (Shared by P65) I/O interface mode INTRX3 INTTX3 Receive counter (÷16 at UART mode) SC3MOD <WU> Serial channel interrupt control RXDCLK SC3MOD <RXE> Transmission counter (÷ 16 at UART mode) TXDCLK Receive control Transmission control CTS3 (Shared by P65) SC3CR <PE> <EVEN> SC3MOD<CTSE> Parity control RXD3 (Shared by P64) Receive buffer 1(Shift register) RB8 Receive buffer 2 (SC3BUF) Error flag TB8 Transmission buffer (SC3BUF) SC3CR <OERR> <PERR> <FERR> TXD3 (Shared by P63) Internal data bus Figure 3.10.28 Block Diagram of the Serial Channel 3 93CW46A-171 2004-02-10 TMP93CW46A Figure 3.10.29 shows the block diagram of the serial channel 4. Serial clock generation circuit TO0TRG (Timer 0 comparator output) BR4CR <BR4CK1:0> BR4CR <BR4ADD> Baud rate generator UART mode SC4MOD <SC1:0> Selector Selector Selector φT0 φT2 φT8 φT32 BRADD4 <BR4K3:0> Prescaler BR4CR <BR4S3:0> SIOCLK SC4MOD <SM1:0> System clock fSYS (φ1) INTRX4 INTTX4 Receive counter (÷16 at UART mode) SC4MOD <WU> Serial channel interrupt control RXDCLK SC4MOD <RXE> Transmission counter (÷ 16 at UART mode) TXDCLK Receive control Transmission control SC4CR <PE> <EVEN> Parity control RXD4 (Shared by P67) Receive buffer 1(Shift register) RB8 Receive buffer 2 (SC4BUF) Error flag TB8 Transmission buffer (SC4BUF) SC4CR <OERR> <PERR> <FERR> TXD4 (Shared by P66) Internal data bus Note 1: No I/O interface mode in serial channel 4. Note 2: No handshake function in serial channel 4. Figure 3.10.29 Block Diagram of the Serial Channel 4 93CW46A-172 2004-02-10 TMP93CW46A 1. Prescaler, Prescaler clock select There are 9-bit prescaler and prescaler clock selection registers to generate input clock for 8-bit timers 0 and 1, 16-bit timers 4 and 5, and Serial Interfaces 0 to 4. Figure 3.10.30 shows the block diagram. Table 3.10.1 shows prescaler clock resolution into the baud rate generator. To CPU 2 To 5-bit prescaler 9-bit prescaler fFPH…… fs Selector XT1 Selector Selector 2 4 8 16 32 64 128 256 512 fc fc/2 2 4 φT1 φT4 φT16 φT256 SYSCR0 <PRCK1:0> Run/stop & clear φT1 φT4 φT16 TRUN<PRRUN> φ1 φT0 φT2 φT8 φT32 SYSCR1<SYSCK> 2 To 8-bit timers 0 and 1 To 16-bit timers 4 and 5 To serial interfaces 0 to 4 fc/4 fc/8 fc/16 SYSCR1<GEAR2:0> X1 ÷2 ÷4 ÷8 ÷16 Figure 3.10.30 The Block Diagram of Prescaler Table 3.10.1 Prescaler Clock Resolution to Baud Rate Generator Select Select Prescaler Gear Value System Clock Clock <GEAR2:0> <SYSCK> <PRCK1:0> 1 (fs) XXX 000 (fc) 00 0 (fc) (fFPH) 001 (fc/2) 010 (fc/4) 011 (fc/8) Prescaler Output Clock Resolution φT0 φT2 φT8 φT32 fs/22 fs/24 fs/26 fs/28 2 4 6 fc/28 7 fc/29 8 fc/210 9 fc/211 10 fc/2 3 fc/2 4 fc/2 5 fc/2 6 fc/2 5 fc/2 6 fc/2 7 fc/2 8 fc/2 fc/2 fc/2 fc/2 100 (fc/16) fc/2 fc/2 fc/2 fc/212 XXX 01 (Low-frequency clock) XXX − fs/24 fs/26 fs/28 XXX 10 (fc/16 clock) XXX − fc/28 fc/210 fc/212 XXX: Don’t care, −: Can not use Note: The fc/16 clock as a prescaler clock can not be used when the fs is used as a system clock. 93CW46A-173 2004-02-10 TMP93CW46A The clock selected among fFPH clock, fc/16 clock, and fs clock is divided by 4 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to “00” and selects the fFPH clock input divided by 4. The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, and φT32 among the prescaler outputs. The prescaler can be run or stopped by the timer operation control register TRUN<PRRUN>. Counting starts when <PRRUN> is set to “1”. The prescaler is cleared to zero and stops operation when <PRRUN> is set to “0”. When the IDLE1 mode (only the oscillator operates) is used, set TRUN<PRRUN> to “0” to stop this prescaler before the “HALT” instruction is executed. 2. Baud rate generator The baud rate generator is a circuit that generates transmission and receiving clocks to determine the transfer rate of the serial channel. The input clock to the baud rate generator, φT0, φT2, φT8, or φT32, is generated by the 9-bit prescaler which is shared by the timers. One of these input clocks is selected by the baud rate generator control register BR0CR<BR0CK1:0>. The baud rate generator includes a frequency divider, which divides frequency by 1, n + m/16 (n = 2 to 15, m = 0 to 15) to 16 values to determine the transfer rate. The transfer rate is determined by setting BR0CR<BR0ADD, BR0S3:0> and BRADD0<BR0K3:0>. • UART mode (1) BR0CR<BR0ADD> = 0 Setting BRADD0<BR0K3:0> is ignored. The baud rate generator divides the selected prescaler clock by N which is set to BR0CK<BR0S3:0>. (N = 1, 2, 3 ...16) (2) BR0CR<BR0ADD> = 1 N + (16 − K)/16 division function is enabled. The baud rate generator divides the selected prescaler clock by N + (16 − K)/16 according to N set to BR0CR<BR0S3:0> (N = 2, 3...15) and K set to BRADD0<BR0K3:0> (K = 1, 2, 3...15). At N = 1 or 16, N + (16 − K)/16 division function is disabled. Set BR0CR<BR0ADD> to “0”. I/O interface mode Note: • N + (16 − K)/16 division function is not available in I/O interface mode. Set BK0CR<BR0ADD> to “0” before dividing by N. 93CW46A-174 2004-02-10 TMP93CW46A How to calculate a transfer rate when the baud rate generator is used is explained below. • UART mode Transfer rate = • ÷ 16 Input clock of baud rate generator Frequency divisor of baud rate generator ÷2 I/O interface mode Transfer rate = • Input clock of baud rate generator Frequency divisor of baud rate generator Integer divisor (N divisor) For example, when the source clock (fc) is 12.288 MHz, the input clock is φT2 (fc/16), and frequency divisor is N (BR0CR<BR0S3:0>) = 5 BR0CR<BRADD0> = 0, the transfer rate in UART mode becomes as follows: * Clock condition System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock Baud rate = • fc/16 ÷ 16 5 = 12.288 × 106 ÷ 16 ÷ 5 ÷ 16 = 9600 (bps) Note: + (16 − K)/16 division function is disabled, and setting BRADD0<BR0K3:0> is invalid. N + (16 − K)/16 divisor (Only in UART mode) Accordingly, when source clock (fc) is 4.8 MHz, the input clock is φT0 , and frequency divisor is N (BR0CR<BR0S3:0>) = 7, “K” (BRADD0<BR0K3:0>) = 3, BR0CR<BRADD0> = 1, the transfer rate in UART mode becomes as follows: * Clock condition Baud rate = System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock fc/4 ÷ 16 7 + (16 − 3)/16 = 4.8 × 106 ÷ 4 ÷ (7 + 13/16) ÷ 16 = 9600 (bps) Table 3.10.2, 3.10.3 show the examples of the transfer rate in UART mode. Additionally, the external clock input is available in the serial clock. (Serial channel 0 to 3). How to calculate a baud rate is explained below. • UART mode Baud rate = External clock input ÷ 16 It is necessary to satisfy (External clock input cycle) ≥ 4/fc + 20 [ns] • I/O interface mode Baud rate = External clock input It is necessary to satisfy (External clock input cycle) ≥ 16/fc [ns]. 93CW46A-175 2004-02-10 TMP93CW46A Table 3.10.2 Selection of Transfer Rate (1) (when baud rate generator is used) Unit (kbps) Input Clock fc [MHz] φT0 φT2 φT8 φT32 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 8 19.200 4.800 1.200 0.300 0 9.600 2.400 0.600 0.150 5 38.400 9.600 2.400 0.600 A 19.200 4.800 1.200 0.300 3 76.800 19.200 4.800 1.200 6 38.400 9.600 2.400 0.600 C 19.200 4.800 1.200 0.300 Frequency Divisor 9.830400 12.288000 14.745600 Note 1: Transfer rates in I/O interface mode are 8 times faster than the values given in the above table. Note 2: This table is calculated when fc is selected as a system clock, the clock gear is set for fc, and the system clock as the prescaler clock input. Table 3.10.3 Selection of Transfer Rate (1) (when timer 0 (Input clock φt1) is used) Unit (kbps) fc TREG0 12.288 MHz 12 MHz 9.8304 MHz 8 MHz 6.144 MHz 1H 96 76.8 62.5 48 2H 48 38.4 31.25 24 3H 32 4H 24 5H 19.2 8H 12 AH 9.6 10H 6 14H 4.8 31.25 16 19.2 12 9.6 6 4.8 3 9.6 4.8 2.4 How to calculate the transfer rate (when timer 0 is used): Transfer rate = The clock frequency selected by the register SYSCR0<PRCK1:0> TREG0 × 8 × 16 (when timer 0 (Input clock φT1) is used) Note 1: Timer 0 match detect signal cannot be used as the transfer clock in I/O interface mode. Note 2: This table is calculated when fc is selected as a system clock, the clock gear is set for fc, and fFPH as the prescaler clock input. 93CW46A-176 2004-02-10 TMP93CW46A 3. Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • I/O interface mode (Channel 1 only) When in SCLK output mode with the setting of SC0CR<IOC> = “0”, the basic clock will be generated by dividing the output of the baud rate generator by 2 as described before. When in SCLK input mode with the setting of SC0CR<IOC> = “1”, the rising edge or falling edge will be detected according to the setting of the SC0CR<SCLKS> register to generate the basic clock. • UART mode The setting of SC0MOD<SC1:0>, will select between the baud rate generator clock, internal clock φ1 (Max 625 Kbps at fc = 20 MHz), or the match detect signal from timer 0 or the external clock (Channel 0 to 3) to generate the basic clock SIOCLK. 4. Receiving counter The receiving counter is a 4-bit binary counter used in asynchronous communication (UART) mode and counts up according to the SIOCLK clock. 16 pulses of SIOCLK are used for receiving 1 bit of data, and the data bit is sampled three times at the 7th, 8th and 9th clock. With these three samples, the received data bit is evaluated by the majority rule. For example, if the sampled data bit is “1”, “0” and “1” at 7th, 8th and 9th clock respectively, the received data is evaluated as “1”. The sampled data “0”, “0” and “1” is evaluated such that the received data bit is determined to be “0”. 5. Receiving control • I/O interface mode When in SCLK output mode with the setting of SC0CR<IOC> = “0”, the RXD0 signal will be sampled at the rising edge of the shift clock which is output to the SCLK0 pin. When in SCLK input mode with the setting SC1CR<IOC> = “1”, the RXD0 signal will be sampled at the rising edge or falling edge of the SCLK0 input according to the setting of the SC0CR<SCLKS> register. • UART mode The receiving control block has a circuit for detecting the start bit by the rule of majority. When two or more “0” are detected during the 3 samples, it is recognized as start bit and the receiving operation is started. The data being received is also evaluated by the majority rule. 93CW46A-177 2004-02-10 TMP93CW46A 6. Receiving buffer To prevent an overrun error, the receiving buffer has a double buffer structure. Received data is stored bit by bit in receiving buffer 1 (Shift register type). When 7 bits or 8 bits of data are stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (SC0BUF) generating an interrupt INTRX0. The CPU reads only receiving buffer 2 (SC0BUF). Even before the CPU reads receiving buffer 2 (SC0BUF), the received data can be stored in receiving buffer 1. However, unless receiving buffer 2 (SC0BUF) is read before all bits of the next data are received by receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of receiving buffer 1 will be lost, although the contents of the receiving buffer 2 and SC0CR<RB8> are still preserved. The parity bit added in 8-bit UART mode and the most significant bit (MSB) in 9-bit UART mode are stored in SC0CR<RB8>. When in 9-bit UART mode, the wakeup function of the slave controller is enabled by setting SC0MOD<WU> to “1”, and interrupt INTRX0 occurs only when SC0CR<RB8> is set to “1”. 7. Transmission counter The transmission counter is a 4-bit binary counter which is used in asynchronous communication (UART) mode and, like a receiving counter, counts by the SIOCLK clock which generates TXDCLK every 16 clock pulses. SIOCLK 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 TXDCLK Figure 3.10.31 Generation of Transmission Clock 8. Transmission controller • I/O interface mode In SCLK output mode with the setting of SC0CR<IOC> = “0”, the data in the transmission buffer is output bit by bit to TXD0 pin at the rising edge of the shift clock which is output from the SCLK0 pin. In SCLK input mode with the setting of SC0CR<IOC> = “1”, the data in the transmission buffer is output bit by bit to the TXD0 pin at the rising edge or falling edge of the SCLK0 input according to the setting of the SC0CR<SCLKS> register. • UART mode When transmission data is written to the transmission buffer sent from the CPU, transmission starts at the rising edge of the next TXDCLK, generating a transmission shift clock TXDSFT. 93CW46A-178 2004-02-10 TMP93CW46A Handshake function Serial channel 0, 2, 3 has a CTS pin. Using this pin, data can be sent in units of one frame; thus, overrun errors can be avoided. The handshake function is enabled/ disabled by SC0MOD<CTSE>. When the CTS0 pin goes high, after completion of the current data send, data send is halted until the CTS0 pin goes low again. When the INTTX0 Interrupt is generated, it requests the next data send to the CPU. Though there is no RTS pin, a handshake function can be easily configured by setting any port assigned to be the RTS function. The RTS should be output “High” to request send data halt after data receive is completed by software in the RXD interrupt routine. TMP93CW46A TMP93CW46A TXD RXD CTS RTS (Any port) Sender Receiver Figure 3.10.32 Handshake Function Timing to write transmission buffer Send is suspended from (A) to (B) CTS (A) 13 (B) 14 15 16 1 2 3 14 15 16 1 2 3 SIOCLK TXDCLK TXD Start bit Bit0 Note 1: If the CTS signal rises during transmission, the next data is not sent after the completion of the current Note 2: Transmission starts at the first TXDCLK clock falling edge after the CTS signal falls. transmission. Figure 3.10.33 Timing of CTS (Clear to send) 93CW46A-179 2004-02-10 TMP93CW46A 9. Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU from the least significant bit (LSB) in order. When all bits are shifted out, the transmission buffer becomes empty and generates INTTX0 interrupt. 10. Parity control circuit When the serial channel control register SC0CR<PE>is set to “1”, it is possible to transmit and receive data with parity. However, parity can be added only in 7-bit UART or 8-bit UART modes. With SC0CR<EVEN> register, even or odd parity can be selected. For transmission, parity is automatically generated according to the data written in the transmission buffer SC0BUF. The data is transmitted after the parity bit is stored in SC0BUF<TB7> when in 7-bit UART mode or in SC0MOD<TB8> when in 8-bit UART mode. <PE> and <EVEN> must be set before the transmission data is written to the transmission buffer. For receiving, data are shifted in the receiving buffer 1, the parity is added after the data is transferred to receiving buffer 2 (SC0BUF), and then compared with SC0BUF<RB7> when in 7-bit UART mode and with SC0MOD<RB8> when in 8-bit UART mode. If they are not equal, a parity error occurs and SC0CR<PERR> flag is set. 11. Error flag Three error flags are provided to increase the reliability of receiving data. 1) Overrun error <OERR> If all bits of the next data are received in receiving buffer 1 while valid data is stored in receiving buffer 2 (SC0BUF), an overrun error will occur. 2) Parity error <PERR> The parity generated for the data shifted in receiving buffer 2 (SC0BUF) is compared with the parity bit received from RXD pin. If they are not equal, a parity error occurs. 3) Framing error <FERR> The stop bit of received data is sampled three times around the center. If the majority is “0”, a framing error occurs. 93CW46A-180 2004-02-10 TMP93CW46A l. Signal generating timing 1) In UART mode Receive Mode 9-Bit 8-Bit + Parity 8-Bit, 7-Bit + Parity, 7-Bit Timing for interrupt generation Around center of bit8 Around center of parity bit Around center of stop bit Timing for framing generation Around center of stop bit Around center of stop bit Around center of stop bit − Around center of parity bit ← Around center of bit8 Around center of parity bit Around center of stop bit Timing for parity error generation Timing for overrun error timing Note: In 9-Bit and 8-Bit+Parity mode, interrupts coincide with the ninth bit pulse.Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error. Send Mode Timing for interrupt generation 2) 9-Bit 8-Bit + Parity 8-Bit, 7-Bit + Parity, 7-Bit Immediately before stop bit sent ← ← In I/O interface mode Timing for send interrupt generation Timing for receive interrupt generation SCLK0 output mode Immediately after rise of last SCLK0 signal (See Figure 3.10.36) SCLK0 input mode Immediately after rise (Rising mode) or fall (Falling mode) of last SCLK0 signal (See Figure 3.10.36.) SCLK0 output mode Immediately after final SCLK0 (When received data are transferred to receive buffer 2 (SC0BUF)) (See Figure 3.10.38.) SCLK0 input mode Immediately after final SCLK0 (When received data are transferred to receive buffer 2 (SC0BUF)) (See Figure 3.10.39.) 93CW46A-181 2004-02-10 TMP93CW46A 3.10.3 Operational Description (1) Mode 0 (I/O interface mode) This mode is used to increase the number I/O pins for transmitting or receiving data to or from an external shifter register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK. Output extension Input extension TMP93CW46A Shift register TXD SI A TMP93CW46A Shift register B B C C RXD QH D SCLK D E SCK SCLK E CLOCK F Port F G RCK A Port G S /L H H TC74HC595 or equivalent TC74HC165 or equivalent Figure 3.10.34 Example of SCLK Output Mode Connection Input port extension Output port extension TMP93CW46A Shift register A Shift register TMP93CW46A TXD C SI RXD C QH D D SCLK E SCK SCLK E CLOCK F F Port G RCK Port G S/L H H External clock TC74HC595 or equivalent A B B External clock TC74HC165 or equivalent Figure 3.10.35 Example of SCLK Input Mode Connection Note: Serial channel 4 has no I/O interface mode. 93CW46A-182 2004-02-10 TMP93CW46A 1. Transmission In SCLK output mode, 8-bit data and synchronous clock are output from TXD0 pin and SCLK0 pin respectively, each time the CPU writes data to the transmission buffer. When all data is output, INTES0<ITX0C> will be set to generate the INTTX0 interrupt. Timing to write transmission data SCLK0 output TXD0 Bit0 Bit1 Bit6 Bit7 TXDSFT ITX0C (INTTX0 interrupt request) Figure 3.10.36 Transmitting Operation in I/O Interface Mode (SCLK output mode) (Channel 0) In SCLK input mode, 8-bit data is output from TXD0 pin when SCLK0 input becomes active after data are written to the transmission buffer by CPU. When all data is output, INTES0<ITX0C> will be set to generate INTTX0 interrupt. SCLK0 input (SCLKS = 0: Rising edge mode) SCLK0 input (SCLKS = 1: Falling edge mode) TXD0 Bit0 Bit1 Bit5 Bit6 Bit7 TXDSFT ITX0C (INTTX0 interrupt request) Figure 3.10.37 Transmitting Operation in I/O Interface Mode (SCLK input mode) (Channel 0) 93CW46A-183 2004-02-10 TMP93CW46A 2. Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to receiving buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit data are received, the data will be transferred to receiving buffer 2 (SC0BUF according to the timing shown below) and INTES0<IRX0C> will be set again to generate INTRX0 interrupt. IRX0C SCLK0 RXD0 Bit1 Bit0 Bit2 Bit7 Bit6 Generate INTRX0 Timing to shift data in the receiving buffer 2 Figure 3.10.38 Receiving Operation in I/O Interface Mode (SCLK output mode) (Channel 0) In SCLK input mode, the data is shifted to receiving buffer 1 when the SCLK input becomes active after the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit data is received, the data will be shifted to receiving buffer 2 (SC0BUF according to the timing shown below) and INTES0<IRX0C> will be set again to generate INTRX0 interrupt. SCLK0 input (SCLKS = 0: Rising edge mode) SCLK0 input (SCLKS = 1: Falling edge mode) RXD0 Bit0 Bit1 Bit2 Bit6 Bit7 Generate INTRX0 Timing to shift data in the receiving buffer 2 Figure 3.10.39 Receiving Operation in I/O Interface Mode (SCLK input mode) (Channel 0) Note: For data receiving, the system must be placed in the receive enable state (SC0MOD<RXE> = “1”) 93CW46A-184 2004-02-10 TMP93CW46A (2) Mode 1 (7-bit UART mode) The 7-bit mode can be set by setting serial channel mode register SC0MOD<SM1:0> to “01”. In this mode, a parity bit can be added, and the addition of the parity bit can be enabled or disabled by serial channel control register SC0CR<PE>, and even parity or odd parity is selected by SC0CR<EVEN> when <PE> is set to “1” (Enable). Setting example: Start When transmitting data with the following format, the control registers should be set as described below. Channel 0 is explained here. Bit0 1 2 3 4 5 6 Even parity Stop Direction of transmission (transmission rate: 2400 bps at fc = 12.288 MHz) * Clock condition System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock ← ← ← ← ← ← ← ← P9CR P9FC SC0MOD SC0CR BR0CR TRUN INTES0 SC0BUF 7 6 X X X 0 5 − − − X X 4 − X 0 1 0 1 Set 7-bit UART mode. X 1 1 X X X 0 0 Add even parity. 0 X 1 X 1 − 0 − 1 − 0 − 1 − Start the prescaler for the baud rate generator. 1 * 1 * 0 * 0 * 0 − − * − * − * − * X 3 − − 2 − 1 − 0 X X 1 1 Select P90 as the TXD0 pin. Set transfer rate at 2400 bps. Enable INTTX0 interrupt and set interrupt level 4. Set data for transmission. X: Don’t care, −: No change (3) Mode 2 (8-bit UART mode) The 8-bit UART mode can be specified by setting SC0MOD<SM1:0> to “10”. In this mode, the parity bit can be added (The addition of a parity bit is enabled or disabled by SC0CR<PE>) and even parity or odd parity is selected by SC0CR<EVEN> when <PE> is set to “1” (enable). Setting example: When receiving data with the following format, the control register should be set as described below. Start Bit0 1 2 3 4 5 6 7 Odd parity Stop Direction of transmission (transmission rate: 9600 bps at fc = 12.288 MHz) * Clock condition System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock 93CW46A-185 2004-02-10 TMP93CW46A Main setting P9CR SC0MOD SC0CR BR0CR TRUN INTES0 ← ← ← ← ← ← 7 6 X 5 − 4 − 3 − 2 − 1 X − 0 0 − Select P91 (RXD0) as the input pin. 0 1 X 1 0 0 1 Enable receiving in 8-bit UART mode. X 0 1 X X X 0 0 Add odd parity. 0 X X − 1 − 0 − 1 − 0 − 1 − Set transfer rate at 9600 bps. 1 − 0 − Start the prescaler for the baud rate generator. − − 1 1 0 0 Enable INTRX0 interrupt and set interrupt level 4. Interrupt processing ACC ← SC0CR AND 00011100 Check for error. if ACC ≠ 0 then ERROR ACC ← SC0BUF Read the received data. X: Don’t care, −: No change (4) Mode 3 (9-bit UART mode) 9-bit UART mode can be specified by setting SC0MOD<SM1:0> to “11”. In this mode, parity bit cannot be added. For transmission, the MSB (9th bit) is written in SC0MOD<TB8>. For receiving it is stored in SC0CR<RB8>. For writing and reading of the buffer, the MSB is read or written first then the rest of the data from SC0BUF. Wakeup function In 9-bit UART mode, the wakeup function of slave controllers is enabled by setting SC0MOD<WU> to “1”. The interrupt INTRX0 occurs only when <RB8> = 1. TXD RXD Master Note: TXD RXD TXD Slave 1 RXD Slave 2 TXD RXD Slave 3 TXD pin of the slave controllers must be in open drain output mode. Figure 3.10.40 Serial Link using Wakeup Function 93CW46A-186 2004-02-10 TMP93CW46A Protocol 1. Select the 9-bit UART mode for the master and slave controllers. 2. Set SC0MOD<WU> bit of each slave controller to “1” to enable data receiving. 3. The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The MSB (Bit8)<TB8> is set to “1”. Start Bit0 1 2 3 4 5 8 7 6 Select code of slave controller Stop “1” 4. Each slave controller receives the above frame, and clears WU bit to “0” if the above select code matches its own select code. 5. The master controller transmits data to the specified slave controller whose SC0MOD<WU> bit is cleared to “0”. The MSB (Bit8)<TB8> is cleared to “0”. Start Bit0 1 2 3 4 Data 6. 5 6 7 Bit 8 Stop “0” The other slave controllers (with the <WU> bit remaining at “1”) ignore the receiving data because their MSBs (Bit8 or <RB8>) are set to “0” to disable the interrupt INTRX0. The slave controllers (WU = 0) can transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission. 93CW46A-187 2004-02-10 TMP93CW46A Setting example: TXD To link two slave controllers serially with the master controller, and use the internal clock φ1 as the transfer clock. RXD TXD Master RXD TXD RXD Slave 1 Slave 2 Select code 00000001 Select code 00001010 Since serial channels 0 and 1 operate in exactly the same way, channel 0 is used for the purposes of explanation. • Setting the master controller Main P9CR P9FC INTES0 ← X ← X ← 1 − − 0 1 X − − − X X X 1 1 0 0 1 1 0 1 Enable INTTX0 and set the interrupt level 4. X − Select P90 as TXD0 pin and P91 as RXD0 pin. ← 1 ← 0 0 1 0 1 1 1 0 Enable INTRX0 and set the interrupt level 5. Set φ1 as the transmission clock in 9-bit UART mode. 0 0 0 0 0 0 1 Set the select code for slave controller 1. INTTX0 interrupt ← 0 SC0MOD ← * SC0BUF − * − * − * − * − * − * − * Sets TB8 to “0”. 0 1 X 1 − 1 1 1 SC0MOD SC0BUF • Set data for transmission. Setting the slave controller Main P9CR P9FC ODE INTES0 SC0MOD ← ← ← ← ← X X X X X X 1 1 0 0 − − X 0 1 − − − X 1 1 X X 1 1 − X X 1 1 Select P91 as RXD0 pin and P90 as TXD0 pin (Open-drain output). 0 Enable INTRX0 and INTTX0. 0 Set <WU> to “1” in the 9-bit UART transmission mode with transfer clock φ1. INTRX0 interrupt ACC ← SC0BUF if ACC = Select code Then SC0MOD ← − − − 0 − − − − 93CW46A-188 Clear <WU> to “0”. 2004-02-10 TMP93CW46A 3.11 Analog/Digital Converter TMP93CW46A contains an analog/digital converter (AD converter) with 8-channel analog input that features 10-bit successive approximation. Figure 3.11.1 shows the block diagram of the AD converter. 8-channel analog input pins (AN7 to AN0) are shared by input-only port P5 which also can be used as a general purpose input port. Internal data bus AD converter mode register (ADMOD1, ADMOD2) Analog input AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREFON Decoder ADCH2 to 0 EOCF ADBF REPET SCAN SPEED Repeat Scan End Busy ADS Speed AD converter control circuit Channel select + Multiplexer Start INTAD interrupt AD conversion result register (ADREG0/4 to ADREG3/7) − VREFH DA converter VREFL Figure 3.11.1 Block Diagram of AD Converter Note 1: This AD converter does not have a built-in sample and hold circuit. Note 2: When the power supply current is reduced in IDLE2, IDLE1, STOP mode, there is possible to set a standby enabling the internal comparator due to a timing. Stop operation of AD converter before execution of “HALT” instruction. And set ADMOD2<SPEED1:0> = “00”. Note 3: The operation of AD converter is guaranteed only when fc (High-frequency oscillator) is used. (Not guaranteed when fs is used) It is guaranteed when with fFPH ≥ 4 MHz. 93CW46A-189 2004-02-10 TMP93CW46A 7 ADMOD1 Bit symbol (005EH) Read/Write After reset Function EOCF 6 5 ADBF REPET R 4 3 2 SCAN 0 AD conversion end flag 1: End AD conversion busy flag 1: Busy 0 Repeat mode 0: Single mode 1: Repeat mode 0 ADS R/W 0 1 R/W 0 0 Scan mode 0: Fixed channel mode 1: Channel scan mode AD conversion start 1: Start Always read as “0”. AD conversion start 0 − 1 Start conversion Always “0” when data is read. AD scan mode 0 Fixed channel mode 1 Channel scan mode AD repeat mode 0 Single mode 1 Repeat mode AD busy flag 0 Not busy 1 Busy AD end flag 0 Not end 1 End Note: ADMOD1<Bit3> and <Bit1:0> are read as “1”. Figure 3.11.2 AD Control Register (1/2) 93CW46A-190 2004-02-10 TMP93CW46A 7 ADMOD2 Bit symbol VREFON (005FH) Read/Write R/W After reset Function 1 String resistance ON/OFF 6 5 4 SPEED1 3 SPEED0 2 1 0 ADCH2 ADCH1 ADCH0 R/W 0 R/W 0 0 Conversion speed 00: 160 states 01: 320 states 10: 640 states 11: 1280 states 0 0 Analog input channel selection Analog input channel selection <SCASN> <ADCH2:0> 0 1 000 AN0 AN0 001 AN1 AN0 → AN1 010 AN2 AN0 → AN1 → AN2 011 AN3 AN0 → AN1 → AN2 → AN3 100 AN4 AN4 101 AN5 AN4 → AN5 110 AN6 AN4 → AN5 → AN6 111 AN7 AN4 → AN5 → AN6 → AN7 Conversion speed 00 160 states (16 µs at 20 MHz) 01 320 states (32 µs at 20 MHz) 10 640 states (64 µs at 20 MHz) 11 1280 states (128 µs at 20 MHz) Ladder resistance ON/OFF selection 0 Ladder resistance OFF 1 Ladder resistance ON Note 1: Set <VREFON> bit to “1” before conversion start (Writing “1” to ADMOD1<ADS>). Note 2: ADMOD2<bit6> and <bit3> are read as “1”. Figure 3.11.3 AD Control Register (2/2) 93CW46A-191 2004-02-10 TMP93CW46A ADREG04L Bit symbol (0060H) Read/Write 7 6 ADR01 ADR00 5 4 1 1 Undefined Function 5 4 3 2 1 0 ADR06 ADR05 ADR04 ADR03 ADR02 R Function Upper 8 bits of AD result for AN0 or AN4 are stored. 7 6 ADR11 ADR10 5 4 1 1 Undefined Function 2 1 0 1 1 1 1 Lower 2 bits of AD result for AN1 or AN5 are stored. 7 6 5 4 ADR19 ADR18 ADR17 ADR16 3 2 1 0 ADR15 ADR14 ADR13 ADR12 R After reset Undefined Function Note: 3 R After reset Bit symbol 1 ADR07 Undefined Read/Write 1 6 After reset (0063H) 1 ADR08 Read/Write ADREG15H 1 7 (0061H) Read/Write 0 ADR09 Bit symbol (0062H) 1 Lower 2 bits of AD result for AN0 or AN4 are stored. ADREG04H Bit symbol 2 R After reset ADREG15L 3 Upper 8 bits of AD result for AN1 or AN5 are stored. The result registers are used both as AN0 and AN4, AN1 and AN5, AN2 and AN6, AN3 and AN7. They are stored in to ADREG04, ADREG15, ADREG26 and ADREG37 respectively. MSB 9 LSB 8 7 6 5 4 3 2 1 0 Converted data for channel X ADREGXH 7 6 5 ADREGXL 4 3 2 1 0 7 6 5 4 3 2 1 0 This is “1” when this register is read. Figure 3.11.4 AD Conversion Result Register (ADREG04, ADREG15) (1/2) 93CW46A-192 2004-02-10 TMP93CW46A ADREG26L Bit symbol (0064H) Read/Write 7 6 ADR21 ADR20 5 4 1 1 Undefined Function 5 4 3 2 1 0 ADR26 ADR25 ADR24 ADR23 ADR22 R Function Upper 8 bits of AD result for AN2 or AN6 are stored. 7 6 ADR31 ADR30 5 4 1 1 3 2 1 0 1 1 1 1 R After reset Undefined Function Bit symbol 1 ADR27 Undefined Read/Write 1 6 After reset (0067H) 1 ADR28 Read/Write ADREG37H 1 7 (0065H) Read/Write 0 ADR29 Bit symbol (0066H) 1 Lower 2 bits of AD result for AN2 or AN6 are stored. ADREG26H Bit symbol 2 R After reset ADREG37L 3 Lower 2 bits of AD result for AN3 or AN7 are stored. 7 6 5 4 ADR39 ADR38 ADR37 ADR36 3 2 1 0 ADR35 ADR34 ADR33 ADR32 R After reset Undefined Function Upper 8 bits of AD result for AN3 or AN7 are stored. MSB 9 LSB 8 7 6 5 4 3 2 1 0 Converted data for channel X ADREGXH 7 6 5 ADREGXL 4 3 2 1 0 7 6 5 4 3 2 1 0 This is “1” when this register is read. Figure 3.11.5 AD Conversion Result Register (ADREG26, ADREG37) (2/2) 93CW46A-193 2004-02-10 TMP93CW46A 3.11.1 Operation (1) Analog reference voltage The high analog reference voltage is applied to the VREFH pin, and the low analog reference voltage is applied to VREFL pin. The reference voltage between VREFH and VREFL is divided by 1024 (Using string resistance) and compared with the analog input voltage for AD conversion. The switch between VREFH and VREFL can be cut (OFF) by writing “0” to ADMOD2<VREFON>. When the conversion can be started when <VREFON> = “0”, a “1” must be written to <VREFON> and wait for 3 µs that the internal reference voltage is stable (Regardless to fc) before writing “1” to ADMOD1<ADS>. (2) Analog input channels The analog input channel is selected by ADMOD2<ADCH2:0>. However, which channel to select depends on the operation mode of the AD converter. In fixed analog input mode, one channel is selected by <ADCH2:0> among eight pins: AN0 to AN7. In analog input channel scan mode, the number of channels to be scanned is specified by <ADCH2:0>, such as only AN0, AN0 → AN1, AN0 → AN1 → AN2, AN0 → AN1 → AN2 → AN3, only AN4, AN4 → AN5, AN4 → AN5 → AN6 → , AN4 → AN5 → AN6 → AN7. When reset, the AD conversion channel register will ADMOD<ADCH2:0> = 000, so that the AN0 pin will be selected. be initialized to The pins which are not used as analog input channels can be used as ordinary input port pins on port P5. (3) Starting AD conversion AD conversion starts when “1” is written to AD conversion register ADMOD1<ADS>. When conversion starts, conversion busy flag ADMOD1<ADBF> which indicates “conversion is in progress” will be set to “1”. (4) AD conversion mode Both fixed AD conversion channel mode and conversion channel scan mode have two conversion modes, single and repeat conversion modes. In fixed channel repeat mode, conversion of the specified single channel is executed repeatedly. In scan repeat mode, scanning from AN0, … → AN3 is executed repeatedly. The AD conversion mode is selected by ADMOD1<REPET, SCAN>. 93CW46A-194 2004-02-10 TMP93CW46A (5) AD conversion speed selection There are four AD conversion speed modes. The selection is determined by ADMOD2<SPEED1:0> register. When reset, ADMOD2<SPEED1:0> will be initialized to “00”, so that the 160 state conversion mode will be selected. (16 µs at 20 MHz) (6) AD conversion end and interrupt • AD conversion single mode ADMOD1<EOCF> for AD conversion end will be set to “1”, ADMOD1<ADBF> busy flag will be reset to “0”, and INTAD interrupt will be enabled when AD conversion of specified channel ends in fixed conversion channel mode or when AD conversion of the last channel ends in channel scan mode. • AD conversion repeat mode For both fixed conversion channel mode and conversion channel scan mode, INTAD should be disabled when in repeat mode. Always set the INTE0AD at “000” to disable the interrupt request. Write “0” to ADMOD1<REPET> to end the repeat mode. Then the repeat mode will be exited as soon as the conversion in progress completed. (7) Storing the AD conversion result The results of AD conversion are stored in ADREG04 to ADREG37 registers for each channel. The result registers are used both as AN0 and AN4, AN1 and AN5, AN2 and AN6, AN3 and AN7. However, the current conversion data can not determine which channels. In repeat mode, the registers are updated whenever conversion ends. ADREG04 to ADREG37 are read-only registers. (8) Reading the AD conversion result The results of AD conversion are stored in ADREG04 to ADREG37 registers. When the contents of one of the lower 2-bit registers ADREG04L, ADREG15L, ADREG26L, and ADREG37L are read, ADMOD1<EOCF> will be cleared to “0”. <EOCF> is not cleared to “0” when the contents of one of the upper 8 bits registers ADREG04H, ADREG15H, ADREG26H, and ADREG37H are read. 93CW46A-195 2004-02-10 TMP93CW46A Setting example: a. When the analog input voltage of the AN3 pin is AD converted by 160 states speed and the result is transferred to the memory address 0100H by AD interrupt INTAD routine. Main setting INTE0AD ADMOD2 ADMOD1 ← 1 ← 1 ← X 1 X X 0 0 0 0 0 0 − X X − 0 1 − 1 X − 1 X Enable INTAD and set interrupt level 4. Specify AN3 pin as an analog input channel and starts AD conversion in 160 states speed mode. INTAD routine WA ← ADREG37 WA (000100H) >> 6 ← WA Read ADREG37L and ADREG37H values and write to WA (16 bits). Right-shifts WA six times and writes 0 in upper bits. Writes contents of WA in memory at 0100H. b. When the analog input voltage of the AN4 to AN7 pins (4 pins) are AD converted by 320 states speed and set the channel scan and repeat mode. Main setting INTE0AD ADMOD2 ADMOD1 ← 1 ← 1 ← X 0 X X 0 0 1 0 1 1 − 0 X − 1 1 − 1 0 − 1 0 INTAD disable. Specify AN4 to AN7 pins as input channel and scan and repeat mode and starts AD conversion. X: Don’t care, −: No change 93CW46A-196 2004-02-10 TMP93CW46A 3.12 Watchdog Timer (Runaway detecting timer), Warm-up Timer TMP93CW46A contains a watchdog timer for runaway detection. The watchdog timer (WDT) is used to return the CPU to a normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt to notify the CPU of the malfunction, and outputs “0” externally from watchdog timer out pin WDTOUT to notify the peripheral devices of the malfunction. Connecting the watchdog timer detect signal to the reset pin internally forces a reset. This watchdog timer consists of 7-stage and 15-stage binary counters. These binary counters are also used as a warm-up timer for the internal oscillator stabilization. This is used for releasing the stop before changing the system clock. 3.12.1 Configuration Figure 3.12.1 shows the block diagram of the watchdog timer (WDT). RESET Internal reset WDMOD<RESCR> WDTOUT WDTI interrupt SYSCR0<WUEF> Enable Q WDTOUT , Reset WDMOD<WDTE> S interrupt control R Selector WDMOD<WARM> Selector Write disable code to WDCR (B1H) WDMOD <WDTP1:0> T45CR<QCU> Selector 2 7-stage binary counter Selector Selector 27 29 211 213 215 15-stage binary counter SYSCR0<WUEF> Reset Reset Write clear code to WDCR (4EH) WDT/warm-up changing HALT instruction (STOP, IDLE1 mode) fc/fs changing warm-up clock fSYS Selector fs Selector XT1 CPU 2 SYSCR1<SYSCK> fc fc/2 fc/4 fc/8 fc/16 SYSCR1<GEAR2:0> X1 ÷2 ÷4 ÷8 ÷16 Figure 3.12.1 Block Diagram of Watchdog Timer/Warm-up Timer 93CW46A-197 2004-02-10 TMP93CW46A The watchdog timer consists of 7-stage and 15-stage binary counters which use System clock (fSYS) as the input clock. Using T45CR<QCU>, the 7-stage binary counter is set to be used or not. The 15-stage binary counter has fSYS/215, fSYS/217, fSYS/219 and fSYS/221 outputs. Selecting one of these outputs with the WDMOD register generates a watchdog interrupt and outputs watchdog timer out when an overflow occurs. For the warm-up counter, 27 and 29 outputs of 15-stage binary counter can be selected using WDMOD<WARM> register. When a stable-external oscillator is used, shorter warm-up time is available using T45CR<QCU> register. When <QCU> = 1, counting value of 27 is selected. When the watchdog timer is in operation, this shorter warm-up time function cannot be selected. This function can be available by setting <QCU> = 0. Since the watchdog timer out pin ( WDTOUT ) outputs “0” for a watchdog timer overflow, the peripheral devices can be reset. The watchdog timer out pin is set to “1” after disabling WDT and clearing the watchdog timer (by writing a clear code 4EH in the WDCR register). Example: LDW (WDMOD), B100H ; Disable LD (WDCR), 4EH ; Write clear code SET 7, (WDMOD) ; Enable again In other words, the WDTOUT keeps outputting “0” until the clear code is written. The watchdog timer out pin can also be connected to the reset pin internally. In this case, the watchdog timer out pin ( WDTOUT ) outputs 0 for 8 to 20 states (12.8 to 32 µs at fc = 20 MHz) and then resets itself. WDT counter n Overflow 0 WDT interrupt Write clear code WDT clear (Software) WDTOUT Figure 3.12.2 Normal Mode Overflow WDT counter n WDT interrupt WDTOUT (Internal reset) 8 to 20 states = 12.8 to 32 µs (at 20 MHz) Figure 3.12.3 Reset Mode 93CW46A-198 2004-02-10 TMP93CW46A 3.12.2 Control Registers Watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Setting the detecting time of watchdog timer <WDTP> This 2-bit register is used to set the watchdog timer interrupt time for detecting the runaway. This register is initialized to WDMOD<WDTP1:0> = “00” when reset. The detecting time of WDT is shown Figure 3.12.6. b. Watchdog timer enable/disable control register <WDTE> When reset, WDMOD<WDTE> is initialized to “1” to enable the watchdog timer. To disable, it is necessary to clear this bit to “0” and write the disable code (B1H) in the watchdog timer control register WDCR. This makes it difficult for the watchdog timer to be disabled by runaway. However, it is possible to return from the disable state to enable state by merely setting <WDTE> to “1”. c. Watchdog timer out reset connection<RESCR> This bit is used to connect the output of the watchdog timer with RESET internally. Since WDMOD<RESCR> is initialized to 0 at reset, a reset by the watchdog timer will not be performed. (2) Watchdog timer control register (WDCR) This register is used to disable and clear of binary counter of the watchdog timer function. • Control By writing the disable code (B1H) in this WDCR register after clearing WDMOD<WDTE> to “0”, the watchdog timer can be disabled. WDMOD ← 0 ← 1 WDCR • − − − − − 0 1 1 0 0 X 0 X 1 Clear WDMOD<WDTE> to “0”. Write the disable code (B1H). Enable control Set WDMOD<WDTE>to “1”. • Watchdog timer clear control The binary counter can be cleared and resume counting by writing clear code (4EH) into the WDCR register. WDCR ← 0 1 0 0 1 1 1 0 93CW46A-199 Write the clear code (4EH). 2004-02-10 TMP93CW46A WDMOD Bit symbol (005CH) Read/Write After reset Function 7 6 5 4 WDTE WDTP1 WDTP0 WARM 3 2 1 0 HALTM1 HALTM0 RESCR DRVE R/W 1 0 WDT control 1: Enable 0 0 Select detecting time See Figure 3.12.6 Warm-up time 0 0 Standby mode 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 0 0 1: Internally 1: Drive the connects pin even WDT out in STOP to the mode reset pin DRVE (Explanation by stop mode) Watchdog timer out control 0 − 1 Connects WDT out to reset Select the standby mode HALT instruction 00 RUN mode (Only the CPU stops) 01 STOP mode (All circuits stop) 10 IDLE1 mode (Only the oscillator operates) 11 IDLE2 mode (CPU and AD stop) at fc = 20 MHz, fs = 32.768 kHz Select the warm-up time System Clock Selection <SYSCK> 1 (fs) 0 (fc) Gear Value <GEAR2:0> XXX (Don’t care) Warm-up Time T45CR<QCU> = 0 WARM = 0 WARM = 1 0.50 s 2.00 s T45CR<QCU> = 1 3.9 ms 000 (fc) 0.82 ms 3.28 ms 6.4 µs 001 (fc/2) 1.64 ms 6.55 ms 12.8 µs 010 (fc/4) 3.28 ms 13.11 ms 25.6 µs 011 (fc/8) 6.55 ms 26.21 ms 51.2 µs 100 (fc/16) 13.11 ms 52.43 ms 102.4 µs Watchdog timer enable/disable control 0 Disable 1 Enable Figure 3.12.4 Watchdog Timer Mode Register 93CW46A-200 2004-02-10 TMP93CW46A 7 6 5 4 3 WDCR Bit symbol − (005DH) Read/Write W 2 1 0 − After reset Function B1H: WDT disable code 4EH: WDT clear code Disable/clear WDT B1H Disable code 4EH Clear code Others Don’t set Figure 3.12.5 Watchdog Timer Control Register at fc = 20 MHz, fs = 32.768 kHz System Clock Selection <SYSCK> 1 (fs) 0 (fc) Note: Watchdog Timer Detecting Time Gear Value <GEAR2:0> WDMOD<WDTP1:0> 00 XXX (Don’t care) 2.00 s 01 8.00 s 10 32.00 s 11 128.0 s 000 (fc) 3.28 ms 13.11 ms 52.43 ms 209.72 ms 001 (fc/2) 6.55 ms 26.24 ms 104.86 ms 419.43 ms 010 (fc/4) 13.11 ms 52.43 ms 209.72 ms 838.86 ms 011 (fc/8) 26.21 ms 104.86 ms 419.43 ms 1.68 s 100 (fc/16) 52.43 ms 209.72 ms 838.86 ms 3.36 s When using as the watchdog timer, write “0” to T45CR<QCU> bit. Figure 3.12.6 Watchdog Timer Detecting Time 93CW46A-201 2004-02-10 TMP93CW46A 3.12.3 Operation The watchdog timer generates interrupt INTWD after the detecting time set in the WDMOD<WDTP1:0> and T45CR<QCU> registers and outputs a low level signal to the WDTOUT pin. For normal operation, the watchdog timer must be zero-cleared by software before an INTWD interrupt is generated. If the CPU malfunctions (Runaway) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter overflows and an INTWD interrupt is generated. The CPU detects malfunction (Runaway) due to the INTWD Interrupt and it is possible to return to normal operation by use of recovery program. By connecting the watchdog timer out pin to peripheral devices’ resets, a CPU malfunction can also be acknowledged by other devices. The watchdog timer restarts operation immediately after reset is released. The watchdog timer stops its operation in the IDLE1 and STOP modes. In the RUN mode, the watchdog timer is operational. When the bus is released (BUSAK = “L”), WDT continues counting. The watchdog timer is enabled in IDLE2 mode, but the over flow interrupt is disabled. Disable the watchdog timer before entering IDLE2 mode. Example: a. Clear the binary counter WDCR ← 0 1 0 0 1 1 1 0 Write clear code (4EH). b. Set the watchdog timer detecting time to 217/fSYS WDMOD ← 1 0 1 − − − X X c. Disable the watchdog timer. − − − − − 0 1 1 0 0 X 0 X 1 Clear WDTE to “0”. Write disable code (B1H). ← 0 − − WDMOD ← 1 0 1 WDCR Executes HALT command − 1 0 0 0 X 0 X 1 Disables WDT and sets IDLE1 mode. 1 WDMOD WDCR ← 0 ← 1 d. Set IDLE1 mode. Set the standby mode. e. Set the STOP mode (Warm-up time: 216/Inputted frequency) ← − − − WDMOD Executes HALT command. 1 0 93CW46A-202 1 X X Set the STOP mode. Execute HALT instruction. Set the standby mode. 2004-02-10 TMP93CW46A 4. “X” used in an expression shows a frequency of clock fFPH selected by SYSCR1<SYSCK>. If a clock gear or a low speed oscillator is selected, a value of “X” is different. The value as an example is calculated at fc, gear = 1/fc (SYSCR1<SYSCK, GEAR2:0> = “0000”). Electrical Characteristics 4.1 Maximum Ratings Parameter Symbol Rating Unit Power supply voltage VCC −0.5 to 6.5 Input voltage VIN −0.5 to VCC + 0.5 Output current (Per pin; PA0 to PA5) IOL1 20 Output current (Per pin; except PA0 to PA5) IOL2 2 Output current (PA0 to PA5 total) ΣIOL1 80 Output current (Total) ΣIOL 120 Output current (Total) ΣIOH −80 Power dissipation (Ta = 85°C) PD 600 Soldering temperature (10 s) TSOLDER 260 mA mW Storage temperature TSTG −65 to 150 Operating temperature TOPR −40 to 85 Note: V °C The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. DC Characteristics (1/2) (VSS = 0 V, Ta = −40 to 85°C) 4.2 Parameter Power supply voltage AVCC = VCC Symbol fc = 4 to 20 MHz VCC Input high voltage Input low voltage AVSS = VSS Note: AD0 to AD15 Condition VIL fc = 4 to 12.5 MHz Min fs = 30 to 34 kHz Typ. (Note) Max Unit 5.5 V 4.5 2.7 VCC ≥ 4.5 V 0.8 VCC < 4.5 V 0.6 Port 2 to port A (except P87) RESET , NMI , INT0 VIL2 EA , AM8/ AM16 VIL3 0.3 X1 VIL4 0.2 VCC AD0 to AD15 VIH 0.3 VCC VIL1 −0.3 VCC = 2.7 to 5.5 V VCC ≥ 4.5 V VCC < 4.5 V 0.25 VCC 2.2 2.0 0.7 VCC Port 2 to port A (except P87) RESET , NMI , INT0 VIH2 EA , AM8/ AM16 VIH3 VCC − 0.3 X1 VIH4 0.8 VCC VIH1 VCC = 2.7 to 5.5 V V 0.75 VCC VCC + 0.3 Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. 93CW46A-203 2004-02-10 TMP93CW46A 4.2 DC Characteristics (2/2) (VSS = 0 V, Ta = −40 to 85°C) Parameter Output low voltage Symbol VOL Condition Min IOL = 1.6 mA (VCC = 2.7 to 5.5 V) VOL = 1.0 V Output low current (PA0 to PA5) IOLA (VCC = 3 V ± 10%) VOL = 1.0 V (VCC = 5 V ± 10%) VOH1 Output high voltage VOH2 Typ. (Note 1) IOH = −400 µA (VCC = 3 V ± 10%) IOH = −400 µA (VCC = 5 V ± 10%) Max Unit 0.45 V 7 mA 16 2.4 V 4.2 VEXT = 1.5 V Darlington drive current (8 output pins max) IDAR Input leakage current ILI 0.0 ≤ VIN ≤ VCC 0.02 ±5 Output leakage current ILO 0.2 ≤ VIN ≤ VCC − 0.2 0.05 ±10 Power down voltage (at STOP, RAM backup) VSTOP VIH2 = 0.8 VCC 2.0 6.0 RESET pull-up resister RRST VCC = 5 V ± 10% 50 150 VCC = 3 V ± 10% 80 200 (Note 2) Pin capacitance CIO Schmitt width RESET , NMI , INT0 VTH Programmable Pull-down resistor RKL Programmable Pull-up resistor RKH NORMAL ICC RUN REXT = 1.1 kΩ −1.0 VIL2 = 0.2 VCC, fc = 1 MHz 10 0.4 1.0 VCC = 5 V ± 10% 10 80 30 150 VCC = 5 V ± 10% 50 150 VCC = 3 V ± 10% 100 300 VCC = 5 V ± 10% 21 28 fc = 20 MHz 17 25 12.5 17 IDLE1 NORMAL VCC = 3 V ± 10% RUN fc = 12.5 MHz (Typ.: VCC = 3.0 V) 2.5 4 7 10 5.5 9 4.5 6 0.7 1 SLOW VCC = 3 V ± 10% 20 35 RUN fs = 32.768 kHz 16 30 11 25 IDLE1 IDLE2 (Typ.: VCC = 3.0 V) 4 IDLE1 STOP mA Ta ≤ 50°C VCC Ta ≤ 70°C = 2.7 to Ta ≤ 85°C µA V kΩ pF V VCC = 3 V ± 10% IDLE2 IDLE2 −3.5 (VCC = 5 V ± 10% only) kΩ mA mA µA 15 10 5.5 V 0.2 20 µA 50 Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guaranteed for total of up to 8 ports. 93CW46A-204 2004-02-10 TMP93CW46A 4.3 AC Characteristics (1) VCC = 5 V ± 10% No. Parameter Symbol Variable 16 MHz Min Max Min 33333 Max 20 MHz Min Max Unit 1 Osc. period (= X) tOSC 50 62.5 50 ns 2 CLK pulse width tCLK 2x − 40 85 60 ns 3 A0 to A23 valid → CLK hold tAK 0.5x − 20 11 5 ns 4 CLK valid→A0 to A23 hold tKA 1.5x − 70 24 5 ns 5 A0 to A15 valid → ALE fall tAL 0.5x − 15 16 10 ns 6 ALE fall → A0 to A15 hold tLA 0.5x − 20 11 5 ns 7 ALE high pulse width tLL x − 40 23 10 ns 8 ALE fall → RD / WR fall tLC 0.5x − 25 6 0 ns 9 RD / WR rise → ALE rise tCL 0.5x − 20 11 5 ns 10 A0 to A15 valid → RD / WR fall tACL x − 25 38 25 ns 11 A0 to A23 valid → RD / WR fall tACH 1.5x − 50 44 25 ns 12 RD / WR rise → A0 to A23 hold tCA 0.5x − 25 6 0 13 A0 to A15 valid → D0 to D15 input tADL 14 A0 to A23 valid → D0 to D15 input 15 RD fall → D0 to D15 input 16 RD low pulse width tRR 17 RD rise → D0 to D15 hold tHR 0 0 0 ns 18 RD rise → A0 to A15 output tRAE x − 15 48 35 ns 19 WR low pulse width tWW 2.0x − 40 85 60 ns 20 D0 to D15 valid → WR rise tDW 2.0x − 55 70 45 ns 21 WR rise → D0 to D15 hold tWD 0.5x − 15 16 10 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold 25 A0 to A23 valid → Port input tAPH 26 A0 to A23 valid → Port hold tAPH2 (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode ns 3.0x − 55 133 95 ns tADH 3.5x − 65 154 110 ns tRD 2.0x − 60 65 40 ns 2.0x − 40 3.5x − 90 tAWH 2.0x + 0 60 129 3.0x − 80 tAWL tCW 85 2.5x − 120 2.5x + 50 ns 85 108 125 ns 70 100 36 206 ns ns ns 5 175 ns ns 27 WR rise → Port valid 28 A0 to A23 valid → RAS fall tASRH 1.0x − 40 23 10 ns 29 A0 to A15 valid → RAS fall tASRL 0.5x − 15 16 10 ns 30 RAS fall → D0 to D15 input tRAC 31 RAS fall → A0 to A15 hold tRAH 0.5x − 15 16 10 ns 32 RAS low pulse width tRAS 2.0x − 40 85 60 ns 33 RAS high pulse width tRP 2.0x − 40 85 60 ns 34 CAS fall → RAS rise tRSH 1.0x − 40 23 10 ns 35 RAS rise → CAS rise tRSC 0.5x − 25 6 0 ns 36 RAS fall → CAS fall tRCD 1.0x − 40 23 10 ns 37 CAS fall → D0 to D15 input tCAC 38 CAS low pulse width tCAS 200 tCP 200 2.5x − 70 86 1.5x − 65 1.5x − 30 200 55 29 64 10 40 ns ns ns ns AC measuring conditions • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD, WR, HWR, R/W, CLK, RAS, CAS0 to CAS2) • Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (Except for AD0 to AD15) 93CW46A-205 2004-02-10 TMP93CW46A (2) VCC = 3 V ± 10% No. Parameter Variable Symbol 12.5 MHz Min Max 33333 Min Max Unit 1 Osc. period (= x) tOSC 80 80 ns 2 CLK pulse width tCLK 2x − 40 120 ns 3 A0 to A23 valid → CLK hold tAK 0.5x − 30 10 ns 4 CLK valid → A0 to A23 hold tKA 1.5x − 80 40 ns 5 A0 to A15 valid → ALE fall tAL 0.5x − 35 5 ns 6 ALE fall → A0 to A15 hold tLA 0.5x − 35 5 ns 7 ALE high pulse width tLL x − 60 20 ns 8 ALE fall → RD / WR fall tLC 0.5x − 35 5 ns 9 RD / WR rise → ALE rise tCL 0.5x − 40 0 ns 10 A0 to A15 valid → RD / WR fall tACL x − 50 30 ns 11 A0 to A23 valid → RD / WR fall tACH 1.5x − 50 70 ns 12 RD / WR rise → A0 to A23 hold tCA 0.5x − 40 0 13 A0 to A15 valid → D0 to D15 input tADL 14 A0 to A23 valid → D0 to D15 input 15 RD fall → D0 to D15 input 16 RD low pulse width tRR 17 RD rise → D0 to D15 hold tHR 0 0 ns 18 RD rise → A0 to A15 output tRAE x − 25 55 ns 19 WR low pulse width tWW 2.0x − 40 120 ns 20 D0 to D15 valid → WR rise tDW 2.0x − 120 40 ns 21 WR rise → D0 to D15 hold tWD 0.5x − 40 0 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold 25 A0 to A23 valid → Port input tAPH 26 A0 to A23 valid → Port hold tAPH2 27 WR rise → Port valid tCP 28 A0 to A23 valid → RAS fall tASRH 1.0x − 60 20 29 A0 to A15 valid → RAS fall tASRL 0.5x − 40 0 30 RAS fall → D0 to D15 input tRAC 31 RAS fall → A0 to A15 hold tRAH 0.5x − 25 15 ns 32 RAS low pulse width tRAS 2.0x − 40 120 ns 33 RAS high pulse width tRP 2.0x − 40 120 ns 34 CAS fall → RAS rise tRSH 1.0x − 55 25 ns 35 RAS rise → CAS rise tRSC 0.5x − 25 15 ns 36 RAS fall → CAS fall tRCD 1.0x − 40 40 37 CAS fall → D0 to D15 input tCAC 38 CAS low pulse width tCAS (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode ns 3.0x − 110 130 ns tADH 3.5x − 125 155 ns tRD 2.0x − 115 45 ns 2.0x − 40 120 tAWH 3.5x − 130 tAWL 3.0x − 100 tCW 2.0x + 0 ns ns 150 ns 140 ns 160 2.5x − 195 2.5x + 50 ns 5 250 200 200 2.5x − 90 1.5x − 40 ns ns ns 0 80 ns ns 110 1.5x − 120 ns ns ns ns AC measuring conditions • Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF • Input level: High 0.9 × VCC/Low 0.1 × VCC 93CW46A-206 2004-02-10 TMP93CW46A (1) Read cycle tOSC X1/XT1 tCLK CLK tAK tKA A0 to A23 CS0 to CS2 tAWH R/W tCW tAWL WAIT tAPH tAPH2 Port input (Note) tASRH tRAS tASRL RAS tRP tRSH tRSC tRAC tRAH tRCD CAS0 to CAS2 tCAS tCAC tADH RD tACH tRR AD0 to AD15 tRD tADL A0 to A15 tAL Note: tRAE tACL tLC ALE tCA tHR D0 to D15 tLA tCL tLL Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93CW46A-207 2004-02-10 TMP93CW46A (2) Write cycle X1/XT1 CLK A0 to A23 CS0 to CS2 R/W WAIT Port output (Note) tCP RAS CAS0 to CAS2 WR , HWR tWW tDW AD0 to AD15 tWD D0 to D15 A0 to A15 ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93CW46A-208 2004-02-10 TMP93CW46A 4.4 AD Conversion Characteristics (VSS = 0 V, AVCC = VCC, AVSS = VSS, Ta = −40 to 85°C) Parameter Symbol Power Supply VREFH Analog reference voltage (+) Analog reference voltage (−) VREFL Analog input voltage range Analog current for analog reference voltage <VREFON> = 1 VAIN Typ. Max VCC − 1.5 VCC VCC VCC = 3 V ± 10% VCC − 0.2 VCC VCC VCC = 5 V ± 10% VSS VSS VSS + 0.2 VCC = 3 V ± 10% VSS VSS VSS + 0.2 VREFL IREF (VREFL = 0 V) <VREFON> = 0 Min VCC = 5 V ± 10% − Error Unit V VREFH VCC = 5 V ± 10% 0.5 1.5 VCC = 3 V ± 10% 0.3 0.9 mA µA VCC = 2.7 to 5.5V 0.02 5.0 VCC = 5 V ± 10% ±1.0 ±3.0 VCC = 3 V ± 10% ±1.0 ±3.0 LSB Note 1: 1LSB = (VREFH − VREFL)/2 [V] 10 Note 2: Minimum operation frequency The operation of this AD converter is guaranteed only when fc (High-frequency oscillator) is used. (It is not guaranteed when fs is used.) Additionally, it is guaranteed with fFPH ≥ 4 MHz. Note 3: The value ICC includes the current with flows through AVCC pin. Note 4: The operation of this AD converter is guaranteed at 5 V ± 10%. 4.5 Serial Channel Timing (1) SCLK input mode Parameter (Note) Variable Symbol Min 12.5 MHz 32.768 MHz Min Max Max Min Max 20 MHz Min SCLK cycle tSCY 16X 488 µs 1.28 µs 0.8 µs Output data → Rising edge of SCLK tOSS tSCY/2 − 5X − 50 91.5 µs 190 ns 100 ns SCLK rising edge → Output data hold tOHS 5X − 100 152 µs 300 ns 150 ns SCLK rising edge → Input data hold tHSR 0 0 0 SCLK rising edge → Effective data input tSRD tSCY − 5X − 100 336 µs Max 0 780 ns 450 ns (2) SCLK output mode Parameter (Note) Variable Symbol 12.5 MHz 32.768 MHz Min Max Min Max SCLK cycle (Programmable) tSCY 16X 8192X Output data → SCLK rising edge tOSS tSCY − 2X − 150 427 µs 970 ns 550 ns SCLK rising edge → Output data hold tOHS 2X − 80 60 µs 80 ns 20 ns SCLK rising edge → Input data hold tHSR 0 0 0 SCLK rising edge → Effective data input tSRD 488 µs tSCY − 2X − 150 250 ms Min Max 20 MHz Min Max 1.28 µs 655.36 µs 0.8 µs 409.6 µs 428 µs 0 970 ns 550 ns (3) SCLK input mode (UART mode) Parameter Variable Symbol Min Max (Note) 32.768 MHz Min Max 12.5 MHz Min Max 20 MHz Min SCLK cycle tSCY 4X + 20 122 µs 340 ns 220 ns Low level SCLK pulse width tSCYL 2X + 5 6 µs 165 ns 105 ns High level SCLK pulse width tSCYH 2X + 5 6 µs 165 ns 105 ns Max Note: fs is used as system clock (fSYS) or fs is used as input clock to prescaler. 93CW46A-209 2004-02-10 TMP93CW46A 4.6 Timer/Counter Input Clock (TI0, TI4, TI5, TI6 and TI7) Parameter 4.7 Symbol Variable Min Max 12.5 MHz Min Max 20 MHz Min Max Clock cycle tVCK 8X + 100 740 500 ns Low level clock pulse width tVCKL 4X + 40 360 240 ns High level clock pulse width tVCKH 4X + 40 360 240 ns Interrupt and Capture (1) NMI and INT0 interrupts Parameter Symbol Variable Min Max 12.5 MHz Min Max 20 MHz Min Unit Max NMI , INT0 low level pulse width tINTAL 4X 320 200 ns NMI , INT0 high level pulse width tINTAH 4X 320 200 ns (2) INT4 to INT7 Parameter 4.8 Symbol Variable Min Max 12.5 MHz Min Max 20 MHz Min Unit Max INT4 to INT7 low level pulse width tINTBL 4X + 100 420 300 ns INT4 to INT7 high level pulse width tINTBH 4X + 100 420 300 ns SCOUT Pin AC Characteristics Parameter Symbol High-level pulse width VCC = 5V ± 10% tSCH VCC = 3V ± 10% Low-level pulse width VCC = 5V ± 10% Variable Min Max 12.5 MHz Min Max 20 MHz Min 0.5X − 10 30 15 0.5X − 20 20 − 0.5X − 10 30 15 0.5X − 20 20 − Max − tSCL VCC = 3V ± 10% − Measurement condition • Output level: High 2.2 V/Low 0.8 V, CL = 10 pF tSCH SCOUT tSCL 93CW46A-210 2004-02-10 Input data RXD Output data TXD Note: 93CW46A-211 0 Valid tOHS tSRD SCLK is reversed in SCLK input falling mode. tOSS tSCY 1 Valid tHSR 2 Valid 3 Valid 4.9 SCLK TMP93CW46A Timing Chart for I/O Interface Mode 2004-02-10 TMP93CW46A 4.10 Timing Chart for Bus Request ( BUSRQ )/Bus Acknowledge ( BUSAK ) (Note 1) CLK tBRC tBRC BUSRQ tCBAL tCBAH BUSAK AD0 to AD15, A0 to A23, CS0 to CS2 , R / W , RAS , CAS0 to CAS2 tBAA tABA (Note 2) (Note 2) RD , WR , HWR ALE Parameter Symbol Variable Min Max 12.5 MHz Min Max 20 MHz Min Max Unit BUSRQ setup time to CLK tBRC CLK→ BUSAK falling edge tCBAL 1.5X + 120 240 195 CLK→ BUSAK rising edge tCBAH 0.5x + 40 80 65 ns Output buffer is off to BUSAK BUSAK to output buffer is on. 120 120 120 ns ns tABA 0 80 0 80 0 80 ns tBAA 0 80 0 80 0 80 ns Note 1: The bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during “wait” cycle. Note 2: This line only shows the output buffer is off state. It doesn’t indicate the signal level is fixed. Just after the bus is released, the signal level which is set before the bus is released is kept dynamically by the external capacitance. Therefore, to fix the signal level by an external resistor during bus releasing, designing is executed carefully because the level-fix will be delayed. The internal programmable pull-up/pull-down resistor is switched active/non-active by an internal signal. 93CW46A-212 2004-02-10 TMP93CW46A 5. Table of Special Function Registers (SFRs) The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 128-byte addresses from 000000H to 00007FH. (1) I/O port (2) I/O port control (3) Timer control (4) Watchdog timer control (5) Serial channel control (6) AD converter control (7) Interrupt control (8) Chip select/wait control (9) Clock control Configuration of the table Symbol Name Address 7 6 1 0 Bit symbol Read/Write Initial value after reset Remarks Note: “Prohibit RMW” in table means that you cannot use RMW instructions to these registers. Example: In case of setting only the bit 0 of register P0CR, you mustn’t use “Set 0, (0002H)” 93CW46A-213 2004-02-10 TMP93CW46A Table 5.1 I/O Register Address Map Address Name 000000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH P0 P1 P0CR 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH P4FC Note: P1CR P1FC P2 P3 P2CR P2FC P3CR P3FC P4 P5 P4CR P6 P7 P6CR P7CR P6FC P7FC P8 P9 P8CR P9CR P8FC P9FC PA PACR Address Name Address Name BRADD4 SC4BUF SC4CR SC4MOD BR4CR ADREG04L ADREG04H ADREG15L ADREG15H ADREG26L ADREG26H ADREG37L ADREG37H B0CS B1CS B2CS BRADD0 BRADD1 CKOCR SYSCR0 SYSCR1 SC0BUF SC0CR SC0MOD BR0CR SC1BUF SC1CR SC1MOD BR1CR ODE INTES2 INTES3 INTES4 WDMOD WDCR ADMOD1 ADMOD2 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH INTE0AD INTE45 INTE67 INTET10 INTEPW10 INTET54 INTET76 INTES0 INTES1 TREG0 TREG1 TMOD TFFCR TREG2 TREG3 P0MOD P1MOD PFFCR BRADD2 SC2BUF SC2CR SC2MOD BR2CR TREG6L TREG6H TREG7L TREG7H CAP3L CAP3H CAP4L CAP4H T5MOD T5FFCR TREG4L TREG4H TREG5L TREG5H CAP1L CAP1H CAP2L CAP2H T4MOD T4FFCR T45CR BRADD3 SC3BUF SC3CR SC3MOD BR3CR 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH TRUN 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Name 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH Address IIMC DMA0V DMA1V DMA2V DMA3V Do not access the addresses without allocated register names. 93CW46A-214 2004-02-10 TMP93CW46A (1) I/O port Symbol Name Address P0 Port 0 00H P1 Port 1 01H P2 P3 Port 2 Port 3 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 P12 P11 P10 0 0 0 P22 P21 P20 0 0 0 P32 P31 P30 (Note 1) P17 P16 0 0 P27 P26 0 0 P37 P36 1 1 06H 07H R/W Undefined Input mode P15 P14 P13 R/W 0 0 0 Input mode P25 P24 P23 *R/W (Note 3) 0 0 0 Input mode P35 P34 P33 *R/W (Note 3) 1 1 1 Input mode 1 P42 P4 Port 4 0CH 0 P5 Port 5 0DH P6 Port 6 12H P7 Port 7 P57 P56 P55 P67 P66 P65 1 1 1 P54 P53 R Input mode P64 P63 *R/W (Note 3) 1 1 Input mode P73 13H 1 P8 P9 Port 8 Port 9 (Note 2) P87 P86 P85 1 1 1 P97 R/W 1 P96 R/W 1 P95 18H 19H 1 Output mode Output mode PA Port A PA7 PA6 PA5 1 1 1 1EH P52 1 1 Output mode P41 P40 *R/W (Note 3) 1 1 Input mode P51 P50 P62 P61 P60 1 1 1 P72 P71 *R/W (Note 3) 1 1 Input mode P82 P81 P84 P83 *R/W (Note 3) 1 1 1 Input mode P94 P93 P92 *R/W (Note 3) 1 1 1 Input mode PA4 PA3 PA2 R/W 1 1 1 Input mode P70 1 P80 1 1 P91 P90 1 1 PA1 PA0 1 1 Note 1: When P30 pin is defined as RD signal output mode (P30F = 1), clearing the output latch register P30 to “0” outputs the RD strobe from P30 pin for PSRAM, even when the internal address is accessed. If the output latch register P30 remains “1”, the RD strobe is output only when the external address is accessed. Note 2: Port 96, 97 is also used as XT1, XT2. Therefore these pins are open drain output type. Read/Write R/W: Either read or write is possible R: Only read is possible W: Only write is possible Prohibit RMW: Prohibit read-modify-write. (Prohibit RES/SET/TSET/CHG/STCF /ANDCF/ORCF/XORCF instruction.) Note 3: *R/W: Read-modify-write is prohibited when controlling the pull-up/pull-down resistors. 93CW46A-215 2004-02-10 TMP93CW46A (2) I/O port control (1/2) Symbol P0CR Name Address Port 0 control 02H (Prohibit RMW) 7 6 5 4 3 2 1 0 P07C P06C P05C P04C P03C P02C P01C P00C 0 0 0 0 0 0 0 0 W 0: In 1: Out (When external access, set as AD7 to AD0 and cleared to “0”.) P17C P1CR Port 1 control 04H (Prohibit RMW) Port 1 function 05H (Prohibit RMW) 0 Port 2 control 08H (Prohibit RMW) Port 2 function 09H (Prohibit RMW) 0 Port 3 control 0AH (Prohibit RMW) Port 3 function 0BH (Prohibit RMW) P11C P10C 0 0 0 0 0 0 0 P16F P15F P14F P13F P12F P11F P10F 0 0 0 0 0 0 0 P26C P25C P24C P23C P22C P21C P20C 0 0 0 0 P23F P22F P21F P20F 0 0 0 0 W 0 0 0 0 <<Refer to the “P2FC”>> P26F P25F P24F W 0 0 0 0 P2FC/P2CR = 00: Input 01: Output 10: A7 to A0 11: A23 to A16 P36C P35C P34C P33C P32C 0 0 W 0 P37F P3FC P12C P1FC/P1CR = 00: Input 01: Output 10: AD15 to AD8 11: A15 to A8 P37C P3CR P13C W P27F P2FC P14C <<Refer to the “P1FC”>> P27C P2CR P15C W P17F P1FC P16C 0 P36F 0 0 0: Input 1: Output P35F P34F P32F 0 0: Port 1: RAS 0 0: Port 1: R/ W 0 0 0: Port 0: Port 1: BUSAK 1: BUSRQ 0 Port 4 control 0EH (Prohibit RMW) Port 4 function 0 0: Port 1: WR 0: Port 1: RD P41C P40C W 0 0 0: Input P42F P4FC P30F 0 0: Port 1: HWR P42C P4CR P31F W 10H (Prohibit RMW) 0 1: Output P41F P40F W 0 0 0 0: Port 1: CS / CAS 93CW46A-216 2004-02-10 TMP93CW46A (2) I/O port control (2/2) Symbol P6CR Name Address Port 6 control 14H (Prohibit RMW) 7 6 5 4 3 2 1 0 P67C P66C P65C P64C P63C P62C P61C P60C 0 0 0 0 0 0 0 0 P71C P70C 0 0 W 0: Input 1: Output P73C P7CR P6FC Port 7 control Port 6 function 15H (Prohibit RMW) P72C W 0 0 0: Input 1: Output 16H (Prohibit RMW) P66F P65F P63F P62F P60F W W W W W 0 0 0 0 0: Port 1: TXD4 0: Port 1: SCLK3 0: Port 1: TXD3 P73F P7FC Port 7 function 17H (Prohibit RMW) P9CR P8FC P9FC Port 8 control Port 9 control Port 8 function Port 9 function 1AH (Prohibit RMW) 1BH (Prohibit RMW) 0 Port A control 0 P86C P85C P84C 0 0 0: Port 1: TO3 0: Port 1: TO2 0: Port 1: TO1 P83C P82C P81C P80C 0 0 0 0 0 0 0 P92C P91C P90C 0 0 0 0: Input 1: Output P97C P96C W W 1 1 P95C P94C P93C W 0 0 0 0: Input 1: Output 1CH (Prohibit RMW) P86F P83F P82F W W W 0 0 0: Port 1: TO6 1DH (Prohibit RMW) 1FH (Prohibit RMW) P71F W PA6C 0 0: Port 1: TO5 0: Port 1: TO4 P95F P93F P92F P90F W W W W 0 0 0 0: Port 1: SCLK1 PA7C PACR P72F 0: Port 1: TXD2 W P87C P8CR 0 0: Port 1: SCLK2 PA5C 0: Port 1: TXD1 PA4C 0 0: Port 1: SCLK0 0: Port 1: TXD0 PA3C PA2C PA1C PA0C 0 0 0 0 W 0 0 0 0 0: Input 1: Output 93CW46A-217 2004-02-10 TMP93CW46A (3) Timer control (1/3) Symbol Name Address 7 6 PRRUN 5 4 3 2 1 0 T5RUN T4RUN P1RUN P0RUN T1RUN T0RUN 0 0 0 0 0 0 T1CLK1 T1CLK0 T0CLK1 T0CLK0 0 0 0 0 R/W TRUN Timer control 20H Prescaler and timer run/stop control 0: Stop and clear 1: Run (Count up) TREG0 8-bit timer register 0 22H (Prohibit RMW) TREG1 8-bit timer register 1 23H (Prohibit RMW) − W Undefined − W Undefined T10M1 TMOD 8-bit timer source CLK & mode R/W 0 T10M0 PWMM1 PWMM0 W 24H (Prohibit RMW) 0 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 00: − 01: 26 − 1 10: 27 − 1 11: 28 − 1 00: TO0TRG 01: φT1 10: φT16 11: φT256 PWM DBEN TFFCR 8-bit timer flip-flop control 25H TREG2 PWM timer register 2 26H TREG3 PWM timer register 3 27H 1 1 00: Invert TFF1 01: Set TFF1 10: Clear TFF1 11: Don’t care 0 1: TFF1 invert enable 0 0: Inverted by timer 0 PWM0S1 PWM0S0 0 0 Undefined − (R)/W (Can read double buffer values.) Undefined 28H (Prohibit RMW) − TFF2 output value FF3RD DB2EN PWM0INT PWM0M 29H (Prohibit RMW) − TFF3 output value T2CLK1 T2CLK0 W 0 0 0 1: Double 0:Overflow 0: PWM buffer mode interrupt enable 1:Compare/ 1: Timer mode match DB3EN PWM1INT PWM1M R PWM1 mode TFF1IS R/W − interrupt P1MOD TFF1IE (R)/W (Can read double buffer values.) R PWM0 mode TFF1C0 W 0 1: Double buffer enable FF2RD P0MOD TFF1C1 R/W 00: TI0 Input 01: φT1 10: φT4 11: φT16 0 0 00: φP1 01: φP4 10: φP16 00: 26 − 1 01: 27 − 1 10: 28 − 1 11: Don’t care 11: Don’t care T3CLK1 T3CLK0 PWM1S1 PWM1S0 0 0 W 0 0 0 1: Double 0: Overflow 0: PWM buffer mode interrupt enable 1: Compare/ 1: Timer mode match interrupt 93CW46A-218 0 0 00: φP1 01: φP4 10: φP16 00: 26 − 1 01: 27 − 1 10: 28 − 1 11: Don’t care 11: Don’t care 2004-02-10 TMP93CW46A (3) Timer control (2/3) Symbol Name Address 7 6 FF3C1 FF3C0 5 4 FF3TRG1 FF3TRG0 W 3 2 FF2C1 FF2C0 R/W 1 1 00: Don’t care 01: Set TFF3 10: Clear TFF3 11: Don’t care W 0 0 00: Prohibit TFF3 invert 01: Invert if matched 10: Set if matched; clear if overflow 11: Clear if matched; set if overflow PWM flip-flop control TREG4L 16-bit timer register 4 low 30H (Prohibit RMW) TREG4H 16-bit timer register 4 high 31H (Prohibit RMW) TREG5L 16-bit timer register 5 low 32H (Prohibit RMW) TREG5H 16-bit timer register 5 high 33H (Prohibit RMW) Undefined CAP1L Capture register 1 low 34H R CAP1H Capture register 1 high 35H CAP2L Capture register 2 low 36H CAP2H Capture register 2 high 37H T4MOD − Undefined − W Undefined − W Undefined − W − Undefined − R Undefined − R Undefined − R Undefined EQ5T5 R/W 0 38H T4FFCR CAP1IN CAP12M1 CAP12M0 W 0 TFF5C0 1 CAP2T4 0 0 Capture timing 00: Disable 01: TI4 ↑ TI5 ↑ 10: TI4 ↑ TI4 ↓ 11: TFF1 ↑ TFF1 ↓ CAP1T4 W 39H CLE EQ5T4 0 1: UC4 clear enable EQ4T4 R/W 1 1 00: Invert TFF5 01: Set TFF5 10: Clear TFF5 11: Don’t care T4CLK1 T4CLK0 0 0 R/W 0:Software capture 1: Don’t care TFF5 INV TRG 0: TRG disable 1: TRG enable TFF5C1 16-bit timer 4 flip-flop control 0 0 00: Prohibit TFF2 invert 01: Invert if matched 10: Set if matched; clear if overflow 11: Clear if matched; set if overflow W CAP2T5 16-bit timer 4 source CLK & mode 0 R/W 1 1 00: Don’t care 01: Set TFF2 10: Clear TFF2 11: Don’t care PFFCR 2AH 1 FF2TRG1 FF2TRG0 0 93CW46A-219 0 Source clock 00: TI4 01: φT1 10: φT4 11: φT16 TFF4C1 TFF4C0 W 0 TFF4 invert trigger 0: Trigger disable 1: Trigger enable 0 1 1 00: Invert TFF4 01: Set TFF4 10: Clear TFF4 11: Don’t care 2004-02-10 TMP93CW46A (3) Timer control (3/3) Symbol Name Address 7 6 5 4 3 2 QCU 1 0 DB6EN DB4EN R/W T45CR T4, T5 control 3AH R/W 0 0 Warm-up timer control − TREG6L 16-bit timer register 6 low 40H (Prohibit RMW) TREG6H 16-bit timer register 6 high 41H (Prohibit RMW) TREG7L 16-bit timer register 7 low 42H (Prohibit RMW) TREG7H 16-bit timer register 7 high 43H (Prohibit RMW) Undefined CAP3L Capture register 3 low 44H R CAP3H Capture register 3 high 45H CAP4L Capture register 4 low 46H CAP4H Capture register 4 high 47H W Undefined − W Undefined − W Undefined − W − Undefined − R Undefined − R Undefined − R Undefined CAP3IN T5MOD 16-bit timer 5 source CLK & mode T5FFCR CAP34M1 CAP34M0 W 1 48H CLE 0 0 Capture timing 00: Disable 01: TI6 ↑ TI7 ↑ 10: TI6 ↑ TI6 ↓ 11: TFF1 ↑ TFF1 ↓ CAP3T6 EQ7T6 0 1: UC5 clear enable EQ6T6 R/W 49H T5CLK1 T5CLK0 0 0 R/W 0:Software capture 1: Don’t care CAP4T6 16-bit timer 5 flip-flop control 0 1: Double buffer enable 0 0 TFF6C1 TFF6C0 W 0 TFF6 invert trigger 0: Trigger disable 1: Trigger enable 93CW46A-220 Source clock 00: TI6 01: φT1 10: φT4 11: φT16 0 1 1 00: Invert TFF6 01: Set TFF6 10: Clear TFF6 11: Don’t care 2004-02-10 TMP93CW46A (4) Watchdog timer Symbol Name Address 7 6 5 4 3 2 1 0 WDTE WDTP1 WDTP0 WARM HALTM1 HALTM0 RESCR DRVE 1 0 0 0 0 0 0 R/W WDMOD Watchdog timer mode 00: 215/fSYS 5CH 1: WDT enable 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS 0 Standby mode 00: RUN mode 14 01: STOP mode 0: 2 / inputted 10: IDLE1 mode frequency 11: IDLE2 mode Warm-up time 1: Connect 1: Drive internally the pin WDT out in stop to reset mode pin 1: 216/ inputted frequency WDCR Watchdog timer control register − W 5DH − B1H: WDT disable code 93CW46A-221 4EH: WDT clear code 2004-02-10 TMP93CW46A (5) Serial channel (1/3) Symbol Name Serial SC0BUF channel 0 buffer Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 RB1 RB0 TB0 50H R (Receiving) /W (Transmission) Undefined RB8 EVEN R SC0CR Serial channel 0 control Undefined 51H PE OERR R/W 0 0 Receiving Parity data bit8 0: Odd PERR FERR SCLKS R (Cleared to 0 by reading) 0 0 0 1: Error 1: Parity enable Overrun Parity CTSE RXE WU 0 0 0: SCLK0 1: SCLK0 1: Input SCLK0 pin SC1 SC0 Framing 1: Even TB8 SM1 SM0 0 0 IOC R/W R/W Serial SC0MOD channel 0 mode Undefined 52H 0 0 Transmission 1: CTS data bit8 − enable BR0ADD 0 1: Receive 1: Wake enable up enable BR0CK1 00: I/O interface 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits 0 0 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 11: SCLK input BR0S3 BR0S2 BR0S1 BR0S0 0 0 0 BR0CK0 R/W BR0CR Baud rate control 0 53H R/W 0 0 Fix at “0”. 1: + (16 − K) /16 divided enable 0 0 00: φT0 01: φT2 10: φT8 11: φT32 Set frequency divisor 0 to F BR0K3 BRADD0 Baud rate control Serial SC1BUF channel 1 buffer BR0K0 0 0 0 0 Set frequency divisor 1 to F (“0” prohibited) RB3 RB2 RB1 RB0 TB3 TB2 RB1 TB0 6BH RB7 TB7 RB6 TB6 RB5 TB5 54H RB4 TB4 R (Receiving) /W (Transmission) Undefined EVEN R Serial channel 1 control BR0K1 R/W RB8 SC1CR BR0K2 Undefined 55H PE R/W 0 Receiving Parity data bit8 0: Odd 1: Even TB8 OERR − PERR FERR SCLKS R (Cleared to 0 by reading) 0 0 0 0 Overrun RXE Parity WU 0 0 0:SCLK1 1: Error 1: Parity enable 1: SCLK1 1: Input SCLK1 pin SC1 SC0 Framing SM1 SM0 IOC R/W R/W Serial SC1MOD channel 1 mode BR1CR Baud rate control Undefined 56H 0 data bit8 57H 0 0 Transmission Fix at “0”. 1: Receive 1: Wake − BR1ADD R/W R/W 0 0 Fix at “0”. 1: + (16 − K) /16 divided enable enable up enable BR1CK1 BR1CK0 0 0 00: I/O interface 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits 0 0 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 11: SCLK input BR1S3 BR1S2 BR1S1 BR1S0 0 0 0 R/W 0 0 00: φT0 01: φT2 10: φT8 11: φT32 93CW46A-222 0 Set frequency divisor 0 to F 2004-02-10 TMP93CW46A (5) Serial channel (2/3) Symbol BRADD1 Name Baud rate control Address 7 6 5 4 3 2 1 0 BR1K3 BR1K2 BR1K1 BR1K0 0 0 0 0 R/W 6CH Set frequency divisor 1 to F (“0” prohibited) ODE1 ODE Serial opendrain enable Serial SC2BUF channel buffer 0 58H 2CH RB7 TB7 RB6 TB6 RB4 TB4 RB3 TB3 1: P90 open drain RB1 RB1 RB0 TB0 RB2 TB2 Undefined EVEN R Serial channel control RB5 TB5 0 1: P93 open drain R (Receiving) /W (Transmission) RB8 SC2CR ODE0 R/W Undefined 2DH PE R/W 0 0 FERR SCLKS 0 Overrun 0 RXE Parity WU 0 0 0: SCLK2 1: SCLK2 1: Input SCLK2 pin SC1 SC0 Framing SM1 IOC R/W 1: Error 1: Parity enable CTSE PERR R (Cleared to 0 by reading) 0 Receiving Parity data bit8 0: Odd 1: Even TB8 OERR SM0 R/W Serial SC2MOD channel mode BR2CR Baud rate control Undefined 2EH 2FH 0 0 Transmission 1: CTS2 data bit8 enable − BR2ADD R/W R/W 0 0 0 1: Receive 1: Wake enable up enable BR2CK1 BR2CK0 0 0 00: I/O interface 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits 0 0 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 11: SCLK input BR2S3 BR2S2 BR2S1 BR2S0 0 0 0 R/W 0 0 Fix at “0”. 1: + (16 − K) /16 divided enable 0 00: φT0 01: φT2 10: φT8 11: φT32 Set frequency divisor 0 to F BR2K3 BRADD2 Baud rate control BR2K2 BR2K1 BR2K0 0 0 R/W 2BH 0 0 Set frequency divisor 1 to F (“0” prohibited) Serial SC3BUF channel buffer 3CH RB7 TB7 RB6 TB6 RB3 TB3 RB2 TB2 RB1 RB1 RB0 TB0 Undefined EVEN R Serial channel 1 control RB4 TB4 R (Receiving) /W (Transmission) RB8 SC3CR RB5 TB5 3DH PE R/W OERR PERR FERR SCLKS R (Cleared to 0 by reading) Undefined 0 0 Receiving data bit8 Parity 0: Odd 1: Even 1: Parity enable 93CW46A-223 0 0 0 1: Error Overrun Parity Framing IOC R/W 0 0 0: SCLK3 1: Input SCLK3 pin 1: SCLK3 2004-02-10 TMP93CW46A (5) Serial channel (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 TB8 − RXE WU SM1 SM0 SC1 SC0 Undefined 0 0 0 0 0 0 0 R/W Serial SC3MOD channel mode BR3CR Baud rate control 3EH Transmission data bit8 3FH 1: CTS3 enable − BR3ADD R/W R/W 0 0 1: Receive 1: Wake enable up enable 00: I/O interface 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits BR3CK1 BR3CK0 BR3S3 0 0 0 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 11: SCLK input BR3S1 BR3S0 BR3S2 R/W Fix at “0”. 1: + (16 − K) /16 divided enable 0 00: φT0 01: φT2 10: φT8 11: φT32 0 0 Set frequency divisor 0 to F. BR3K3 BR3K2 BR3K1 BR3K0 0 0 R/W BRADD3 SC4BUF Baud rate control Serial channel buffer 0 3BH RB7 TB7 RB6 TB6 4DH RB4 TB4 1 to F (“0” prohibited) RB2 RB1 TB2 RB1 RB3 TB3 RB0 TB0 R (Receiving) /W (Transmission) EVEN R Serial channel control RB5 TB5 4CH RB8 SC4CR 0 Set “K” (N + (16 − k)/16 divided) Undefined Undefined OERR PERR PE R/W 0 Receiving Parity data bit 0: Odd 1: Even − TB8 FERR R (Cleared to 0 by reading) 0 0 0 0 1: Error 1: Parity enable Overrun Parity Framing RXE WU SM1 SM0 0 0 SC1 SC0 0 0 R/W Serial SC4MOD channel mode BR4CR Baud rate control Undefined 4EH Transmission data bit8 4FH 0 0 0 Fix at “0”. 1: Receive 1: Wake enable up enable − BR4ADD R/W R/W 0 0 Fix at “0”. 1: + (16 − K) /16 divided enable 00: Reserved 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits BR4CK1 BR4CK0 BR4S3 0 0 0 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 BR4S2 11: SCLK in BR4S1 BR4S0 R/W 0 00: φT0 01: φT2 10: φT8 11: φT32 0 0 Set frequency divisor 0 to F BR4K3 BR4K2 BR4K1 BR4K0 0 0 R/W BRADD4 Baud rate control 0 4BH 0 Set “K” (N + (16 − k)/16 divided) 1 to F (“0” prohibited) 93CW46A-224 2004-02-10 TMP93CW46A (6) AD converter control Symbol ADMOD1 Name AD mode register 1 Address 7 6 5 4 EOCF ADBF REPET SCAN 0 0 R 5EH 1: Busy VREFON ADMOD2 *1) AD REG04L AD REG04H *1) AD REG15L AD REG15H *1) AD REG26L AD REG26H *1) AD REG37L AD REG37H *1: AD mode register 2 AD result register 0/4 low AD result register 0/4 high AD result register 1/5 low AD result register 1/5 high AD result register 2/6 low AD result register 2/6 high AD result register 3/7 low AD result register 3/7 high 1 SPEED0 ADCH2 ADCH0 R/W 0 ADR01 ADCH1 1: Start R/W String Resistance Switch ON/OFF 0 0 1: Repeat 1: Scan SPEED1 1 R/W 0 R/W 5FH 2 ADS R/W 0 1: End 3 0 0 SPEED 0 0 Analog input channel select ADR00 R 60H Undefined ADR09 ADR08 1 1 ADR07 ADR06 1 1 1 1 ADR05 ADR04 ADR03 ADR02 1 1 1 1 ADR15 ADR14 ADR13 ADR12 1 1 1 1 ADR25 ADR24 ADR23 ADR22 1 1 1 1 ADR35 ADR34 ADR33 ADR32 R 61H Undefined ADR11 ADR10 R 62H Undefined ADR19 ADR18 1 1 ADR17 ADR16 R 63H Undefined ADR21 ADR20 R 64H Undefined ADR29 ADR28 1 1 ADR27 ADR26 R 65H Undefined ADR31 ADR30 R 66H Undefined ADR39 ADR38 1 1 ADR37 ADR36 R 67H Undefined Data to be stored in AD conversion result register low are the lower 2 bits of the conversion result. The contents of the lower 6 bits of this register are always read as “1”. MSB LSB 9 8 7 6 5 4 3 2 1 0 Converted data of channel “X” ADREGXH 7 6 5 4 3 2 1 0 ADREGXL 7 6 5 4 3 2 1 0 This is “1” when this is read. 93CW46A-225 2004-02-10 TMP93CW46A (7) Interrupt control (1/2) Symbol Name Address Interrupt enable 0 & AD INTE 0AD 70H (Prohibit RMW) Interrupt enable 4/5 INTE45 71H (Prohibit RMW) Interrupt enable 6/7 INTE67 72H (Prohibit RMW) Interrupt INTET10 enable timer 1/0 INTEPW 10 73H (Prohibit RMW) Interrupt enable PWM 1/0 74H (Prohibit RMW) Interrupt enable INTET54 T register 5/4 75H (Prohibit RMW) Interrupt enable INTET76 T register 7/6 76H (Prohibit RMW) INTES0 Interrupt enable serial 0 INTES1 Interrupt enable serial 1 INTES2 Interrupt enable serial 2 INTES3 Interrupt enable serial 3 INTES4 Interrupt enable serial 4 77H (Prohibit RMW) 78H (Prohibit RMW) 59H (Prohibit RMW) 5AH (Prohibit RMW) 5BH (Prohibit RMW) 7 6 IADC R/W 0 IADM2 I5C R/W 0 I7C R/W 0 IT1C R/W 0 IPW1C R/W 0 IT5C R/W 0 IT7C R/W 0 ITX0C R/W 0 ITX1C R/W 0 ITX2C R/W 0 ITX3C R/W 0 ITX4C R/W 0 IxxM2 IxxM1 IxxM0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 IxxC 0 1 5 4 IADM1 IADM0 W 0 0 0 INTAD I5M2 I5M1 I5M0 W 0 0 0 INT5 I7M2 I7M1 I7M0 W 0 0 0 INT7 IT1M2 IT1M1 IT1M0 W 0 0 0 INTT1 (Timer 1) IPW1M2 IPW1M1 IPW1M0 W 0 0 0 INTT3 (Timer 3/PWM1) IT5M2 IT5M1 IT5M0 W 0 0 0 INTTR5 (TREG5) IT7M2 IT7M1 IT7M0 W 0 0 0 INTTR7 (TREG7) ITX0M2 ITX0M1 ITX0M0 W 0 0 0 INTTX0 ITX1M2 ITX1M1 ITX1M0 W 0 0 0 INTTX1 ITX2M2 ITX2M1 ITX2M0 W 0 0 0 INTTX2 ITX3M2 ITX3M1 ITX3M0 W 0 0 0 INTTX3 ITX4M2 ITX4M1 ITX4M0 W 0 0 0 INTTX4 3 2 1 0 I0C R/W 0 I0M2 I0M1 W 0 I0M0 I4M1 W 0 I4M0 I6M1 W 0 I6M0 0 0 INT0 I4C R/W 0 I4M2 0 0 INT4 I6C R/W 0 I6M2 0 0 INT6 IT0C R/W 0 IPW0C R/W 0 IT4C R/W 0 IT6C R/W 0 IRX0C R/W 0 IRX1C R/W 0 IRX2C R/W 0 IRX3C R/W 0 IRX4C R/W 0 IT0M2 IT0M1 W 0 0 INTT0 (Timer 0) IPW0M2 IPW0M1 W 0 0 INTT2 (Timer 2/PWM0) IT4M2 IT4M1 W 0 0 INTTR4 (TREG4) IT6M2 IT6M1 W 0 0 INTTR6 (TREG6) IRX0M2 IRX0M1 W 0 0 INTRX0 IRX1M2 IRX1M1 W 0 0 INTRX1 IRX2M2 IRX2M1 W 0 0 INTRX2 IRX3M2 IRX3M1 W 0 0 INTRX3 IRX4M2 IRX4M1 W 0 0 INTRX4 IT0M0 0 IPW0M0 0 IT4M0 0 IT6M0 IRX0M0 0 IRX1M0 0 IRX2M0 0 IRX3M0 0 IRX4M0 0 Function (Write) Prohibit interrupt request. Set interrupt request level to “1”. Set interrupt request level to “2”. Set interrupt request level to “3”. Set interrupt request level to “4”. Set interrupt request level to “5”. Set interrupt request level to “6”. Prohibit interrupt request. Function (Read) Indicate no interrupt request. Indicate interrupt request. Function (Write) Clear interrupt request flag. − − − − − Don’t care − − − − − 93CW46A-226 2004-02-10 TMP93CW46A (7) Interrupt control (2/2) Symbol DMA0V Name DMA 0 request vector Address 7CH (Prohibit RMW) 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 0 0 0 DMA1V2 DMA1V1 DMA1V0 0 0 0 DMA2V2 DMA2V1 DMA2V0 0 0 0 DMA3V2 DMA3V1 DMA3V0 0 0 0 I0IE I0LE NMIREE W W W 0 0 W 0 0 0 Micro DMA0 start vector DMA1V5 DMA1V DMA 1 request vector 7DH (Prohibit RMW) DMA1V4 DMA1V3 W 0 0 DMA2V5 DMA2V4 0 Micro DMA1 start vector DMA2V DMA 2 request vector 7EH (Prohibit RMW) DMA2V3 W 0 0 0 Micro DMA2 start vector DMA3V DMA 3 request vector 7FH (Prohibit RMW) DMA3V5 DMA3V4 DMA3V3 0 0 0 W Micro DMA3 start vector IIMC Interrupt input mode control 7BH (Prohibit RMW) 1: INT0 input enable 93CW46A-227 0 0: INT0 edge mode 1: Operate even at 1: INT0 level mode rise edge NMI 2004-02-10 TMP93CW46A (8) Chip select/wait controller Symbol B0CS B1CS B2CS Note: Name Block 0 CS/WAIT control register Block 1 CS/WAIT control register Block 2 CS/WAIT control register Address 68H (Prohibit RMW) 69H (Prohibit RMW) 6AH (Prohibit RMW) 5 4 3 2 1 0 B0E 7 B0CAS B0BUS B0W1 B0W0 B0C1 B0C0 W W W W W W W 0 0 0 0 0 0 0 1: B0CS master bit 6 0: CS0 1: CAS0 0: 16-bit bus 1: 8-bit bus 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits 00: 7F00H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B1E B1CAS B1BUS B1W1 B1W0 B1C1 B1C0 W W W W W W W 0 0 0 0 0 0 0 1: B1CS master bit 0: 16-bit bus 1: 8-bit bus 0: CS1 1: CAS1 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits 00: 1080H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B2E B2CAS B2BUS B2W1 B2W0 B2C1 B2C0 W W W W W W W 1 0 0 0 0 0 0 1: B2CS master bit 0: CS2 1: CAS2 0: 16-bit bus 1: 8-bit bus 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits 00: 28000H to 01: 400000H to 10: 800000H to 11: C00000H to After reset, only “Block 2” is set to enable. 93CW46A-228 2004-02-10 TMP93CW46A (9) Clock control Symbol Name Address 7 6 5 4 3 2 1 0 SCOSEL SCOEN ALEEN CLKEN 0 0 R/W CKOCR Clock output control register 006DH XTEN RXEN RXTEN 0 CLK pin SCOUT select output control control 0: fFPH control 0: I/O port 0:High-Z output 0:High-Z output 1: SCOUT output 1: ALE output 1: CLK output 1: fSYS XEN 0 SCOUT RSYSCK ALE pin WUEF PRCK1 PRCK0 0 0 R/W 1 SYSCR0 System clock control register 0 0 1 0 0 Warm-up Low- High- Low- Select clock frequency frequency frequency frequency after released timer oscillator (fc) oscillator (fs) STOP mode (Write) oscillator (fc) oscillator (fs) 0: Stop 006EH 0 High- 0: Stop after released after released 0: fc 1: Oscillation 1: Oscillation STOP mode 0: Stop Select prescaler clock 00: fFPH 01: fs 10: fc/16 0: Don’t care STOP mode 1: fs 11: (Reserved) 1: Start timer 0: Stop 1: Oscillation 1: Oscillation (Read) 0: End warm up 1: Not end warm up SYSCK GEAR2 GEAR1 GEAR0 0 0 R/W 0 SYSCR1 System clock control register 1 006FH 1 Select Select gear value of high frequency (fc) system clock 000: fc 0: fc 001: fc/2 1: fs 010: fc/4 (Note 1) 011: fc/8 100: fc/16 101: Reserved) 110: (Reserved) 111: (Reserved) Note 1: The high-frequency oscillator will be enabled regardless the value of SYSCR0<XEN> when SYSCR1<SYSCK> is set to “0”. On the other hand, the low frequency oscillator will be enabled regardless the value of SYSCR0<XTEN> when SYSCR1<SYSCK> is set to “1”. Note 2: CKOCR<bit7:4> is read to “1”. 93CW46A-229 2004-02-10 TMP93CW46A 6. Port Section Equivalent Circuit Diagram • Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active “1” when the halt mode setting register is set to the STOP mode and the CPU executes the halt instruction. When the drive enable bit WDMOD<DRVE> is set to “1”, however, stop remains at “0”. • The input protection resistance ranges from several tens of ohms to several hundreds of ohms. ■ P0 (AD0 to AD7), P1 (AD8 to AD15, A8 to A15), P2 (A16 to A23, A0 to A7) VCC Output data P-ch Output enable STOP N-ch I/O Input data N-ch Input enable ■ Programmable pull-down resistor (Only PORT2) P30 ( RD ), P31 ( WR ) VCC Output data OUT STOP 93CW46A-230 2004-02-10 TMP93CW46A ■ P32 to P37, P40 to P41, P61 to P62, P64 to P65, P67, P7, P80 to P86, P91 to P92, P94 to P95, PA6 to PA7 VCC Output data VCC Output enable STOP Programmable pull-up resistor (Not exist in port A6, A7) I/O Input data Input enable ■ PA0 to PA5 Output data I/O Output enable STOP Input data Input enable ■ P42 ( CS2 and CAS2 ) VCC Output data Output enable Stop I/O Input data Programmable pull-down resistor Input enable 93CW46A-231 2004-02-10 TMP93CW46A ■ P5 (AN0 to AN7) Analog input channel select Analog input Input Input data Input enable ■ P87 (INT0) VCC Output data Output enable Stop VCC Input data I/O Schmitt Interrupt request ■ Programmable pull-up resistor P90 (TXD0), P93 (TXD1), P60 (TXD2), P63 (TXD3), P66 (TXD4) VCC Output data Open-drain enable VCC STOP Programmable pull-up resistor I/O Input data Input enable Note: P60, P63 and P66 have no open-drain function. 93CW46A-232 2004-02-10 TMP93CW46A ■ P96 (XT1) and P97 (XT2) Clock Input enable Oscillator Input data P97 (XT2) Output data Output enable Input enable Input data P96 (XT1) Ouput data Output enable STOP Low-frequency oscillation enable ■ NMI NMI Input Schmitt ■ WDTOUT WDTOUT ■ OUT CLK VCC Output enable VCC P-ch Internal CLK OUT STOP N-ch Internal reset Test circuit Input enable 93CW46A-233 2004-02-10 TMP93CW46A ■ EA Input ■ AM8/ AM16 Input ■ ALE VCC Internal ALE P-ch OUT N-ch Output enable ■ RESET VCC Input Internal reset Schmitt WDTOUT Reset enable ■ X1, X2 Clock Oscillator X2 P-ch N-ch High-frequency oscillation enable X1 93CW46A-234 2004-02-10 TMP93CW46A ■ VREFH, VREFL VREFON P-ch VREFH String resistance VREFL 93CW46A-235 2004-02-10 TMP93CW46A 7. Points of Note and Restrictions (1) Special expression 1. Explanation of a built-in I/O register: Register symbol<Bit symbol> Example: TRUN<T0RUN> … Bit T0RUN of register TRUN 2. Read, modify and write instruction An instruction which CPU reads data from memory and writes the data to the same memory location by one instruction. Example 1: SET 3, (TRUN) … Set bit3 of TRUN Example 2: INC 1, (100H) … Increment the data of 100H • The representative read-modify-write instructions in the TLCS-900 Exchange instruction EX (mem), R Arithmetic operation ADD (mem), R/# SUB (mem), R/# INC #3, (mem) Logic operation AND (mem), R/# XOR (mem), R/# Bit manipulation STCF #3/A, (mem) SET #3, (mem) TSET #3, (mem) Rotate, Shift RLC (mem) RL (mem) SLA (mem) SLL (mem) RLD (mem) 3. fc, fFPH, fSYS, ADC SBC DEC (mem), R/# (mem), R/# #3, (mem) OR (mem), R/# RES CHG #3, (mem) #3, (mem) RRC RR SRA SRL RRD (mem) (mem) (mem) (mem) (mem) 1 state The clock frequency input from X1, X2 pins is called fc, and the clock selected by SYSCR1<SYSCK> is called fFPH, and fFPH divided by 2 clock frequency is called fSYS. One cycle of fSYS is called 1 state. 93CW46A-236 2004-02-10 TMP93CW46A (2) Care points 1. EA , AM8/ AM16 pin Fix these pins to VCC or GND unless changing voltage. 2. TEST1, TEST2 pin Connect the TEST1 pin with the TEST2 pin. 3. Reserved area in memory space The 256 bytes of memory area between FFFF00H to FFFFFFH can not be used because they are reserved. 4. Standby mode (IDLE1) When the IDLE1 mode (Operates only oscillator) is used, set TRUN<PRRUN> to “0” to stop prescaler before “HALT” instruction is executed. 5. Warm-up counter The warm-up counter operates when the STOP mode is released even if the system uses an external oscillator. As a result, it takes the warm-up time from inputting the releasing request to outputting the system clock. 6. Micro DMA (DRAM refresh mode) When the bus is released ( BUSAK = “0”). DRAM refresh cannot be performed because of the micro DMA cannot access the bus. 7. Programmable pull-up/pull-down resistance The programmable pull-up/pull-down resistors can be selected ON/OFF by the program when the ports are used as the input ports. In case where the ports are used as outputs, they can not be selected ON/OFF by program. The data registers (e.g., P2, P3 ...) are used for selecting ON/OFF of pull-up/pull-down resistors. As a result, read-modify-write instructions are prohibited. 8. Bus releasing function Refer to the note about the bus release in 3.5 “Functions of Ports” because the pin state, when the bus is released, is written. 9. Watchdog timer The watchdog timer starts operation immediately after the reset is released. When the watchdog timer is not used, disable watchdog timer. 10. Watchdog timer When the bus is released, both internal memory and internal I/O can not be accessed. But the internal I/O continues to operate. So, the watchdog timer continues to run. Therefore, be careful about the bus releasing time and set the detection timer of watchdog timer. 11. AD converter The ladder resistor between VREFH and VREFL pins can be cut by program to reduce the power consumption. When the standby mode is used, disable in the program before the “HALT” instruction is executed. And set ADMOD2<SPEED1:0> = “00”. 12. CPU (Micro DMA) Only the “LDC cr, r”, “LDC r, cr” instruction can be used to access the control registers like transfer source address register (DMASn) in the CPU. 13. POP SR instruction Please execute POP SR instruction during DI condition. 93CW46A-237 2004-02-10 TMP93CW46A 14. Pin states in STOP mode Open-drain output state. Input gate in operation. Set output to “L” or attach pull up on pin so that the input gate stays constant. 15. Releasing the HALT mode by requesting an interruption Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. 93CW46A-238 2004-02-10 TMP93CW46A 8. Package Dimensions P-LQFP100-1414-0.50F Unit: mm 93CW46A-239 2004-02-10 TMP93CW46A 93CW46A-240 2004-02-10