19-0736; Rev 0; 1/07 2:1 Multiplexer and 1:2 Demultiplexer with Loopback Features The MAX9396 consists of a 2:1 multiplexer and a 1:2 demultiplexer with loopback. The multiplexer section (channel B) accepts two differential inputs and generates a single differential output. The demultiplexer section (channel A) accepts a single differential input and generates two parallel differential outputs. The MAX9396 features a loopback mode that connects the input of channel A to the output of channel B and connects the selected input of channel B to the outputs of channel A. The differential inputs of the MAX9396 accept CML/LVPECL levels and can also accept LVDS inputs with common-mode voltages from +0.6V to (V CC 0.05V). The differential outputs are LVDS compatible and drive 100Ω loads. Three LVCMOS/LVTTL logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel B (BSEL), and the other two for loopback control of channels A and B (LB_SELA and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility. Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the commonmode voltage is below +0.6V. Ultra-low 57psP-P (typ) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in highspeed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees 1.25Gbps operation and less than 87ps (max) skew between channels. The MAX9396 is available in a 32-pin TQFP package and is specified over the -40°C to +85°C extended temperature range. ♦ Guaranteed 1.25Gbps Operation with 450mV (min) Differential Output Swing ♦ Integrated 100Ω Resistors on Differential Inputs ♦ Simultaneous Loopback Control ♦ 2ps(RMS) (max) Random Jitter ♦ AC Specifications Guaranteed for 150mV Differential Input ♦ Signal Inputs Accept Any Differential Signals with VCM = +0.6V to (VCC - 0.05V) ♦ LVDS Outputs for Clock or High-Speed Data ♦ Low-Level Input Fail-Safe Detection ♦ +3.0V to +3.6V Supply Voltage Range ♦ LVCMOS/LVTTL Logic Inputs Ordering Information PART TEMP RANGE MAX9396EHJ+ -40°C to +85°C PKG CODE 32 TQFP H32-1 +Denotes a lead-free package. Typical Operating Circuit +3.0V TO +3.6V 0.1µF 0.01µF Z0 = 50Ω INA OUTA0 Z0 = 50Ω Z0 = 50Ω INA OUTA0 Z0 = 50Ω OUTA1 Z0 = 50Ω OUTA1 Z0 = 50Ω OUTB Z0 = 50Ω OUTB Z0 = 50Ω VCC 100Ω Applications MAX9396 INB0 High-Speed Telecom/Datacom Equipment LVDS RECEIVER INB0 INB1 Central Office Backplane Clock Distribution INB1 DSLAMs ENA0 Protection Switching Fault-Tolerant Systems PINPACKAGE ENA1 ENB LVCMOS/LVTTL LOGIC INPUTS LB_SELA LB_SELB BSEL GND GND GND GND Pin Configuration and Functional Diagram appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9396 General Description MAX9396 2:1 Multiplexer and 1:2 Demultiplexer with Loopback ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.1V IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, BSEL, LB_SEL_ to GND....................................................-0.3V to (VCC + 0.3V) IN_ _ to IN_ _..........................................................................±3V Short-Circuit Duration (OUT_ _, OUT_ _) ...................Continuous Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 13.1mW/°C above +70°C)........1047mW Junction-to-Ambient Thermal Resistance in Still Air 32-Pin TQFP............................................................+76.4°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection (Human Body Model) (IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, BSEL, LB_SEL_)..±2kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, EN_ _ = VCC, VCM = +0.6V to (VCC - 0.05V), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25°C.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V LVCMOS/LVTTL INPUTS (EN_ _, BSEL, LB_SEL_) Input High Voltage VIH 2.0 VCC Input Low Voltage VIL 0 0.8 V Input High Current IIH VIN = +2.0V to VCC 0 20 µA Input Low Current IIL VIN = 0V to +0.8V -1 +10 µA VID VILD > 0V and VIHD < VCC, Figure 1 0.1 3.0 V 0.6 VCC 0.05 V |VID| ≤ 3.0V (VIN = 0V to +VCC, IN_ _, or IN_ _ open) -15 +200 µA RIN IN_ _ to IN_ _ 80 100 120 Ω VOD RL = 100Ω, Figure 2 450 540 600 mV 50 mV 1.6 V 50 mV DIFFERENTIAL INPUTS (IN_ _, IN_ _) Differential Input Voltage Input Common-Mode Range VCM Single-Ended Input Current IIN_ _, IIN_ _ Differential Input Termination LVDS OUTPUTS (OUT_ _, OUT_ _) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Common-Mode Voltage Change in Magnitude of VOS Between Complementary Output States 2 ∆VOD Figure 2 VOS Figure 2 ∆VOS Figure 2 1.4 1.5 _______________________________________________________________________________________ 2:1 Multiplexer and 1:2 Demultiplexer with Loopback (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, EN_ _ = VCC, VCM = +0.6V to (VCC - 0.05V), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25°C.) (Notes 1, 2, and 3) PARAMETER SYMBOL Output Short-Circuit Current (Output(s) Shorted to GND) |IOS| Output Short-Circuit Current (Outputs Shorted Together) |IOSB| CONDITIONS VID = ±100mV (Note 4) MIN TYP MAX VOUT_ _ or V OUT_ _ = 0V 28 40 VOUT_ _ = V OUT_ _ = 0V 17 24 UNITS mA VID = ±100mV, VOUT_ _ = V OUT_ _ (Note 4) 12 mA SUPPLY CURRENT Supply Current ICC RL = 100Ω, EN_ _ = VCC 56 75 RL = 100Ω, EN_ _ = VCC, switching at 625MHz (1.25Gbps) 56 75 mA AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, fIN ≤ 625MHz, tR_IN = tF_IN = 125ps, RL = 100Ω ±1%, |VID| ≥ 150mV, VCM = +0.6V to (VCC - 0.075V), EN_ _ = VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, fIN = 625MHz, TA = +25°C.) (Note 5) PARAMETER SYMBOL SEL to Switched Output tSWITCH Disable Time to Differential Output Low MAX UNITS Figure 3 1.1 ns tPHD Figure 4 1.7 ns Enable Time to Differential Output High tPDH Figure 4 1.7 ns Data Rate fDR VOD > 450mV, 223 - 1 PRBS 1.25 Low-to-High Propagation Delay tPLH Figures 1, 5 250 340 630 ps High-to-Low Propagation Delay tPHL Figures 1, 5 250 355 630 ps Pulse Skew |tPLH – tPHL| Output Channel-to-Channel Skew tSKEW tCCS CONDITIONS MIN Figures 1, 5 (Note 6) TYP Gbps 18 Figure 6 (Note 7) 86 ps 87 ps Output Low-to-High Transition Time (20% to 80%) tR fIN_ _ = 100MHz, Figures 1, 5 170 220 350 ps Output High-to-Low Transition Time (80% to 20%) tF fIN_ _ = 100MHz, Figures 1, 5 170 210 350 ps Added Random Jitter tRJ fIN_ _ = 625MHz, clock pattern (Note 8) 0.45 2 ps(RMS) Added Deterministic Jitter tDJ 1.25Gbps, 223 - 1 PRBS (Note 8) 57 120 psP-P Measurements obtained with the device in thermal equilibrium. All voltages referenced to GND except VID, VOD, and ∆VOD. Current into the device defined as positive. Current out of the device defined as negative. DC parameters are production tested at TA = +25°C and guaranteed by design and characterization for TA = -40°C to +85°C. Current through either output. Guaranteed by design and characterization. Limits set at ±6 sigma. tSKEW is the magnitude difference of differential propagation delays for the same output over the same condtions. tSKEW = |tPHL - tPLH|. Note 7: Measured between outputs of the same device at the signal crossing points for a same-edge transition under the same conditions. Does not apply to loopback mode. Note 8: Device jitter added to the differential input signal. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: _______________________________________________________________________________________ 3 MAX9396 DC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25°C, fIN = 6.25MHz, Figure 5.) VCC = +3.3V 55 50 VCC = +3V 500 fIN = 100MHz 330 RISE/FALL TIME (ps) VCC = +3.6V 60 400 300 200 MAX9396 toc03 600 OUTPUT AMPLITUDE (mV) 65 360 MAX9396 toc02 700 MAX9396 toc01 70 OUTPUT RISE/FALL TIME vs. TEMPERATURE OUTPUT AMPLITUDE vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) 300 270 240 45 100 210 40 0 180 tR tF -40 -15 -10 35 0.2 0 85 60 0.4 0.6 0.8 -15 140 120 INPUT CURRENT (µA) 430 405 tPHL 355 tPLH 330 VIN_ _ = VCC 100 80 60 40 20 305 35 MAX9396 toc05 455 10 SINGLE-ENDED INPUT CURRENT vs. TEMPERATURE MAX9396 toc04 480 VIN_ _ = 0V 0 280 -20 -40 -15 10 35 TEMPERATURE (°C) 4 -40 TEMPERATURE (°C) PROPAGATION DELAY vs. TEMPERATURE 380 1.0 FREQUENCY (GHz) TEMPERATURE (°C) PROPAGATION DELAY (ps) MAX9396 2:1 Multiplexer and 1:2 Demultiplexer with Loopback 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 2:1 Multiplexer and 1:2 Demultiplexer with Loopback PIN NAME FUNCTION 1, 2, 3, 30, 31, 32 N.C. No Connection. Not internally connected. 4, 9, 20, 25 GND Ground 5 ENB Channel B Output Enable. Drive ENB high to enable the LVDS outputs for channel B. An internal 435kΩ resistor to GND pulls ENB low when unconnected. 6 OUTB Channel B LVDS Noninverting Output 7 OUTB Channel B LVDS Inverting Output 8, 13, 24, 29 VCC Power-Supply Input. Bypass each VCC to GND with a 0.1µF and 0.01µF ceramic capacitor. Install both bypass capacitors as close as possible to the device, with the 0.01µF capacitor closest to the device. 10 INB0 LVPECL/CML Inverting Input. An internal 68kΩ resistor to GND pulls the input low when unconnected. 11 INB0 LVPECL/CML Noninverting Input. An internal 68kΩ resistor to GND pulls the input low when unconnected. 12 LB_SELB Loopback Select for Channel B Output. Connect LB_SELB to GND or leave unconnected to reproduce the INB_ (INB_) differential inputs at OUTB (OUTB). Connect LB_SELB to VCC to loop back the INA (INA) differential inputs to OUTB (OUTB). An internal 435kΩ resistor to GND pulls LB_SELB low when unconnected. 14 INB1 LVPECL/CML Inverting Input. An internal 68kΩ resistor to GND pulls the input low when unconnected. 15 INB1 LVPECL/CML Noninverting Input. An internal 68kΩ resistor to GND pulls the input low when unconnected. 16 BSEL Channel B Multiplexer Control Input. Selects the differential input to reproduce at the B channel differential output. Connect BSEL to GND or leave unconnected to select the INB0 (INB0) set of inputs. Connect BSEL to VCC to select the INB1 (INB1) set of inputs. An internal 435kΩ resistor to GND pulls BSEL low when unconnected. 17 ENA1 Channel A1 Output Enable. Drive ENA1 high to enable the A1 LVDS outputs. An internal 435kΩ resistor to GND pulls the ENA1 low when unconnected. 18 OUTA1 Channel A1 LVDS Inverting Output 19 OUTA1 Channel A1 LVDS Noninverting Output _______________________________________________________________________________________ 5 MAX9396 Pin Description 2:1 Multiplexer and 1:2 Demultiplexer with Loopback MAX9396 Pin Description (continued) PIN NAME 21 ENA0 FUNCTION Channel A0 Output Enable. Drive ENA0 high to enable the A0 LVDS outputs. An internal 435kΩ resistor to GND pulls ENA0 low when unconnected. 22 OUTA0 Channel A0 LVDS Inverting Output 23 OUTA0 Channel A0 LVDS Noninverting Output 26 INA LVPECL/CML Noninverting Input. An internal 68kΩ resistor to GND pulls the input low when unconnected. 27 INA LVPECL/CML Inverting Input. An internal 68kΩ resistor to GND pulls the input low when unconnected. LB_SELA Loopback Select for Channel A Output. Connect LB_SELA to GND or leave unconnected to reproduce the INA (INA) differential inputs at OUTA_ (OUTA_). Connect LB_SELA to VCC to loop back the INB_ (INB_) differential inputs to OUTA_ (OUTA_). An internal 435kΩ resistor to GND pulls LB_SELA low when unconnected. 28 Detailed Description The MAX9396 high-speed, low-power 2:1 multiplexer and 1:2 demultiplexer with loopback provides signal redundancy switching in telecom and storage applications. This device selects one of two remote signal sources for local input and buffers a single local output signal to two remote receivers. The multiplexer section (channel B) accepts two differential inputs and generates a single LVDS-compatible output. The demultiplexer section (channel A) accepts a single differential input and generates two parallel LVDScompatible outputs. The MAX9396 features a loopback mode that connects the input of channel A to the output of channel B and connects the selected input of channel B to the outputs of channel A. LB_SELA and LB_SELB provide independent loopback control for each channel. Three LVCMOS/LVTTL logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel B (BSEL), and the other two for loopback control of channels A and B (LB_SELA and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility. 6 Input Fail-Safe The differential inputs of the MAX9396 possess internal fail-safe protection. Fail-safe circuitry forces the outputs to a differential-low condition for undriven inputs or when the common-mode voltage is below +0.6V. The MAX9396 provides low-level input fail-safe detection for LVPECL, CML, and other VCC-referenced differential inputs. Select Function BSEL selects the differential input pair to transmit through OUTB (OUTB) for LB_SELB = GND or through OUTA_ (OUTA_) for LB_SELA = VCC. LB_SEL_ controls the loopback function for each channel. Connect LB_SEL_ to GND to select the normal inputs for each channel. Connect LB_SEL_ to VCC to enable the loopback function. The loopback function routes the input of channel A to the output of channel B, and the inputs of channel B to the outputs of channel A. See Tables 1 and 2 for a summary of the input/output routing between channels. _______________________________________________________________________________________ 2:1 Multiplexer and 1:2 Demultiplexer with Loopback VIN_ _ VIHD VID = 0V VID = 0V tPLH tPHL VIN_ _ VILD VOUT_ _ Applications Information Differential Inputs VOD = 0V The MAX9396 inputs accept any differential signaling standard within the specified common-mode voltage range. The fail-safe feature detects common-mode input signal levels and generates a differential output low condition for undriven inputs or when the commonmode voltage is below +0.6V. Leave unused inputs unconnected or connect to GND. 80% VOD = 0V 50% Differential Traces Input and output trace characteristics affect the performance of the MAX9396. Connect each input and output to a 50Ω characteristic impedance trace. Maintain the distance between differential traces and eliminate sharp corners to avoid discontinuities in differential impedance and maximize common-mode noise immunity. Minimize the number of vias on the differential input and output traces to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces. Output Termination Terminate the transmission line with a 100Ω resistor at the receiver inputs for proper operation. Ensure that the output currents do not exceed the current limits specified in the Absolute Maximum Ratings. Observe the total thermal limits of the MAX9396 under all operating conditions. Cables and Connectors Use matched differential impedance for transmission media. Use cables and connectors with matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables. 80% VOD = 0V 50% 20% 20% tR Power-Supply Bypassing Bypass each VCC to GND with high-frequency surfacemount ceramic 0.1µF and 0.01µF capacitors in parallel as close as possible to the device. Install the 0.01µF capacitor closest to the device. VOD = 0V VOUT_ _ tF VID = VIN_ _ - VIN_ _ VOD = VOUT_ _ - VOUT_ _ Figure 1. Output Transition Time and Propagation Delay Timing Diagram OUT_ _ MAX9396 VOD 22kΩ RL/2 IN_ _ 100Ω VOS IN_ _ 22kΩ RL/2 OUT_ _ EN_ _ = HIGH VID = VIN_ _ - VIN_ _ ∆VOD = ⎪VOD - VOD*⎪ RL = 100Ω ±1% ∆VOS = ⎪VOS - VOS*⎪ VOD AND VOS ARE MEASURED WITH VID = +100mV. VOD* AND VOS* ARE MEASURED WITH VID = -100mV. Figure 2. Test Circuit for VOD and VOS Balanced cables, such as twisted pair, offer superior signal quality and tend to generate less EMI due to canceling effects. _______________________________________________________________________________________ 7 MAX9396 Enable Function The EN_ _ logic inputs enable and disable each set of differential outputs. For example, connect ENA0 to VCC to enable the OUTA0/OUTA0 differential output pair or connect ENA0 to GND to disable the OUTA0/OUTA0 differential output pair. The differential output pairs assert to a differential low condition when disabled. MAX9396 2:1 Multiplexer and 1:2 Demultiplexer with Loopback VIHD INB0 VID = 0V VILD INB0 VIHD INB1 VID = 0V VILD INB1 VIH 1.5V 1.5V VIL BSEL OUT_ _ VOD = 0V INB0 INB1 INB0 VOD = 0V OUT_ _ tSWITCH tSWITCH EN_0 = EN_1 = HIGH VID = VIN_ _ - VIN_ _ Figure 3. Input to Rising/Falling Edge Select and Mux Switch Timing Diagram MAX9396 OUT_ _ 22kΩ CL RL/2 IN_ _ 100Ω +1.25V RL/2 IN_ _ 22kΩ RL = 100Ω ±1% OUT_ _ CL = 1.0pF CL EN_ _ PULSE GENERATOR 50Ω VEN_ _ 1.5V 3V 1.5V 0V tPHD VOUT_ _ WHEN VID = +100mV VOUT_ _ WHEN VID = -100mV VOUT_ _ WHEN VID = -100mV VOUT_ _ WHEN VID = +100mV tPDH 50% 50% 50% 50% tPHD tPDH VID = VIN_ _ - VIN_ _ Figure 4. Output Active-to-Disable and Disable-to-Active Test Circuit and Timing Diagram 8 _______________________________________________________________________________________ 2:1 Multiplexer and 1:2 Demultiplexer with Loopback MAX9396 Table 1. Input Select Truth Table LOGIC INPUTS DIFFERENTIAL OUTPUTS LB_SELA LB_SELB BSEL OUTA_ / OUTA_ OUTB / OUTB 0 0 0 INA selected INB0 selected 0 0 1 INA selected INB1 selected 0 1 X INA selected INA selected 1 0 0 INB0 selected INB0 selected 1 0 1 INB1 selected INB1 selected 1 1 0 INB0 selected INA selected 1 1 INB1 selected INA selected 1 X = Don’t care. LB_SELA INA MAX9396 PULSE GENERATOR CL 22kΩ OUTA0 0 100Ω INA RL LB 22kΩ OUTA0 CL FROM CHANNEL B CL 22kΩ OUTA1 RL 22kΩ OUTA1 CL RL = 100Ω ±1% CL = 1.0pF ENA0 = ENA1 = HIGH 1 CHANNEL SHOWN. Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit PCB Layout Use a four-layer PCB providing separate signal, power, and ground planes for high-speed signaling applications. Bypass VCC to GND as close as possible to the device. Install termination resistors as close as possible to the receiver inputs. Match the electrical length of the differential traces to minimize signal skew. Table 2. Loopback Select Truth Table LB_SEL_ OUT_ _ GND or open Normal inputs selected. VCC Loopback inputs selected. _______________________________________________________________________________________ 9 MAX9396 2:1 Multiplexer and 1:2 Demultiplexer with Loopback VOUTA0 VOD = 0V VOD = 0V tCCS tCCS VOUTA0 VOUTA1 VOD = 0V VOD = 0V VOUTA1 VOD = VOUT_ _ - VOUT_ _ Figure 6. Output Channel-to-Channel Skew Functional Diagram LB_SELA ENA0 MAX9396 OUTA0 INA OUTA0 100Ω 0 22kΩ INA 22kΩ LB 22kΩ OUTA1 OUTA1 ENA1 22kΩ LB_SELB INB0 22kΩ LB OUTB 0 100Ω INB0 OUTB ENB 0 INB1 22kΩ 1 100Ω INB1 BSEL 10 ______________________________________________________________________________________ 2:1 Multiplexer and 1:2 Demultiplexer with Loopback Chip Information PROCESS: BiCMOS N.C. N.C. N.C. VCC LB_SELA INA INA GND TOP VIEW 32 31 30 29 28 27 26 25 + N.C. 1 24 VCC N.C. 2 23 OUTA0 N.C. 3 22 OUTA0 21 ENA0 GND 4 MAX9396 ENB 5 20 GND OUTB 6 19 OUTA1 OUTB 7 18 OUTA1 VCC 8 14 15 16 BSEL INB0 13 INB1 INB0 12 INB1 11 VCC 10 LB_SELB 9 GND 17 ENA1 TQFP ______________________________________________________________________________________ 11 MAX9396 Pin Configuration Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32L TQFP, 5x5x01.0.EPS MAX9396 2:1 Multiplexer and 1:2 Demultiplexer with Loopback PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm 21-0110 12 ______________________________________________________________________________________ B 1 2 2:1 Multiplexer and 1:2 Demultiplexer with Loopback PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm 21-0110 B 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX9396 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)