P4C174 HIGH SPEED 8K x 8 CACHE TAG STATIC RAM FEATURES High Speed Address-To-Match - 8 ns Maximum Access Time Data Retention at 2V for Battery Backup Operation High-Speed Read-Access Time Advanced CMOS Technology – 8/10/12/15/20/25 ns (Commercial) – 15/20/25 ns (Military) Low Power Operation Package Styles Available — 28 Pin 300 mil DIP — 28 Pin 300 mil Plastic SOJ Open Drain MATCH Output Reset Function Single Power Supply — 5V±10% 8-Bit Tag Comparison Logic Automatic Powerdown During Long Cycles DESCRIPTION the addressed memory location. 8K Cache lines can be mapped into 1M-Byte address spaces by comparing 20 address bits organized as 13-line address bits and 7page address bits. The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8. The CMOS memory has equal access and cycle times. Inputs are fully TTL-compatible. The cache tag RAMs operate from a single 5V±10% power supply. An 8-bit data comparator with a MATCH output is included for use as an address tag comparator in high speed cache applications. The reset function provides the capability to reset all memory locations to a LOW level. Low power operation of the P4C174 is enhanced by automatic powerdown when the memory is deselected or during long cycle times. Also, data retention is maintained down to VCC = 2.0. Typical battery backup applications consume only 30 µW at VCC = 3.0V. The MATCH output of the P4C174 reflects the comparison result between the 8-bit data on the I/O pins and PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM DIP (C5, P5), SOJ (J5) Document # SRAM118 REV C 1 Revised August 2006 P4C174 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C Symbol RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Grade(2) Ambient Temperature GND VCC Commercial 0°C to +70°C 0V 5.0V ± 10% CIN Input Capacitance Commercial 0°C to +70°C 0V 5.0V ± 10% COUT Output Capacitance Symbol Parameter Conditions Typ. Unit VIN = 0V 5 pF VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C174 Min Max Test Conditions Unit VIH Input High Voltage 2.2 VCC +0.5 V VIL Input Low Voltage –0.5(3) 0.8 V VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD VOL VOH ILI ILO VCC –0.2 VCC +0.5 0.2 V Input Clamp Diode Voltage VCC = Min., IIN = 18 mA –1.2 V Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current 0.4 V Output Leakage Current –0.5(3) V IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. 2.4 V VCC = Max. Com’l. Mil. –5 -10 +5 +10 µA VIN = GND to VCC VCC = Max., CE = VIH, Com’l. –5 +5 µA VOUT = GND to VCC Mil. -10 ___ ___ +10 25 40 mA Com’l. ___ 5 mA Mil. ___ 25 ISB CE ≥ VIH Com’l. Standby Power Supply Mil. Current (TTL Input Levels) VCC = Max ., f = Max., Outputs Open ISB1 Standby Power Supply Current (CMOS Input Levels) CE ≥ VHC VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Document # SRAM118 REV C 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 12 P4C174 DATA RETENTION CHARACTERISTICS (P4C174 Military Temperature Only) Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Test Conditons Min Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V V 2.0 10 CE ≥ VCC –0.2V, 15 600 900 µA 0 ns tRC§ ns VIN ≥ VCC –0.2V or VIN ≤ 0.2V Unit *TA = +25¹C §tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current* Temperature Range Commercial Military –8 –10 –12 200 180 170 –15 170 –20 –25 Unit 155 150 mA 160 155 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. Document # SRAM118 REV C Page 3 of 12 P4C174 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter –8 –12 –10 Min Max 8 Min Max Min 10 –15 Max Min Max Min Max Min Max 20 25 Unit ns Read Cycle Time tAA Address Access Time tOH Address Change to Output Change tAC Chip Enable LOW to Output Valid tLZ Chip Enable LOW to Output LOW-Z (1) tHZ Chip Enable HIGH to Output HIGH -Z (1) 5 5 5 8 8 10 ns tOE Output Enable LOW to Output Valid 5 6 6 8 10 12 ns tOLZ Output Enable LOW to Output LOW-Z (1) tOHZ Output Enable HIGH to Output HIGH -Z (1) tPU Chip Enable LOW or Address Change to Powerup tpUPD Powerup to Powerdown 3 10 3 8 3 10 5 20 12 5 20 15 5 20 5 20 ns 10 0 20 ns ns 0 0 20 25 8 ns ns 3 0 0 25 3 3 0 0 20 3 3 0 0 15 3 3 0 0 12 3 3 0 15 –25 tRC 8 12 –20 ns ns 25 ns Note: 1. Transition is measured ± 200 mV from steady state voltage with Output Load B. OE CONTROLLED)(2, 3) READ CYCLE NO. 1 (OE Document # SRAM118 REV C Page 4 of 12 P4C174 READ CYCLE NO. 2 (ADDRESS CONTROLLED)(2) CE CONTROLLED)(2, 3) READ CYCLE NO. 3 (CE Notes: 1. Transition is measured ±200 mV from steady state voltage with Output Load B. This parameter is sampled, not 100% tested. 2. CE is LOW, OE is LOW, WE is HIGH for READ cycle. CE or WE must be HIGH during address transitions. 3. All address lines are valid no later than the transition of CE to LOW. 4. READ cycle time is measured from the last valid address to the first transitioning address. 5. Powerup occurs as a result of any of the following conditions: a) Falling edge of CE. b) Falling edge of WE (CE active). c) Any address line transition (CE active). d) Any Data line transition (CE and WE active). This device automatically powers down after TPUPD has elapsed from any of the prior conditions. Power dissipation is therefore a function of cycle rate, not CE pulse width. Document # SRAM118 REV C 6. CE is LOW, WE is LOW for WRITE cycle. CE or WE must be HIGH during address transitions. 7. WRITE cycle time is measured from the last valid address to the first transitioning address. 8. OE is LOW for this WRITE cycle to show TWZ and TOW. Page 5 of 12 P4C174 AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, 0°C to +70°C) Symbol Parameter –8 –10 –12 –15 –20 –25 Min Max Min Max Min Max Min Max Min Max Min Max Unit tWC Write Cycle Time 8 10 12 15 20 20 ns tCW Chip Enable LOW to End of Write Address Valid to Beginning of Write Address Valid to End of Write End of Write to Address Change 7 9 10 12 15 15 ns 0 0 0 0 0 0 ns 7 9 10 12 15 15 ns 0 0 0 0 0 0 ns tWP Write Pulse Width 7 9 10 12 15 15 ns tDW Data Valid to End of Write 6 6 6 7 10 10 ns tDH End of Write to Data Change 0 0 0 0 0 0 ns tOW Write Enable HIGH to Output LOW-Z (1) Write Enable LOW to Output HIGH-Z (1) 0 0 0 0 0 0 ns tAS tAW tAH tWZ 4 4 4 5 7 7 ns WE CONTROLLED)(6) WRITE CYCLE NO. 1 (WE CE CONTROLLED)(6) WRITE CYCLE NO. 2 (CE Document # SRAM118 REV C Page 6 of 12 P4C174 AC CHARACTERISTICS - MATCH CYCLE (VCC = 5.0V ± 10%, 0°C to +70°C) Symbol Parameter tMC Match Cycle Time tADM Address Valid to MATCH Valid Address Change to MATCH Change Chip Enable LOW to MATCH Valid Chip Enable HIGH to MATCH HIGH tADMH tCEM tCEMHI tOEMHI tWEMHI –8 Data Valid to MATCH Valid tDAMH Data Change to MATCH Change –12 –15 –20 –25 Min Max Min Max Min Max Min Max Min Max Min Max 8 10 8 3 Output Enable LOW to MATCH HIGH Write Enable LOW to MATCH HIGH tDAM –10 0 12 10 3 15 12 3 20 15 3 25 20 3 Unit ns 25 3 ns ns 7 8 8 10 10 15 ns 7 8 8 10 10 15 ns 7 9 10 12 15 20 ns 7 9 10 12 15 20 ns 7 9 10 13 15 15 ns 0 0 0 0 0 ns MATCH TIMING Document # SRAM118 REV C Page 7 of 12 P4C174 AC CHARACTERISTICS - RESET CYCLE (VCC = 5.0V ± 10%, 0°C to +70°C) –8 Parameter Symbol –10 –12 –15 –20 –25 Min Max Min Max Min Max Min Max Min Max Min Max Unit tRRC Reset Cycle Time 35 40 45 50 50 60 ns tRP Reset Pulse Width 8 10 12 12 15 15 ns tRPU Reset LOW to Powerup 0 0 0 0 0 0 ns tRPD Reset LOW to Powerdown tRMHI Reset LOW to MATCH HIGH 0 tRIX Reset LOW to Inputs Ignored Reset LOW to inputs Recognized 0 Powerup to RESET LOW 8 tRIR tPUR 35 8 40 0 10 0 35 45 0 0 40 10 10 50 0 12 0 0 45 12 50 15 0 0 50 20 ns 20 ns ns 0 50 15 60 60 25 ns ns RESET TIMING AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Mode CE WE Output Power Input Rise and Fall Times < 3ns Standby H X High Z Standby Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L High Z Active Output Load Document # SRAM118 REV C Outputs Loads A, B & C Page 8 of 12 P4C174 OUTPUT LOAD A OUTPUT LOAD B OUTPUT LOAD C ORDERING INFORMATION SELECTION GUIDE The P4C174 is available in the following temperature, speed and package options. Temperature Range Commercial Miliitary Temperature Military Processed* Package Speed 8 10 12 15 20 25 Plastic DIP -8PC -10PC -15PC -15PC -20PC -25PC Plastic SOJ Side Brazed DIP -8JC N/A -10JC N/A -15JC N/A -15JC -15CM -20JC -20CM -25JC -25CM Side Brazed DIP N/A N/A N/A -15CMB -20CMB -25CMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM118 REV C Page 9 of 12 P4C174 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q C5 SIDE BRAZED DUAL IN-LINE PACKAGE 28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - J5 SOJ SMALL OUTLINE IC PACKAGE 28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - Document # SRAM118 REV C Page 10 of 12 P4C174 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P5 PLASTIC DUAL IN-LINE PACKAGE 28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0° 15° Document # SRAM118 REV C Page 11 of 12 P4C174 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM118 P4C174 HIGH SPEED 8Kx8 CACHE TAG STATIC RAM REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid B Nov-05 JDB Corrected error in Selection Guide C Aug-06 JDB Updated SOJ package information Document # SRAM118 REV C DESCRIPTION OF CHANGE Page 12 of 12