CXA1786N 1.1GHz-band PLL IC for Mobile Communications For the availability of this product, please contact the sales office. Descriptions The CXA1786N is a frequency synthesizer PLL IC developed for use in mobile communication systems. This IC has low current consumption, small package and is suitable for portable sets of cellular telephone and others. 20 pin SSOP (Plastic) Features • Low current consumption Icc = 6.0mA (typ.) 0.3mA (typ.) in power saving mode • Maximum operating frequency 1.1GHz guaranteed • Operating supply voltage range 2.7 to 5.5V • Ultra small 20-pin SSOP package • Two types of phase comparator output: For external charge pump φR φP Two internal charge pumps DO1 DO2 Structure Bipolar silicon monolithic IC Absolute Maximum Ratings • Supply voltage Vcc • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Applications 1.1GHz-band mobile communication equipment such as cellular telephones Operating Condition Supply voltage 7 –35 to +85 –65 to +150 300 Vcc V °C °C mW 2.7 to 5.5 V Block Diagram and Pin Configuration OSCI 1 NC 2 OSCO 3 Vp 4 VCC 5 DO 1 6 GND 7 LD 8 Phase Comparator Reference Programmable Counter 14bits Pulse Swallow Counter 7bits NC FIN Charge Pump 2 Charge Pump 1 φR 19 NC 18 φP 17 TEST 16 DO2 15 FC 14 LAT 13 DATA 12 PS 11 CK Programmable Counter 11bits 9 10 20 2-modulus prescaler 1 1 or 64/65 128/129 1-bit Latch 14-bit Latch 18-bit Shift Resister 1-bit Shift Resister 18-bit Latch Pulse swallow programmable counter Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93929A8Y CXA1786N Pin Description Pin No. Symbol Typical pin voltage (DC) Equivalent circuit VCC 1 OSCI 2.2V Description Reference frequency signal input. 1 10 10 FIN VCO signal input. GND 2 9 NC — No connected. — 19 VCC 3 OSCO High: 2.2V Low: 2.0V 3 500Ω GND Reference frequency signal output. Oscillator is formed by connecting the crystal resonator between this pin and the OSCI pin; the oscillator signal is used as the reference frequency signal. 4 VP 3V — Power supply for the charge pump outputs (Do1, Do2) and phase comparator outputs (φR, φP). 5 VCC 3V — Power supply. 6 DO1 DO2 7 GND 8 LD 18 φP 20 φR 11 CK 13 DATA Charge pump 1 output. GND Charge pump 2 output. Outputs only when the LAT pin is High; in high impedance when the LAT pin is Low. 6 — 16 Vp 16 — Ground. Vp (LD is VCC) High: 2.2V Low: 0.1V 8 18 20 GND VCC Open Low Lock detection signal output. Phase comparator output. Used for the external charge pump. Clock input. Data input. 11 13 14 LAT 14 GND –2– Latch input. CXA1786N Pin No. 12 Symbol Typical pin voltage (DC) Equivalent circuit Description PS VCC Open High 12 15 15 17 FC TEST GND High: 2.2V Low: 2.0V 17 –3– Power saving pin. Power saving mode when this pin is Low. Switching for the phases of phase comparator output and the output signals of counter (reference, programmable) output to the TEST pin. The signal output which is frequency-divided at the counter. CXA1786N Electrical Characteristics (Vcc = Vp = 3V, Ta = 25°C, refer to the Electrical Characteristics Measurement Circuit) Item Symbol Conditions Min. Typ. Max. Unit Current consumption Icc 5.84 8.7 mA Current consumption (in power saving mode) Icc (PS) 360 510 µA FIN operating frequency fin Vcc = Vp = 2.7V to 5.5V Ta = –35°C to +85°C 100 1100 MHz FIN input level Pin Vcc = Vp = 2.7V to 5.5V Ta = –35°C to +85°C –10 10 dBm OSCI operating frequency fosc Vcc = Vp = 2.7V to 5.5V Ta = –35°C to +85°C 5 20 MHz OSCI input level Vosc Vcc = Vp = 2.7V to 5.5V Ta = –35°C to +85°C 0.5 2 Vpp DO1 High output current DO2 IOH –1 mA DO1 Low output current DO2 IOL 1 DO1 High impedance DO2 leak current (leak current DO2 off) IOZ –1 φR φP LD High output voltage VOH IL = 0.1mA φR φP LD Low output voltage VOL IL = 0.1mA CK DATA LAT PS PS 2 mA 1 V 2.18 70.3 500 Vcc × 0.7 High input voltage VIH High input current IOH Low input voltage VIL Low input current IIL VIN = GND except for PS –1 Low input current IIL VIN = GND –30 –4– mV V –1 VIN = Vcc µA –15.5 1 µA Vcc × 0.3 V 1 µA µA CXA1786N Item FC CK DATA LAT PS PS FC Symbol Conditions Min. Typ. High input voltage VIH High input current IIH Low input voltage VIL Low input current IIL VIN = GND High input voltage VIH Vcc = VP = 5.5V Vcc × 0.7 High input current IIH Vcc = VP = 5.5V, VIN = Vcc –1 Low input voltage VIL Vcc = VP = 5.5V Low input current IIL Vcc = VP = 5.5V, VIN = GND except for PS –20 0 Low input current IIL Vcc = VP = 5.5V, VIN = GND –60 –27.7 High input voltage VIH Vcc = VP = 5.5V Vcc – 0.05 High input current IIH Vcc = VP = 5.5V, VIN = Vcc –1 Low input voltage VIL Vcc = VP = 5.5V Low input current IIL Vcc = VP = 5.5V, VIN = GND Max. Vcc – 0.05 VIN = Vcc V –1 –50 –5– –60 Unit –18.9 1 µA 0.05 V 1 µA V 1 µA Vcc × 0.3 V 1 µA µA V –34.7 1 µA 0.05 V 1 µA CXA1786N Electrical Characteristics Measurement Circuit Frequency Counter OUT A A Oscilloscope A Controller 5.1k A A V CK FIN FC PS DO2 NC TEST DATA φP 11 LD 12 LAT 13 GND 14 DO1 15 Vcc 16 VP 17 OSCO 18 NC 19 OSCI 20 NC A φR V 1 2 3 4 5 6 7 8 9 10 51 1µ 1000p V 1000p 1µ S.G. 1000p CXA1786N + 51 A V + A A 16 S.G. 51 1000p 51 DATA PS NC FIN 2 3 4 5 6 7 8 9 10 DO2 Controller 1k 1k 1k 1 FC LD CK 11 LAT TEST 12 GND φP 13 DO1 NC 14 Vcc φR 15 VP 17 OSCO 18 NC 19 OSCI 20 1k Power save LAT DATA CK Application Circuit 1µ TCXO 1000p 1000p 1000p 1000p CXA1786N + 51 L.P.F. V.C.O. Output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –6– CXA1786N Description of Operation 1. Data Setting Method The data is set using three signals — CK, DATA, and LAT in this IC. In that case, the serial data as described below is input. (1) Data input method The 15 bits of data should be input to the reference counter latch and the 18 bis of data to the pulse swallow programmable counter latch to set the all initializing state in this IC. Every one bit of data is retrieved into the shift resister at the rising edge of clock input to the CK pin when the data is input to the DATA pin. The input data is retrieved into the reference counter latch or the pulse swallow programmable counter latch according to the state of the final bit C. The data is latched when the latch pulse is input to the LAT pin after 16 bits of data or 19 bits of data, which were added with the bit C, are sent to the shift resister. For actual use, first input the 16 bits (including the frequency division setting bit SW for 2-modulus prescaler) of reference counter data from the controller as indicated above. In this time, set the final bit C High. Next, input the 19 bits of pulse swallow programmable counter data in the same way. In this time, set the final bit C Low. Then, all of the interior state has been set. Hereafter, when only the programmable counter data is to be changed, only the latter 19 bits of programmable counter data should be changed. (In this case, set the bit C Low.) (2) Control data construction The control data consists of 16 bits for the reference counter and 19 bits for the pulse swallow programmable counter. The final bit of them is the identification code and the contents of data are discriminated by identifying the code. The frequency division value is composed of the binary values whose head is MSB as described on the next page. –7– CXA1786N (a) Data structure of reference counter Input direction SW RD RC RB RA R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 C (First, input the SW bit and input the C bit last.) R0 to RD: Frequency division number of reference counter (Binary value with R0 as LSB) SW: Switching bit of frequency division numbers of 2-modulus pre-scaler block for programmable counter. C: SW 1 0 Frequency division number 64/65-frequency division 128/129-frequency division This code decides the latch direction of data; set to High. (b) Data structure of pulse swallow programmable counter Input direction MA M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S6 S5 S4 S3 S2 S1 S0 C (First, input the MA bit and input the C bit last.) M0 to MA: Frequency division number of main counter (Binary value with M0 as LSB) S0 to S6: Frequency division number of swallow counter (Binary value with S0 as LSB) C: This code decides the latch direction of data; set to Low. The frequency division value of programmable counter can be obtained with the following equation; N×M+S N: Frequency division value of 2-modulus pre-scaler (64 or 128) (M > S) M: Main counter value S: Swallow counter value (1) Data input timing t1 to t5 ≥ 500ns DATA (SW bit or MA bit) (C bit) CK t1 t2 t3 LAT t4 Data is read at the rising edge of CK. t5 –8– CXA1786N 2. Power Save Pin (PS) This pin is left High when it is open and in power saving mode at Low. All circuits except for reference counter latch and pulse swallow programmable counter latch are set to off in the power saving mode. At that mode, Do1 and Do2 are high impedance and the data cannot be set. ∗ The data of reference counter and programmable counter are hold in power saving mode. 3. Do1 and Do2 Pins These are the charge pump output pins. Do1 operates always. Do2 operates only when the LAT pin is High ; it is in high impedance state when the LAT pin is Low. 4. FC Pin This pin switches the charge pump outputs (Do1, Do2) and the phases of phase comparator outputs (φP, φR). (Refer to the Table 1.) 5. TEST Pin This pin is for monitoring the counter output signal. The reference counter output and the pulse swallow programmable counter output are switched according to the FC state as shown at Table 1. This pin is emitter follower output High level = Vcc – Vf and Low level = Vcc – Vf – 200mV (200mV amplitude). The DC bias current is decreased to save the power consumption so that the amplitude may not be monitored for monitoring the waveforms with oscilloscope. In that case, connect the TEST pin to ground with an approximately 5kΩ resistor. Table 1. Phase comparator and TEST Pin outputs FC: High or open FC: Low Do1 (2) φR φP fr > fp H L L fr fr = fp Z L H fr < fp L H H ∗ Z: High impedance H: High L: Low φR φP TEST L H H fp fr Z L H fp fr H L L fp TEST Do1 (2) fr: Output frequency of reference counter fp: Output frequency of programmable counter –9– CXA1786N 6. Reference signal (the input signal of reference counter) The external oscillator signal can be used as the reference signal by inputting the signal of the external oscillator to the OSCI pin, and the reference signal can be also generated by connecting the crystal resonator to the OSCI and OSCO pins. (1) Generation of the reference signal by the external oscillator Input the signal to the OSCI pin via a capacitor as shown below when the external oscillator signal is use as the reference signal. OSCI NC OSCO 1 2 3 (2) Generation of the reference signal by the built-in oscillator Connect the crystal resonator between OSCI and OSCO pins as shown below. Use the crystal resonator of several MHz and confirm the stability of the oscillation and others. The capacitance ratio of CI and Co should be 1 to 2:1, and their values should be selected so that the serial capacitance of CI and Co may be the load capacitance specified by the crystal vibrator. OSCI NC OSCO 1 2 3 CI CO Notes on Operation • Be careful to use this IC because the electrostatic resistance is the rank "A" due to handling the higher frequency signal of 1GHz • Make the input route of the RF signal from the VCO as short as possible. • Connect the Vcc and Vp pins to the ground respectively via the by-pass capacitors as short as possible because the frequency of signal used in this IC is higher. – 10 – CXA1786N Example of Representative Characteristics FIN input level vs. Input frequency ICC vs. Ta 10 7 ICC (current of VCC and Vp) [mA] 0 FIN input level [dBm] Vcc = 3V –10 –20 –30 –40 25°C 85°C 35°C –50 –60 –70 Vcc, Vp 5V 6 Vcc, Vp 3V 5 4 3 2 –35 –25 10 100 0 25 85 Ta [°C] 1000 FIN input frequency [MHz] ICC vs. VCC OSCI input level vs. Input frequency 7 10 ICC (current of VCC and Vp) [mA] Vcc = 3V OSCI input level [dBm] 0 –10 –20 –30 25°C 85°C 35°C –40 1 10 6 Ta = 25°C 5 4 3 2 100 2.7 3 4 VCC and Vp voltage [V] OSCI input frequency [MHz] – 11 – 5 5.5 CXA1786N Package Outline Unit: mm 20PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗6.5 ± 0.1 0.1 11 20 1 6.4 ± 0.2 ∗4.4 ± 0.1 A 10 + 0.05 0.15 – 0.02 0.65 + 0.1 0.22 – 0.05 0.13 M 0.5 ± 0.2 0.1 ± 0.1 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-20P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE SSOP020-P-0044 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 12 –