FAIRCHILD 74ACT175

74AC175, 74ACT175
Quad D-Type Flip-Flop
tm
Features
General Description
■ ICC reduced by 50%
The AC/ACT175 is a high-speed quad D-type flip-flop.
The device is useful for general flip-flop requirements
where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-toHIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input
resets all flip-flops, independent of the Clock or D-type
inputs, when LOW.
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ Asynchronous common reset
■ True and complement output
■ Outputs source/sink 24mA
■ ACT175 has TTL-compatible inputs
Ordering Information
Order
Number
Package
Number
Package Description
74AC175SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
74AC175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT175SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
74ACT175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D3
Data Inputs
CP
Clock Pulse Input
MR
Master Reset Input
Q0–Q3
True Outputs
Q0–Q3
Complement Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
74AC175, 74ACT175 Quad D-Type Flip-Flop
April 2007
Functional Description
The AC/ACT175 consists of four edge-triggered D-type
flip-flops with individual D inputs and Q and Q outputs.
The Clock and Master Reset are common. The four flipflops will store the state of their individual D inputs on the
LOW-to-HIGH clock (CP) transition, causing individual Q
and Q outputs to follow. A LOW input on the Master
Reset (MR) will force all Q outputs LOW and Q outputs
HIGH independent of Clock or Data inputs. The AC/
ACT175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
IEEE/IEC
Inputs @ tn, MR = H
Outputs @ tn+1
Dn
Qn
Qn
L
L
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
2
74AC175, 74ACT175 Quad D-Type Flip-Flop
Logic Symbol
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
IIK
Parameter
Rating
Supply Voltage
–0.5V to +7.0V
DC Input Diode Current
VI = –0.5V
–20mA
VI = VCC + 0.5V
+20mA
VI
DC Input Voltage
IOK
DC Output Diode Current
–0.5V to VCC + 0.5V
VO = –0.5V
–20mA
VO = VCC + 0.5V
+20mA
VO
DC Output Voltage
–0.5V to VCC + 0.5V
IO
DC Output Source or Sink Current
±50mA
ICC or IGND DC VCC or Ground Current per Output Pin
±50mA
TSTG
Storage Temperature
–65°C to +150°C
TJ
Junction Temperature
140°C
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
Parameter
Supply Voltage
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
VI
Input Voltage
VO
Output Voltage
TA
Operating Temperature
∆V / ∆t
Rating
0V to VCC
0V to VCC
–40°C to +85°C
Minimum Input Edge Rate, AC Devices:
125mV/ns
VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V
∆V / ∆t
Minimum Input Edge Rate, ACT Devices:
125mV/ns
VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
3
74AC175, 74ACT175 Quad D-Type Flip-Flop
Absolute Maximum Ratings
Symbol
VIH
Parameter
VCC
(V)
Minimum HIGH Level
Input Voltage
3.0
Maximum LOW Level
Input Voltage
3.0
Minimum HIGH Level
Output Voltage
3.0
TA = +25°C
Conditions
VOUT = 0.1V
or VCC – 0.1V
2.1
2.1
2.25
3.15
3.15
2.75
3.85
3.85
1.5
0.9
0.9
2.25
1.35
1.35
2.75
1.65
1.65
2.99
2.9
2.9
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
4.5
4.5
VOUT = 0.1V
or VCC – 0.1V
5.5
VOH
Guaranteed Limits
1.5
5.5
VIL
Typ.
TA = –40°C to +85°C
IOUT = –50µA
Units
V
V
V
VIN = VIL or VIH:
VOL
Maximum LOW Level
Output Voltage
3.0
IOH = –12mA
2.56
2.46
4.5
IOH = –24mA
3.86
3.76
4.86
4.76
0.002
0.1
0.1
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
0.36
0.44
–24mA(1)
5.5
IOH =
3.0
IOUT = 50µA
V
VIN = VIL or VIH:
3.0
IOL = 12mA
4.5
IOL = 24mA
0.36
0.44
5.5
IOL = 24mA(1)
0.36
0.44
±0.1
±1.0
µA
IIN(3)
Maximum Input
Leakage Current
5.5
VI = VCC, GND
IOLD
Minimum Dynamic
Output Current(2)
5.5
VOLD = 1.65V Max.
75
mA
5.5
VOHD = 3.85V Min.
–75
mA
Maximum Quiescent
Supply Current
5.5
VIN = VCC or GND
40.0
µA
IOHD
ICC
(3)
4.0
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
4
74AC175, 74ACT175 Quad D-Type Flip-Flop
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
Parameter
VCC
(V)
Conditions
Typ.
TA = –40°C to +85°C
Guaranteed Limits
Units
VOUT = 0.1V or
VCC – 0.1V
1.5
2.0
2.0
1.5
2.0
2.0
VOUT = 0.1V or
VCC – 0.1V
1.5
0.8
0.8
5.5
1.5
0.8
0.8
4.5
IOUT = –50µA
4.49
4.4
4.4
5.49
5.4
5.4
3.86
3.76
4.86
4.76
0.001
0.1
0.1
0.001
0.1
0.1
0.36
0.44
0.36
0.44
±0.1
±1.0
µA
1.5
mA
75
mA
–75
mA
40.0
µA
Minimum HIGH Level
Input Voltage
5.5
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
TA = +25°C
4.5
4.5
5.5
V
V
V
VIN = VIL or VIH:
4.5
VOL
Maximum LOW Level
Output Voltage
IOH = –24mA
–24mA(4)
5.5
IOH =
4.5
IOUT = 50µA
5.5
V
VIN = VIL or VIH:
4.5
IOL= 24mA
24mA(4)
5.5
IOL=
Maximum Input
Leakage Current
5.5
VI = VCC, GND
ICCT
Maximum ICC/Input
5.5
VI = VCC – 2.1V
IOLD
Minimum Dynamic
Output Current(5)
5.5
VOLD = 1.65V Max.
5.5
VOHD = 3.85V Min.
Maximum Quiescent
Supply Current
5.5
VIN = VCC or GND
IIN
IOHD
ICC
0.6
4.0
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
5
74AC175, 74ACT175 Quad D-Type Flip-Flop
DC Electrical Characteristics for ACT
TA = +25°C,
CL = 50pF
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
TA = –40°C to +85°C,
CL = 50pF
VCC (V)(6)
Min.
Typ.
3.3
149
214
139
5.0
187
244
187
Propagation Delay,
CP to Qn or Qn
3.3
2.0
9.5
12.0
2.0
13.5
5.0
1.5
7.0
9.0
1.0
9.5
Propagation Delay,
CP to Qn or Qn
3.3
2.5
8.5
13.0
2.0
14.5
5.0
1.5
6.0
9.5
1.5
10.5
Propagation Delay,
MR to Qn
3.3
3.0
7.5
12.5
2.5
13.5
5.0
2.0
5.5
9.0
1.5
10.0
Propagation Delay,
MR to Qn
3.3
3.0
8.5
11.0
2.5
12.5
5.0
2.0
6.0
8.5
1.5
9.0
Parameter
Maximum Clock Frequency
Max.
Min.
Max.
Units
MHz
ns
ns
ns
ns
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for AC
TA = +25°C,
CL = 50pF
Symbol
tS
tH
tW
tW
tREC
TA = –40°C to +85°C,
CL = 50pF
VCC (V)(7)
Typ.
Setup Time, HIGH or LOW,
Dn to CP
3.3
2.0
4.5
4.5
5.0
1.0
3.0
3.0
Hold Time, HIGH or LOW,
Dn to CP
3.3
1.0
1.0
1.0
5.0
1.0
1.0
1.0
CP Pulse Width,
HIGH or LOW
3.3
2.5
4.5
4.5
5.0
2.0
3.5
3.5
MR Pulse Width, LOW
3.3
2.5
4.5
5.0
5.0
2.0
3.5
3.5
Parameter
Recovery Time, MR to CP
Guaranteed Minimum
3.3
–2.0
0
0
5.0
–1.0
0
0
Units
ns
ns
ns
ns
ns
Note:
7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
6
74AC175, 74ACT175 Quad D-Type Flip-Flop
AC Electrical Characteristics for AC
TA = +25°C,
CL = 50pF
Symbol
Parameter
VCC (V)(8)
Min.
Typ.
TA = –40°C to +85°C,
CL = 50pF
Max.
Min.
Max.
145
Units
fMAX
Maximum Clock
Frequency
5.0
175
236
MHz
tPLH
Propagation Delay,
CP to Qn or Qn
5.0
2.0
6.0
10.0
1.5
11.0
ns
tPHL
Propagation Delay,
CP to Qn or Qn
5.0
2.0
7.0
11.0
1.5
12.0
ns
tPLH
Propagation Delay,
MR to Qn
5.0
2.0
6.0
9.5
1.5
10.5
ns
tPHL
Propagation Delay,
MR to Qn
5.0
2.0
5.5
9.5
1.5
10.5
ns
Note:
8. Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for ACT
TA = +25°C,
CL = 50pF
Symbol
tS (H)
Parameter
VCC (V)(9)
Setup Time, Dn to CP
Typ.
5.0
tS (L)
TA = –40°C to +85°C,
CL = 50pF
Guaranteed Minimum
3.0
2.0
2.0
3.0
2.5
2.5
0
1.0
1.0
Units
ns
tH
Hold Time, HIGH or LOW,
Dn to CP
tW
CP Pulse Width,HIGH or LOW
5.0
4.0
3.0
3.5
ns
tW
MR Pulse Width, LOW
5.0
4.0
3.0
4.0
ns
trec
Recovery Time, MR to CP
5.0
0
0
0
ns
5.0
ns
Note:
9. Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Conditions
Typ.
Units
CIN
Input Capacitance
VCC = OPEN
4.5
pF
CPD
Power Dissipation Capacitance
VCC = 5.0V
45.0
pF
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
7
74AC175, 74ACT175 Quad D-Type Flip-Flop
AC Electrical Characteristics for ACT
74AC175, 74ACT175 Quad D-Type Flip-Flop
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
8
74AC175, 74ACT175 Quad D-Type Flip-Flop
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
9
5.00±0.10
4.55
5.90
4.45 7.35
0.65
4.4±0.1
1.45
5.00
0.11
12°
MTC16rev4
Figure 4. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
10
74AC175, 74ACT175 Quad D-Type Flip-Flop
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
74AC175, 74ACT175 Quad D-Type Flip-Flop
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 5. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
11
®
ACEx
Across the board. Around the world.¥
ActiveArray¥
Bottomless¥
Build it Now¥
CoolFET¥
CROSSVOLT¥
CTL™
Current Transfer Logic™
DOME¥
2
E CMOS¥
®
EcoSPARK
EnSigna¥
FACT Quiet Series™
®
FACT
®
FAST
FASTr¥
FPS¥
®
FRFET
GlobalOptoisolator¥
GTO¥
HiSeC¥
i-Lo¥
ImpliedDisconnect¥
IntelliMAX¥
ISOPLANAR¥
MICROCOUPLER¥
MicroPak¥
MICROWIRE¥
MSX¥
MSXPro¥
OCX¥
OCXPro¥
®
OPTOLOGIC
®
OPTOPLANAR
PACMAN¥
POP¥
®
Power220
®
Power247
PowerEdge¥
PowerSaver¥
®
PowerTrench
Programmable Active Droop¥
®
QFET
QS¥
QT Optoelectronics¥
Quiet Series¥
RapidConfigure¥
RapidConnect¥
ScalarPump¥
SMART START¥
®
SPM
STEALTH™
SuperFET¥
SuperSOT¥-3
SuperSOT¥-6
SuperSOT¥-8
SyncFET™
TCM¥
®
The Power Franchise
®
TinyLogic
TINYOPTO¥
TinyPower¥
TinyWire¥
TruTranslation¥
PSerDes¥
®
UHC
UniFET¥
VCX¥
Wire¥
™
TinyBoost¥
TinyBuck¥
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Definition
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
www.fairchildsemi.com
12
74AC175, 74ACT175 Quad D-Type Flip-Flop
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.